Figure 6-6 Block diagram of a five-bit parallel adder circuit using full adders.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
 Addition - The parallel binary adder

Although this is a parallel device we do need to

consider propagation delay

Each FA is required to wait for the lower order FA to

provide the carry output. This is cumulative.

The speed of operation becomes limited by carry

propagation or carry ripple
 Arithmetic Unit

Figure 6-4 Functional parts of an ALU. © 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
 Arithmetic Unit
The 74LS382 (TTL) IC provides an integrated Arithmetic Logic
Unit

This 20-pin IC provides inputs for two 4-bit numbers A3..A0 and
B3..B0 and a 4-bit output F3..F0

Clear: S2..S0 = (0 0 0) the outputs are cleared

Add: Adds the two inputs
Subtract: Subtract 1 input from the other, A and B set by S[]
XOR: Bitwise XOR
OR: Bitwise OR
AND: Bitwise AND
Preset: S2..S0 = (1 1 1) the outputs are preset
Figure 6-15 (a) Block symbol for 74LS382/HC382 ALU chip; (b) function table showing how select
inputs (S) determine what operation is to be performed on A and B inputs.
© 2007 Pearson Education, Inc.
Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
 Binary Multiplication
Consider multiplying two decimal numbers; for example
624 × 321. (624 is called the multiplicand and 321 is called
the multiplier).
We can write the product as equal to
(1 × 624) + (20 × 624) + (300 × 624).
Alternatively, we could write the product as
(1 × 624) + (2 × 6240) + (3 × 62400).
In this method, after being multiplied by each digit, the
multiplicand is shifted to the left and has a zero (0) added to
its right-hand end. The method of multiplying binary
numbers is identical to that used with decimals.
 Binary Multiplication

Consider the multiplication of 1001 by 1101 in a digital

machine.
10012 x 11012 = 910 x 1310 = 11101012 = 11710
As with decimals the product can be written as
(1 × 1001) + (0 × 10010) + (1 × 100100) + (1 × 1001000)
= 1110101

After being multiplied by each binary digit, the multiplicand is shifted

to the left and has a zero (0) added to its right-hand end.
 Binary Multiplication
One difference with digital circuits is that because they add
only two numbers at a time, the process they would follow
would be to add the partial products as follows:

(1 × 1001) + (0 × 10010) + (1 × 100100) + (1 × 1001000)

= 1001 + 100100
= 101101 + 1001000
= 1110101
 Binary Multiplication
Binary Multiplication Circuit
How many bits do we need to multiply 2 4-bit numbers.
15 x 15 = 225
1 1 1 1 x 1 1 1 1 =1 1 1 0 0 0 0 1

8-Bit System
 Binary Multiplication
Binary Multiplication Circuit
A circuit that will perform binary multiplication is shown
on the next slide.
This circuit contains three registers X, B, A
The X register stores the multiplier bits
The B register stores the multiplicand bits
The A register (accumulator) stores the partial products
X and B are shift registers (X shifts right, B shifts left).
 ADD X0
Common CLK inputs
transfer
Clock
D D D D D D D D
CLK CLK CLK CLK CLK CLK CLK CLK
Accumulator
A7 A A5 A4 A3 A2 A1 A0
6 C0 = 0

To S4
FFs To
A4 -A 7 S5 FFs
8-bit parallel adder
S6 A0 -A3
D inputs S7 D inputs

B7 B6 B5 B 4 B3 B 2 B 1 B0 D
Multiplicand D D D D D CLK
D D
CLK CLK CLK CLK CLK CLK CLK

Multiplier

D X3 D X2 D X1 D X0
A triggers B and X
shift CLK CLK CLK CLK
Clock
Pulses

A register triggers on p o sitiv e clocktransition.

B and X registers trigger on n e g a tiv e edge.
Binary multiplier circuit
 Binary Multiplication
Binary Multiplication Circuit - Operation
1) An 8-bit parallel adder adds the bits A7 … A0 from the accumulator to the bits
B7 … B0 from the B register. The adder outputs are connected to the D inputs
of A, and data is transferred to A when a clock pulse gets through the AND
gate. Data is input to A on the PGT of the clock pulse while X and B shift on
NGT of the clock pulse.

2) To commence a multiplication (e.g. 1001 × 1101), the A registers would first be

cleared (DC clear is not shown on the diagram) and the numbers 1001 and 1101
entered into the B and X registers respectively. (For simplicity, the method of
entering these is also not shown on the circuit diagram.) Once the number 1001
is entered into B, the output of the adder will be 1001 + 0000 = 1001.
 Binary Multiplication
Binary Multiplication Circuit - Operation
3) On the PGT of the first clock pulse, as X0 = 1, the output of the AND gate
becomes 1 and thus the A registers are clocked. The output of the adder (1001)
is transferred to the A register. On the NGT of this clock pulse, the contents of
the X register shift to the right, while the contents of the B register shift to the
left, with a 0 now in the LSB.

4) On the PGT of the second clock pulse, the clock signal does not pass through
the AND gate as the value from the X register is 0. Hence the A register is
unchanged. On the NGT, the X and B registers are shifted as before.
 Binary Multiplication
Binary Multiplication Circuit - Operation
5) On the PGT of the third clock pulse, as X = 1, the output of the AND gate
becomes 1 and thus the A registers are clocked. The output of the adder
(101101) is transferred to the A register. On the NGT of this clock pulse, the
contents of the X register again shift to the right, while the contents of the B
register shift to the left.

6) On the PGT of the fourth clock pulse, as X is again 1, the output of the AND
gate becomes 1 and thus the A registers are clocked. The output of the adder
(1110101) is transferred to the A register. On the NGT of this clock pulse, the
contents of the X register again shift to the right, while the contents of the B
register shift to the left. The X register bits are now all zero, and the process is
complete.

The similarities between the process described above and the way we perform
multiplication manually should be noted.
 Binary Multiplication - AHDL
Fortunately for us, AHDL has a megafunction for multiplication too.
It is used as follows:
INCLUDE "lpm_mult.inc";
SUBDESIGN multiply
(
a[3..0], b[3..0] : INPUT;
s[7..0] : OUTPUT;
)
BEGIN
(s[]) = lpm_mult (a[], b[],,,)
WITH (LPM_WIDTHA = 4, LPM_WIDTHB = 4, LPM_WIDTHP = 8,
LPM_WIDTHS = 4)
END;