Digital Design

using
VerilogHDL

Presented by

Kailash Chandra Ray

kcr@ece.iitkgp.ernet.in

Advanced VLSI Design Laboratory

Indian Institute Of Technology, Kharagpur
 VLSI DESIGN FLOW :Front End Design
specification

Algorithmic analysis
Behavioral
representation
Architectural Design

SYNTHESIS Design verification

Logic design
Gate level
representation Logic verification

Logic Net list

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 An Example: Typical Architecture of IC

DATA PATH CONTROL

REG1 Logic REG2

CONTROLLER
LOGIC
Main Logic
Logic
Unit
REG3

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A Laboratory Flow for ASIC Design (Cell Based)

HDL
Verilog-XL (Cadence)

Logic Simulation
SimVision (Cadence)

Design Compiler (Synopsys) Synthesis

Physical Design
Silicon Ensemble (Cadence)

Physical
Hercules (Avant) Verification
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 Hardware Description Language

HDL

VHDL VerilogHDL

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 VerilogHDL: History

• Gateway Design Automation

• Cadence purchased Gateway in 1989.
• Verilog was placed in the public domain.
• Open Verilog International (OVI) was created
to develop the Verilog Language as IEEE
standard.

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 Identifiers & Logic Values in Verilog
Identifiers
9 Any Sequence of letter, digits,
dollar sign, underscore.
9 First character must be a
letter or underscore.
™ It cannot be a dollar sign.
™ Cannot use characters such as
hyphen, brackets, or # in
verilog names
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Logic Values
‰ Predefined logic value system
or value set:
‘0’, ‘1’ ,’x’ and ‘z’;
‰ ‘x’ means uninitialized or
unknown logic value
‰ ‘z’ means high impedance
value.
7
 Verilog Data Types

¾ Integer

¾ Nets: Key Word is WIRE

¾ Registers : Key Word is REG

• Temporary storage of variables similar to high level languages.

¾ Wires: Key Word is WIRE

• Analogous to a wire in an ASIC.

• Cannot store or hold a value.

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Hierarchical Design using modular concept

top_module

module1 module2 Module-n

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 Black Box Design for VLSI Architecture of a
CHIP

Module Definition

BLACK BOX O/P PORTS

I/P PORTS (Module)

I/O PORTS

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 Modular Design using Verilog HDL
module module_name (port_names);
-----------
port_types input [port_size] input_port_names;
----------- output [port_size] output_port_names;
wire declaration wire [wire_size] wire_names;
reg declaration reg [reg_size] reg_names;
-----------

Black Box
description

endmodule

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 Module Instatiation

Module top_module_name(Port_names);
input [port_size] input_port_names;
output [port_size] output_port_names;
wire [wire_size] wire_names;
------------
module_name1 instatiation_name1(port_conections);
module_name2 instatiation_name2(port_conections);
-----------
endmodule
By Position/Ordering By Names

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 PORT CONNECTIONS: An Example

a1
top_mod
in0 a3
moda
a2 w1
c1

in1 modc c3 out

c2
b1 w2
in3 b2 modb b3

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 Port Connections in Verilog HDL
(By Position/Ordering)
in0 a1 top_mod
module moda(a1,a2,a3); a3
input a1,a2; a2
moda w1
c1
output a3; in1 modc c3 out
----- c2
b1 w2
endmodule in3 b2 modbb3
module modb(b1,b2,b3)
input b1,b2;
output b3 module top_mod(in0,in1,in2,out);
----- input in0,in1,in2;
Endmodule
output out;
module modc(c1,c2,c3) wire w1,w2;
input c1,c2; moda mi0(in0,in1,w1);
output c3
----- modb mi1(in1,in2,w2);
endmodule modc mi2(w1,w2,out);
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endmodule 14
 Port Connections in Verilog HDL (By Name)

in0 a1 top_mod
module moda(a1,a2,a3); a3
input a1,a2; a2
moda w1
c1
output a3; in1 modc c3 out
----- c2
b1 w2
endmodule in3 b2 modbb3
module modb(b1,b2,b3)
input b1,b2;
output b3 module top_mod(in0,in1,in2,out);
----- input in0,in1,in2;
endmodule
output out;
module modc(c1,c2,c3) wire w1,w2;
input b1,b2; moda mi0(.a1(in0), .a2(in1), .a3(w1));
output c3 modb mi1(.b1(in1), .b2(in2), .b3(w2));
-----
endmodule
modc mi2(.c1(w1), .c2(w2), .c3(out));
endmodule
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 Modular Design using Verilog HDL

module module_name (port_names);

-----------
port_types
-----------
wire declaration Switch level description
reg declaration
Gate level description
Black Box
description Data Flow description

Behavioral description
endmodule
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 Switch Level Design

MOS Transistors as Switch

S D S D

G G
pmos nmos

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 Switch Level Design (cont..)

• CMOS Inverter design : As an Example

vdd module cmos_inv (vdd, gnd, in, out);

input vdd, gnd;
pmos input in;
output out;
in out
pmos p0 (vdd, out, in);
nmos
nmos n0 (out, gnd, in);

endmodule

gnd

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 Switch Level Design (cont..)

Design and Model following components using

Verilog HDL

¾ Design NAND,NOR gates using CMOS logic

¾ Integrate for AND,OR,XOR gates

¾ Design Transmission gates using pass transistors

¾ Design Macro modules like multiplexers,

demultiplexers, Flipflops, Adder, Subtractor and etc.

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 Gate Level/Structural Design
Multiplexer using primitives module mux (f, a, b, sel);
output f ;
a f1
nsel g1 input a, b, sel;
g4 f
g3 wire nsel, f1, f2;
b
g2
sel f2
and g1(f1, a, nsel),
and g2(f2, b, sel);
or g3(f, f1, f2);
not g4(nsel, sel);

endmodule

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 An Example: 4-bit Adder design

4-bit adder

FA FA FA FA

carry sum carry sum carry sum carry sum

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 Structural representation – example
module FA (co, s, a, b, c);
//4-bit adder input a, b, c;
output s, co;
module add4bit (s, c4, ci, a, b); sum s1 (s, a, b, c);
input [3:0] a, b; carry c1 (co, a, b, c);
endmodule
input ci;
output [3:0] s; module carry (co, a, b, c);
output c4; input a, b, c;
output co;
wire [2:0] co;
wire x, y, z;
FA a0 (co[0], s[0], a[0], b[0], ci); and g1 (x, a, b);
FA a1 (co[1], s[1], a[1], b[1], co[0]); and g2 (y, a, c);
and g3 (z, b, c);
FA a2 (co[2], s[2], a[2], b[2], co[1]); or g4 (co, x, y, z);
FA a3 (c4, s[3], a[3], b[3], co[2]); endmodule
endmodule module sum ( s, a, b, c);
input a, b, c;
output s;
xor x1(s,a,b,c)
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endmodule
 Dataflow Design

• RHS assigned by LHS

Conditional statements
Or
Logic Expressions

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 Dataflow Design (cont..)

• RHS assigned by LHS Using • RHS assigned by LHS Using

conditional statements Logical expressions

module mux (f, a, b, sel); module mux (f, a, b, sel);

output f; output f;
input a, b, sel; input a, b, sel;

assign f <= sel ? b :a; assign f <= a& (~sel) | b& sel;

endmodule endmodule

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 Behavioral Design

Some of Behavioral Key words are

¾ Conditional Statements : If, if…else, case;

¾ Loop Statements : for, while, forever;

¾ Behavioral Blocks: always, initial

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 Behavioral Verilog HDL codes
Multiplexer: As an Example
module module_name (port_names); module mux (f, a, b, sel);

input [port_size] input_port_names; input [3:0]a, b;

output [port_size] output_port_names; input sel;
output [3:0] f;
wire [wire_size] wire_names; reg [3:0] f;
reg [reg_size] reg_names;
always @(a or b or sel)
always @(sensitivity list)
.……………………… if (sel)
behavioral statements f = b;
………………………. else
f = a;

endmodule endmodule

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 Flipflop Design: An Example
module DFF (d, q, qbar, clk, reset);
input d,clk,reset;
output q,qbar;
reg q,qbar;
always @(posedge clk or posedge reset)
begin
if (sel)
begin
q = 1’b0;
qbar = 1’b1;
end
else
begin
q = d;
qbar = ~d;
end
end
endmodule
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 Behavioral Statements

• Continuous assignment Statements

using assign

• Procedural assignment statements:

¾ Blocking assignment (using = )

¾ Non blocking assignment (using <= )

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 Blocks Statements

Sequential Block statements:

• Sequential block is a group of statements between a
begin and an end.
• A sequential block, in an always statement executes
repeatedly.
• Inside an initial statement, it operates only once.
Parallel Block statements :
Statements are enclosed within
fork
…..
…..
join
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 Block statements: Examples

always @(a or b or c); always @(a or b or c);

begin fork
#5 d = a+b; #5 d = a+b;
#10 e = a-c; #10 e = a-c;
#15 f = b+c; #15 f = b+c;
end join

initial
begin
#5 d = a+b;
#10 e = a-c;
#15 f = b+c;
end
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 Examples

• Blocking: Statement executed at

always @(A1 or B1 or C1 or M1) time t causing M1 to be
assigned at t+3
begin
M1=#3(A1 & B1); Statement executed at
time t+3 causing Y1 to be
Y1= #1(M1|C1); assigned at time t+4
end

• Non-blocking:
always @(A2 or B2 or C2 or M2) Statement executed at
time t causing M2 to be
begin assigned at t+3
M2<=#3(A2 & B2);
Y2<=#1(M1 | C1); Statement executed at
time t causing Y2 to be
end assigned at time t+1.
Uses old values.

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 Example: Physical Implementation

• Blocking Assignment • Non Blocking Assignment

module BA (clk, a, b, c ) module NBA (clk, a, b, c )
input clk, a, b; input clk, a, b;
output c; output c;
reg b, c; reg b, c;
always @(posedge clk) always @(posedge clk)
begin begin
b =a; b<=a;
c =b; c<=b;
end end
endmodule endmodule

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 Example: Physical Implementation

a b c
b
DFF
a
DFF DFF
c
DFF

blocking Non-blocking

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 Design using Functions & Tasks
Function Task
module m_name (port_declaration) module m_name (port_declaration)
…… ……
Begin Begin
…… ……
ret_val= func_name (arguments); task_name (arguments);
end end

function func_name;//declaration task task_name;//declaration

input declaration input declaration
variable_declaration output declaration
begin variable_declaration
<statements> begin
end <statements>
endfunction end
endtask
endmodule endmodule

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 FSM Design using VerilogHDL
module parity (clk, reset, i, o);
input clk, reset, i;
Reset
output o;
reg st, next_st, o;
parameter st_even = 0, st_odd = 1;
Even/0
always @(posedge clk or posedge reset)
begin i=1 i=1
if (reset == 1)
st <= st_even; Odd/1
else
st <= next_st;
end

/* state transitions */

/* output computation */
endmodule
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 State Transitions & Output computations
//State Transitions
always @(i or st)
begin
if (i == 1) begin Reset
if (st == st_even)
next_st = st_odd;
else
next_st = st_even; Even/0
end
else
next_st = st; i=1 i=1
end

//Output Computation Odd/1

always @(st)
begin
if (st == st_even)
o = 0;
else
o = 1;
end

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 Simulation using Test Bench

• Testbench generates stimulus and checks response

• Coupled to model of the system
• Pair is run simultaneously

Test Vector Stimulus

Generator

Testbench System Model

(tb.v) (top.v)
Response
Result
checker

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 An Example: multiplexer
//mux21.v
module mux21 (in0, in1, sel, out);
input in0,in1,sel;
output out;
assign out = (~sel & in0)| (sel & in1);
endmodule

//tb_mux21.v
module tb_mux21 (in0, in1, sel, out);
reg IN0,IN1,SEL;
wire OUT;
mux21 muxtop(IN0, IN1, SEL, OUT);
initial //Test Vector Generator
begin
IN0=1’b1; IN1=1’b0;SEL=1’b1;
#2 IN0=1’b1; #3 IN1=1’b0; #5 SEL=1’b1;
end
initial //Check Response
$display(‘%b,%b,%b,%b’, IN0, IN1,SEL,OUT);
endmodule
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 Test Bench with High level Language

Test Vector
Generator

Testbench System Model

PLI
(tb.c/c++) (top.v)

Result
checker

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 Conclusion
¾ Write RTL codes i.e. Synthesizable codes for
design
¾ Avoid Non Synthesizable codes
i.e. initial, #, while
¾ Write Mixed codes in Test Bench
¾ Write codes which can be translated into hardware
¾ Write structural codes for design on your effort
• Finally, remember that you are a better
designer than the tool!
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 Reference

1. Introduction to Verilog HDL

By Sameer Panitkar

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 Thank You

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