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COURSE E3-327,GROUP 2 REPORT NO.

1, SEPTEMBER 2009 1

Fabrication and Characterization of MOS Capacitors


Abheek Bardhan, Arjun Shetty, Arun Mahodaya,
Pradeep Dixena, Pramod M, Ramachandran R

Name Type of Doping Dielectric


Abstract—MOS capacitors are fabricated with SiO2 and G2W1 n SiO2
Eu2 O3 (High-K) as dielectric materials on p-type and n-type G2W2 p SiO2
silicon wafers. The measured thickness of SiO2 and Eu2 O3 is G2W3 n Eu2 O3
22.8 nm and 38.5 nm respectively. The fixed oxide charges of G2W4 p Eu2 O3
n-type wafers is greater than p-type wafers by a factor of 1000.
Interface trap density for wafers with RF sputtered Eu2 O3 is TABLE I: Wafer labels and dielectric materials
more than for wafers with thermally grown oxide. SiO2 has
lower leakage compared to Eu2 O3 and the former shows F-N
Tunneling. The High-K dielectric capacitor breaks down around
6 V while SiO2 at 28 V. The measured results show that thermally
A. Importance of MOS Capacitors
grown oxide has desirable properties compared to RF sputtered The MOS capacitor is often used as a test structure due
oxide of comparable thickness. to its simple fabrication process. The structure can yield con-
Index Terms—MOS Capacitor, High-K dielectric, CV, IV siderable information regarding the properties of the dielectric
Characterization used, the underlying silicon and the dielectric/silicon interface.
Capacitance vs Voltage test results offer a wealth of device
L IST OF S YMBOLS and process information, including bulk and interface charges,
dielectric thickness, flatband voltage, threshold voltage, etc.
VG Votage of metal with reference to semiconductor
VF B Flat band voltage
VT H Threshold voltage B. High-K Dielectrics
NA,D Acceptor and donar doping concentration
Cacc Accumulation capacitance As transistors have decreased in size, the thickness of the
COX Oxide capacitance SiO2 gate dielectric has steadily decreased to increase the gate
Cdep Depletion capacitance
Cg Gate capacitance
capacitance and thereby drive current and device performance.
Cmin Minimum gate capacitance As the thickness scales below 2 nm, leakage currents due to
Si Permitivity of silicon tunnelling increase drastically, leading to high standby power
OX Permitivity of dielectric
tOX thickness of dielectric
consumption and reduced device reliability. Replacing the
ψs Substrate potential SiO2 gate dielectric with a high-k material allows increased
ni Intrinsic carrier concentration of silicon gate capacitance for larger dielectric thickness without the
φt Voltage equivalent of temperature
Wdep Depletion width in silicon
adverse leakage effects. The MOS capacitor curves are shown
Cit Interface trap capacitance in Fig. 1.
Dit Interface trap density The following non idealities occur in MOS capacitors [3,
EOX Field across the dielectric
φOX Barrier between conduction band of Si and dielectric KN Bhat].
q Electron charge 1) Work function difference between metal and sub-
h̄ Planks constant
m∗ Effective mass of electron in oxide
strate : Changes the threshold voltage of the MOS
capacitor.
2) Fixed oxide charges : These charges arise due to
partially oxidised Si atoms at the interface. Positive
I. I NTRODUCTION
charges cause shift in CV curves to the left and vise
HE MOS capacitor consists of a Metal-Oxide-
T Semiconductor structure. There is a semiconductor
substrate with a thin oxide layer and a top metal contact,
versa.
3) Interface traps : The dangling bonds at Si-dielectric
interface lead to surface states in the forbidden gap
referred to as the gate. A second metal layer forms an ohmic which can hold charges depending on the location of
contact to the back of the semiconductor and is called the fermi level.
bulk contact. The structure of MOS capacitor is shown in
Fig. 1(a). Silicon substrate is chosen because it is stable as
II. FABRICATION S TEPS
a semiconductor even at higher temperatures and its native
oxide SiO2 can be grown easily. SiO2 is generally used as Four different types of MOS capacitors are fabricated, by
gate dielectric and for passivation. varying the type of doping of the substrates and the dielectric
material. These four types with their codes are given in Tab. I.
Abheek and Arjun are with the Department of NIS, IISc, Bangalore The initial material taken are the 2 inch pieces of <100>
Arun Mahodaya, Pradeep Dixena, Pramod M, Ramachandran R are with
Department of Electrical and Communication Engineering, IISc, Bangalore. prime quality Si wafers. The fabrication steps for the two
e-mail: nanofabiisc@googlegroups.com capacitors are shown in Fig. 2. After the growth of SiO2 or
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 2

- EC
Cgs /Cox -- --
øm - q*psiSi
1 HFCV
Ef
qVapp Ei
GATE
EV
BULK

OXIDE
LFCV
OHMIC CONTACT

0 VTH,n VGS
(a)
(b) (c)

Fig. 1: (a) MOS device [4](b) Ideal CV curves of a nMOS capacitor [1] (c) Band bending of MOS capacitor for VT < VG [9]

Parameter Value Units


Time of deposition 6 min
Pre sputtering time 10 min
Base pressure 2×10−5 mbar
Pressure 7×10−3 mbar
Voltage 1.5 KV
Target-Wafer distance 6 cm
Target surface area 2.5 inch
Rate of deposition 1.6 nm/min

TABLE III: Parameter for RF sputtering

confirmed by the hydrophobic nature of the wafer on Si


surface.

B. Thermal Oxidation
Thermal oxidation is carried out for the wafers G2W1 and
G2W2 for the growth of SiO2 layer on the cleaned Si surfaces.
The wafers are loaded in the furnace at 1000◦ C and having an
initial N2 ambient. Then oxygen gas is passed for 25 minutes.
At the end of this duration, the ambient is again switched to
N2 and wafers are then unloaded.
Fig. 2: Fabrication steps of (a) SiO2 and (b) Eu2 O3 as
dielectric materials. C. RF Sputtering
The RF magnetron sputtering technique is used to deposit
High-K dielectric layer of Eu2 O3 on the cleaned wafer sam-
deposition of Eu2 O3 , p-type wafer are annealed as described ples G2W3 and G2W4. Parameters in the sputtering process
in Sec. II-D. The final step of fabrication involves forming gas are shown in Tab. III. First, vacuum is created by bringing
annealing described in Sec. II-J. down the pressure of sputtering chamber to 2×10−5 mbar.
Then flushing is carried out using Ar gas and the pressure
A. Wafer Cleaning increases to 7×10−3 mbar. Pre-sputtering for 10 min is carried
All the four wafers described in Tab. I are cleaned as to avoid the deposition of any impurities on the wafer which
described by the steps shown in Tab. II [6]. The following may be present on the surface of the target. In the present
precautions are observed during wafer cleaning. experiment, the oxide thickness required is 10 nm and the
1) All the chemicals are CMOS grade and they are taken rate of deposition is 1.6 nm/min. Hence the sputtering time is
only in Quartz beaker. allowed for 6 min.
2) Above 80◦ C H2 O2 can dissociate and Si Wafer can get
oxidized in an uncontrolled way. D. Annealing
3) During HF dip, the solution is always taken in teflon The p-type wafers are annealed at 1000◦ C in the inert
beaker. atmosphere of N2 with flow rate of 3 Lts/min for about 30
4) Si is hydrophobic, while SiO2 is hydrophilic. The min.This process decreases the lattice defects present in the
completion of the etching of the native oxide layer is sample and hence reduces the fixed oxide charges.
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 3

Step Process Name Chemical Condition Duration Remark


No. Composition
1 SC1 Cleaning N H4 OH:H2 O2 :DI 80◦ C 10 min Organic impurities and alkali ions like
Water=1:1:5 F e3+ , Al3+ , M g 2+ are removed
2 DI rinse DI Water Room Temp. - Chemicals are flushed out.
3 HF dip HF:DI Water=1:50 Room Temp. 30 sec Native oxide layer is removed
4 DI rinse DI Water Room Temp. - Chemicals are flushed out.
5 SC2 Cleaning HCl:H2 O2 :DI Wa- 80◦ C 10 min Ionic impurities with insoluble hydroxides
ter=1:1:6 are removed
6 DI rinse DI Water Room Temp. - Chemicals are flushed out.
7 Blow drying Nitrogen Room Temp. - Water droplets adhered to the wafer surface
are removed.

TABLE II: Wafer cleaning steps

E. Thermal Evaporation Process Method/Material Comment


Photoresist AZ5214E Positive photoresist
Aluminium is deposited on the wafers for formation of
Coating Method Spin coating For uniform thick-
one of the terminals of the MOS capacitor. Hindvac thermal ness
sputtering unit is used to deposit thin films of metals on Ramp speed 500 rpm/sec Duration 5 s
the substrates. The target material is resistively heated with Spin speed 3000 rpm Duration 35 s
a tungsten filament. The metal melts and evaporates, these Softbake at 110◦ C 50-60 s Evaporate solvents
vapours move straight up (low pressure chamber) and deposit in photoresist
on the substrate. The parameters for thermal evaporation are UV exposure (Carl Wavelength=350 nm Duration : 13 s
Suss MJB3 Mask
given in Tab. IV. Aligner)
Parameter Value Units Developer MF26A Duration : 50 s
Pressure 2×10−5 mbar Cleaning DI Waer To remove devel-
Low tension voltage 30 V oper
Target metal Al - Drying Blow drying N2 gas
Substrate Wafers -
Heating at 125◦ C 2 min Hardening of pho-
toresist
TABLE IV: Parameters for thermal evaporation
TABLE V: Photolithography steps
F. Photolithography
Photolithography is carried out on the wafers to pattern Process Method/Material Comment
the top electrode in order to get MOS capacitors of different Etchant H3 P O4 : Composition 19:1:4
dimensions. The details of photolithography are given in HN O3 : by volume
Tab. V DI W ater
Etch rate ≈ 2 nm/s Depends of etchant
G. Aluminium Etching composition
G1W1 40.56 s
After the wafers have been patterned using photolithogra-
G2W2 43.72 s
phy, the Al metallization from the unexposed area should be Etch Duration
G2W3 34 s
etched out. The process of etching is described in Tab. VI
G2W4 41.3 s
Cleaning DI Water To remove etchant
H. Back Oxide Etching
Photoresist removal Acetone and IPA -
During the thermal oxidation (Sec. II-B), the back surface of
wafers G2W1 and G2W2 will be oxidised forming SiO2 . This TABLE VI: Etching steps
oxide should to be removed to form the back side metal contact
of the MOS capacitor. Buffered HF (100 gm of N H4 OH,
150 ml of DI water = V with (V/3) of HF) is used in the ratio
1:20 with DI water to etch the oxide . This gives etch rate J. Forming Gas Annealing
of about 30 nm/min. Complete removal of the oxide can be
noticed when the hydrophilic oxide turn to hydrophobic nature
of the underlying silicon. The wafer is cleaned with DI water At Si-dielectric interface the periodicity of Si crystal ter-
and dried (blow drying) with N2 . minates. The dangling bonds of Si will lead to interface
states, these bonds have to be passivated. Passivation is done
I. Back contact Formation using forming gas (a mixture of N2 :H2 ::9:1) at 450◦ C for
After back oxide etching described in Sec. II-H, aluminium 30 min. The H atoms being light, diffuse through dielectric and
is deposited on the back surface of all the wafer using thermal passivate the dangling bonds, thereby reducing the interface
evaporation described is Sec. II-E. The back contact will trap states. Fig. 3 shows the MOS capacitors of different sizes
reduce the effect of contact resistance of the substrate. after the fabrication process.
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 4

SiO2 measured using FTPadvanced instrument is shown in


Tab. VIII.
Location p-type n-type
Pre-anneal Post-anneal
T1 T2 T1 T2 T1 T2
Left 28.3 27.8 31.4 31.4 29.8 30.2
Right 29.3 28.9 32.7 31.6 30.6 30.6
Center 30.1 30.4 31.8 32.6 29.2 29.8

TABLE VIII: Thickness of SiO2 measured using FTP in nm

C. Alumium thickness measurements


A surface profiler is used to measure the thickness of
Aluminium pads. Profilometer is an instrument that measures
Fig. 3: Fabricated wafers clockwise G2W1, G2W2, G2W3, the profile of a surface and hence its roughness. A contact
G2W4. surface profilometer is used in the measurements. In this
instrument a diamond stylus with a microtip is pressed in
contact with the sample with a specific force of the order
III. M EASUREMENTS of milligrams. This tip then scans the sample surface and
A. Resistivity Measurements the displacement of the tip in vertical direction generates
1) A four point probe measurement system is used for an analog signal that gives a measure of surface roughness.
measuring sheet resistance and resistivity of the system. Tab. III-C shows the thickness of aluminium deposited by
2) Current is passed through the outer pair of probes and thermal evaporation described in Sec. II-E.
voltage is measured between the inner pair of probes.
If the separation between the probes is larger than the D. CV Measurements
thickness of the wafer and if it is smaller than the size of The C-V measurement is done using Agilent 4284 Precision
the wafer then the sheet resistance can be approximated LCR Meter. The capacitance is determine for different regions
by (V/I)=0.22ρs [10]. of operation. The meter measures the small signal current
3) Resistivity is measured on 3 locations on the wafer. The due to a small signal voltage sitting on a DC level. Open
sheet resistance and resistivity is shown in Tab. VII. correction is done for the LCR meter to compensate for cable
4) Resistivity is determined as follows impedance. The signal is given at the back terminal to mitigate
ρ = ρsh ∗ t (1) the effect of parasitic impedances. The LCR meter settings for
CV measurement is given in Tab. 10. The DC voltage is swept
where ρsh is the sheet resistance and t is the thickness from inversion to accumulation to avoid deep depletion. The
of the wafer. here results of CV measurements are shown is Sec. IV
• t=390-400 µm for N-type wafer
• t=265-295 µm for P-type wafer
E. I-V Mesurements
Type Center Left Right Units The I-V measurement is done using 4155C Semiconductor
n
9.55 9.9089 9.6915 mΩ.cm Parameter Analyzer . The input voltage is swept from 0 V
238.789 247.723 242.287 Ω/sq to +15 V and the gate leakage current is determined. The
1.233 1.2410 1.2539 Ω.cm
p
41.9187 42.0687 42.5062 Ω/sq voltage is applied on the top terminal unlike in the case of
CV measurements. The maximum power dissipation for IV
TABLE VII: Sheet resistance and resistivity of N-type (G2W1)
and P-type (G2W2) wafer
Wafer Gate Wafer Al thickness (nm) tavg
type oxide name (nm)
t1 t2
N Si02 G2 W 1 61.3 58.7 60
B. FTP Measurements P Si02 G2 W 2 54.7 65.2 60
The Film Thickness Probe FTPadvanced instrument is used N Eu2 O3 G2 W 3 53.0 44.9 49
P Eu2 O3 G2 W 4 45.7 30.7 38.2
for thickness measurement of transparent and semitransparent
films on transparent and absorbing substrates [2]. The principle TABLE IX: Aluminium thickness measurements
of the thickness measurement is based on the interference
patterns in the reflectivity spectrum of light reflected off a Parameter Value Units
layered sample. Initially the elipsometry is used to obtained Small signal AC 5 mVRM S
Hold time 100 ms
optical constants and these are input initially to the system DC step 100 mV
to be used for further measurements. The range of thickness
has to be initially given to the instrument. The thickness of TABLE X: LCR meter settings for capacitance measurements
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 5

r,Si 11.7
measurement instrument is limited to 2 W. Hence for a DC r,SiO2 3.9
voltage of 20 V, the current is limited to 50 mA. The results r,Eu2 O3 24 [5, High-K]
of IV measurements is shown in Sec. V. KB 1.38×1023 J/K
T 298 K
q 1.6×10−19 C
IV. CV M EASUREMENT R ESULTS h̄ 1.0545×10−34 Js
mO 9.1×10−31 Kg
The CV plots from the measured data is shown in Fig. 4 m∗SiO 0.0.39mO
2
m∗Eu O 0.11mO [8]
and Fig. 5. 2 3
χAl 4.1 eV
χSi 4.05 eV
Eg,Si 1.12 eV
ni 1.15×1016 m−3

TABLE XI: List of Contants

Fig. 4: Normalised capacitance vs gate voltage curves of


MOS capacitors with n-type and p-type wafers and SiO2 as
dielectric
Fig. 6: Doping concentration of different wafers.
Average doping concentration of n-type is
1.678×1015 cm−3 (4.6×1014 cm−3 by resistivity
measurement with µn =1400 cm2 /V.s) and for p-type
is 1.678×1016 cm−3 (1.12×1016 cm−3 by resistivity
measurement with µp =450 cm2 /V.s)

Fig. 5: Normalised capacitance vs gate voltage curves of


MOS capacitors with n-type and p-type wafers and Eu2 O3
as dielectric

The procedure used to analyse measured CV data is de- Fig. 7: Oxide thickness of different wafers. The oxide thick-
scribed in Appendix A. In accordance to this procedure, a ness of SiO2 conforms with the FTP measurement described
software program is written to process the measured data. in Sec. III-B, while the thickness of Eu2 O3 is higher than the
predicted deposited value of 10 nm (Sec. II-C)
The figures Fig. 6 to Fig. 10 show different parameters
obtained through extraction of measured data.
The plot of interface trap density Dit for all the four wafers
is shown in Fig. 10. A. F-N Tunneling
2
The plots of J/EOX vs EOX shown in Fig. 11 and ig. 12
V. IV M EASUREMENT R ESULTS
are obtained by the procedure described in Appendix. C. Using
The procedure used to analyse measured IV data is de- these plots the barrier energy φOX between EC,Si and EC,OX
scribed in Appendix C. is obtained.
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 6

Parameter G2W1 G2W2 G2W3 G2W4 Units


ρ 9.71 1.24 - - Ω.cm
ρs 242.93 42.16 - - Ω/sq
twaf er 400 295 400 295 µm
NA (by ρs ) - 1.12×1016 - - cm−3
ND (by ρs ) 4.46×1014 - - - cm−3
NA (by CV) - 1.37×1016 - 9.13×1015 cm−3
ND (by CV) 1.67×1015 - 1.84×1015 - cm−3
COX 2.02 1.5 6.68 5.28 fF/µm2
tOX 20.2 25.4 33.5 43.6 nm
Breakdown voltage 26.4 -30.4 4 -10.4 V
Threshold voltage -0.7 0.4 -3 -1.8 V
φOX 3.49 2.97 - 0.773 eV
Dit,min 2.5×1015 1.41×1015 1.9×1016 1.38×1016 m−2 eV −1

TABLE XII: Extracted parameters from C-V and I-V measurements

Fig. 8: Fixed charges of different wafers. The figure shows


that the fixed charges of the p-type wafers is less than n-
type wafers. This is because the p-type wafers are annealed
as described in Sec. II-D.

B. Breakdown Voltage
Breakdown voltages of different wafers is shown in Fig. 13
The following parameters were extracted by IV and CV
measurements and they are summarised in Tab. V-B.

A PPENDIX A
A NALYSIS OF CV M EASUREMENTS
The procedure used to analyse the measured data of the
MOS capacitor is detailed here [4, Brews], [10, taur]. . The Fig. 9: Variation of Dit for different values of ψs (for G2W1
algorithm was implemented in Matlab to analyse the data and above and G2W2 below). The figure shows that Dit,min of
obtain the plots. n-type wafer is more than p-type because n-type wafers are
not annealed in inert ambient.
A. Determination of NA,D
1) The capacitance of the measured CV curve is normalised
for area.
5) Using the above value of Wdep,max , Equ. 4 is solved
2) The maximum value of capacitance is assigned COX , it
numerically to obtain the doping concentration of the
assumed that Cacc and Cinv is very large compared to
substrate (It is assumed that the substrate is uniformly
COX .
doped).
3) Minimum capacitance (Cmin ) of CV curves is a series
combination of COX and Cdep . Cdep at inversion can √
be obtained using Equ. 2 with Cg = Cmin . 4Si ln(NA,D /ni )φt
−1 −1
Wdep,max = (4)
Cg = (COX + Cdep,min )−1 (2) qNA,D
4) Wdep is obtained by Equ. 3.
Si Equ. 4 is valid beyond inversion and without deep
Wdep,max = (3) depletion.
Cdep
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 7

Fig. 12: With p-type wafers, SiO2 shows F-N tunneling of


electrons which gives φOX,SiO2 =2.61 eV while F-N tunneling
is for Eu2 O3 gives φOX,SiO2 =0.52 eV.

Fig. 10: Variation of Dit for different values of ψs (for G2W3


above and G2W4 below). The figure shows that Dit,min of
n-type wafers is more than p-type because n-type wafers are
not annealed in inert ambient. In comparison with Fig. 9, for a
given wafer type, Eu2 O3 has higher interface states compared
to SiO2 .

Fig. 13: Breakdown voltages of different wafers, it is seen


that SiO2 breaks drastically at a higher voltage unlike Eu2 O3
where leakage increases slowly. This shows that the quality of
SiO2 is better.

2) Under the assumption that there are no fixed charges,


the ideal mid gap gate voltage is given by Equ. 7.
qNA,D Wmid
Vmid,ideal = φM S + φB + (7)
Fig. 11: With n-type wafers, SiO2 shows F-N tunneling of COX
electrons which gives φOX,SiO2 =3.91 eV while F-N tunneling 3) The difference ∆V = Vmid,ideal − Vmid is the contribu-
is not apparent for Eu2 O3 . tion of fixed oxide charge given in Equ. 8.
Qf = COX ∆V (8)
B. Determination of Qf 4) The curve is shifted by ∆V to remove the effect of Qf .
1) The effect of Qit is zero when EF = Ei . This condition
is used to determine Qf . At mid gap, Wmid is given by C. Determination of Dit
Equ. 5.
√ The presence of Qit will cause the CV to stretch [4, Brews].
2Si ln(NA,D /ni )φt Considering p-type substrate, if the gate voltage is reduced,
Wmid = (5) such that the Fermi level is brought closer to valence band,
qNA,D
the interface state are uncovered. These interface states behave
We can obtain the gate capacitance at mid gap using similar to fixed positive charges causing the CV curve to shift
Equ. 6. left. Similarly, applying a positive voltage at the gate such
−1 −1 −1 that if Ef crosses Ei towards EC , more interface states are
Cg,mid = (COX + Cmid ) (6)
covered which behave like negative fixed charges and cause
where Cmid = Si /Wmid . Using Cg,mid , Vmid is the CV curve to move towards right. The following procedures
obtained from the measured data. is used to determine Dit
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 8

resistance Rleak is the equivalent model for dielectric leakage


and C’ and R’ are the values measured by LCR meter.
1) Accumulaion : CSi → COX since Cacc >> COX
and Rleak is small and finite since the majority carriers
respond to the small signal variation. Equ. 13 can be
approximated as.

0 1
Cacc = 2 + COX (14)
ω 2 COX Rleak
Equ. 14 shows that the measured capacitance C’ is
higher than COX and this value reduces with increase
Fig. 14: (a) and (b) Model of MOS capacitor (c) Components in frequency. This necessitates correction of maximum
resolved by LCR meter capacitance from C-V curve to obtain COX . If the oxide
thickness is small then the leakage is large which implies
that R’ will be smaller. This means that the dependence
1) For each value of Cg at Vit from the measured data, of C’ with frequency increases for lower oxide thickness.
Cdep is obtained using Equ. 2. Surface potential ψs is 2) Inversion : CSi → Cdep since Cinv,dep → 0 and Rleak
calculated using Equ. 9. is large since the minority carriers do not respond to the
√ small signal variation. Equ. 13 can be approximated as.
2Si ψs
Wdep = (9) Cdep COX
qNA,D 0
Cinv = (15)
Cdep + COX
Where Wdep = Si /Wdep .
The Equ. 15 is independent of Rleak .
2) The ideal value of gate voltage is obtained from Equ. 10
using ψs from Equ. 9.
A PPENDIX C
qNA,D Wdep
Vg,ideal = φM S + ψs + (10) A NALYSIS OF IV M EASUREMENTS
COX
The IV measurements are used to determine the break down
3) The difference ∆Vit = Vg,ideal − Vit is the contribution voltage and the barrier of the dielectric. Since the dielectric
of Qit given in Equ. 11. thickness for all the wafers is greater than 10 nm, The IV plots
Qf = COX ∆Vit (11) are analysed for Fowler-Nordheim (F-N) Tunneling. When F-
N tunneling occurs, the current density is given by Equ. 16.
4) A plot of Qit vs ψs and Dit vs ψs is obtained. Where ( √ )
3/2
qDit = dQit /dψs . q 3 EOX
2
4 2m∗φOX
JF N = exp − (16)
8πhφOX 3h̄qEOX
A PPENDIX B Where
VARIATION OF ACCUMULATION CAPACITANCE WITH
VG − VF B − ψs,acc
FREQUENCY EOX = (17)
tOX
The measured capacitance varies with frequency of mea- ψs,acc,p−type = −Eg /2 + φB (18)
surement. This can be explained as follows. The LCR meter
ψs,acc,n−type = Eg /2 − φB (19)
will apply a voltage and determine the current, this current
is resolved into in phase and out of phase components. The 2
A plot of log(J√F N /EOX ) vs 1/EOX gives a straight line
3/2
in phase and out of phase capacitance will be resolved into 4 2m∗φOX
with slope = − 3h̄q [7, Lenzlinger], using which φOX
resistance and capacitance respectively as shown in Fig. 14.
can be determined.
The leakage resistance of the dielectric can be modeled as a
resistor in parallel to COX . The value of resistor depends on
the region of operation of the MOS capacitor. C ONCLUSION
From the models in Fig. 14(b) and Fig. 14(c), the following MOS capacitors were fabricated using SiO2 and Eu2 O3 as
relations can be derived. dielectric materials. The capacitor uses Si substrate with Al
as another terminal. The following conclusion are drawn from
Rleak
R 0 = RC + 2 2 R2 (12) the measurements.
1+ ω COX leak 1) The wafer doping concentration obtained by CV mea-
CSi (1 + ω 2 COX
2 2
Rleak ) surements are comparable to resistivity measurements.
C0 = 2 2 (13) 2) The oxide thickness of SiO2 conforms with the FTP
1 + ω COX Rleak (COX + CSi )
measurement described in Sec. III-B, while the thickness
Here, ω is the angular frequency of measurement, CSi is of Eu2 O3 is higher than the predicted deposited value
the capacitance of the silicon substrate, RC is the contact of 10 nm.
COURSE E3-327,GROUP 2 REPORT NO. 1, SEPTEMBER 2009 9

3) Fixed charges of the p-type wafers is less than n-type


wafers. This is because the p-type wafers are annealed
in inert ambient.
4) Dit of n-type wafers is more than p-type because n-type
wafers are not annealed in inert ambient. For a given
wafer type, Eu2 O3 has higher interface states compared
to thermally grown SiO2 .
5) For large EOX , SiO2 shows F-N tunneling while F-N
tunneling is not apparent for Eu2 O3 .
6) The High-K dielectric capacitor breaks down around
6 V while SiO2 at 28 V. The measured results show
that thermally grown oxide has desirable properties
compared to RF sputtered High-K dielectric oxide of
comparable thickness.

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Technology. John-Wiley & Sons, 1982.
[5] H.R. Huff and D.C. Gilmer. High dielectric constant materials: VLSI
MOSFET applications. Springer Verlag, 2005.
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