BSIMMG

Berkeley Common-Multi-Gate Transistor Model

An Advanced Physical Compact Model for

Nano-FETs
The Berkeley common-multi-gate (BSIMMG) model is developed
to meet the present and future needs of circuit designers employ-
ing advanced nano field-effect transistors (nano-FETs), such as
FinFETs, with a potential to extend the technology roadmap into
sub-25nm region. The BSIMMG model provides maximum versa-
tility regarding multi-gate device geometry, novel materials and
fabrication technology without compromising the ease of use and
simulation efficiency characteristic for the previous generations
of BSIM compact models.

Model Features
• Surface potential based model with extra electrostatic control
from the end-gates
• Optional simplified surface potential solution for further
improvements of the computational efficiency
• Quantum mechanical effects
• Corner-induced effective width reduction
• Short channel effects including threshold voltage roll-off, DIBL,
sub-threshold slope effects and channel length modulation
Different multi-gate architectures in BSIMMG.
• Poly-silicon gate depletion effects
• Mobility degradation
• Hybrid-surface-orientation mobility Benefits of Using BSIMMG
• Velocity saturation
• Versatility in choosing double, triple, quadruple or cylindrical
• Velocity overshoot with source end velocity limit
multi-gate FET structures realized either in bulk silicon or SOI
• The internal and external, bias dependent, series resistance technology
model
• Based on physical surface potential formulations, the BSIMMG
• Gate tunneling current model is continuous, symmetric, scalable and predictive over
• Gate induced drain and source leakage currents (GIDL, GISL) wide range of device parameters
• Impact ionization • The BSIMMG model captures almost all the important physical
• Non-quasi-static effects phenomena specific for nano-FETs
• Parasitic capacitances • Parameters for non-silicon channel devices and high-k metal-
• Junction capacitances and currents gate stack structures
• Temperature effects and self-heating • Adjustable complexity of the extrinsic RC network and surface
• Thermal/flicker/shot noise potential solution to the required model accuracy and simulation
efficiency
• Geometry scaling and binning of the model parameters
• Possibility to switch between the BSIM and PSP based channel
mobility models.
 Silvaco Implementation
• The BSIMMG model is implemented as a part of ModelLib,
Silvaco’s compact SPICE model library. It can be accessed within
SmartSpice in either 4-port bulk or 3-port SOI versions specifying
the model selector LEVEL=51 or LEVEL=52, respectively
• The Silvaco implementation is fully compliant to the original
Berkeley Verilog-A code for the BSIMMG model version 103.0.
• The node collapsing scheme is selected by combination of the
BSIMMG control parameters specified in model and instance
device statements
• Print, plot, save or measure the most important device internal
The choice of SOI or silicon bulk multi-gate technologies in BSIMMG. variables during and after simulation
• The Silvaco implementation is compatible with VZERO and
BYPASS options and parallel architecture algorithms to
achieve greater speed performance as well as DCGMIN
option for improved convergence

Surface potential in BSIMMG in comparison to 3-D simulation.

The third derivative of the BSIMMG drain-source current in the Gummel

symmetry test for different gate voltages.

Normalized capacitance from BSIMMG model (lines) and

TCAD (symbols).

References
1. M. V. Dunga, C.-H. Lin, M. Niknejad, and C. Hu, “BSIMMG: A
Compact Model for Multi-Gate Transistors” in Planar Double-
Gate Transistor, A. Amara, O. Rozeau, eds., Springer, 2009.
2. M. V. Dunga, Ph.D. Dissertation: Nanoscale CMOS Modeling. The transient response of the 17-stage ring oscillator test case .
UC Berkeley, 2007.
3. B. Yu, H. Lu, M. Liu, and Y. Taur, “Explicit continuous models for
double-gate and surrounding-gate Mosfets,” IEEE Transaction on
Electron Devices, vol. 54, no. 10, pp. 2715–2722, October 2007. Rev. 111809_02