Electronics from the Bottom Up: A Preview (July 2007)

The nano-MOSFET:
a brief introduction

Mark Lundstrom

Network for Computational Nanotechnology

Electrical and Computer Engineering
Purdue University
West Lafayette, IN USA
NCN
www.nanohub.org www.nanoHUB.org 1
molecular-scale electronics

Reddy, et al., Science, 315 16 March, 2007

S G D

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the MOSFET as L --> 0

IDS I D =WCoxυ SAT (VGS − VT )

μeff Cox (VGS − VT )VDS

W
ID =
L

VDS

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off-equilibrium transport

υ SAT

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 outline

1) Introduction
2) Conceptual view of nanoscale devices
3) The nano-MOSFET
4) Discussion
5) Conclusions

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 generic model of a nano-device

Gate

EF1 D(E − U SCF ) EF1-qVD

h h
γ1 = γ2 =
τ1 τ2
S. Datta, Quantum Transport: Atom to Transistor, Cambridge, 2005
S. Datta, ‘Concepts in Quantum Transport’
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 quantum transport with dissipation

Gate

[H]
EF1 EF2
device
[Γ1 ] [Γ2 ]
[Σ S ]

Non-equilibrium Green’s Function Approach (NEGF)

S. Datta, Quantum Transport: Atom to Transistor, Cambridge, 2005
S. Datta, “Concepts in Quantum Transport”

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quantum transport with nanoMOS

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 atomistic / quantum effects in CNTFETs

Al EC
Gate
HfO2 EF1
D S
10 nm SiO2

p++ Si EF2
EV
A. Javey, J. Guo, et al., Nature,
424, 654, 2003.
SiyuSiyu
Koswatta,
KoswattaD. Nikonov,
and D. Nikonov
et al., Appl.
Phys.
Appl.
Lett.,
Phys.
87, 2005.
Lett., 89, 021325, 2006

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 physics of transistors

S G D electron energy vs. position

VD= VDD
source drain
SiO2

silicon

E.O.Johnson, RCA Review, 1973

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 physics of transistors

S G D electron energy vs. position

VD= VDD
source drain
SiO2

silicon

E.O.Johnson, RCA Review, 1973

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 filling states in a ballistic MOSFET

EC h2k 2
2m*
E(k)

EF1

E C (0)
EF1-qVD

ε(x)

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 filling states

f (υx, υy)
ε1 vs. x for VGS = 0.5V
Increasing VDS
--->
ε1 (eV)

-10 -5 0 5 10
X (nm) --->

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 carrier velocity vs. VDS

ε1 vs. x for VGS = 0.5V

Increasing VDS
EC (eV) --->

Increasing VDS

-10 -5 0 5 10
X (nm) --->

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 velocity saturation in a ballistic MOSFET

ε1 vs. x for VGS = 0.5V

--->
Increasing VDS
υ(0)

υinj (107 cm/s)

--->
ε1 (eV)

-10 -5 0 5 10
X (nm) ---> VDS --->

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υ (0) → υ%T 15
 filling states in a ballistic MOSFET

(
Cox (VG − VT ) = q n + + n − )
EC
( )
h2k 2
2m* I D = qW υ + n + − υ − n −
E(k)

EF1

E C (0)
EF1-qVD

ε(x)

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 see: the
FETToy on www.nanoHUB.org
ballistic MOSFET

I DS ( on ) = W C G υ%T (VGS − VT )

IDS
2q 2
(V )
α
≈M G
− VT
h
1 ≤ α ≤ 1.5

VDS

K. Natori, JAP, 76, 4879, 1994. www.nanoHUB.org 17

 scattering

Gate

EF1 D(E − U SCF ) EF1-qVD

l
τ 1 = τ 2 = l 2D
2

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 where scattering matters (the most)

ε1 vs. x for VGS = 0.5V

Increasing VDS
≈ LL
ll<<
--->
--->
(eV)
ε11 (eV)

-10
-10 -5
-5 00 55 10
10
X (nm) --->

See: P. Palestri, R. Clerc, D. www.nanoHUB.org

Esseni, L. Lucci, and L. Selmi, 2006 IEDM.
19
 outline

1) Introduction
2) Conceptual view of nanoscale devices
3) The nano-MOSFET
4) Discussion
5) Conclusions

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 traditional MOSFET theory

VGGS(V
[1 − ⎛F11/ 2−(ηe−FqV
VT−)υV%T )υT ⎜ 2)
DS
F ⎞(η ) ]
/ kB T
ID = G (C
=W −GS 1/ 2 F1
I DWC
[ 0 F2)
1 ⎝
+ 1F +(ηe − qV
F (η⎟⎠ ) ]
DS / k B T
0 F1

υT
ID = W CG (VGS − VT )VDS
k BT q

⎛ υT L ⎞
⎜⎝ k T q ⎟⎠ CG (VGS − VT )VDS
W
ID =
L q tt
B
μB = *
m
I D = μ BCG (VGS − VT )VDS
W L
tt =
L υ th
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 connection to traditional theory

1 1 1
′ CG (VGS − VT )VDS
W
I D = μeff = +
L μeff
′ μeff μ B

μB =~ L m*

ballistic limit occurs when: μeff >> μ B

for silicon with L = 10 nm: μeff >> 40 cm 2 /V-s

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 S/D tunneling

4) 3)

2) 1)

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from M. Luisier, ETH Zurich
 65 nm technology vs. ballistic limit

Ballistic (RSD = 0)

Ballistic (RSD = 180)

Measured

S. Tyagi et al., IEDM Tech. Dig., p. 1070-1072, 2005

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 role of the quantum contact resistance

h 12.8KΩ
RMIN = 2 =
2q M M IDS

W 1μm
M =2 ≈4 ≈ 400
(λF 2 ) 0.010
L
RCH =
RMIN ≈ 30 Ω − μm W μeff Cox (VGS − VT )

(T = 0K ) VDS

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 additional considerations

1) Mathematical formulation of the ballistic model including 2D

electrostatics, multiple subbands, various channel materials, etc.

2) Physics of scattering.

3) Where does the voltage drop? What is the quasi-Fermi level?, etc.

4) Behavior with channel length.

5) Where does present-day technology stand?

6) Application to nanowires, nanotubes, …

7) What do detailed, quantum-scale simulations have to say?

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 outline

1) Introduction
2) Conceptual view of nanoscale devices
3) The nano-MOSFET
4) Discussion
5) Conclusions

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 conclusions

1) The bottom-up perspective provides a new and

useful conceptual and computational foundation for
electronics at the nanoscale.

2) CMOS device models can benefit from insights and

approaches from this new approach.

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 for more information

Nanoscale Transistors, by Jing Guo and Mark Lundstrom, Springer, 2006

www.nanoHUB.org:

ƒ Nanoscale Transistors (online course in ‘nanocurriculum’)

ƒ Ballistic Nanotransistors (in ‘learning modules’)
ƒ FETToy or nanoMOS (online simulation tools)
ƒ or search ‘lundstrom’

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