Acer Aspire E5-575 735T DAZAAMB16E0 Quanta ZAA-x16 - Ironman - SK (ZAA) & Captain - SK (ZAAA) - 2016-0203-C-Gerber

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ZAA Serials SKL ULT SYSTEM BLOCK DIAGRAM

BOM
VRAM IV@ : iGPU
D
GPU GDDR5/ 1.35V EV@ : Optimus
D
SKY LAKE ULT 15W PCIE1-4 N16S-GTR P19~20 KBL15@ :For Key/B 15"
MCP 1356pins PCI-E x4 KBL17@ : For Key/B 17"
TX/RX X4 N16S-GT1 KBL@ : Key/B backlight
DDR4-SODIMM CHA Dual Channel DDR4 IMC TPM@ : TPM
X'TAL 27MHz
P12 GS@ :G-SENSOR
CLK TDI@ : Touch PAD I2C
P14~P18
EDP
TSU@ : Toutch Screen (USB)
DDR4-SODIMM CHB eDP TSI@ : Toutch Screen (I2C)
P13 X4 eDP Conn. P23
GT3@ : GT3 CPU
NAC@ : Non IOAC
DC+GT3e DDI2 RTD2166
VGA Conn. IOAC@ : For IOAC
42 mm X 24 mm DP-2 X2 P23 SP@ : Special part
P22
SATA0 GC6@ : for GC6
SATA - HDD Main & 2'nd
P27 SATA +5V_S5 FPD@ : for 8 Pin Finger/P.
TPS25810 GKA@ : For kill GPU A-chanle.
SATA ODD SATA1 P21 GKB@ : For kill GPU B-chanle.
P27 USB3.0/2.0 Type-C connector
ROM@ : For SKL or KBL
PTN36242 P21 TYC@ : For Type-C
C
P21 C
Integrated PCH
USB2-9
POA DDI1
DP-1 PTN3366BS HDMI Conn.
Finger/ print P27 X4 P24
P24
USB3-1 & USB3-2

USB3.0/2.0
USB2-7 USB2-1 & USB2-2 USB3 Port MB side
CCD(Camera) USB3 port 2
P23 USB3 port 1
USB2.0 PCI-E x1 M.2 SSD P30
USB2-6
Touch Screen X1 P28
P23
CLK
USB2-5
Blue Tooth PCIE-6
P30 PCI-E x2 X1 MINI CARD
I/O board USB2-4 WLAN+BT
X'TAL P28
32.768KHz
USB2 IO*2 I/O Board Conn. USB2-3 Cardreader
P28 PCIE-5 LAN_CRD_COMBO CONN. 2in 1
P25
RTL8411
DMIC_CLK0 X'TAL 24MHz X1
B DMIC_DATA0 10/100/1G P25 B
CLK
RJ45
Small/B Audio jack P6 RTC P25
BATTERY
Azalia P2~P10 I2C_0
IHDA
SPI X'TAL 25MHz
D-MIC LPC
SPI ROM
P26 8M+4M P7
EC
Int. D-MIC ALC255 TPM(option) BQ24780S G5316RZ1D Thermal Protection
AUDIO CODEC IT8987 P27 Batery Charger P33 +1.2VSUS P37 P41
P26 P31
Discharger
TPS51225R ISL95859HRTZ-T UP1658RQKF

+3V/+5V P34 +VCORE/VCCSA/VCCGT +VGPU_CORE P42
P38-39
RT8237CZQW RT8068AZQW
+1V_S5 P35 ISL95808 P43
+1.05V_GFX/+3V_GFX
VCCSA P39 +1.5V_GFX
K/B HALL
Speaker*2 LED BL Touch PAD Fan Driver NB681GD-Z
P26 P29
K/B Con. SENSOR (Fan signal)
A
P29 Con. P29 P29 P23 P29 +VCCOPC/+VCCEOPIOP36
A
CH6221M9A00 CAP CHIP 22U 6.3V(+-20%,X5R,0805)H1.25 remove TPM from SKL , KBL keeps it.---- for B2
CH6221M9A01 CAP CHIP 22U 6.3V(+-20%,X5R,0805)H1.25 add POA FUNCTION, , add 0hm*4 between EC to POA conn & server VST * 7 pcs
CH6221M9A02 CAP CHIP 22U 6.3V(+-20%,X5R,0805)H1.25 POA ( change FP power from 3v to 5v )
Quanta Computer Inc.
P7
PROJECT : ZAA
Size Document Number Rev
1A
Block Diagram
Date: Friday, February 05, 2016 Sheet 1 of 48
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AJ0QKKQVT00 -->CPU(1356P)KBL 1.7G QKKQ(FCBGA) -----no use

AJ0QKKSUT00 -->CPU(1356P)KBL 2.4G QKKS(FCBGA)
AJ0QKJWQT02 -->CPU(1356P)KBL-U 2.6G QKJW(BGA) QCI PN ---- C-test
i3-6100U AJSR2EUUT07
i5-6200U AJSR2EYUT07 Skylake ULT (DISPLAY,eDP)
i7-6500U AJSR2EZRT07
i5-6267U AJSR2JK8T02--no use
SKL_ULT
U35A
D D
<24> INT_HDMITX2N
E55 C47 EDP_TXN0 <23>
F55 DDI1_TXN[0] EDP_TXN[0] C46
<24> INT_HDMITX2P
E58 DDI1_TXP[0] EDP_TXP[0] D46
EDP_TXP0 <23> eDP Panel +3V
HDMI
<24> INT_HDMITX1N DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 <23>
F58 C45
<24> INT_HDMITX1P DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 <23>
<24> INT_HDMITX0N
F53 A45 EDP_TXN2 <23>
G53 DDI1_TXN[2] EDP_TXN[2] B45 DDI2_AUXN R533 *100K_4
<24>
<24>
INT_HDMITX0P
INT_HDMICLK-
F56 DDI1_TXP[2] EDP_TXP[2] A47
EDP_TXP2
EDP_TXN3
<23>
<23>
For 4K
G56 DDI1_TXN[3] EDP_TXN[3] B47 DDI2_AUXP R532 *100K_4
<24> INT_HDMICLK+ DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 <23>
<22> DDI2_TXN0
C50 E45 EDP_AUXN <23>
D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45
<22> DDI2_TXP0 DDI2_TXP[0] EDP_AUXP EDP_AUXP <23>
<22> DDI2_TXN1
C52
D52 DDI2_TXN[1] B52 DP_UTIL R546 *0_4 PCH_BRIGHT
<22> DDI2_TXP1
A50 DDI2_TXP[1] EDP_DISP_UTIL Change for leakage
R553 *0_4
To RTS2166 iC TP4395
B50 DDI2_TXN[2] G50 +3V_S5
TP4394 D51 DDI2_TXP[2] DDI1_AUXN F50
TP4392 C51 DDI2_TXN[3] DDI1_AUXP E48 DDI2_AUXN DDI2_AUXN <22>
TP4393 DDI2_TXP[3] DDI2_AUXN F48 DDI2_AUXP DDI2_AUXP <22>
DDI2_AUXP G46 CRT_CLK R577 *2.2K_4 +3V
DISPLAY SIDEBANDS DDI3_AUXN F46 CRT_DATA R152 2.2K_4
L13 DDI3_AUXP
<24> HDMI_DDCCLK_SW
L12 GPP_E18/DDPB_CTRLCLK +3V_S5 L9 SIO_EXT_SCI# R781 20K/F_4
<24> HDMI_DDCDATA_SW GPP_E19/DDPB_CTRLDATA +3V_S5 +3V_S5 GPP_E13/DDPB_HPD0 INT_HDMI_HPD <24>
L7 PCH_DP_HPD
CRT_CLK N7
+3V_S5 GPP_E14/DDPC_HPD1 L6 PCH_TypeC_UPFb#
PCH_DP_HPD <22>
PCH_TypeC_UPFb# R11251 20K/F_4
CRT_DATA N8 GPP_E20/DDPC_CTRLCLK +3V_S5 +3V_S5 GPP_E15/DDPD_HPD2 N9 R571 *short_4 SIO_EXT_SCI#
PCH_TypeC_UPFb# <21> +3V_S5
GPP_E21/DDPC_CTRLDATA +3V_S5 +3V_S5 GPP_E16/DDPE_HPD3 SIO_EXT_SCI# <31> For Type-C change
L10 EDP_HPD EDP_HPD <23>
N11 +3V_S5 GPP_E17/EDP_HPD
TP4390 N12 GPP_E22/DDPD_CTRLCLK +3V_S5 R12
<27> PCH_ODD_EN GPP_E23/DDPD_CTRLDATA +3V_S5 EDP_BKLTEN PCH_BLON <23>
R11 PCH_BRIGHT
EDP_BKLTCTL PCH_BRIGHT <23>
+VCCIO 24.9/F_4 R154 EDP_RCOMP E52 U13 EDP_VDD_EN <23>
EDP_RCOMP <PART_SYM_NUM> EDP_VDDEN
eDP_RCOMP PCH_DP_HPD R564 100K_4
SP@SKL_ULT/BGA
EDP_HPD R563 100K_4
Trace length < 100 mils
C
Trace width = 20 mils C
Trace spacing = 25 mils 100k pull-down on PCH side
+1V_VCCST
1K_4 R529 CPU_THRMTRIP# H_PECI (50ohm)

Route on microstrip only
49.9/F_4 R788 CATERR#
Spacing >18 mils SKL_ULT
U35D
Trace Length: 0.4~6.125 iches
CATERR# D63
TP65 A54 CATERR#
H_PECI
<31> H_PECI PECI
H_PROCHOT# R531 499/F_4 H_PROCHOT#_R C65
<31,32,37> H_PROCHOT# PROCHOT# JTAG
THRMTRIP# R530 100/F_4 CPU_THRMTRIP# C63
Avoid 125Mhz A65 THERMTRIP# B61 XDP_TCK0
SKTOCC# PROC_TCK D60 XDP_TDI_CPU PCH JTAG MP remove(Intel)
CPU MISC PROC_TDI
XDP_BPM#0 C55 A61 XDP_TDO_CPU JTAG_TCK,JTAG_TMS
+VCCIO TP89 D55 BPM#[0] PROC_TDO C60
BPM#[0:7] XDP_BPM#1 XDP_TMS_CPU
TP90
XDP_BPM#2 B54 BPM#[1] PROC_TMS B59 PCH_TRST#
Trace Length < 9000mils +1V_VCCST
Trace Length 1~6 inches TP64
XDP_BPM#3 C56 BPM#[2] PROC_TRST# Change to +1V_VCCST 11/6
Length match < 300 mils TP62 BPM#[3] B56
R465 1K_4 H_PROCHOT# XDP_TCK1
A6 PCH_JTAG_TCK D59 XDP_TDI R796 *short_4 XDP_TDI_CPU
GPP_E3/CPU_GP0 +3V_S5 PCH_JTAG_TDI
A7 +3V_S5 A56 XDP_TDO R795 *short_4 XDP_TDO_CPU
BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 XDP_TMS R797 *short_4 XDP_TMS_CPU XDP_TDO R559 51_4
<4> DGPU_PW_CTRL# GPP_B3/CPU_GP2 +3V_S5 PCH_JTAG_TMS
AY5 +3V_S5 C61 PCH_TRST# XDP_TMS R514 51_4
GPP_B4/CPU_GP3 PCH_TRST# A59 XDP_TCK0 XDP_TDI R515 51_4
JTAGX If use Intel DCI USB 3.0 fixture need to short
SM_RCOMP[0:2] R635 49.9/F_4 AT16 1. XDP_TDO <--> XDP_TDO_CPU
R646 49.9/F_4 AU16 PROC_POPIRCOMP XDP_TCK0 R513 *1K_4
Trace length < 500 mils PCH_OPIRCOMP 2. XDP_TDI <--> XDP_TDI_CPU
R158 49.9/F_4 H66
Trace width = 12~15 mils H65 OPCE_RCOMP 3. XDP_TMS <--> XDP_TMS_CPU
R162 49.9/F_4
Trace spacing = 20 mils OPC_RCOMP
<PART_SYM_NUM>
XDP_TCK0 R558 51_4
SP@SKL_ULT/BGA
B XDP_TCK1 R537 *51_4 B
PCH_TRST# R534 51_4
2/16
,XDP_TCK1,XDP_TMS
don't need pull up or pull down
5/29 XDP_TCK0 R558 Stuff
+1V_VCCST
CPU thermal trip
+VCCIO <5,8,32,34,37,40>
3
+1V_VCCST <5,8,9,37>
IMVP_PWRGD_3V 2 Q31
U33 +1V_VCCST +3V
FDV301N
1 5
NC VCC
1
1
R485
2 C628 10K_4 +1V_VCCST
<37> IMVP_PWRGD A *0.1u/16V_4 R74
2
A 1K_4 A
3 4 IMVP_PWRGD_3V
GND Y IMVP_PWRGD_3V <8>
R488
2
*74AUP1G07GW *1K_4
THRMTRIP# 1 3
SYS_SHDN# <31,33,40>
R478 *0_4 Q5 MMBT3904-7-F

PROJECT : ZAA
1A
Skylake 1/4 (DDI/eDP)
WWW.AliSaler.Com 5 4 3 2
Date: Friday, February 05, 2016
1
Sheet 2 of 48
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Change Data and DQS to interleave.
SKL ULT (DDR3L) SKL ULT (DDR3L)

SKL_ULT
<12> M_A_DQ[63:0] U35B SKL_ULT
<13> M_B_DQ[63:0] U35C
D AU53 D
DDR0_CKN[0] M_A_CLK0# <12>
M_A_DQ0 AL71 AT53 M_A_CLK0 <12>
M_A_DQ1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 M_B_DQ0 AF65 AN45
DDR0_DQ[1] DDR0_CKN[1] M_A_CLK1# <12> DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] M_B_CLK0# <13>
M_A_DQ2 AN68 AT55 M_A_CLK1 <12> M_B_DQ1 AF64 AN46 M_B_CLK1# <13>
M_A_DQ3 AN69 DDR0_DQ[2] DDR0_CKP[1] M_B_DQ2 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45
DDR0_DQ[3] DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] M_B_CLK0 <13>
M_A_DQ4 AL70 BA56 M_A_CKE0 <12> M_B_DQ3 AK64 AP46 M_B_CLK1 <13>
M_A_DQ5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 M_B_DQ4 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1]
DDR0_DQ[5] DDR0_CKE[1] M_A_CKE1 <12> DDR1_DQ[4]/DDR0_DQ[20]
M_A_DQ6 AN70 AW56 M_B_DQ5 AF67 AN56 M_B_CKE0 <13>
M_A_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 M_B_DQ6 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55
DDR0_DQ[7] DDR0_CKE[3] DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] M_B_CKE1 <13>
M_A_DQ8 AR70 M_B_DQ7 AK66 AN55
M_A_DQ9 AR68 DDR0_DQ[8] AU45 M_B_DQ8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDR0_DQ[9] DDR0_CS#[0] M_A_CS#0 <12> DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
M_A_DQ10 AU71 AU43 M_A_CS#1 <12> M_B_DQ9 AF68
M_A_DQ11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 M_B_DQ10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDR0_DQ[11] DDR0_ODT[0] M_A_ODT0_DIMM <12> DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] M_B_CS#0 <13>
M_A_DQ12 AR71 AT43 M_A_ODT1_DIMM <12> M_B_DQ11 AH68 AY42 M_B_CS#1 <13>
M_A_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[1] M_B_DQ12 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42
DDR0_DQ[13] DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] M_B_ODT0_DIMM <13>
M_A_DQ14 AU70 BA51 M_A_A5 M_B_DQ13 AF69 AW42 M_B_ODT1_DIMM <13>
M_A_DQ15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 M_A_A9 M_B_DQ14 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
M_A_DQ16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 M_A_A6 M_B_DQ15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 M_B_A5
M_A_DQ17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 M_A_A8 M_B_DQ16 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 M_B_A9
M_A_DQ18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52M_A_A7 M_B_DQ17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 M_B_A6
M_A_DQ19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 M_B_DQ18 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 M_B_A8
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] M_A_BG#0 <12> DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
M_A_DQ20 BA65 AW54M_A_A12 M_B_DQ19 AN65 AP48 M_B_A7
M_A_DQ21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 M_A_A11 M_B_DQ20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52
DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] M_B_BG#0 <13>
M_A_DQ22 BA63 BA55 M_A_ACT# <12> M_B_DQ21 AP66 AN50 M_B_A12
M_A_DQ23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 M_B_DQ22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 M_B_A11
DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] M_A_BG#1 <12> DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
M_A_DQ24 BA61 M_B_DQ23 AU65 AN53 M_B_ACT# <13>
M_A_DQ25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 M_A_A13 M_B_DQ24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52
DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] M_B_BG#1 <13>
M_A_DQ26 BB59 AU48 M_A_CAS# <12> M_B_DQ25 AU61
M_A_DQ27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 M_B_DQ26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 M_B_A13
DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] M_A_WE# <12> DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
M_A_DQ28 BB61 AU50 M_A_RAS# <12> M_B_DQ27 AN60 AY43 M_B_CAS# <13>
M_A_DQ29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 M_B_DQ28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44
DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] M_A_BA#0 <12> DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] M_B_WE# <13>
M_A_DQ30 BA59 AY51 M_A_A2 M_B_DQ29 AP61 AW44 M_B_RAS# <13>
C M_A_DQ31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 M_B_DQ30 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 C
DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_A_BA#1 <12> DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M_B_BA#0 <13>
M_A_DQ32 AY39 AT50 M_A_A10 M_B_DQ31 AU60 AY47 M_B_A2
M_A_DQ33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 M_A_A1 M_B_DQ32 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] M_B_BA#1 <13>
M_A_DQ34 AY37 AY50 M_A_A0 M_B_DQ33 AT40 AW46M_B_A10
M_A_DQ35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 M_A_A3 M_B_DQ34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 M_B_A1
M_A_DQ36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 M_A_A4 M_B_DQ35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 M_B_A0
M_A_DQ37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] M_B_DQ36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 M_B_A3
M_A_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 M_B_DQ37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 M_B_A4
DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] M_A_DQS#0 <12> DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
M_A_DQ39 BB37 AM69 M_A_DQS0 <12> M_B_DQ38 AP37
M_A_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 M_B_DQ39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66
DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] M_A_DQS#1 <12> DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] M_B_DQS#0 <13>
M_A_DQ41 AW35 AT70 M_A_DQS1 <12> M_B_DQ40 AT33 AH65 M_B_DQS0 <13>
M_A_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 M_B_DQ41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69
DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] M_A_DQS#2 <12> DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] M_B_DQS#1 <13>
M_A_DQ43 AW33 AY64 M_A_DQS2 <12> M_B_DQ42 AU30 AG70 M_B_DQS1 <13>
M_A_DQ44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 M_B_DQ43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66
M_A_DQ45 BA35 BA60 M_A_DQS3 <12> M_B_DQ44 AR33 AR65 M_B_DQS2 <13>
M_A_DQ46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 M_B_DQ45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61
M_A_DQ47 BB33 AY38 M_A_DQS4 <12> M_B_DQ46 AR30 AR60 M_B_DQS3 <13>
M_A_DQ48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 M_B_DQ47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38
M_A_DQ49 AW31 BA34 M_A_DQS5 <12> M_B_DQ48 AU27 AR38 M_B_DQS4 <13>
M_A_DQ50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 M_B_DQ49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32
DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] M_A_DQS#6 <12> DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] M_B_DQS#5 <13>
M_A_DQ51 AW29 AY30 M_A_DQS6 <12> M_B_DQ50 AT25 AR32 M_B_DQS5 <13>
M_A_DQ52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 M_B_DQ51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25
DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] M_A_DQS#7 <12> DDR1_DQ[51] DDR1_DQSN[6] M_B_DQS#6 <13>
M_A_DQ53 BA31 BA26 M_A_DQS7 <12> M_B_DQ52 AP27 AR27 M_B_DQS6 <13>
M_A_DQ54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] M_B_DQ53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22
DDR0_DQ[54]/DDR1_DQ[38] DDR1_DQ[53] DDR1_DQSN[7] M_B_DQS#7 <13>
M_A_DQ55 BB29 AW50 M_A_ALERT# M_A_ALERT# <12> M_B_DQ54 AN25 AR21 M_B_DQS7 <13>
M_A_DQ56 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 M_B_DQ55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR M_A_PARITY <12> DDR1_DQ[55]
M_A_DQ57 AW27 M_B_DQ56 AT22 AN43 M_B_ALERT# M_B_ALERT# <13>
M_A_DQ58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 M_B_DQ57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43
DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA +VREF_CA_CPU DDR1_DQ[57] DDR1_PAR M_B_PARITY <13>
M_A_DQ59 AW25 AY68 +VREFDQ_SA_M3 M_B_DQ58 AU21 AT13 CPU_DRAMRST#
M_A_DQ60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 TP4344 For GDDR5 remove M_B_DQ59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP_0
DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +VREFDQ_SB_M3 DDR1_DQ[59] DDR_RCOMP[0]
M_A_DQ61 BA27 M_B_DQ60 AN22 AT18 SM_RCOMP_1
M_A_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CTRL M_B_DQ61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2
B M_A_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL +3V_S5 M_B_DQ62 AP21 DDR1_DQ[61] DDR_RCOMP[2] B
DDR0_DQ[63]/DDR1_DQ[47] M_B_DQ63 AN21 DDR1_DQ[62] DDR CH - B
<PART_SYM_NUM> +1.2VSUS DDR1_DQ[63] <PART_SYM_NUM>
SP@SKL_ULT/BGA
SP@SKL_ULT/BGA
R682
2
M_A_A[13:0] *100K_4 M_B_A[13:0]

M_A_A[13:0] <12> M_B_A[13:0] <13>
R621 *10K_4 1 3 DDR_VTTT_PG_CTRL <36>
Q35
*DTC144EU
For Sx ,stuff Q? in DDR_VTT_CNTL

DRAM COMP
+3V_S5 <2,4,6,7,8,9,11,21,25,27,28,29,31,33,35,36,41>
+1.2VSUS <5,12,13,36>
SM_RCOMP_0 120/F_4 R685

DRAMRST SM_RCOMP_1 80.6/F_4 R678
+1.2VSUS
1 SM_RCOMP_2 100/F_4 R681
A R679 A
470_4
CPU DRAM
2
CPU_DRAMRST# R670 *short_4 DDR3_DRAMRST# <12,13>
1
C750
*0.1u/16V_4
2
PROJECT : ZAA
1A
Skylake 2/3 (DDR3 I/F)
5 4 3 2 1
5 4 3 2 1
SKL ULT (SIDEBAND ) GPIO

H_PECI (50ohm)
Route on microstrip only SKL_ULT
Spacing >18 mils U35F
Trace Length: 0.4~6.125 iches Add GPU Power Control Siganls LPSS ISH
H_PWRGOOD (50ohm) VGPU_EN AN8 +3V_S5

<41> VGPU_EN GPP_B15/GSPI0_CS# P2
Trace Length: 1~11.25 inches <14> DGPU_HOLD_RST# DGPU_HOLD_RST# AP7 +3V_S5 +3V_S5 GPP_D9
GPP_B16/GSPI0_CLK P3
DGPU_PWR_EN AP8 +3V_S5 +3V_S5 GPP_D10
<42> DGPU_PWR_EN GPP_B17/GSPI0_MISO P4
GSPI0_MOSI AR7 +3V_S5 +3V_S5 GPP_D11
D GPP_B18/GSPI0_MOSI P1 D
+3V_S5 GPP_D12
AM5 +3V_S5
<16> DGPU_PWROK GPP_B19/GSPI1_CS# M4
<14,17> GC6_FB_EN GC6_FB_EN AN7 +3V_S5 +3V_S5 GPP_D5/ISH_I2C0_SDA
GPP_B20/GSPI1_CLK N3
AP5 +3V_S5 +3V_S5 GPP_D6/ISH_I2C0_SCL
+3V_S5 <17> DGPU_EVENT# GPP_B21/GSPI1_MISO
GSPI1_MOSI AN5 +3V_S5
GPP_B22/GSPI1_MOSI N1
PU 2.2K for touch pad I2C bus(400 KHz) +3V_S5 GPP_D7/ISH_I2C1_SDA N2
AB1 +3V_S5 +3V_S5 GPP_D8/ISH_I2C1_SCL
<29> ACCEL_INTA GPP_C8/UART0_RXD
2.2K_4 R167 I2C0_SDA Touch PAD <27> ODD_PRSNT# AB2 +3V_S5
GPP_C9/UART0_TXD AD11
2.2K_4 R166 I2C0_SCL TPD_INT#_D W4 +3V_S5 +1.8V_S5 GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_C10/UART0_RTS# AD12
*2.2K_4 R165 I2C1_SDA <23> TP_INT_PCH AB3 +3V_S5 +1.8V_S5 GPP_F11/I2C5_SCL/ISH_I2C2_SCL
*2.2K_4 R169 I2C1_SCL GPP_C11/UART0_CTS#
Touch Screen UART2_RXD AD1
GPP_C20/UART2_RXD +3V_S5 U1 Reserve UART FFC connector for Win 7 debug
UART2_TXD AD2 +3V_S5 +3V_S5 GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_C21/UART2_TXD U2 +3V_S5
UART2 for RMT UART2_RTS# AD3 +3V_S5 +3V_S5 GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_C22/UART2_RTS# U3
UART2_CTS# AD4 +3V_S5 +3V_S5 GPP_D15/ISH_UART0_RTS#
GPP_C23/UART2_CTS# U4
+3V_S5 GPP_D16/ISH_UART0_CTS#/SML0BALERT#
+3V GPU Control PU/PD I2C0_SDA U7
AC1
UART2_RXD R275 *49.9K/F_4
<29> I2C0_SDA GPP_C16/I2C0_SDA
+3V_S5 +3V_S5 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
Touch PAD I2C0_SCL U6 +3V_S5 +3V_S5 GPP_C13/UART1_TXD/ISH_UART1_TXD UART2_TXD R280 *49.9K/F_4
<29> I2C0_SCL GPP_C17/I2C0_SCL AC3
+3V_S5 GPP_C14/UART1_RTS#/ISH_UART1_RTS# UART2_RTS# R283 *49.9K/F_4
AB4
*10K_4 R220 VGPU_EN *10K_4 R196 I2C1_SDA U8 +3V_S5 +3V_S5 GPP_C15/UART1_CTS#/ISH_UART1_CTS# UART2_CTS# R290 *49.9K/F_4
<23> I2C1_SDA GPP_C18/I2C1_SDA
Touch Screen I2C1_SCL U9 +3V_S5
<23> I2C1_SCL GPP_C19/I2C1_SCL AY8
*10K_4 R257 DGPU_PWR_EN *100K_4 R256 +3V_S5 GPP_A18/ISH_GP0 BA8
AH9 +1.8V_S5 +3V_S5 GPP_A19/ISH_GP1
GPP_F4/I2C2_SDA BB7
*GC6@10K_4 R204 GC6_FB_EN *GC6@10K_4 R199 AH10 +1.8V_S5 +3V_S5 GPP_A20/ISH_GP2
GPP_F5/I2C2_SCL BA7
+3V_S5 GPP_A21/ISH_GP3 AY7
1A-1 20131015 For GC6 NV DG GC6_FB_EN PD. AH11 +1.8V_S5 +3V_S5 GPP_A22/ISH_GP4
GPP_F6/I2C3_SDA AW7
AH12 +1.8V_S5 +3V_S5 GPP_A23/ISH_GP5
+3V GPP_F7/I2C3_SCL AP13
+3V_S5 GPP_A12/BM_BUSY#/ISH_GP6
AF11 +1.8V_S5 UART2_RXD
AF12 GPP_F8/I2C4_SDA UART2_TXD TP4354
GPP_F9/I2C4_SCL +1.8V_S5 TP4355
R208 10K_4 DGPU_HOLD_RST# UART2_RTS#
<PART_SYM_NUM> UART2_CTS# TP4356
TP4357
SP@SKL_ULT/BGA
high UMA Only

C DGPU_PW_CTRL# GPU power is control by PCH SKL_ULT
C
U35G
low GPIO (Discrete, SG or Optimize)
HDA C742 *10p/50V_4 AUDIO
+3V R667 33_4 HDA_SYNC_R BA22

<26> PCH_AZ_CODEC_SYNC HDA_SYNC/I2S0_SFRM
R644 33_4 HDA_BCLK_R AY22
<2> DGPU_PW_CTRL# <26> PCH_AZ_CODEC_BITCLK HDA_BLK/I2S0_SCLK
<26> PCH_AZ_CODEC_SDOUT R645 33_4 HDA_SDO_R BB22 SDIO/SDXC
BA21 HDA_SDO/I2S0_TXD
<26> PCH_AZ_CODEC_SDIN0 HDA_SDI0/I2S0_RXD
R127 EV@100K_4 DGPU_PW_CTRL# R115 *IV@1K_4 AY21 +3V_S5 AB11
DGPU_PWROK R110 *10K_4 R660 33_4 HDA_RST#_R AW22 HDA_SDI1/I2S1_RXD SD GPI GPP_G0/SD_CMD AB13
<26> PCH_AZ_CODEC_RST# HDA_RST#/I2S1_SCLK
+3V_S5 SD GPI GPP_G1/SD_DATA0
J5 +3V_S5 AB12
DGPU_PWROK PD on GPU side C739 AY20 GPP_D23/I2S_MCLK +3V_S5
+3V_S5 SD GPI GPP_G2/SD_DATA1 W12
22P/50V_4 AW20 I2S1_SFRM SD GPI GPP_G3/SD_DATA2 W11
I2S1_TXD +3V_S5 SD GPI GPP_G4/SD_DATA3
+3V_S5 W10
AK7
SD GPI GPP_G5/SD_CD# W8
GPP_F1/I2S2_SFRM
+1.8V_S5 +3V_S5 SD GPI GPP_G6/SD_CLK
AK6 +1.8V_S5 +3V_S5 W7
VGA H/W Setup ESD request 2015/12/21 AK9 GPP_F0/I2S2_SCLK SD GPI GPP_G7/SD_WP
DGPU_PW_CTRL#
GPP_F2/I2S2_TXD
+1.8V_S5
Signal Menu AK10 +1.8V_S5 BA9
GPP_F3/I2S2_RXD +3V_S5 GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
UMA Only 1 UMA Hidden UMA boot +3V_S5 GPP_A16/SD_1P8_SEL
DMIC_CLK0_R H5 AB7 200/F_4 R174
TP4372 DMIC_DATA0_R D7 GPP_D19/DMIC_CLK0 +3V_S5 SD_RCOMP
SG/Optimise 0 GPU Hidden GPU boot TP4373 GPP_D20/DMIC_DATA0 +3V_S5
D8 AF13
Strapping C8 GPP_D17/DMIC_CLK1 +3V_S5 +1.8V_S5 GPP_F23
SPKR R624 *20K/F_4 GPP_D18/DMIC_DATA1 +3V_S5
<26> SPKR SPKR AW5
545659-103 GPP_B14/SPKR +3V_S5
<PART_SYM_NUM>
Skylake-U Strapping Table SP@SKL_ULT/BGA Touchpad INT +3V_S5
Pin Name Strap description Sampled Configuration note TPD_INT#_D TDI@10K_4 R177
0 = *Disable Top Swap (iPD 20K) R625 *1K_4 SPKR
B GPP_B14 (SPKR) Top-Block Swap override PCH_PWROK +3V B
1 = Enable Top Swap Mode
0 = *Disable No Reboot (iPD 20K) GSPI0_MOSI +3V
GPP_B18 No reboot PCH_PWROK +3V R619 *1K_4
(GSPI0_MOSI) 1 = Enable No Reboot Mode S5 S5
2
0 = *Disable Intel ME Cryp to TLS(iPD 20K) R160 *10K_4 1 3 TPD_INT#_D
GPP_C2 TLS Confidentiality RSMRST# +3V_S5 SMBALERT# <7> <29,31> TPD_INT#
(SMBALERT#) 1 = Enable Intel ME Cryp to TLS
Q20
0 = *SPI (iPD 20K) *TDI@2N7002K
GPP_B22 Boot BIOS Strap Bit (BBS) PCH_PWROK +3V R207 *1K_4 GSPI1_MOSI
1 = LPC R164 *short_4
(GSPI1_MOSI)
0 = *LPC is selected for EC (iPD 20K)
GPP_C5 eSPI or LPC RSMRST# +3V_S5 R586 *1K_4 SML0ALERT# <7>
(SML0ALERT#) 1 = eSPI selected for EC
SPI0_MOSI Reserved RSMRST# (iPU 15 ~ 40K)
SPI0_MISO Reserved RSMRST# (iPU 15 ~ 40K)
GPP_B23
(SML1ALERT# Reserved RSMRST# (iPD 20K)
+3V_S5 <2,3,6,7,8,9,11,21,25,27,28,29,31,33,35,36,41>
/PCHHOT#) +3V <2,6,7,8,9,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>
SPI0_IO2 Reserved RSMRST# (iPU 15 ~ 40K)
A SPI0_IO3 Reserved RSMRST# (iPU 15 ~ 40K) A
0 = *Enable security in the Flash

HDA_SDO / Flash Descriptor Security
Description (iPD 20K) change location to near CPU to prevent impact HDA_SDO signal
I2S_TXD0 Override / Intel ME Debug Mode PCH_PWROK
1 = Disable Flash Descriptor Security (Override) HDA_SDO_R R737 1K_4
ME_WR# <31>
GPP_E19 0 = *Port B is not detected (iPD 20K)

Display Port B Detected PCH_PWROK
(DDPB_CTRLDATA) 1 =Port B is detected Quanta Computer Inc.
0 = *Port C is not detected (iPD 20K) PROJECT : ZAA
GPP_E21
WWW.AliSaler.Com Display Port C Detected PCH_PWROK 1 =Port C is detected Size Document Number Rev
(DDPC_CTRLDATA) 1A
Skylake 6/7 (PEG/DMI/FDI)
5 4 3 2 1
5 4 3 2 1
+VCCCORE
U35L SKL_ULT +VCCCORE
Backside cap A30

CPU POWER 1 OF 4
G32 Primary side cap

VCC_A30 VCC_G32
A34
VCC_A34 S0 VCC VCC_G33
G33
C184
C243 C233 C226 C203 C219 C224 C236 C255 C251
A39
A44 VCC_A39 0.55V~1.5V VCC_G35
G35
G37 C666 C645 C144 C650 C659 C150
VCC_A44 VCC_G37
1U/6.3V_2 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 AK33
VCC_AK33 2+2 peak 24A VCC_G38
G38 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8
AK35
VCC_AK35 2+2 TPY 17A VCC_G40
G40
Backside cap Primary side cap

AK37 G42
VCC_AK37 VCC_G42
AK38
VCC_AK38 2+3e peak 24A VCC_J30
J30
AK40
VCC_AK40 2+3e TPY 17A VCC_J33
J33
AL33 J37
C214 C245 AL37 VCC_AL33 VCC_J37 J40 C679 C667 C674 C664 C673 C675 C663 C678
C676 C258 C259 C647 C651 C657 C257 AL40 VCC_AL37 VCC_J40 K33 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4
1U/6.3V_2 1U/6.3V_2 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 AM32 VCC_AL40 VCC_K33 K35
AM33 VCC_AM32 VCC_K35 K37
VCC_AM33 VCC_K37
Backside cap
AM35 K38
AM37 VCC_AM35 VCC_K38 K40 +VCCCORE
D AM38 VCC_AM37 VCC_K40 K42 R96 100/F_4 D
VCC_AM38 VCC_K42
100 ohm Near CPU
G30 K43 VCORE_SENSE <37>
C189 C222 C235 VCC_G30 VCC_K43
VCORESS_SENSE <37>
C273 C272 C282 C289 C252 TP12 K32 E32 +1V_VCCST
22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 RSVD_K32 VCC_SENSE E33 R98 100/F_4 SVID Layout note: need routing together
1U/6.3V_4
TP20 AK32 VSS_SENSE and ALERT need between CLK and DATA.
RSVD_AK32
Backside cap +VCCOPC
B63 H_CPU_SVIDART#
VIDALERT#
AB62
P62 VCCOPC_AB62S0 1.0V 3A VIDSCK
A63
D64
H_CPU_SVIDCLK
H_CPU_SVIDDAT R138 C814 C815 C816 C817 C818 C819
For 2+3e CPU V62 VCCOPC_P62 VIDSOUT 100/F_4 1000P/50V_4 *1000P/50V_4 *1000P/50V_4 *1000P/50V_4 *1000P/50V_4 *1000P/50V_4
C212 C196 C201 C262 C215 VCCOPC_V62 G20
VCCSTG_G20 +VCCSTG
C227 C246 +1.8V_PRIM +1.8V_PRIM H63
VCC_OPC_1P8_H63
1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_4 Sx C174
1U/6.3V_2 +VCCOPC R172 *GT3@100/F_4 G61
VCC_OPC_1P8_G61 1.8V 50mA H_CPU_SVIDDAT H_CPU_SVIDDAT <37>
Backside cap
1U/6.3V_4
<35> +VCCOPC_SRC R634 *GT3@0_4 AC63 Place PU resistor
R636 *GT3@0_4 AE63 VCCOPC_SENSE
<35> 681_AGND VSSOPC_SENSE GT3 CPU close to CPU +1V_VCCST
C181 C228 C269 C237 C209 C285 R176 *GT3@100/F_4 AE62 DATA & CLK
VCCEOPIO
C200 AG62
VCCEOPIO S0 1.0V 3A must be equal (± 0.1 inch).
1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 Place PU resistor
1U/6.3V_2 +VCCEOPIO AL63 close to CPU R134
AJ62 VCCEOPIO_SENSE 54.9/F_4
VSSEOPIO_SENSE
100 ohm near CPU
For 2+3e CPU <PART_SYM_NUM> H_CPU_SVIDART# R552 220/F_4 VR_SVID_ALERT#_VCORE <37>
+VCCEOPIO Backside cap +VCCOPC_SRC

681_AGND
R633
R632
*GT3@0_4
*GT3@0_4
SP@SKL_ULT/BGA
U35M SKL_ULT +VCCGT H_CPU_SVIDCLK

C708 C709 For 2+3e CPU H_CPU_SVIDCLK <37>
Primary side cap

*GT3@10u/6.3V_4 *GT3@10u/6.3V_4 CPU POWER 2 OF 4
N70
A48 VCCGT N71
+VCCOPC VCCGT VCCGT
Backside cap 1.0V_CPU 3A A53 R63
VCCGT VCCGT
A58
VCCGT S0 VCCGT VCCGT
R64 C199 C190 C702 C690 C248 C697 C696
+VCCOPC A62
VCCGT 0.55~1.5V VCCGT
R65 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8
Backside cap
+1.8V_PRIM
A66 R66
VCCGT VCCGT
2+2 peak 31A
Primary side cap
C688 C684 C681 C685 C689 AA63 R67
VCCGT VCCGT
C682 C683 AA64
VCCGT 2+2 TPY 15A VCCGT
R68
C687 C686 *GT3@10u/6.3V_4 *GT3@1U/6.3V_2 *GT3@1U/6.3V_2 AA66 R69
*GT3@10u/6.3V_4 For 2+3e CPU
*GT3@10u/6.3V_4 *GT3@1U/6.3V_4 *GT3@1U/6.3V_2
*GT3@1U/6.3V_4
*GT3@1U/6.3V_4 AA67 VCCGT
2+3e peak 56A
VCCGT R70
VCCGT VCCGT
AA69
VCCGT 2+3e TPY 17A VCCGT
R71 C693 C705 C178 C706 C171 C707 C4732
AA70 T62 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6
For 2+3e CPU AA71 VCCGT VCCGT U65
47u/6.3V_8
C VCCGT VCCGT C
Primary side cap

R565 AC64 U68
*GT3@0_6 AC65 VCCGT VCCGT U71
+1.8V_S5 +1.8V_PRIM +VCCGT VCCGT VCCGT
Backside cap
AC66 W63
AC67 VCCGT VCCGT W64
AC68 VCCGT VCCGT W65
AC69 VCCGT VCCGT W66 C692 C704 C202 C4816 C694 C691 C703
AC70 VCCGT VCCGT W67 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6
C186 C185 C155 C158 C232 C218 C151 C161 C223 C148 AC71 VCCGT VCCGT W68
10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 J43 VCCGT VCCGT W69
J45 VCCGT VCCGT W70
J46 VCCGT VCCGT W71
VCCGT VCCGT
Backside cap
J48 Y62
VCCGT VCCGT +VCCGT
Primary side cap
J50
VCCGT
J52
VCCGT S0 VCCGTX
C197
C194
C193 C188
C241
C240 C239 C198 C204 C206 J53
J55 VCCGT 0.55~1.5V VCCGTX_AK42
AK42
AK43
VCCGT VCCGTX_AK43
1U/6.3V_2 1U/6.3V_4 1U/6.3V_2 1U/6.3V_2 1U/6.3V_4 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 J56
VCCGT 2+2 X VCCGTX_AK45
AK45
J58 AK46 C303 C310 C277 C302 C307 C274 C275 C276
VCCGT VCCGTX_AK46
J60
VCCGT 2+3e peak 6A VCCGTX_AK48 AK48 *GT3@22u/6.3V_6 22u/6.3V_6 *GT3@22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 *GT3@22u/6.3V_6
K48
VCCGT 2+3e TPY 4A VCCGTX_AK50 AK50 *GT3@22u/6.3V_6 *GT3@22u/6.3V_6
K50 AK52
C195 K52 VCCGT VCCGTX_AK52 AK53
C205 K53 VCCGT VCCGTX_AK53 AK55
VCCGT VCCGTX_AK55
Backside cap
1U/6.3V_4 1U/6.3V_2 K55 AK56
K56 VCCGT VCCGTX_AK56 AK58
L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46 C291 C279 C281 C324 C316 C280 C290 C317
L64 VCCGT VCCGTX_AL46 AL50 *GT3@10u/6.3V_4 *GT3@10u/6.3V_4 *GT3@10u/6.3V_4 *GT3@10u/6.3V_4
L65 VCCGT VCCGTX_AL50 AL53 *GT3@10u/6.3V_4 *GT3@10u/6.3V_4 *GT3@10u/6.3V_4 *GT3@10u/6.3V_4
L66 VCCGT VCCGTX_AL53 AL56
L67 VCCGT VCCGTX_AL56 AL60
+VCCCORE <37,38> VCCGT VCCGTX_AL60
L68 AM48
+VCCOPC <35>
L69 VCCGT VCCGTX_AM48 AM50 For 2+3e CPU
L70 VCCGT VCCGTX_AM50 AM52
+VCCEOPIO <35> +VCCGT VCCGT VCCGTX_AM52
L71 AM53
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
R155 N66 VCCGT VCCGTX_AU58 AU63
+1.8V_S5 <8,9,10,40> VCCGT VCCGTX_AU63
100 ohm Near CPU 100/F_4 N67 BB57
+VCCGT <37,38> VCCGT VCCGTX_BB57
N69 BB66
VCCGT VCCGTX_BB66
B +1V_VCCST <2,8,9,37> B
<37> VCCGT_SENSE J70 AK62
J69 VCCGT_SENSE VCCGTX_SENSE AL61
<37> VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE
<PART_SYM_NUM>
R161
+VCCIO <2,8,32,34,37,40> SP@SKL_ULT/BGA
100/F_4
+VCCSA <37,39>
+1.2VSUS <3,12,13,36>
+1V_SUS <34> +1.2VSUS U35N SKL_ULT
+VCCIO
Backside cap S3
CPU POWER 3 OF 4 S0
0.85V/0.95V
Backside cap Imax 3(A)
VDDQ_AU23 DDR3L
AU23 AK28
VCCIO
AU28
VDDQ_AU28 1.35V 3.0A VCCIO
AK30
AU35 AL30
VDDQ_AU35 VCCIO
VDDQ_AU42 2A
C313 C308 C311 C312 AU42 AL42 C266 C297 C264 C298
C318 C328 BB23 VCCIO AM28 C284 C283
10u/6.3V_4 10u/6.3V_4 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 BB32 VDDQ_BB23 VCCIO AM30 10u/6.3V_4 10u/6.3V_4 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2
BB41 VDDQ_BB32 VCCIO AM42
VDDQ_BB41 VCCIO
Primary side cap
BB47
VDDQ_BB47
Primary side cap S0 1.15V
BB51 AK23
VDDQ_BB51 VCCSA
2+2 peak 5A VCCSA
AK25
2+2 TPY 4A VCCSA
G23
AM40
VDDQC 2+3e peak 5.1A VCCSA
G25 C701 C710 C700 C711
2+3e TPY 5A VCCSA
G27
A18 G28 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
C326 C323 C325 C327 VCCST S3 1.0V 120mA VCCSA J22
10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 A22 VCCSA J23 +VCCSA
VCCSTG_A221.0V 40mA VCCSA
Backside cap
J27
AL23 S0 VCCSA K23
+VDDQC VCCPLL_OC VCCSA K25
K20 S0 1.0V 260mA VCCSA K27
R194 *short_4 K21 VCCPLL_K20 VCCSA K28 C254 C238 C247 C229 C221 C263 C288
+1.2VSUS VCCPLL_K21 VCCSA
Backside cap
K30 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4
C299 +1V_VCCST S3 1.0V 120mA VCCSA
C286 AM23 TP17
VCCIO_SENSE
Backside cap
1U/6.3V_2 10u/6.3V_4 AM22 TP14
VSSIO_SENSE
C677 H21
R550 *short_6 +VCCSTG VSSSA_SENSE H20 C207 C278 C260 C267 C249
+1V_SUS VCCSA_SENSE
1U/6.3V_4 R109 100/F_4 C216 C242
Primary side cap SP@SKL_ULT/BGA

<PART_SYM_NUM>
VSASS_SENSE <37>
1U/6.3V_2 1U/6.3V_2 1U/6.3V_4 1U/6.3V_4 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2
C176 VSA_SENSE <37>
Primary side cap

A +VCCIO R135 *short_6 A
Backside cap
1U/6.3V_4 +VCCSA
+VCCPLL R122 100/F_4
C114 C643 C641 C165 C642 C157
+1V_SUS R112 *short_6 100 ohm near CPU 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4
C172
Primary side cap 1U/6.3V_4

PROJECT : ZAA
1A
Skylake 12/13/14 (POWER)
5 4 3 2 1
5 4 3 2 1
+3V <2,4,7,8,9,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>
+3V_S5
+3VPCU
<2,3,4,7,8,9,11,21,25,27,28,29,31,33,35,36,41>
<9,11,23,25,26,27,28,29,31,32,33,40,41,42> Skylake ULT (GPU, SATA , ODD, CLK ,USB2&3)
+3V_RTC <8,9,31>
+1V_S5 <9,34>
SKL_ULT
U35H
SSIC / USB3
PCIE/USB3/SATA
H8
USB3_RXN0 <30>
PCH PU/PD +3V_S5
USB3_1_RXN G8
USB3_1_RXP USB3_RXP0 <30>
<14> PEG_RX#0 H13 C13 USB3_TXN0 <30> MB USB3.0 ( Charger IC )
G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13
<14> PEG_RX0 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_TXP0 <30>
<14> PEG_TX#0 C653 EV@0.22u/10V_4 C_PEG_TX#0 B17 USB_OC0# R541 10K_4
D
C652 EV@0.22u/10V_4 C_PEG_TX0 A17 PCIE1_TXN/USB3_5_TXN J6 USB_OC1# R540 10K_4
D
<14> PEG_TX0 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB3_RXN1 <30>
H6 USB_OC2# R543 10K_4
USB3_2_RXP/SSIC_1_RXP USB3_RXP1 <30>
<14> PEG_RX#1 G11 B13 USB3_TXN1 <30> MB USB3.0 USB_OC3# R542 10K_4
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
<14> PEG_RX1 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3_TXP1 <30>
<14> PEG_TX#1 C656 EV@0.22u/10V_4 C_PEG_TX#1 D16
C655 EV@0.22u/10V_4 C_PEG_TX1 C16 PCIE2_TXN/USB3_6_TXN J10
dGPU PEG*4 <14> PEG_TX1 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
USB3_RXN2 <21>
USB3_3_RXP/SSIC_2_RXP USB3_RXP2 <21> +3V
<14> PEG_RX#2 H16 B15 USB3_TXN2 <21>
G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
<14> PEG_RX2 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3_TXP2 <21>
<14> PEG_TX#2 C661 EV@0.22u/10V_4 C_PEG_TX#2 D17 For TYPE-C
C662 EV@0.22u/10V_4 C_PEG_TX2 C17 PCIE3_TXN E10
<14> PEG_TX2 PCIE3_TXP USB3_4_RXN USB3_RXN3 <21>
F10 DEVSLP0 R573 *10K_4
USB3_4_RXP USB3_RXP3 <21>
<14> PEG_RX#3 G15 C15 USB3_TXN3 <21> SATA_DEVSLP1 R574 *10K_4
F15 PCIE4_RXN USB3_4_TXN D15 SATA_DEVSLP2 R575 *10K_4
<14> PEG_RX3 PCIE4_RXP USB3_4_TXP USB3_TXP3 <21>
<14> PEG_TX#3 C654 EV@0.22u/10V_4 C_PEG_TX#3 B19 PIRQA# R631 *10K_4
C660 EV@0.22u/10V_4 C_PEG_TX3 A19 PCIE4_TXN AB9
<14> PEG_TX3 PCIE4_TXP USB2N_1 USBP0- <30>
AB10 MB USB3.0 Charger IC )
USB2P_1 USBP0+ <30>
TP4380 F16 SATAGP1 R569 *10K_4
TP4379 E16 PCIE5_RXN AD6
PCIE5_RXP USB2N_2 USBP1- <30>
TP4382 C19 AD7 USBP1+ <30> MB USB3.0
TP4381 D19 PCIE5_TXN USB2P_2
PCIE5_TXP AH3
USB2N_3 USBP2- <30>
For Thunderbolt TP4385 G18 AJ3 DB USB2.0
F18 PCIE6_RXN USB2P_3 USBP2+ <30>
TP4383
TP4386 D20 PCIE6_RXP AD9
PCIE6_TXN USB2N_4 USBP3- <30> +3V_S5
TP4384 C20 AD10 For 17" DB use Add SSD ID 1/14
PCIE6_TXP USB2P_4 USBP3+ <30>
F20 AJ1 USBP4- <28> Hight is SSD , Low is ODD
<27> SATA_RXN0 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2
<27> SATA_RXP0
B21 PCIE7_RXP/SATA0_RXP USB2P_5 USBP4+ <28> BT
HDD <27> SATA_TXN0
A21 PCIE7_TXN/SATA0_TXN
USB2
AF6 SATAGP0
<27> SSD_ID R568 10K_4 R570 100K_4
<27> SATA_TXP0 PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USBP5- <23>
G21 USB2P_6 USBP5+ <23> Touch Screen
<27> SATA_RXN1 F21 PCIE8_RXN/SATA1A_RXN AH1
<27> SATA_RXP1 PCIE8_RXP/SATA1A_RXP USB2N_7 USBP6- <23>
ODD D21 AH2 USBP6+ <23> CCD
<27> SATA_TXN1 PCIE8_TXN/SATA1A_TXN USB2P_7
C21
<27> SATA_TXP1 PCIE8_TXP/SATA1A_TXP AF8
USB2N_8 USBP7- <21>
C <25> PCIE_RX5-_LAN E22 AF9 USBP7+ <21> For TYPE-C C
E23 PCIE9_RXN USB2P_8
<25> PCIE_RX5+_LAN PCIE9_RXP
LAN C668 0.1u/16V_4 PCIE_TX5- B23 AG1
<25>
<25>
PCIE_TX5-_LAN
PCIE_TX5+_LAN C669 0.1u/16V_4 PCIE_TX5+ A23 PCIE9_TXN USB2N_9 AG2
USBP8-
USBP8+
<27>
<27> POA
Skylake-U userd 24 MHz (50 Ohm ESR) XTAL
PCIE9_TXP USB2P_9
<28> PCIE_RX6-_WLAN F25 AH7 TP4377
E25 PCIE10_RXN USB2N_10 AH8 TP4378 C665 10P/50V_4
<28> PCIE_RX6+_WLAN PCIE10_RXP USB2P_10 USBCOMP
WIFI C648 0.1u/16V_4 PCIE_TX6- D23 24MHz: BG624000078
<28> PCIE_TX6-_WLAN
C649 0.1u/16V_4 PCIE_TX6+ C23 PCIE10_TXN AB6 USBCOMP R178 113/F_4
Impedance = 50 ohm
<28> PCIE_TX6+_WLAN Trace length < 500 mils
3
4
PCIE10_TXP USB2_COMP AG3 USB2_ID R587 1K_4
USB2_ID 38.4MHz : ?
R562 100/F_4 PCIE_RCOMPN F5 AG4 R778 1K_4 Trace spacing = 15 mils Y4
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE R536
PCIE_RCOMPP 24MHz
+3V_S5 A9 USB_OC0# USB_OC0# <30> MB U3 1M_4
XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1#
TP91 +3V_S5 USB_OC1# <30> MB U3
1
2
XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2# XTAL24_IN
TP92
PIRQA# BB11 PROC_PREQ# +3V_S5 GPP_E11/USB2_OC2# B9 USB_OC3#
USB_OC2# <30> DB U2 XTAL24_OUT C658 10P/50V_4
GPP_A7/PIRQA#
+3V_S5 +3V_S5 GPP_E12/USB2_OC3# USB_OC3# <21> For Type-C
E28 +3V_S5 J1 DEVSLP0 DEVSLP0 <27>
<28> SATA_RXN3/PEG_RXN9_L0 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0
E27 J2 SATA_DEVSLP1
<28> SATA_RXP3/PEG_RXP9_L0 D24 PCIE11_RXP/SATA1B_RXP +3V_S5 GPP_E5/DEVSLP1 J3 SATA_DEVSLP2
For M.2 SSD -NA <28> SATA_TXN3/PEG_TXN9_L0
C24 PCIE11_TXN/SATA1B_TXN +3V_S5 GPP_E6/DEVSLP2 SATA_DEVSLP2 <28>
<28> SATA_TXP3/PEG_TXP9_L0 E30 PCIE11_TXP/SATA1B_TXP H2 SATAGP0 Note: Change Y4 to 38.4 MHz(ESR 30 ohm) for Cannonlake U
<28> SATA_RXN3/PEG_RXN10_L1
F30 PCIE12_RXN/SATA2_RXN +3V_S5 GPP_E0/SATAXPCIE0/SATAGP0 H3 SATAGP1
<28> SATA_RXP3/PEG_RXP10_L1 PCIE12_RXP/SATA2_RXP +3V_S5 GPP_E1/SATAXPCIE1/SATAGP1
For M.2 SSD -1 A25 G4
<28> SATA_TXN3/PEG_TXN10_L1 PCIE12_TXN/SATA2_TXN +3V_S5 GPP_E2/SATAXPCIE2/SATAGP2 NGFF_SATA_DET <28>
B25
<28> SATA_TXP3/PEG_TXP10_L1 PCIE12_TXP/SATA2_TXP H1 CH01006JB08 -> 10p
+3V_S5 GPP_E8/SATALED#
<PART_SYM_NUM> RTC Clock 32.768KHz (RTC) CH01506JB06 -> 15p
CH-6806TB01 -> 6.8p
SP@SKL_ULT/BGA
C351 8.2p/50V_4 RTC_X1
1
Trace length < 1000 mils
Y2 R255
32.768KHZ 10M_4 BG332768453 -> SEG
U35J SKL_ULT C362 8.2p/50V_4 RTC_X2 BG332768104 -> TXC
2
B B
CLOCK SIGNALS
D42
<14> CLK_PCIE_VGA# CLKOUT_PCIE_N0
N16S VGA <14> CLK_PCIE_VGA C42
R235 *short_4 CLK_PCIE_REQ0# AR10 CLKOUT_PCIE_P0
<14> CLK_PEGA_REQ# GPP_B5/SRCCLKREQ0# +3V_S5
<28> NGFF_SSD_CLK# R11112 *short_4 NGFF_SSD_CLK#_C B42
R11113 *short_4 NGFF_SSD_CLK_C A42 CLKOUT_PCIE_N1 F43 CLK_PCIE_XDPN
M.2 SSD <28> NGFF_SSD_CLK
R11111 *short_4 CLK_PCIE_REQ1# AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_PCIE_XDPP
TP93 RTC Circuitry (RTC)
<28> PCIE_CLKREQ_NGFF_SSD# GPP_B6/SRCCLKREQ1# +3V_S5 CLKOUT_ITPXDP_P TP94
TP4389 D41 BA17 SUSCLK +3VPCU 1B-1
CLKOUT_PCIE_N2 +3V_S5 GPD8/SUSCLK SUSCLK <28>
For Thunderbolt TP4387 C41
CLK_PCIE_REQ2# AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN
GPP_B7/SRCCLKREQ2# +3V_S5 XTAL24_IN E35 XTAL24_OUT
On SKL voltage at VCCRTC does not exceed 3.2V
D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF R512 2.7K/F_4 R304
CLKOUT_PCIE_P3 XCLK_BIASREF +1V_S5
TP22 CLK_PCIE_REQ3# AT10 1.5K/F_4 +3V_RTC
GPP_B8/SRCCLKREQ3# +3V_S5 AM18 RTC_X1 +3V_RTC
B40 RTCX1 AM20 RTC_X2 D7
Trace width = 30 mils
LAN
<25> CLK_PCIE_LANN CLKOUT_PCIE_N4 RTCX2

A40 +3V_RTC_2 R299
<25> CLK_PCIE_LANP CLKOUT_PCIE_P4
R229 *short_4 CLK_PCIE_REQ4# AU8 AN18 SRTC_RST# RTC_RST#
<25> CLK_PCIE_LAN_REQ# GPP_B9/SRCCLKREQ4# +3V_S5 SRTCRST# AM16 RTC_RST# RTC_RST# <11> VCCRTC_2 R308 1K_4 +3V_RTC_1
1
E40 RTCRST# 20K/F_4
WLAN
<28> CLK_PCIE_WLANN CLKOUT_PCIE_N5

<28> CLK_PCIE_WLANP E38 R301 BAT54C
R224 *short_4 CLK_PCIE_REQ5# AU7 CLKOUT_PCIE_P5 45.3K/F_4 C380 J1
<28> PCIE_CLKREQ_WLAN# GPP_B10/SRCCLKREQ5# +3V_S5 1V power plane +3V_RTC_[0:2] 1u/6.3V_4 *JUMP
2
0.71 checklist p14 Trace width = 20 mils R300
1
<PART_SYM_NUM> BT1 SRTC_RST#
SP@SKL_ULT/BGA
20K/F_4
BAT_CONN
2
C381 C382
1u/6.3V_4 1u/6.3V_4
+3V Rev:D add for EC reset RTC
A SRTC_RST# RTC_RST# 1A-22013/10/16 Chage +3V_RTC_0 to VCCTC_2. A
CLK_PCIE_REQ0# R234 10K_4

3
CLK_PCIE_REQ1# R215 10K_4 1. AHL03003057 DBV CR2032

2. AHL03003003 VDE CR2032
CLK_PCIE_REQ2# R227 *10K_4 CLR_CMOS 2 CLR_CMOS 2
<31> CLR_CMOS
Q6059 Q6060
CLK_PCIE_REQ3# R618 *10K_4 *2N7002K 2N7002K
CLK_PCIE_REQ4# R228 10K_4 R786
1
CLK_PCIE_REQ5# R223 10K_4 100K_4
PROJECT : ZAA
WWW.AliSaler.Com
1A
Skylake 9/10 (PEG/USB/CLK)
5 4 3 2 1
5 4 3 2 1
SKL_ULT
U35E
SPI - FLASH
PCH_SPI_CLK AV2
SMBUS, SMLINK
R7 PCH_MBCLK0_R
Strapping
SPI0_CLK +3V_S5 GPP_C0/SMBCLK
PCH_SPI_SO AW 3 R8 PCH_MBDAT0_R
PCH_SPI_SI AV3 SPI0_MISO +3V_S5 GPP_C1/SMBDATA R10 SMBALERT# +3V
SPI0_MOSI +3V_S5 GPP_C2/SMBALERT# SMBALERT# <4>
D PCH_SPI_IO2 AW 2 +3V_S5 D
PCH_SPI_IO3 AU4 SPI0_IO2 R9 VGA_MBCLK
PCH_SPI_CS0# AU3 SPI0_IO3 +3V_S5 GPP_C3/SML0CLK W2 VGA_MBDATA CLKRUN# R630 8.2K/F_4
AU2 SPI0_CS0# +3V_S5 GPP_C4/SML0DATA W1 SML0ALERT# IRQ_SERIRQ R629 10K_4
SPI0_CS1# +3V_S5 GPP_C5/SML0ALERT# SML0ALERT# <4>
AU1 EC_RCIN# R639 10K_4
SPI0_CS2# W 3 SMB_ME1_CLK
+3V_S5 GPP_C6/SML1CLK V3 SMB_ME1_DAT
SPI - TOUCH +3V_S5 GPP_C7/SML1DATA AM7 SML1ALERT#
+3V_S5 GPP_B23/SML1ALERT#/PCHHOT# SMB1ALERT# <29>
M2 +3V_S5
M3 GPP_D1/SPI1_CLK +3V_S5
J4 GPP_D2/SPI1_MISO +3V_S5 +3V_S5
V1 GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
+3V_S5 eSPI change to 15 ohm ckl v0.71 p.24 SMBus
V2 +3V_S5
M1 GPP_D22/SPI1_IO3 AY13 R659 *short_4
LPC
GPP_D0/SPI1_CS# +3V_S5 +3V_S5 GPP_A1/LAD0/ESPI_IO0 BA13 R640 *short_4
LPC_LAD0 <27,28,31>
PCH_MBCLK0_R 2.2K_4 R578
+3V_S5 GPP_A2/LAD1/ESPI_IO1 BB13 LPC_LAD1 <27,28,31> PCH_MBDAT0_R
R653 *short_4 2.2K_4 R580
C LINK +3V_S5 GPP_A3/LAD2/ESPI_IO2 LPC_LAD2 <27,28,31>
AY12 R668 *short_4 VGA_MBDATA 2.2K_4 R585
G3 +3V_S5 GPP_A4/LAD3/ESPI_IO3 BA12 LPC_LAD3 <27,28,31> VGA_MBCLK
LPC_LFRAME# <27,28,31> 2.2K_4 R582
G2 CL_CLK +3V_S5 GPP_A5/LFRAME#/ESPI_CS# BA11
G1 CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET#
CL_RST#
+3V_S5 C806 0.1u/16V_4
For M.2 wifi module must eSPI change to 15 ohm +3V_S5
2/10 add C806 for EMI request ,
AW 9 R623 22_4
R652 *short_4 EC_RCIN# AW 13 +3V_S5 GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9
CLK_PCI_EC <31> R748 no stuiff from EC site
<31> SIO_RCIN# GPP_A0/RCIN# +3V_S5 +3V_S5 GPP_A10/CLKOUT_LPC1 move at CPU site
AW 11 R626 22_4 SML1ALERT# *150K_4 R205
GPP_A8/CLKRUN# PCLK_TPM <27>
IRQ_SERIRQ AY11 +3V_S5 R627 22_4
<27,31> IRQ_SERIRQ GPP_A6/SERIRQ +3V_S5 CLKRUN#
CLK_PCI_LPC <28>
CLKRUN# <27,31>
<PART_SYM_NUM>
SP@SKL_ULT/BGA Termination Resistor Requirement for PCH PCHHOT# Pin
C4723
*22p/50V_4
Reserve PU 150K resister
C C
EMI
SP@ socket P/N: DFHS08FS023 only for A-TEST
SPI ROM Vender Size Quanta P/N Vender P/N Platform
WND 8M AKE3EFP0N07 W25Q64FVSSIQ SKL
Skylake
3.3V GGD 8M AKE2EZN0Q00 GD25B64CSIGR KBL
Winbound for SKL / Giga for KBL
+3V_S5 R11127 0_6
+3V_LDO_EC R11126 *0_6 +3V_PCH_ME +3V

D2B change to 2.2k
+3V_PCH_ME
R576 R572
1
U41
8
C754 0.1u/16V_4 SMBus(PCH) 2.2K_4 2.2K_4
1A-13 PCH_SPI_CS0# Q32
CS# VCC 5 S0
PCH_SPI_SO R650 15_4 SPI_SO_8M 2 7 SPI_HOLD_IO3_ME R698 1K_4
PCH_SPI_SO_EC R588 15_4 IO1/DO IO3/HOLD# PCH_MBDAT0_R 3 4
CLK_SDATA <12,13,22,29>
3 6 SPI_CLK_8M R684 15_4 PCH_SPI_CLK
IO2/W P# CLK
5 SPI_SI_8M R691 15_4 PCH_SPI_SI S5 2
4 IO0/DI
GND PCH_MBCLK0_R 6 1
B
CLK_SCLK <12,13,22,29> B
C747
ROM@W25Q64FV -- 8MB *22p/50V_4
PCH_SPI_CLK_EC R687 15_4 PCH_XDP_WLAN/S5 2N7002DW DDR_TP/S0
PCH_SPI_SI_EC R654 15_4
R649 1K_4 SPI_WP_IO2_ME

+3V_PCH_ME
SMBus(EC)
3.3K is original and for no PCH_SPI_IO2 R589 15_4 SPI_WP_IO2_ME
support fast read function
reserve for SPI fast read
PCH_SPI_IO3 R239 15_4 SPI_HOLD_IO3_ME
PCH_SPI_CLK_EC
<31> PCH_SPI_CLK_EC
<31> PCH_SPI_SI_EC PCH_SPI_SI_EC
PCH_SPI_SO_EC 2ND_MBCLK R171 *short_4 SMB_ME1_CLK
<31> PCH_SPI_SO_EC <17,31> 2ND_MBCLK
2ND_MBDATA R175 *short_4 SMB_ME1_DAT
<17,31> 2ND_MBDATA
R602 *short_4 PCH_SPI_CS0#

<31> SPI_CS0#_UR_ME
+3V
+3V_S5
<2,4,6,8,9,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>
<2,3,4,6,8,9,11,21,25,27,28,29,31,33,35,36,41>
EC/S5
+3V_PCH_ME
R591 10K_4 SPI_CS0#_UR_ME
A A

PROJECT : ZAA
1A
Skylake 5 (SATA/HDA/SPI)
5 4 3 2 1
5 4 3 2 1
SKL_ULT
U35K
SYSTEM POWER MANAGEMENT
Change for leakage
AT11
+3V_S5 GPP_B12/SLP_S0# TP4367 +3V_S5 +3V
AP15 SUSB# SUSB# <11,31,33>
+VCCIO PCI_PLTRST# AN10 +3V_S5 GPD4/SLP_S3# BA16 SUSC#
GPP_B13/PLTRST# +3V_S5 GPD5/SLP_S4# SUSC# <11,31>
11/12 Reserve PU 10K <11> SYS_RESET#
SYS_RESET# B5
SYS_RESET#
+3V_S5 GPD10/SLP_S5#
AY16 PCH_SLP_S5# PCH_SLP_S5# <11>
R655 *short_4 PCH_RSMRST# AY17 +3V_S5 PCH_VRALERT# R211 10K_4
<31> RSMRST# RSMRST#
R544 *10K_4 PROC_PWRGD R554 10K_4 PROC_PWRGD A68
I SLP_SUS#
AN15
AW15
PCH_SLP_SUS#
PCH_SLP_LAN#
TP4369
SYS_RESET# R561 10K_4
VCCST_PWRGD B65 PROCPWRGD I SLP_LAN# BB17 PCH_SLP_WLAN#

TP30
VCCST_PWRGD +3V_S5 GPD9/SLP_WLAN# AN16 PCH_SLP_A#
TP23
D +3V_S5 GPD6/SLP_A# PCH_SLP_A# <11> D
SYS_PWROK R556 *short_4 SYS_PWROK_R B6 *short_4 R677
SYS_PWROK DNBSWON# <31> +3V_S5
R643 *0_4 EC_PWROK_R BA20 BA15 PCH_PWRBTN#
DPWROK_R BB20 PCH_PWROK +3V_S5 GPD3/PWRBTN# AY15 PCH_ACPRESENT *short_4 R676
DSW_PWROK +3V_S5 GPD1/ACPRESENT SB_ACDC <31>
AU13 PCH_BATLOW# PCH_ACPRESENT R651 8.2K/F_4
+3V_S5 GPD0/BATLOW# TP74
EC only PD, so PD 10K <31> PCH_SUSPWRACK PCH_SUSPWRACK R11140 *short_4 AR13 PCH_BATLOW# R628 8.2K/F_4
SUSACK#_R AP11 GPP_A13/SUSWARN#/SUSPWRDNACK +3V_S5
TP4368 GPP_A15/SUSACK# +3V_S5 AU11 PCIE_LAN_WAKE# R250 10K_4
+3V_S5 GPP_A11/PME# TP29
PCH_SUSPWRACK <25,28> PCIE_LAN_WAKE# PCIE_LAN_WAKE# BB15 AP16 INTRUDER# R249 +3V_RTC
AM15 WAKE# INTRUDER# 1M_4 MPHY_EXT_PWR R195 *1K_4
TP84 AW17 GPD2/LAN_WAKE# +3V_S5 AM10 MPHY_EXT_PWR Rev:F add
AT15 GPD11/LANPHYPC +3V_S5 +3V_S5 GPP_B11/EXT_PWR_GATE# AM11 PCH_VRALERT#
R11114 GPD7/RSVD +3V_S5 GPP_B2/VRALERT# TP19 PCH_RSMRST# R642 10K_4
+3V_S5
<PART_SYM_NUM> PCH_PWROK R648 10K_4
10K_4 SYS_PWROK_R R555 10K_4
SP@SKL_ULT/BGA
SKL_ULT
U35I
CSI-2
A36 C37 +3V_S5

B36 CSI2_DN0 CSI2_CLKN0 D37
CSI2_DP0 CSI2_CLKP0 REV:E tPLT15(max 200us)
C38 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
->SLP_S4# assertion to
C36 CSI2_DP1 CSI2_CLKP1 C29 VDDQ(+1.35VSUS) ramp C811 *0.1u/16V_4
D36 CSI2_DN2 CSI2_CLKN2 D29 down start(SUSON)
A38 CSI2_DP2 CSI2_CLKP2 B26
CSI2_DN3 CSI2_CLKN3
5
B38 A26
CSI2_DP3 CSI2_CLKP3 2 SUSC#
C31 E13 R145 100/F_4 SUSON_R 4
D31 CSI2_DN4 CSI2_COMP B7 <34,36> SUSON_R 1 SUSON
CSI2_DP4 +3V_S5 GPP_D4/FLASHTRIG SUSON <31>
C33 TP63
Board ID +1.8V_S5 D33 CSI2_DN5 U48
3
A31 CSI2_DP5 EMMC
*TC7SH08FU
B31 CSI2_DN6 AP2 RAM_ID1
C R610 SP@10K_4 RAM_ID1 R611 *SP@10K_4 A33 CSI2_DP6 +1.8V_S5 GPP_F13/EMMC_DATA0 AP1 RAM_ID2 C
R612 10K_4 RAM_ID2 R613 *10K_4 B33 CSI2_DN7 +1.8V_S5 GPP_F14/EMMC_DATA1 AP3 RAM_ID3
R614 10K_4 RAM_ID3 R615 *10K_4 CSI2_DP7 +1.8V_S5 GPP_F15/EMMC_DATA2 AN3 Board_ID0
R595 *10K_4 Board_ID0 R600 10K_4 A29 +1.8V_S5 GPP_F16/EMMC_DATA3 AN1 Board_ID1 R790 *short_4
R598 SP@10K_4 Board_ID1 R599 SP@10K_4 B29 CSI2_DN8 +1.8V_S5 GPP_F17/EMMC_DATA4 AN2 Board_ID2
R605 SP@10K_4 Board_ID2 R608 SP@10K_4 C28 CSI2_DP8 +1.8V_S5 GPP_F18/EMMC_DATA5 AM4 Board_ID3
R592 SP@10K_4 Board_ID3 R590 SP@10K_4 D28 CSI2_DN9 +1.8V_S5 GPP_F19/EMMC_DATA6 AM1 Board_ID4
CSI2_DP9 +1.8V_S5 GPP_F20/EMMC_DATA7 Board_ID4 <23>
Board_ID4 R593 10K_4 A27
B27 CSI2_DN10 AM2 Board_ID5
R606 *10K_4 Board_ID5 R607 10K_4 C27 CSI2_DP10 +1.8V_S5 GPP_F21/EMMC_RCLK AM3 Board_ID6
R764 10K_4 Board_ID6 R765 *10K_4 D27 CSI2_DN11 +1.8V_S5 GPP_F22/EMMC_CLK AP4 Board_ID7
R766 SP@10K_4 Board_ID7 R767 SP@10K_4 CSI2_DP11 +1.8V_S5 GPP_F12/EMMC_CMD
AT1 200/F_4 R616
EMMC_RCOMP
<PART_SYM_NUM>
+3V_S5
SP@SKL_ULT/BGA +3V_S5
REV:E tPLT17(max REV:E tPLT18(max 200 us)
C812 *0.1u/16V_4
200us) ->SLP_S3# C813 *0.1u/16V_4
->SLP_S3# assertion to
Low High Low High assertion to IMVP VCCIO VR(MAIND for +1V_S5
5
VR_ON(VRON) deassertion to +VCCIO) disabled
5
2 SUSB#
BOARD_ID0 VRAM X32 VRAM X16 BOARD_ID5 14" 15/17" 2 SUSB# 4
4 <33,36,40> MAINON_R 1 MAINON
<35,37> VRON_R MAINON <27,31>
1 VRON VRON <31>
BOARD_ID1 Non IOAC IOAC BOARD_ID6 Reserved Reserve U49
3
U50 *TC7SH08FU
(Default)
3
*TC7SH08FU
GPU--> KA GPU--> KB
BOARD_ID2 No G-sensor G-sensor BOARD_ID7 (Kill A-chanel) (Kill B-chanel)
(Default) R791 *short_4
R792 *short_4
BOARD_ID3 No TPM TPM
BOARD_ID4 No touch panel touch panel

B Power Sequence Non Deep Sx
B
Rev:D change to shortpad

<31> PCH_PWROK R647 *short_4 EC_PWROK_R
EC_PWROK R131 *0_4 SYS_PWROK_R
For platforms not supporting Deep B2A

+VCCIO <2,5,32,34,37,40> S0->S5 & S0->S3
+3V_RTC <6,9,31> Sx, connect directly to RSMRST# No Deep Sx Rev:D change to shortpad Power of sequence 1us
+3V <2,4,6,7,9,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42> SUSB# -> VCCST_PWRGD
DPWROK_R R661 *short_4 PCH_RSMRST#
+3V_S5 <2,3,4,6,7,9,11,21,25,27,28,29,31,33,35,36,41> VCCST PWRGD CRB is via +1.05V PG +3V_S5
+1.8V_S5 <5,9,10,40>
+1V_VCCST <2,5,9,37>
+3V_S5 U6 C808 0.1u/16V_4
+1V_VCCST
5 1
VCC NC
5
C164 2 SUSB#
R85 0.1u/16V_4 2 VCCST_PWRGD_EN_L 4
A 1VCCST_PWRGD_EN
1K_4
VCCST_PWRGD VCCST_PWRGD_R 4 3 U47
3
Y GND C823 C824 TC7SH08FU
R89 60.4/F_4 *1000P/50V_4 *1000P/50V_4
C136 74AUP1G07GW
1000P/50V_4
+3V +3V_S5
SYSPWOK Shortpad change
R777 *0_4
PLTRST# Buffer to 60.4 ohm. 11/6
C332 0.1u/16V_4 C168 *0.1u/16V_4 Stuff 1000P/50V
5
Reserve 1000P/50V
5
2
4 2 EC_PWROK
PLTRST# <14,25,27,28,31> EC_PWROK <31>
A PCI_PLTRST# 1 SYS_PWROK 4 PCH_PWROK *0_4 R103 A
1 HWPG *short_4 R102
IMVP_PWRGD_3V <2> <31> HWPG
U14
3
TC7SH08FU R214 U8 Rev:D change netmane for HWPG

3
100K_4 *TC7SH08FU R130

*10K_4
R113 *0_4
R560 *short_4

PROJECT : ZAA
WWW.AliSaler.Com
1A
Skylake 9/11 (PWROK/Board_ID)
5 4 3 2 1
5 4 3 2 1
VCCPRIM_1P0 & VCCPRIM_CORE Short GPIO Group Power Plane

U35S SKL_ULT
Rev:D change to shortpad SKL_ULT
U35O C292 *1U/6.3V_4
RESERVED SIGNALS-1 Rev:F Remove Short Jumper for all +1V_S5 C268 1U/6.3V_4
CPU POWER 4 OF 4
C230 1U/6.3V_4
E68 BB68 AB19 C265 *1U/6.3V_4
CFG[0] RSVD_TP_BB68 +1V_S5 VCCPRIM_1P0
D B67
CFG[1] RSVD_TP_BB69
BB69 AB20
VCCPRIM_1P0 1.0V 696mA VCCPGPPA
AK15 +VCCPGPPA R198 *short_6 +3V_S5
D
D65
CFG[2]
C217 1U/6.3V_4 P18
VCCPRIM_1P0 S5 VCCPGPPB
AG15 +VCCPGPPB R185 *short_6 +3V_S5
D67
CFG[3] RSVD_TP_AK13
AK13
TP95 44mA VCCPGPPC
Y16 +VCCPGPPC R182 *short_6 +3V_S5
CFG4 E70
CFG[4] RSVD_TP_AK12
AK12
+1V_S5
AF18
VCCPRIM_CORE S5 VCCPGPPD
Y15 +VCCPGPPD R187 *short_6 +3V_S5
C68
CFG[5] Rev:F reserve TP C698 1U/6.3V_4 AF19
VCCPRIM_CORE 1.0V 2.574A VCCPGPPE
T16 +VCCPGPPE R179 *short_6 +3V_S5
D68
CFG[6] RSVD_BB2
BB2 V20
VCCPRIM_CORE S5 33mA VCCPGPPF
AF16 +VCCPGPPF R192 *short_6 +1.8V_S5
C67
CFG[7] RSVD_BA3
BA3 Rev:F Stuff C699 C699 47u/6.3V_8 V21
VCCPRIM_CORE 41mA VCCPGPPG
AD15 +VCCPGPPG R188 *short_6 +3V_S5
F71 C256 1U/6.3V_4
CFG[8]
G69
F70 CFG[9] AU5
1U/6.3V_4 C712 +VCCDSW_1P0 AL1
DCPDSW _1P0 1.0V 75mA with AJ21 pin
VCCPRIM_3P3_V19
V19 +VCCPRIM_3P3 C270 *1U/6.3V_4
CFG[10] TP5
G68
CFG[11] TP6
AT5
+1V_S5
K17
VCCMPHYAON_1P0 1.0V 1.0V VCCPRIM_1P0_T1
T1 +VCCPRIM_1P0 R11131 *short_6 +1V_S5
H70
CFG[12]
C695 1U/6.3V_4 C793 1U/6.3V_4 L1
VCCMPHYAON_1P0 22mA C250 1U/6.3V_4
G71
CFG[13] S5 6mA 1.8V VCCATS_1P8
AA1 +VCCATS_1P8 R180 *short_6 +1.8V_S5
H69 D5 N15 R240 *short_6
CFG[14] RSVD_D5 +1V_S5 VCCMPHYGT_1P0_N15 +3V_S5
G70
CFG[15] RSVD_D4
D4 C191 1U/6.3V_4 N16
VCCMPHYGT_1P0_N16 1.0V <1mA VCCRTCPRIM_3P3
AK17 +VCCPRTCPRIM_3P3 C348 0.1U/16V_4
B2 N17 C349 1U/6.3V_4
RSVD_B2 VCCMPHYGT_1P0_N17
E63
CFG[16] RSVD_C2
C2 C182 47u/6.3V_8 P15
VCCMPHYGT_1P0_P15 1.258A VCCRTC_AK19
AK19 +VCCPRTC R252 *short_6 +3V_RTC
F63
CFG[17]
P16
VCCMPHYGT_1P0_P16 3.0V+ VCCRTC_BB14
BB14 C322 1U/6.3V_4
E66 RSVD_B3
B3
A3 K15
RTC BB10 DCPRTC
C352
C732
0.1U/16V_4
0.1U/16V_4
CFG[18] RSVD_A3 VCCAMPHYPLL_1P0 DCPRTC
F66
CFG[19] AW 1
C179 1U/6.3V_4 L15
VCCAMPHYPLL_1P0 1.0V A14
RSVD_AW 1 VCCCLK1 +1V_S5
R156 49.9/F_4 CFG_RCOMP E60
CFG_RCOMP +1V_S5
V15
VCCAPLL_1P0 1.0V 26mA 1.0V
RSVD_E1
E1 S5 VCCCLK2
K19
+1V_S5 R153 1.5K/F_4 E8
ITP_PMODE RSVD_E2
E2
+1V_S5
AB17
VCCPRIM_1P0_AB17 135mA C680 *1U/6.3V_4
C225 *1U/6.3V_4 Y18
VCCPRIM_1P0_Y18 1.0V 696mA VCCCLK3
L21
AY2
AY1 RSVD_AY2 RSVD_BA4
BA4
BB4 R210 *0_6 +VCCPDSW_3P3 AD17
S5 S5 N20
RSVD_AY1 RSVD_BB4 +3VPCU VCCDSW _3P3_AD17 VCCCLK4
+3V_S5 R212 0_6 AD18
VCCDSW _3P3_AD18 3.3V S5
D1
RSVD_D1 RSVD_A4
A4 *0.1U/16V_4 C314 AJ17
VCCDSW _3P3_AJ17 118mA VCCCLK5
L19
C D3 C4 R789 0_6 C
RSVD_D3 RSVD_C4 +3V
K46 BB5
+1.5V R683 *0_6
C748
+VCCHDA
1U/6.3V_4
AJ19
VCCHDA 1.5V 30mA VCCCLK6
A10
C672 1U/6.3V_4
RSVD_K46 TP4
K45
RSVD_K45 +3V_S5 R193 +VCCPSPI AJ16
VCCSPI 3.3V 11mA S5 GPP_B0/CORE_VID0
AN11 V0P85A_VID0
TP31
AL25 RSVD_A69
A69
B69
*short_6
AF20
+3V GPP_B1/CORE_VID1
AN13
RSVD_AL25 RSVD_B69 VCCSRAM_1P0
AL27
RSVD_AL27 +1V_S5
AF21
VCCSRAM_1P0 1.0V
RSVD_AY3
AY3 R759 *short_4 T19
VCCSRAM_1P0 642mA
C71 C192 1U/6.3V_4 T20
B70 RSVD_C71 D71 VCCSRAM_1P0
RSVD_B70 RSVD_D71
F60 RSVD_C70
C70
Rev:D change to +3V_S5 R186 *short_6
C261
+VCCPRIM_3P3
1U/6.3V_4
AJ21
VCCPRIM_3P3_AJ21 3.3V 75mA S5
RSVD_F60
A52 RSVD_C54
C54
D54
shortpad +1V_S5
AK20
VCCPRIM_1P0_AK20 1.0V 696mA S5
RSVD_A52 RSVD_D54 N18
+1V_S5 VCCAPLLEBB
BA70
BA68 RSVD_TP_BA70 TP1
AY4
BB3
C173 1U/6.3V_4 1.0V 33mA <PART_SYM_NUM>
RSVD_TP_BA68 TP2
SP@SKL_ULT/BGA
J71 AY71 R760 *short_4
J68 RSVD_J71 VSS_AY71 AR56 R762 **GT3@0_4
RSVD_J68 ZVM# LPM_ZVM_N <35>
F65 AW 71
G65 VSS_F65 RSVD_TP_AW 71 AW 70
VSS_G65 RSVD_TP_AW 70 For 2+3e CPU No Stuff
F61 AP56
E61 RSVD_F61 MSM# C64 R761 100K_4 TP88
RSVD_E61 PROC_SELECT#
<PART_SYM_NUM>
+1V_VCCST
B SP@SKL_ULT/BGA B
Pin Name Strap description Configuration Note

1 = *Normal Operation; No stall (iPU 3K) +1V_S5 <6,34>
CFG[0] Stall reset sequence after PCU PLL lock until de-asserted +3VPCU <6,11,23,25,26,27,28,29,31,32,33,40,41,42>
0 = Stall +3V_S5 <2,3,4,6,7,8,11,21,25,27,28,29,31,33,35,36,41>
+3V <2,4,6,7,8,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>
CFG[1] Reserved Configuration lane

+1V_VCCST <2,5,8,37>
1 = *Normal Operation(iPU 3K) +1.8V_S5 <5,8,10,40>
CFG[2] PCI Express* Static x16 Lane Numbering Reversal H & S processor used only +3V_RTC <6,8,31>
0 = Lan number reversed
CFG[3] Reserved Configuration lane
1 = Disabled (iPU 3K) CFG4

CFG[4] eDP enable R548 1K_4
0 = *Enabled
00 = 1x8, 2x4 PCI Express*

01 = reserved
CFG[6:5] PCI Express* Bifunction H & S processor used only
A 10 = 2x8 PCI Express* A
11 = 1x16 PCI Express*

1 = *PEG Train immediatedly follow
CFG[7] PEG Training RESET# de-assertion (iPU 3K)
H & S processor used only
0 = PEG wait for BIOS for training
CFG[19:8] Reserved Configuration lane PROJECT : ZAA
1A
Skylake PCH-LP 15/19 (POWER)
5 4 3 2 1
5 4 3 2 1
Skylake ULT (GND)

SKL_ULT SKL_ULT SKL_ULT
U35P U35Q U35R U35T SKL_ULT
D D
GND 1 OF 3 GND 2 OF 3 GND 3 OF 3 SPARE
A5 AL65 AT63 BA49 F8 L18 AW69 F6

A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2 AW68 RSVD_AW69 RSVD_F6 E3
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20 +1.8V_S5 AU56 RSVD_AW68 RSVD_E3 C11
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4 AW48 RSVD_AU56 RSVD_C11 B11
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8 C7 RSVD_AW48 RSVD_B11 A11
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 R775 *0_4 U12 RSVD_C7 RSVD_A11 D12
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13 U11 RSVD_U12 RSVD_D12 C12
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19 H11 RSVD_U11 RSVD_C12 F52
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21 RSVD_H11 RSVD_F52
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6 C794
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65 <PART_SYM_NUM>
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68 *1U/6.3V_4
VSS VSS VSS VSS VSS VSS SP@SKL_ULT/BGA
AD13 AM68 AV71 BB43 G63 P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
C
Reserve 1uF no stuff in CPU U11,U12 ball C
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21 support Cannonlake-U PCH
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
VSS VSS VSS VSS VSS VSS +1.8V_S5 <5,8,9,40>
AG21 AP58 AW60 D58 K71 Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 <PART_SYM_NUM>
AJ15 VSS VSS AR20 B14 VSS VSS E18
B SP@SKL_ULT/BGA B
AK11 VSS VSS AR42 B34 VSS VSS E53
AK27 VSS VSS AR5 B58 VSS VSS F1
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
A AL58 VSS VSS AT56 VSS VSS BA41 A
AL64 VSS VSS AT58 VSS
VSS VSS
<PART_SYM_NUM> <PART_SYM_NUM> Quanta Computer Inc.

SP@SKL_ULT/BGA SP@SKL_ULT/BGA
PROJECT : ZAA
1A
Skylake 10/17/18 (GND)
5 4 3 2 1
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5 4 3 2 1
D D
C C
B B
APS1 R289 *0_6 APS3 R272 *0_6 APS7
Intel APS Fixture use

+3V_S5
CN2
1 APS1 R291 *0_6
1 2 R282 *0_4
2 3 APS3 R278 *0_6 SUSB# <8,31,33>
3 +3VPCU
4 R279 *0_4
4 5 R274 *0_4 PCH_SLP_S5# <8>
5 SUSC# <8,31> +3V_S5 <2,3,4,6,7,8,9,21,25,27,28,29,31,33,35,36,41>
6 R273 *0_4
6 PCH_SLP_A# <8> +3VPCU <6,9,23,25,26,27,28,29,31,32,33,40,41,42>
7 APS7 R271 *0_6 +3VPCU
7 8
8 9 R268 *0_4
9 10 RTC_RST# <6>
10 11 R265 *0_4
11 12 NBSWON# <29,31>
12 13 R267 *0_4 SYS_RESET#
A 13 14 SYS_RESET# <8> A
14 15
15 16
16 17
17
18
18 Quanta Computer Inc.
*ACES_88511-180N
PROJECT :ZAA
1A
CPU/PCH XDP
5 4 3 2 1
5 4 3 2 1
<3> M_A_A[13:0] P/N and F/P M_A_DQ[63:0] <3>

JDIM1A
M_A_A0 144 8 M_A_DQ0
M_A_A1 133 A0 DQ0 7 M_A_DQ4
M_A_A2 132 A1 DQ1 20 M_A_DQ2
M_A_A3 131 A2 DQ2 21 M_A_DQ6 R11170 *0_4
M_A_A4 128 A3 DQ3 4 M_A_DQ5 +2.5V
A4 DQ4
0-7
D M_A_A5 126 3 M_A_DQ1 D
M_A_A6 127 A5 DQ5 16 M_A_DQ7 JDIM1B
C1265 10U/6.3V_6
M_A_A7 122 A6 DQ6 17 M_A_DQ3 111
M_A_A8 125 A7 DQ7 28 M_A_DQ13 112 VDD1 C1267 0.1U/10V_4
M_A_A9 121 A8 DQ8 29 M_A_DQ8 117 VDD2 +3V
M_A_A10 146 A9 DQ9 41 M_A_DQ15 118 VDD3 255 R11133 *short_4
M_A_A11 120 A10/AP DQ10 42 M_A_DQ10 123 VDD4 VDDSPD
A11 DQ11
8-15 VDD5
M_A_A12 119 24 M_A_DQ9 +1.2VSUS 124
M_A_A13 158 A12 DQ12 25 M_A_DQ12 129 VDD6 257
151 A13 DQ13 38 M_A_DQ11 130 VDD7 VPP1 259 0.5A
<3> M_A_WE# 156 A14/WE# DQ14 37 M_A_DQ14 135 VDD8 VPP2 +2.5V_SUS
<3> M_A_CAS# 152 A15/CAS# DQ15 50 M_A_DQ21 136 VDD9
<3> M_A_RAS# A16/RAS# DQ16 49 M_A_DQ16
2250mA 141 VDD10 258
162 DQ17 62 M_A_DQ23 142 VDD11 VTT DDR_VTTREF
TP154
165 S2#/C0 DQ18 63 M_A_DQ22 147 VDD12 600mA
TP153
S3#/C1 DQ19
16-23 VDD13
46 M_A_DQ17 148
DQ20 45 M_A_DQ20 153 VDD14 164 VREF_CA_DIMM0
114 DQ21 58 M_A_DQ18 154 VDD15 VREF_CA
<3> M_A_ACT# 143 ACT# DQ22 59 M_A_DQ19 159 VDD16
<3> M_A_PARITY 116 PARITY DQ23 70 M_A_DQ28 160 VDD17
<3> M_A_ALERT# M_A_EVENT# 134 ALERT# DQ24 71 M_A_DQ29 163 VDD18
108 EVENT# DQ25 83 M_A_DQ30 VDD19
+1.2VSUS <3,13> DDR3_DRAMRST# RESET# DQ26 84 M_A_DQ26 24-31
DDR4 SODIMM 260 PIN
DDR4 SODIMM 260 PIN

C1258 *0.1U/10V_4 DQ27 66 M_A_DQ25 1 2
DQ28 67 M_A_DQ24 5 VSS1 VSS48 6
DQ29 79 M_A_DQ31 9 VSS2 VSS49 10
R10885 DQ30 80 M_A_DQ27 15 VSS3 VSS50 14
DQ31 174 M_A_DQ37 19 VSS4 VSS51 18
240/F_4 DQ32 VSS5 VSS52
173 M_A_DQ33 23 22
M_A_EVENT# DQ33 187 M_A_DQ35 27 VSS6 VSS53 26
DQ34 186 M_A_DQ39 31 VSS7 VSS54 30
*1K_4 M_A_EVENT# DQ35 170 M_A_DQ32 35 VSS8 VSS55 36
<13> PM_THRMTRIP#
R10890
DQ36
33-39 VSS9 VSS56
169 M_A_DQ36 39 40
DQ37 183 M_A_DQ34 43 VSS10 VSS57 44
Close to PCH DQ38 182 M_A_DQ38 47 VSS11 VSS58 48
DQ39 195 M_A_DQ41 51 VSS12 VSS59 52
150 DQ40 194 M_A_DQ40 57 VSS13 VSS60 56
<3> M_A_BA#0 145 BA0 DQ41 207 M_A_DQ42 61 VSS14 VSS61 60
C <3> M_A_BA#1 BA1 DQ42 VSS15 VSS62 C
+3V 115 208 M_A_DQ45 65 64
(260P)
(260P)
<3> M_A_BG#0 113 BG0 DQ43 191 M_A_DQ47 69 VSS16 VSS63 68
<3> M_A_BG#1 BG1 DQ44
40-47 VSS17 VSS64
190 M_A_DQ44 73 72
149 DQ45 203 M_A_DQ43 77 VSS18 VSS65 78
<3> M_A_CS#0 157 S0# DQ46 204 M_A_DQ46 81 VSS19 VSS66 82
<3> M_A_CS#1 109 S1# DQ47 216 M_A_DQ53 85 VSS20 VSS67 86
R10872 R10880 R10889
<3> M_A_CKE0 110 CKE0 DQ48 215 M_A_DQ49 89 VSS21 VSS68 90
*10K_4 *10K_4 *10K_4
<3> M_A_CKE1 CKE1 DQ49 228 M_A_DQ51 93 VSS22 VSS69 94
137 DQ50 229 M_A_DQ55 99 VSS23 VSS70 98
<3> M_A_CLK0 CK0 DQ51
48-55 VSS24 VSS71
CHA_SA0 CHA_SA1 CHA_SA2 139 211 M_A_DQ48 103 102
<3> M_A_CLK0# 138 CK0# DQ52 212 M_A_DQ52 107 VSS25 VSS72 106
<3> M_A_CLK1 140 CK1 DQ53 224 M_A_DQ54 +1.2VSUS 167 VSS26 VSS73 168
<3> M_A_CLK1# CK1# DQ54 225 M_A_DQ50 171 VSS27 VSS74 172
R10882 R10886 R10877
10K_4 10K_4 10K_4 155 DQ55 237 M_A_DQ62 175 VSS28 VSS75 176
<3> M_A_ODT0_DIMM 161 ODT0 DQ56 236 M_A_DQ59 181 VSS29 VSS76 180
<3> M_A_ODT1_DIMM ODT1 DQ57 249 M_A_DQ60 185 VSS30 VSS77 184
253 DQ58 250 M_A_DQ61 R10891 189 VSS31 VSS78 188
<7,13,22,29> CLK_SCLK 254 SCL DQ59 232 M_A_DQ58 193 VSS32 VSS79 192
<7,13,22,29> CLK_SDATA SDA DQ60
56-63 240/F_4
VSS33 VSS80
233 M_A_DQ63 197 196
CHA_SA0 256 DQ61 245 M_A_DQ56 M_A_DQS8 201 VSS34 VSS81 202
CHA_SA1 260 SA0 DQ62 246 M_A_DQ57 205 VSS35 VSS82 206
+1.2VSUS CHA_SA2 166 SA1 DQ63 +1.2VSUS 209 VSS36 VSS83 210
SA2 13 M_A_DQS0 213 VSS37 VSS84 214
92 DQS0 34 217 VSS38 VSS85 218
R10896 240/F_4 M_A_CB0 CB0 DQS1
M_A_DQS1
VSS39 VSS86
R10871 240/F_4 M_A_CB1 91 55 M_A_DQS2 223 222
101 CB1 DQS2 76 227 VSS40 VSS87 226
R10875 240/F_4 M_A_CB2 CB2 DQS3
M_A_DQS3
VSS41 VSS88
R10881 240/F_4 M_A_CB3 105 179 M_A_DQS4 R10894 231 230
88 CB3 DQS4 200 235 VSS42 VSS89 234
R10879 240/F_4 M_A_CB4 CB4 DQS5
M_A_DQS5 240/F_4
VSS43 VSS90
R10884 240/F_4 M_A_CB5 87 221 M_A_DQS6 239 238
100 CB5 DQS6 242 M_A_DQS#8 243 VSS44 VSS91 244
R10888 240/F_4 M_A_CB6 CB6 DQS7
M_A_DQS7
M_A_DQS[7:0] <3> VSS45 VSS92
R10892 240/F_4 M_A_CB7 104 97 M_A_DQS8 247 248
CB7 DQS8 251 VSS46 VSS93 252
12 11 M_A_DQS#0 VSS47 VSS94
33 DM0 DQS#0 32 M_A_DQS#1
+1.2VSUS 54 DM1 DQS#1 53 M_A_DQS#2
75 DM2 DQS#2 74 M_A_DQS#3 261
178 DM3 DQS#3 177 M_A_DQS#4 GND 262
B DM4 DQS#4 GND B
199 198 M_A_DQS#5
220 DM5 DQS#5 219 M_A_DQS#6
241 DM6 DQS#6 240 M_A_DQS#7
96 DM7 DQS#7 95 M_A_DQS#8 M_A_DQS#[7:0] <3>
DM8 DQS#8
Place these Caps near So-Dimm1.

1uF/10uF 4pcs on each side of connector VREF DQ0 M1 Solution +1.2VSUS
+1.2VSUS DDR_VTTREF VREF_CA_DIMM0
C1244 1U/6.3V_4 C1259 0.1U/16V_4 R10883

C1251 1U/6.3V_4 1K/F_4
C1271 1U/6.3V_4 C1255 10U/6.3V_6
+1.2VSUS <3,5,13,36> VREF_CA_DIMM0
C1275 1U/6.3V_4 +VREF_CA_CPU R10878 2/F_6 *0_4 R10887 +VDDQ
+3V <2,4,6,7,8,9,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>
C1260 1U/6.3V_4
+2.5V_SUS <13,36>
C1249 1U/6.3V_4
DDR_VTTREF <13,36>
1
C1273 1U/6.3V_4 +2.5V_SUS C1252
C1245 1U/6.3V_4 1023 Change R10410 0.022U/25V_4 R10895
C1253 1U/6.3V_4 C1266 0.1U/16V_4 1K/F_4
from 2ohm to 24.9ohn
2
C1270 10U/6.3V_6
+VDDQ <13,36>
C1256 1U/6.3V_4 C1257 10U/6.3V_6 R10873 24.9/F_4
+VREF_CA_CPU <3> +3V
C1254 1U/6.3V_4
A C1276 0.1U/16V_4 A
C1261 1U/6.3V_4
C1268 10U/6.3V_6
C1263 10U/6.3V_6
C1247 10U/6.3V_6
C1272 10U/6.3V_6
C1248 10U/6.3V_6
C1262 10U/6.3V_6
C1246 10U/6.3V_6
C1250 10U/6.3V_6
C1264 10U/6.3V_6
PROJECT :ZAA
DDR4 DIMM-STD(5.2H) CHA 1A

5 4 3 2 1
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5 4 3 2 1
M_B_DQ[63:0] <3>
<3> M_B_A[13:0] P/N and F/P R11174 *0_4
+2.5V
JDIM2A
M_B_A0 144 8 M_B_DQ1
M_B_A1 133 A0 DQ0 7 M_B_DQ4 JDIM2B
C1322 10U/6.3V_6
M_B_A2 132 A1 DQ1 20 M_B_DQ7 111
M_B_A3 131 A2 DQ2 21 M_B_DQ3 112 VDD1
A3 DQ3
0-7 VDD2
C1338 0.1U/10V_4
M_B_A4 128 4 M_B_DQ0 117 +3V
M_B_A5 126 A4 DQ4 3 M_B_DQ5 118 VDD3 255 R11134 *short_4
D A5 DQ5 VDD4 VDDSPD D
M_B_A6 127 16 M_B_DQ2 +1.2VSUS 123
M_B_A7 122 A6 DQ6 17 M_B_DQ6 124 VDD5
M_B_A8 125 A7 DQ7 28 M_B_DQ13 129 VDD6 257
M_B_A9 121 A8 DQ8 29 M_B_DQ9 130 VDD7 VPP1 259 +2.5V_SUS
M_B_A10 146 A9 DQ9 41 M_B_DQ14 135 VDD8 VPP2
A10/AP DQ10
8-15 VDD9 0.5A
M_B_A11 120 42 M_B_DQ15 136
M_B_A12 119 A11 DQ11 24 M_B_DQ12 141 VDD10 258
M_B_A13 158 A12 DQ12 25 M_B_DQ8
2250mA 142 VDD11 VTT DDR_VTTREF
151 A13 DQ13 38 M_B_DQ11 147 VDD12
<3> M_B_WE# 156 A14/WE# DQ14 37 M_B_DQ10 148 VDD13 600mA
<3> M_B_CAS# 152 A15/CAS# DQ15 50 M_B_DQ21 153 VDD14 164 VREF_CA_DIMM1
<3> M_B_RAS# A16/RAS# DQ16 49 M_B_DQ17 154 VDD15 VREF_CA
162 DQ17 62 M_B_DQ19 159 VDD16
TP158
S2#/C0 DQ18
16-23 VDD17
TP157 165 63 M_B_DQ22 160
S3#/C1 DQ19 46 M_B_DQ20 163 VDD18
DQ20 45 M_B_DQ16 VDD19
114 DQ21 58 M_B_DQ18
DDR4 SODIMM 260 PIN

<3> M_B_ACT# 143 ACT# DQ22 59 M_B_DQ23 1 2
<3> M_B_PARITY 116 PARITY DQ23 70 M_B_DQ28 5 VSS1 VSS48 6
<3> M_B_ALERT# M_B_EVENT# 134 ALERT# DQ24 71 M_B_DQ25 9 VSS2 VSS49 10
108 EVENT# DQ25 83 M_B_DQ26 15 VSS3 VSS50 14
+1.2VSUS <3,12> DDR3_DRAMRST# RESET# DQ26
24-31 VSS4 VSS51
84 M_B_DQ31 19 18
DDR4 SODIMM 260 PIN

C1317 *0.1U/10V_4 DQ27 66 M_B_DQ29 23 VSS5 VSS52 22
DQ28 67 M_B_DQ24 27 VSS6 VSS53 26
DQ29 79 M_B_DQ30 31 VSS7 VSS54 30
DQ30 80 M_B_DQ27 35 VSS8 VSS55 36
R10928 DQ31 174 M_B_DQ32 39 VSS9 VSS56 40
240/F_4 DQ32 173 M_B_DQ36 43 VSS10 VSS57 44
DQ33 187 M_B_DQ39 47 VSS11 VSS58 48
M_B_EVENT# DQ34 VSS12 VSS59
186 M_B_DQ35 32-39 51 52
DQ35 170 M_B_DQ33 57 VSS13 VSS60 56
R10921 *1K_4 M_B_EVENT# DQ36 169 M_B_DQ37 61 VSS14 VSS61 60
<12> PM_THRMTRIP# DQ37 183 M_B_DQ38 65 VSS15 VSS62 64
(260P)
DQ38 182 M_B_DQ34 69 VSS16 VSS63 68
Close to PCH DQ39 195 M_B_DQ45 73 VSS17 VSS64 72
150 DQ40 194 M_B_DQ40 77 VSS18 VSS65 78
<3> M_B_BA#0 145 BA0 DQ41 207 M_B_DQ42 81 VSS19 VSS66 82
C <3> M_B_BA#1 BA1 DQ42 VSS20 VSS67 C
115 208 M_B_DQ47 40-47 85 86
(260P)
+3V <3> M_B_BG#0 113 BG0 DQ43 191 M_B_DQ44 89 VSS21 VSS68 90
<3> M_B_BG#1 BG1 DQ44 190 M_B_DQ41 93 VSS22 VSS69 94
149 DQ45 203 M_B_DQ43 99 VSS23 VSS70 98
<3> M_B_CS#0 157 S0# DQ46 204 M_B_DQ46 103 VSS24 VSS71 102
<3> M_B_CS#1 109 S1# DQ47 216 M_B_DQ53 107 VSS25 VSS72 106
<3> M_B_CKE0 110 CKE0 DQ48 215 M_B_DQ49 167 VSS26 VSS73 168
<3> M_B_CKE1 CKE1 DQ49 228 M_B_DQ54 171 VSS27 VSS74 172
R10924 R10940 R10923 DQ50
48-55 VSS28 VSS75
137 229 M_B_DQ55 175 176
*10K_4 10K_4 *10K_4 <3> M_B_CLK0 139 CK0 DQ51 211 M_B_DQ48 181 VSS29 VSS76 180
<3> M_B_CLK0# 138 CK0# DQ52 212 M_B_DQ52 185 VSS30 VSS77 184
CHB_SA0 CHB_SA1 CHB_SA2 <3> M_B_CLK1 CK1 DQ53 VSS31 VSS78
140 224 M_B_DQ51 189 188
<3> M_B_CLK1# CK1# DQ54 225 M_B_DQ50 193 VSS32 VSS79 192
R10943 R10937 R10927 155 DQ55 237 M_B_DQ61 197 VSS33 VSS80 196
10K_4 *10K_4 10K_4 <3> M_B_ODT0_DIMM 161 ODT0 DQ56 236 M_B_DQ60 201 VSS34 VSS81 202
<3> M_B_ODT1_DIMM ODT1 DQ57 249 M_B_DQ59 205 VSS35 VSS82 206
253 DQ58 250 M_B_DQ62 209 VSS36 VSS83 210
<7,12,22,29> CLK_SCLK SCL DQ59
56-63 VSS37 VSS84
254 232 M_B_DQ57 213 214
<7,12,22,29> CLK_SDATA SDA DQ60 233 M_B_DQ56 217 VSS38 VSS85 218
CHB_SA0 256 DQ61 245 M_B_DQ58 223 VSS39 VSS86 222
CHB_SA1 260 SA0 DQ62 246 M_B_DQ63 227 VSS40 VSS87 226
+1.2VSUS CHB_SA2 166 SA1 DQ63 M_B_DQS[7:0] <3> 231 VSS41 VSS88 230
SA2 13 M_B_DQS0 +1.2VSUS 235 VSS42 VSS89 234
92 DQS0 34 239 VSS43 VSS90 238
R10931 240/F_4 M_B_CB0 CB0 DQS1
M_B_DQS1
VSS44 VSS91
R10936 240/F_4 M_B_CB1 91 55 M_B_DQS2 243 244
101 CB1 DQS2 76 247 VSS45 VSS92 248
R10933 240/F_4 M_B_CB2 CB2 DQS3
M_B_DQS3
VSS46 VSS93
R10939 240/F_4 M_B_CB3 105 179 M_B_DQS4 251 252
88 CB3 DQS4 200 VSS47 VSS94
R10941 240/F_4 M_B_CB4 CB4 DQS5
M_B_DQS5 R10926
R10922 240/F_4 M_B_CB5 87 221 M_B_DQS6 240/F_4
100 CB5 DQS6 242
R10942 240/F_4 M_B_CB6 CB6 DQS7
M_B_DQS7
R10925 240/F_4 M_B_CB7 104 97 M_B_DQS8 M_B_DQS8 261
CB7 DQS8 M_B_DQS#[7:0] <3> GND 262
12 11 M_B_DQS#0 +1.2VSUS GND
33 DM0 DQS#0 32 M_B_DQS#1
+1.2VSUS 54 DM1 DQS#1 53 M_B_DQS#2
75 DM2 DQS#2 74 M_B_DQS#3
178 DM3 DQS#3 177 M_B_DQS#4
B DM4 DQS#4 B
199 198 M_B_DQS#5 R10929
220 DM5 DQS#5 219 M_B_DQS#6
DM6 DQS#6 240/F_4 +1.2VSUS <3,5,12,36>
241 240 M_B_DQS#7
96 DM7 DQS#7 95 M_B_DQS#8 M_B_DQS#8 +3V <2,4,6,7,8,9,12,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>
DM8 DQS#8 +2.5V_SUS <12,36>
DDR_VTTREF <12,36>
+VDDQ <12,36>
+VREFDQ_SB_M3 <3>
Place these Caps near So-Dimm0.

For EMI RESERVE 1uF/10uF 4pcs on each side of connector
+1.2VSUS DDR_VTTREF VREF DQ1 M1 Solution
+1.2VSUS
+1.2VSUS C1332 1U/6.3V_4 C1315 1U/6.3V_4
EC39 *120P/50V_4 EC36 *120P/50V_4 C1325 1U/6.3V_4 C1311 1U/6.3V_4 +1.2VSUS
EC48 *120P/50V_4 EC47 *120P/50V_4 C1309 1U/6.3V_4 C1310 1U/6.3V_4
EC42 *120P/50V_4 EC43 *120P/50V_4 C1318 1U/6.3V_4 C1319 1U/6.3V_4

R10934
EC49 120P/50V_4 EC38 *0.1U/16V_4 C1337 1U/6.3V_4 C1333 1U/6.3V_4 1K/F_4
EC46 *120P/50V_4 EC41 *0.1U/16V_4 C1314 1U/6.3V_4 +VREFDQ_SB_M3 R10932 2/F_6 VREF_CA_DIMM1 *0_4 R10935
+VREFDQ_SB_M3 +VDDQ
1
EC44 *120P/50V_4 EC37 *0.1U/16V_4 C1336 1U/6.3V_4
VREF_CA_DIMM1 C1329
EC45 *120P/50V_4 EC50 *0.1U/16V_4 C1335 1U/6.3V_4 0.022U/25V_4 R10938
2
C1323 0.1U/16V_4 1K/F_4
C1330 10U/6.3V_6 C1327 10U/6.3V_6 R10930

A DDR_VTTREF 24.9/F_4 A
C1312 10U/6.3V_6
EC35 *120P/50V_4 +2.5V_SUS
C1321 10U/6.3V_6
EC40 *120P/50V_4 C1320 0.1U/16V_4
C1331 10U/6.3V_6
C1324 10U/6.3V_6
C1328 10U/6.3V_6
C1334 10U/6.3V_6 +3V
C1313 10U/6.3V_6 C1326 0.1U/16V_4 Quanta Computer Inc.

C1308 10U/6.3V_6 C1316 10U/6.3V_6
PROJECT :ZAA
DDR4 DIMM-RVS(5.2H) CHB 1A

5 4 3 2 1
1 2 3 4 5 6 7 8
N16S-GT1-KA-A2 GM107-710-KA-A2 AJ0N16S0T22 B/S PN

U3002A
SP@N16P-GT
N16S-GT1-KB-A2 GM107-710-KB-A2 AJSR2JK8T02
PEX_IOVDD/Q : 3300mA
+1.05V_GFX AG19
AG21 PEX_IOVDD_1 PEX_RX0
AN12
AM12
PEG_TX0 <6> N16S-GTR-B-A2 GM108-770-A2 AJ0N16S0T24
To be placed no further from the GPU AG22 PEX_IOVDD_2 [PEG Interface] PEX_RX0_N AN14
PEG_TX#0
PEG_TX1
<6>
<6>
than bewteen the PS and GPU AG24 PEX_IOVDD_3 PEX_RX1 AM14
PEX_IOVDD_4 PEX_RX1_N PEG_TX#1 <6>
AH21 AP14 PEG_TX2 <6>
C4000 EV@22U/6.3V_6 AH25 PEX_IOVDD_5 PEX_RX2 AP15
PEX_IOVDD_6 PEX_RX2_N PEG_TX#2 <6>
C4001 EV@22U/6.3V_6 AN15 PEG_TX3 <6>
PEX_RX3 +1.05V_GFX <15,16,42>
C4002 EV@22U/6.3V_6 AG13 AM15 PEG_TX#3 <6>
PEX_IOVDDQ_1 PEX_RX3_N +3V_GFX <16,17,31,42>
A C4003 EV@22U/6.3V_6 AG15 AN17 A
PEX_IOVDDQ_2 PEX_RX4 +3V_MAIN <15,16,17>
C4004 EV@10U/6.3V_6 AG16 AM17
PEX_IOVDDQ_3 PEX_RX4_N +3V <2,4,6,7,8,9,12,13,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>
C4005 EV@10U/6.3V_6 AG18 AP17
C4006 EV@10U/6.3V_6 AG25 PEX_IOVDDQ_4 PEX_RX5 AP18
C4007 EV@10U/6.3V_6 AH15 PEX_IOVDDQ_5 PEX_RX5_N AN18
AH18 PEX_IOVDDQ_6 PEX_RX6 AM18
AH26 PEX_IOVDDQ_7 PEX_RX6_N AN20
PLACE NEAR BALLS AH27 PEX_IOVDDQ_8 PEX_RX7 AM20
AJ27 PEX_IOVDDQ_9 PEX_RX7_N AP20
C4008 EV@1U/6.3V_4 AK27 PEX_IOVDDQ_10 PEX_RX8 AP21
C4009 EV@1U/6.3V_4 AL27 PEX_IOVDDQ_11 PEX_RX8_N AN21
C4010 EV@1U/6.3V_4 AM28 PEX_IOVDDQ_12 PEX_RX9 AM21
3V MAIN POWER
C4011 EV@1U/6.3V_4 AN28 PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_RX9_N
PEX_RX10
AN23 GC6:+3V_MAIN +3V_GFX +3V_GFX
AM23
PEX_RX10_N AP23 3/11 GC6 timing issue from
PLACE UNDER BGA PEX_RX11 AP24
GC6 Power control 200K change to 100K
PEX_RX11_N AN24
C4012 EV@4.7U/6.3V_4 PEX_RX12 AM24
C4014 EV@4.7U/6.3V_4 PEX_RX12_N AN26 +3V_GFX R4000 C4013
PEX_RX13 60mil
AM26 EV@10K_4
1
PEX_RX13_N AP26 EV@0.022U/25V_4
PEX_RX14 AP27 R4003
PEX_RX14_N AN27 *0_8
PEX_RX15 AM27 R4001 R4002 EV@100K_4 2 Q4000
PEX_RX15_N EV@AO3413
EV@10K_4
3
AK14 PEG_RXP0_C C4015 EV@0.22U/10V_4 60mil
PEX_TX0 PEG_RX0 <6> +3V_MAIN
AJ14 PEG_RXN0_C C4016 EV@0.22U/10V_4
PEG_RX#0 <6>
3
PEX_TX0_N AH14 PEG_RXP1_C C4017 EV@0.22U/10V_4 C4019
PEX_TX1 PEG_RX1 <6>
B AG14 PEG_RXN1_C C4018 EV@0.22U/10V_4 <17> +3V_MAIN_EN 2 B
PEX_TX1_N PEG_RX#1 <6>
AK15 PEG_RXP2_C C4020 EV@0.22U/10V_4 EV@0.022U/25V_4
PEX_TX2 PEG_RX2 <6>
AJ15 PEG_RXN2_C C4021 EV@0.22U/10V_4 Q4001 N16V stuff not support GC6 2.0.
PEX_TX2_N PEG_RX#2 <6>
AL16 PEG_RXP3_C C4022 EV@0.22U/10V_4 EV@2N7002K
PEX_TX3 PEG_RX3 <6>
AK16 PEG_RXN3_C C4023 EV@0.22U/10V_4
PEG_RX#3 <6>
1
PEX_TX3_N AK17
PEX_TX4 AJ17
PEX_TX4_N AH17
AC6 PEX_TX5 AG17
AJ28 NC_1 PEX_TX5_N AK18
AJ4 NC_2 PEX_TX6 AJ18
AJ5 NC_3 PEX_TX6_N AL19
AL11 NC_4 PEX_TX7 AK19
C15 NC_5 PEX_TX7_N AK20
D19 NC_6 PEX_TX8 AJ20
D20 NC_7 PEX_TX8_N AH20
D23 NC_8 PEX_TX9 AG20 +3V +3V
D26 NC_9
NC_10
PEX_TX9_N
PEX_TX10
AK21 GC6 PEGX_RST# +3V_GFX
H31 AJ21
NC_11 PEX_TX10_N <17> SYS_PEX_RST_MON#
T8 AL22
V32 NC_12 PEX_TX11 AK22
Y1 NC_13 PEX_TX11_N AK23 C4024
Y2 NC_14 PEX_TX12 AJ23 GC6@0.1U/16V_4 C4025 R4004
Y3 NC_15 PEX_TX12_N AH23 GC6@0.1U/16V_4 *GC6@10K_4
5
AA1 NC_16 PEX_TX13 AG23
5
PLACE CLOSE TO BGA AA2 NC_17 PEX_TX13_N AK24 2
NC_18 PEX_TX14 <8,25,27,28,31> PLTRST#
C4026 EV@4.7U/6.3V_4 AA3 AJ24 4 RST_MON# R11108 *short_4 2
C4027 EV@1U/6.3V_4 AA4 NC_19 PEX_TX14_N AL25 1 4 PEGX_RST#
NC_20 PEX_TX15 <4> DGPU_HOLD_RST#
AA5 AK25 1
C AA6 NC_21 PEX_TX15_N C4030 U4001 C
3
C4028 EV@0.1u/16V_4 AA7 NC_22 GC6@74AHC1G09GW
3
C4029 *EV@0.1U/16V_4 AA8 NC_23 AL13 U4002 R4005
NC_24 PEX_REFCLK CLK_PCIE_VGA <6>
C4031 *EV@0.1U/16V_4 AK13 CLK_PCIE_VGA# <6> EV@1000p/50V_4 GC6@TC7SH08FU(F) GC6@100K_4
PEX_REFCLK_N <17> GPU_PEX_RST_HOLD#
PLACE CLOSE TO GPU BALLS
AJ26 PEX_TSTCLK R4006 *EV@200/F_4 *NGC6@0_4
J8 PEX_TSTCLK_OUT AK26 PEX_TSTCLK# RST_MON# R4007 PEGX_RST#
K8 3V3_AON_1 PEX_TSTCLK_OUT_N
+3V_GFX 3V3_AON_2
+3V_MAIN L8 AJ11
M8 3V3_MAIN_1 NC AJ12 PEGX_RST#
VDD33 : 85mA 3V3_MAIN_2 PEX_RST_N PEGX_RST# <17>
PLACE CLOSE TO BGA

PEX_CLKREQ_N
AK12 PEX_CLKREQ# R4008 EV@10K_4 +3V_GFX
GC6 FBVDDQ_EN
C4032 EV@4.7U/6.3V_4 +1.05V_GFX
C4033 EV@1U/6.3V_4 AP29 PEX_TERMP R4009 EV@2.49K/F_4 <4,17> GC6_FB_EN GC6_FB_EN 1
PEX_TERMP
R4010 *short_6
B2A 3
FBVDDQ_EN <42>
PLACE CLOSE TO GPU BALLS AK11 TESTMODE R4011 EV@10K_4
C4034 EV@0.1u/16V_4 TESTMODE 2
<41> GPU_PWR_GD C3A
1
C4035 EV@0.1u/16V_4 AG26 PEX_PLLVDD PEX_PLLVDD : 150mA C4036 EV@4.7U/6.3V_4 PLACE NEAR GPU D4000
PEX_PLLVDD GC6@BAT54CW_200MA R4012
AH12 PEX_SVDD_3V3 : 210mA +3V_GFX C4037 EV@1U/6.3V_4 PLACE NEAR GPU GC6@1M_4
PEX_PLL_HVDD AG12 EV@0.1u/16V_4 C4038
2
PEX_SVDD_3V3 EV@4.7U/6.3V_4 C4039 C4040 EV@0.1u/16V_4 PLACE UNDER GPU BALLS
EV@4.7U/6.3V_4 C4041
D
P8 3.3V_AUX D
3.3V_AUX_NC PLACE NEAR BGA
TP4000
L4 +3V_MAIN
VDD_SENSE VGA_VCCSENSE <41>
2
L5
GND_SENSE VGA_VSSSENSE <41>
PEX_CLKREQ# 1 3
CLK_PEGA_REQ# <6>
PROJECT : ZAA
Q4002 Size Document Number Rev
EV@2N7002KW_115MA 1A
N16 - 1/5 (PCIE)
1 2 3 4 5 6 7 8
WWW.AliSaler.Com
1 2 3 4 5 6 7 8
U3002B U3002C
SP@N16P-GT SP@N16P-GT
FBB_CMD0 D13 G9 VMB_DQ0
<20> FBB_CMD0 FBB_CMD1 E14 FBB_CMD0 FBC_D00 E9 VMB_DQ1 VMB_DQ0 <20>
<20> FBB_CMD1 FBB_CMD1 FBC_D01 VMB_DQ1 <20>
FBA_CMD0 U30 L28 VMA_DQ0 FBB_CMD2 F14 G8 VMB_DQ2
<19> FBA_CMD0 FBA_CMD1 T31 FBA_CMD0
[MEMORY I/F A]
FBA_D00 M29 VMA_DQ1 VMA_DQ0 <19> <20> FBB_CMD2 FBB_CMD3 A12 FBC_CMD2 MEMORY I/F C FBC_D02 F9 VMB_DQ3 VMB_DQ2 <20>
<19> FBA_CMD1 FBA_CMD1 FBA_D01 VMA_DQ1 <19> <20> FBB_CMD3 FBB_CMD3 FBC_D03 VMB_DQ3 <20>
FBA_CMD2 U29 L29 VMA_DQ2 FBB_CMD4 B12 F11 VMB_DQ4
FBA_CMD3 R34 M28 VMA_DQ3 FBB_CMD5 C14 G11 VMB_DQ5
<19> FBA_CMD3 FBA_CMD4 R33 FBA_CMD3 FBA_D03 N31 VMA_DQ4 VMA_DQ3 <19> <20> FBB_CMD5 FBB_CMD6 B14 FBB_CMD5 FBC_D05 F12 VMB_DQ6 VMB_DQ5 <20>
FBA_CMD5 U32 P29 VMA_DQ5 FBB_CMD7 G15 G12 VMB_DQ7
<19> FBA_CMD5 FBA_CMD6 U33 FBA_CMD5 FBA_D05 R29 VMA_DQ6 VMA_DQ5 <19> <20> FBB_CMD7 FBB_CMD8 F15 FBC_CMD7 FBC_D07 G6 VMB_DQ8 VMB_DQ7 <20>
FBA_CMD7 U28 P28 VMA_DQ7 FBB_CMD9 E15 F5 VMB_DQ9
FBA_CMD8 V28 J28 VMA_DQ8 FBB_CMD10 D15 E6 VMB_DQ10
<19> FBA_CMD8 FBA_CMD9 V29 FBA_CMD8 FBA_D08 H29 VMA_DQ9 VMA_DQ8 <19> <20> FBB_CMD10 FBB_CMD11 A14 FBB_CMD10 FBC_D10 F6 VMB_DQ11 VMB_DQ10 <20>
A <19> FBA_CMD9 FBA_CMD9 FBA_D09 VMA_DQ9 <19> <20> FBB_CMD11 FBB_CMD11 FBC_D11 VMB_DQ11 <20> A
FBA_CMD10 V30 J29 VMA_DQ10 FBB_CMD12 D14 F4 VMB_DQ12
<19> FBA_CMD10 FBA_CMD11 U34 FBA_CMD10 FBA_D10 H28 VMA_DQ11 VMA_DQ10 <19> <20> FBB_CMD12 FBB_CMD13 A15 FBB_CMD12 FBC_D12 G4 VMB_DQ13 VMB_DQ12 <20>
FBA_CMD12 U31 G29 VMA_DQ12 FBB_CMD14 B15 E2 VMB_DQ14
FBA_CMD13 V34 E31 VMA_DQ13 FBB_CMD15 C17 F3 VMB_DQ15
<19> FBA_CMD13 FBA_CMD14 V33 FBA_CMD13 FBA_D13 E32 VMA_DQ14 VMA_DQ13 <19> <20> FBB_CMD15 FBB_CMD16 D18 FBB_CMD15 FBC_D15 C2 VMB_DQ16 VMB_DQ15 <20>
FBA_CMD15 Y32 F30 VMA_DQ15 FBB_CMD17 E18 D4 VMB_DQ17
<19> FBA_CMD15 AA31 FBA_CMD15 FBA_D15 C34 VMA_DQ15 <19> <20> FBB_CMD17 F18 FBB_CMD17 FBC_D17 D3 VMB_DQ17 <20>
FBA_CMD16 VMA_DQ16 FBB_CMD18 VMB_DQ18
FBA_CMD17 AA29 D32 VMA_DQ17 FBB_CMD19 A20 C1 VMB_DQ19
FBA_CMD18 AA28 B33 VMA_DQ18 FBB_CMD20 B20 B3 VMB_DQ20
<19> FBA_CMD18 AC34 FBA_CMD18 FBA_D18 C33 VMA_DQ18 <19> <20> FBB_CMD20 C18 FBB_CMD20 FBC_D20 C4 VMB_DQ20 <20>
FBA_CMD19 VMA_DQ19 FBB_CMD21 VMB_DQ21
FBA_CMD20 AC33 F33 VMA_DQ20 FBB_CMD22 B18 B5 VMB_DQ22
<19> FBA_CMD20 FBA_CMD21 AA32 FBA_CMD20 FBA_D20 F32 VMA_DQ21 VMA_DQ20 <19> <20> FBB_CMD22 FBB_CMD23 G18 FBB_CMD22 FBC_D22 C5 VMB_DQ23 VMB_DQ22 <20>
FBA_CMD22 AA33 H33 VMA_DQ22 FBB_CMD24 G17 A11 VMB_DQ24
FBA_CMD23 Y28 H32 VMA_DQ23 FBB_CMD25 F17 C11 VMB_DQ25
<19> FBA_CMD23 FBA_CMD24 Y29 FBA_CMD23 FBA_D23 P34 VMA_DQ24 VMA_DQ23 <19> <20> FBB_CMD25 FBB_CMD26 D16 FBB_CMD25 FBC_D25 D11 VMB_DQ26 VMB_DQ25 <20>
FBA_CMD25 W 31 P32 VMA_DQ25 FBB_CMD27 A18 B11 VMB_DQ27
<19> FBA_CMD25 FBA_CMD26 Y30 FBA_CMD25 FBA_D25 P31 VMA_DQ26 VMA_DQ25 <19> <20> FBB_CMD27 FBB_CMD28 D17 FBB_CMD27 FBC_D27 D8 VMB_DQ28 VMB_DQ27 <20>
FBA_CMD27 AA34 P33 VMA_DQ27 FBB_CMD29 A17 A8 VMB_DQ29
FBA_CMD28 Y31 L31 VMA_DQ28 FBB_CMD30 B17 C8 VMB_DQ30
<19> FBA_CMD28 FBA_CMD29 Y34 FBA_CMD28 FBA_D28 L34 VMA_DQ29 VMA_DQ28 <19> <20> FBB_CMD30 FBB_CMD31 E17 FBC_CMD30 FBC_D30 B8 VMB_DQ31 VMB_DQ30 <20>
<19> FBA_CMD29 FBA_CMD29 FBA_D29 VMA_DQ29 <19> <20> FBB_CMD31 FBC_CMD31 FBC_D31 VMB_DQ31 <20>
FBA_CMD30 Y33 L32 VMA_DQ30 F24 VMB_DQ32
<19> FBA_CMD30 V31 FBA_CMD30 FBA_D30 L33 VMA_DQ30 <19> FBC_D32 G23 VMB_DQ32 <20>
FBA_CMD31 VMA_DQ31 VMB_DQ33
<19> FBA_CMD31 FBA_CMD31 FBA_D31 VMA_DQ31 <19> FBC_D33 VMB_DQ33 <20>
AG28 VMA_DQ32 FBB_DBI0 E11 E24 VMB_DQ34
FBA_D32 VMA_DQ32 <19> <20> FBB_DBI[7:0] FBC_DQM0 FBC_D34 VMB_DQ34 <20>
AF29 VMA_DQ33 FBB_DBI1 E3 G24 VMB_DQ35
FBA_DBI0 P30 FBA_D33 AG29 VMA_DQ34 VMA_DQ33 <19> FBB_DBI2 A3 FBC_DQM1 FBC_D35 D21 VMB_DQ36 VMB_DQ35 <20>
<19> FBA_DBI[7:0] FBA_DQM0 FBA_D34 VMA_DQ34 <19> FBC_DQM2 FBC_D36 VMB_DQ36 <20>
FBA_DBI1 F31 AF28 VMA_DQ35 FBB_DBI3 C9 E21 VMB_DQ37
FBA_DBI2 F34 FBA_DQM1 FBA_D35 AD30 VMA_DQ36 VMA_DQ35 <19> FBB_DBI4 F23 FBC_DQM3 FBC_D37 G21 VMB_DQ38 VMB_DQ37 <20>
FBA_DBI3 M32 FBA_DQM2 FBA_D36 AD29 VMA_DQ37 VMA_DQ36 <19> FBB_DBI5 F27 FBC_DQM4 FBC_D38 F21 VMB_DQ39 VMB_DQ38 <20>
FBA_DBI4 AD31 FBA_DQM3 FBA_D37 AC29 VMA_DQ38 VMA_DQ37 <19> FBB_DBI6 C30 FBC_DQM5 FBC_D39 G27 VMB_DQ40 VMB_DQ39 <20>
FBA_DBI5 AL29 FBA_DQM4 FBA_D38 AD28 VMA_DQ39 VMA_DQ38 <19> FBB_DBI7 A24 FBC_DQM6 FBC_D40 D27 VMB_DQ41 VMB_DQ40 <20>
FBA_DBI6 AM32 FBA_DQM5 FBA_D39 AJ29 VMA_DQ40 VMA_DQ39 <19> FBC_DQM7 FBC_D41 G26 VMB_DQ42 VMB_DQ41 <20>
B FBA_DBI7 AF34 FBA_DQM6 FBA_D40 AK29 VMA_DQ41 VMA_DQ40 <19> FBC_D42 E27 VMB_DQ43 VMB_DQ42 <20> B
FBA_DQM7 FBA_D41 AJ30 VMA_DQ42 VMA_DQ41 <19> FBB_EDC0 D10 FBC_D43 E29 VMB_DQ44 VMB_DQ43 <20>
FBA_D42 VMA_DQ42 <19> <20> FBB_EDC[7:0] FBC_DQS_W P0 FBC_D44 VMB_DQ44 <20>
AK28 VMA_DQ43 FBB_EDC1 D5 F29 VMB_DQ45
FBA_EDC0 M31 FBA_D43 AM29 VMA_DQ44 VMA_DQ43 <19> FBB_EDC2 C3 FBC_DQS_W P1 FBC_D45 E30 VMB_DQ46 VMB_DQ45 <20>
<19> FBA_EDC[7:0] FBA_DQS_W P0 FBA_D44 VMA_DQ44 <19> FBC_DQS_W P2 FBC_D46 VMB_DQ46 <20>
FBA_EDC1 G31 AM31 VMA_DQ45 FBB_EDC3 B9 D30 VMB_DQ47
FBA_EDC2 E33 FBA_DQS_W P1 FBA_D45 AN29 VMA_DQ46 VMA_DQ45 <19> FBB_EDC4 E23 FBC_DQS_W P3 FBC_D47 A32 VMB_DQ48 VMB_DQ47 <20>
FBA_EDC3 M33 FBA_DQS_W P2 FBA_D46 AM30 VMA_DQ47 VMA_DQ46 <19> FBB_EDC5 E28 FBC_DQS_W P4 FBC_D48 C31 VMB_DQ49 VMB_DQ48 <20>
FBA_EDC4 AE31 FBA_DQS_W P3 FBA_D47 AN31 VMA_DQ48 VMA_DQ47 <19> FBB_EDC6 B30 FBC_DQS_W P5 FBC_D49 C32 VMB_DQ50 VMB_DQ49 <20>
FBA_EDC5 AK30 FBA_DQS_W P4 FBA_D48 AN32 VMA_DQ49 VMA_DQ48 <19> FBB_EDC7 A23 FBC_DQS_W P6 FBC_D50 B32 VMB_DQ51 VMB_DQ50 <20>
FBA_EDC6 AN33 FBA_DQS_W P5 FBA_D49 AP30 VMA_DQ50 VMA_DQ49 <19> FBC_DQS_W P7 FBC_D51 D29 VMB_DQ52 VMB_DQ51 <20>
FBA_EDC7 AF33 FBA_DQS_W P6 FBA_D50 AP32 VMA_DQ51 VMA_DQ50 <19> FBC_D52 A29 VMB_DQ53 VMB_DQ52 <20>
FBA_DQS_W P7 FBA_D51 AM33 VMA_DQ52 VMA_DQ51 <19> D9 FBC_D53 C29 VMB_DQ54 VMB_DQ53 <20>
FBA_D52 AL31 VMA_DQ53 VMA_DQ52 <19> E4 FBC_DQS_RN0 FBC_D54 B29 VMB_DQ55 VMB_DQ54 <20>
M30 FBA_D53 AK33 VMA_DQ54 VMA_DQ53 <19> B2 FBC_DQS_RN1 FBC_D55 B21 VMB_DQ56 VMB_DQ55 <20>
H30 FBA_DQS_RN0 FBA_D54 AK32 VMA_DQ55 VMA_DQ54 <19> A9 FBC_DQS_RN2 FBC_D56 C23 VMB_DQ57 VMB_DQ56 <20>
E34 FBA_DQS_RN1
FBA_DQS_RN2
FBA_D55
FBA_D56
AD34 VMA_DQ56 VMA_DQ55
VMA_DQ56
<19>
<19>
GDDR5 NO USE D22 FBC_DQS_RN3
FBC_DQS_RN4
FBC_D57
FBC_D58
A21 VMB_DQ58 VMB_DQ57
VMB_DQ58
<20>
<20>
M34 AD32 VMA_DQ57 D28 C21 VMB_DQ59
GDDR5 NO USE AF30 FBA_DQS_RN3
FBA_DQS_RN4
FBA_D57
FBA_D58
AC30 VMA_DQ58 VMA_DQ57
VMA_DQ58
<19>
<19>
A30 FBC_DQS_RN5
FBC_DQS_RN6
FBC_D59
FBC_D60
B24 VMB_DQ60 VMB_DQ59
VMB_DQ60
<20>
<20>
AK31 AD33 VMA_DQ59 B23 C24 VMB_DQ61
AM34 FBA_DQS_RN5 FBA_D59 AF31 VMA_DQ60 VMA_DQ59 <19> FBC_DQS_RN7 FBC_D61 B26 VMB_DQ62 VMB_DQ61 <20>
AF32 FBA_DQS_RN6 FBA_D60 AG34 VMA_DQ61 VMA_DQ60 <19> FBC_D62 C26 VMB_DQ63 VMB_DQ62 <20>
FBA_DQS_RN7 FBA_D61 AG32 VMA_DQ62 VMA_DQ61 <19> FBC_D63 VMB_DQ63 <20>
FBA_D62 AG33 VMA_DQ63 VMA_DQ62 <19>
AA27 FBA_D63 VMA_DQ63 <19> D12
+1.35V_GFX FBVDDQ_1 FBC_CLK0 VMB_CLK0 <20>
AA30 E12
AB27 FBVDDQ_2 R30 FBC_CLK0_N E20 VMB_CLK0# <20>
FBVDDQ_3 FBA_CLK0 VMA_CLK0 <19> FBC_CLK1 VMB_CLK1 <20>
AB33 R31 F20
FBVDDQ_4 FBA_CLK0_N VMA_CLK0# <19> FBC_CLK1_N VMB_CLK1# <20>
AC27 AB31
AD27 FBVDDQ_5 FBA_CLK1 AC31 VMA_CLK1 <19>
FBVDDQ_6 FBA_CLK1_N VMA_CLK1# <19>
AE27 G14 FBB_DEBUG0_K
AF27 FBVDDQ_7 FBB_CMD32 G20 TP4104
C4100 EV@1U/6.3V_4 FBB_DEBUG1_K
FBVDDQ_8 FBB_CMD33 TP4105
C C4101 EV@1U/6.3V_4 AG27 R28 FBA_DEBUG0_K C12 FBB_DEBUG0 R4100 *EV@60.4/F_4 C
FBVDDQ_9 FBA_CMD32 TP4106 FBB_CMD34 +1.35V_GFX
C4102 EV@1U/6.3V_4 B13 AC28 FBA_DEBUG1_K C20 FBB_DEBUG1 R4102 *EV@60.4/F_4
FBVDDQ_10 FBA_CMD33 TP4107 FBB_CMD35
C4103 EV@1U/6.3V_4 B19 R32 FBA_DEBUG0 *EV@60.4/F_4 R4103
FBVDDQ_12 FBA_CMD34 +1.35V_GFX
E13 AC32 FBA_DEBUG1 *EV@60.4/F_4 R4105
E19 FBVDDQ_13 FBA_CMD35 F8
B2A H10 FBVDDQ_15 H26 FBB_W CK01 E8 VMB_WCK01 <20>
FBVDDQ_16 FB_VREF FBB_W CK01_N VMB_WCK01# <20>
C4104 EV@0.1U/16V_4 H11 A5
H12 FBVDDQ_17 K31 FBB_W CK23 A6 VMB_WCK23 <20>
C4105 EV@0.1U/16V_4
FBVDDQ_18 FBA_W CK01 VMA_WCK01 <19> FBB_W CK23_N VMB_WCK23# <20>
C4106 EV@0.1U/16V_4 H13 L30 D24
H14 FBVDDQ_19 FBA_W CK01_N H34 VMA_WCK01# <19> FBB_W CK45 D25 VMB_WCK45 <20>
C4107 EV@0.1U/16V_4
FBVDDQ_20 FBA_W CK23 VMA_WCK23 <19> FBB_W CK45_N VMB_WCK45# <20>
H18 J34 B27
FBVDDQ_23 FBA_W CK23_N VMA_WCK23# <19> FBB_W CK67 VMB_WCK67 <20>
H19 AG30 C27
H20 FBVDDQ_24 FBA_W CK45 AG31 VMA_WCK45 <19> FBB_W CK67_N VMB_WCK67# <20>
FBVDDQ_25 FBA_W CK45_N VMA_WCK45# <19>
H21 AJ34
H22 FBVDDQ_26 FBA_W CK67 AK34 VMA_WCK67 <19> D6
EV@HCB1005KF-330T30 L4207 +1.05V_GFX
FBVDDQ_27 FBA_W CK67_N VMA_WCK67# <19> NC
H23 D7
H24 FBVDDQ_28 J30 C4719 EV@0.1U/16V_4 NC C6
H8 FBVDDQ_29 NC J31 R4114 EV@10K_4 NC B6
H9 FBVDDQ_30 NC J32 NC F26
L27 FBVDDQ_31 NC J33 C4721 EV@22U/6.3V_6 NC E26
M27 FBVDDQ_32 NC AH31 NC A26
N27 FBVDDQ_33 NC AJ31 NC A27
PLACE CLOSE TO BGA P27 FBVDDQ_34 NC AJ32 *SP@HCB1005KF-330T30 L4206 NC
FBVDDQ_35 NC +3V_MAIN For 16E
R27 AJ33 C262 close to H27 (under GPU)
C4108 EV@4.7U/6.3V_4 T27 FBVDDQ_36 NC SP@HCB1005KF-330T30 L4100 H17 FB_PLLAVDD
FBVDDQ_37 +1.05V_GFX For 16P FBB_PLL_AVDD
C4109 EV@4.7U/6.3V_4 T30 E1 PS_FB_CLAMP +FB_PLLAVDD : 62mA
C4110 EV@4.7U/6.3V_4 T33 FBVDDQ_38 FB_CLAMP B2A
C4113 EV@4.7U/6.3V_4 Y27 FBVDDQ_39 K27 FB_DLLAVDD C4114 EV@0.1U/16V_4 B2A
FBVDDQ_44 FB_DLL_AVDD C574 close to K27 (under GPU)
C4111 EV@10U/6.3V_6 C4112
C4115 EV@10U/6.3V_4 U27 FB_PLLAVDD +1.35V_GFX C4116 EV@0.1U/16V_4 C575 close to U27 (under GPU) EV@0.1U/16V_4
FBA_PLL_AVDD
B16 F1 FBVDDQ_SENSE
C576 near to GPU
D R4115 *EV@0_4 D
C4117 *EV@10U/6.3V_4 E16 FBVDDQ_AON_1 FB_VDDQ_SENSE C4118 EV@10U/6.3V_4
C4815 *EV@10U/6.3V_4 H15 FBVDDQ_AON_2 F2 FB_GND_SENSE R4116 *EV@0_4 C4812 EV@10U/6.3V_4
H16 FBVDDQ_AON_3 FB_GND_SENSE
C4119 EV@22U/6.3V_6 V27 FBVDDQ_AON_4 J27 FB_CAL_PD_VDDQ R4117 EV@40.2/F_4
FBVDDQ_AON_5 FB_CAL_PD_VDDQ +1.35V_GFX
W 27
W 30 FBVDDQ_AON_6 H27 FB_CAL_PU_GND R4118 EV@42.2/F_4
FBVDDQ_AON_7 FB_CAL_PU_GND +1.35V_GFX <19,20,42>
W 33
FBVDDQ_AON_8
FB_CALTERM_GND
H25 FB_CAL_TERM_GND R4119 EV@60.4/F_4
+1.05V_GFX <14,16,42>
PROJECT : ZAA
N16 - 2/5 (Memory) 1A

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
U3002D
SP@N16P-GT
AH8 AM6
IFPAB_PLLVDD IFPA_TXC AN6
[IFPA/B_LVDS] IFPA_TXC_N AP3
AG8 IFPA_TXD0 AN3
IFPA_IOVDD IFPA_TXD0_N AN5
AG9 IFPA_TXD1 AM5
IFPB_IOVDD IFPA_TXD1_N
IFPA_TXD2
AL6
AK6
3V_MAIN_PWGD +3V_GFX
IFPA_TXD2_N AJ6
A A
AJ8 IFPA_TXD3 AH6
IFPAB_RSET IFPA_TXD3_N
AJ9 +3V
IFPB_TXC AH9 R4200
IFPB_TXC_N AP6 EV@1.5K/F_4
IFPB_TXD4 AP5
+3V_MAIN <14,15,17> IFPB_TXD4_N AM7 R4201 3V_MAIN_PW GD
+1.05V_GFX <14,15,42> IFPB_TXD5 3V_MAIN_PW GD <41,42>
AL7 EV@4.7K_4
+3V_GFX <14,17,31,42> IFPB_TXD5_N
3
AN8
+3V <2,4,6,7,8,9,12,13,14,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42> IFPB_TXD6 AM8 R4202
IFPB_TXD6_N AK8 2
IFPB_TXD7 *EV@100K/F_4
3
AL8
IFPB_TXD7_N R4203 EV@4.7K_4 2
+3V_MAIN
C4200 Q4200
1
AF7 AG3 Q4201 EV@1000p/50V_4 EV@DTC144EU
1
IFPC_PLLVDD IFPC_AUX_I2CW_SCL AG2 C4201 EV@MMBT3904-7-F
AG7
[IFPC/D_TMDS]IFPC_AUX_I2CW_SDA_N AK1 *EV@1000p/50V_4
IFPD_PLLVDD IFPC_L0 +1.05V_GFX and GPU core power EN
AJ1
IFPC_L0_N AJ3
IFPC_L1 AJ2
IFPC_L1_N AH3
IFPC_L2 AH4
IFPC_L2_N AG5
AF6 IFPC_L3 AG4
IFPC_IOVDD IFPC_L3_N
AG6 AK3
IFPD_IOVDD IFPD_AUX_I2CX_SCL AK2
IFPD_AUX_I2CX_SDA_N AM1
B IFPD_L0 AM2 B
IFPD_L0_N AM3
AF8 IFPD_L1 AM4
IFPC_RSET IFPD_L1_N AL3
AN2 IFPD_L2 AL4
NC IFPD_L2_N AK4 +3V_GFX
IFPD_L3 AK5
IFPD_L3_N
DGPU_PGOK-1
AB8 AB3 +3V R4204
IFPEF_PLLVDD IFPE_AUX_I2CY_SCL AB4 EV@4.7K_4
[IFPE/F_DP] IFPE_AUX_I2CY_SDA_N AD2
AC7 IFPE_L0 AD3
AC8 IFPE_IOVDD IFPE_L0_N AD1 R4205
IFPF_IOVDD IFPE_L1 DGPU_PW ROK <4>
AC1 EV@4.7K_4
IFPE_L1_N AC2
IFPE_L2
3
AD6 AC3
IFPEF_RSET IFPE_L2_N AC4
IFPE_L3 AC5 2 Q4202 R4206
IFPE_L3_N
3
EV@100K/F_4
AF3 R4207 EV@4.7K_4 DGPU_POK2 2 Q4203 EV@DTC144EUA
IFPF_AUX_I2CZ_SCL <42> HW PG_1.35VGFX
AF2 EV@METR3904-G
1
IFPF_AUX_I2CZ_SDA_N AE3 C4202
1
IFPF_L0 AE4 C4203 EV@1000P/50V_4
IFPF_L0_N AF4 *EV@1000P/50V_4
IFPF_L1 AF5
IFPF_L1_N AD4
IFPF_L2 AD5
IFPF_L2_N AG1
C IFPF_L3 AF1 C
IFPF_L3_N
AG10 AK9
DACA_VDD DACA_RED AL10
[DACA/B_CRT] DACA_GREEN AL9
AP9 DACA_BLUE
DACA_VREF
AM9
AP8 DACA_HSYNC AN9
DACA_RSET DACA_VSYNC XTAL27_IN
XTAL27_OUT
Y4200
R4 I2CA_SCL EV@1.8K/F_4 R4208
I2CA_SCL R5 I2CA_SDA EV@1.8K/F_4 R4209 3 2
I2CA_SDA 4 1
PLACE CLOSE TO GPU PLACE CLOSE TO BALLS
PLLVDD : 200mA EV@27MHZ_10
+1.05V_GFX L4200 EV@HCB1005KF-330T30 NV_PLLVDD AD8
PLLVDD
B2A Reserve C4206 C4207
C4204 C4205 EV@10P/50V_4 EV@10P/50V_4
EV@22U/6.3V_6 EV@0.1U/16V_4 +3V_GFX
B2A
XTAL_OUTBUFF R4210 *EV@10K_4
PLLVDD AE8
SP_PLLVDD
C5092 Close to AE8
D D
C5090 Close to AD7AD7 H3 XTAL27_IN
L4201 EV@BLM15PX181SN1D_1.5A XTAL_IN H2 XTAL27_OUT
+1.05V_GFX VID_PLLVDD XTAL_OUT
[XTAL IN] J4 XTAL_OUTBUFF R4211 EV@10K_4
XTAL_OUTBUFF H1
B2A XTAL_SSIN
XTAL_SSIN R4212 EV@10K_4
C4208 C4209 C4210 C4211
EV@22U/6.3V_6 EV@4.7U/6.3V_4 EV@0.1U/16V_4 EV@0.1U/16V_4
PROJECT : ZAA
WWW.AliSaler.Com
1A
N16 - 3/5 (Display)
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Package DevID
Default setting : N16S-GTR, Sansung 4GB (default)
0x134D
N16S-GTR GB4b-128
+3V_GFX +3V_MAIN
STRAP0
DG : STUFF 50KΩ PU TO 3.3V_AON N16S-GT1-KA GB4b-128 0x179c
GT1-KA/KB
N16S-GT1-KB GB4b-128 0x179c
2
R4300 R4301 R4302 R4303 R4304
EV@49.9K/F_4 *EV@45.3K/F_4 *EV@15K/F_4 *EV@34.8K/F_4 *EV@20K/F_4 R4305 R4306 R4307
SP@4.99K/F_4 SP@4.99K/F_4 *EV@10K/F_4
Resistor P/N
1
A
STRAP0 4.99K---> CS24992FB26 A
STRAP1 ROM_SI
STRAP2 ROM_SO 10K ---> CS31002FB26
STRAP3 ROM_SCLK 15K ---> CS31502FB24
U3002E STRAP4
SP@N16P-GT 20K ---> CS32002FB29
R4308 R4309 R4310 R4311 R4312
R4313
SP@4.99K/F_4
R4314
SP@4.99K/F_4
R4315
EV@4.99K/F_4
24.9K --->CS32492FB16
[MIOA] *EV@4.99K/F_4 *EV@4.99K/F_4 *EV@24.9K/F_4 *EV@4.99K/F_4 *EV@45.3K/F_4 30.1K --->CS33012FB18
34.8K---> CS33482FB22
45.3K ---> CS34532FB18
+3V_GFX
GTR 49.9K ---> CS34992FB10
R4316 EV@10K_4 GPU_OVT# N16S-GTR VRAM Configuration Table: N16S-GTR-B-A2 GM108-770-A2 AJ0N16S0T24
R4317 EV@10K_4 GPU_ALERT
R4318 EV@10K_4 GPU_EVENT#_D ROM_SI DESCRIPTION Vendor Vendor P/N STN P/N ROM_SI
R4319 EV@10K_4 GPIO12_ACIN PU +3V_MAIN PD 4GbX2 0011 (0x3) GDDR5 128MBx32,2500MHz SAMSUNG K4G41325FC-HC03 --C die AKG5PGDT505 20K Pull down
(1GB) 0110 (0x6) GDDR5 128MBx32,2500MHz HYNIX H5GC4H24AJR-T2C --A die AKG5PWUTW21 34.8K Pull down
R4320
Page14 PU
*EV@10K_4 +3V_MAIN_EN
4.99K 1000 0000
R4321 EV@10K_4 SYS_PEX_RST_MON#
10K 1001 0001 4GbX4 0011 (0x3) GDDR5 256MBx16,2500MHz SAMSUNG K4G41325FC-HC03 --C die AKG5PGDT505 20K Pull down
(2GB) 0110 (0x6) GDDR5 256MBx16,2500MHz HYNIX H5GC4H24AJR-T2C --A die AKG5PWUTW21 34.8K Pull down
R4322 EV@10K_4 GPU_PEX_RST_HOLD#
15K 1010 0010
8GbX2 0000 (0x0) GDDR5 256MBx32,2500MHz SAMSUNG K4G80325FB-HC03 --B die AKG5QGDT502 4.99K Pull down
R4323 *EV@10K_4 GPIO10_VREF
20K 1011 0011 (2GB) 0001 (0x1) GDDR5 256MBx32,2500MHz MICRON MT51J256M32HF-60:A--A die AKG5LGUTL04 10K Pull down
R4324 EV@10K_4 DGPU_PSI
24.9K 1100 0100
8GbX4 0000 (0x0) GDDR5 512MBx16,2500MHz SAMSUNG K4G80325FB-HC03 --B die AKG5QGDT502 4.99K Pull down
30.1K 1101 0101 (4GB) 0001 (0x1) GDDR5 512MBx16,2500MHz MICRON MT51J256M32HF-60:A--A die AKG5LGUTL04 10K Pull down
B [MIOB] B
R4325 EV@10K_4 GPIO10_VREF
34.8K 1110 0110
R4326 EV@10K_4 GC6_FB_EN_R
45.3K 1111 0111
N16S-GT1-KA-A2 GM107-710-KA-A2 AJ0N16S0T22
N16S-GT1-KA/KB-A2 VRAM Configuration Table: N16S-GT1-KB-A2 GM107-710-KB-A2 AJ0N16S0T23
Mutil-level mode strapping: ROM_SI DESCRIPTION Vendor Vendor P/N STN P/N ROM_SI
Reserve PU/PD for Debug Rx=40.2k PD 4GbX2

(1GB)
0011 (0x3)
0110 (0x6)
GDDR5 128MBx32,2500MHz
GDDR5 128MBx32,2500MHz
SAMSUNG
HYNIX
K4G41325FC-HC03 --C die
H5GC4H24AJR-T2C --A die
AKG5PGDT505
AKG5PWUTW21
20K Pull down
34.8K Pull down
+3V_MAIN 1.ROM_SCLK =4.99K PD
2.ROM_SO = 4.99K PD for GTR ; 4GbX4 0011 (0x3) GDDR5 256MBx16,2500MHz SAMSUNG K4G41325FC-HC03 --C die AKG5PGDT505 20K Pull down
R4330 *EV@10K_4 JTAG_TMS
4.99K UP for GT1-KA/KB (2GB) 0110 (0x6) GDDR5 256MBx16,2500MHz HYNIX H5GC4H24AJR-T2C --A die AKG5PWUTW21 34.8K Pull down
R4331 *EV@10K_4 JTAG_TDI 3.ROM_SI= VRAM Configuration Table 8GbX2 0000 (0x8) GDDR5 256MBx32,2500MHz SAMSUNG K4G80325FB-HC03 --B die AKG5QGDT502 4.99K Pull up
R4332 *EV@10K_4 JTAG_TCK 4.STRAP0 = 49.9k PU (2GB) 0001 (0x9) GDDR5 256MBx32,2500MHz MICRON MT51J256M32HF-60:A--A die AKG5LGUTL04 10K Pull up
R4334 EV@10K_4 JTAG_TRST# 5.Strap4~1 = Reserve Pull up and Pull down
8GbX4 0000 (0x8) GDDR5 512MBx16,2500MHz SAMSUNG K4G80325FB-HC03 --B die AKG5QGDT502 4.99K Pull up
(4GB) 0001 (0x9) GDDR5 512MBx16,2500MHz MICRON MT51J256M32HF-60:A--A die AKG5LGUTL04 10K Pull up
TP4300 JTAG_TCK AM10 P6 GC6_FB_EN_R

TP4301 JTAG_TMS AP11 JTAG_TCK GPIO0 M3 TP4302
TP4303 JTAG_TDI AM11 JTAG_TMS [MISC_GPIO/I2C/JTAG/THER] GPIO1 L6 TP4304 (GB4b-128)
TP4305 JTAG_TDO AP12 JTAG_TDI GPIO2 P5 TP4306
JTAG_TDO GPIO3
TP4307 JTAG_TRST# AN11
JTAG_TRST_N GPIO4
P7 TP4308 Logical Logical Logical Logical
GPIO5
L7 +3V_MAIN_EN
+3V_MAIN_EN <14> Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
M7 GPU_EVENT#_D
GPIO6
R4337 EV@1.8K/F_4 I2CB_SCL R7
I2CB_SCL GPIO7
N8 TP4309 ROM_SCLK SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED 0000
C R4338 EV@1.8K/F_4 I2CB_SDA R6 C
I2CB_SDA
GPIO8
L3 SYS_PEX_RST_MON# SYS_PEX_RST_MON# <14> ROM_SI RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0] Refer table
R4339 EV@1.8K/F_4 I2CC_SCL R2
I2CC_SCL ROM_SO DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE 0000 ---GTR
R4340 EV@1.8K/F_4 I2CC_SDA R3 M2 GPU_ALERT
I2CC_SDA GPIO9
GPIO10
L1 GPIO10_VREF GPIO10_VREF <19,20> 1000 ---GT1/KA/KB
M5
GPIO11 PWM-VID <41>
GFX_SCL T4
I2CS_SCL GPIO12
N3 GPIO12_ACIN STRAP0 Keep footprint to PU to 3V3_AON and PD to GND [Stuff 49.9K PU]
GFX_SDA T3 M4 DGPU_PSI
I2CS_SDA GPIO13 DGPU_PSI <41>
GPIO14
N4 STRAP1
P2 Keep footprint to PU to 3V3_AON and PD to GND [Do Not Stuff]
GPIO15
K4
THERMDN GPIO16
R8 STRAP2
K3 M6
THERMDP GPIO17
GPIO18
R1 STRAP3
P3
GPIO19
GPIO20
P4
+3V_GFX
STRAP4
P1 GPU_PEX_RST_HOLD#
GPIO21 GPU_PEX_RST_HOLD# <14>
+3V_GFX
2
H4 ROM_SCLK Q4300A *EV@ME2N7002DKW-G_115MA

STRAP0 J2 ROM_SCLK H6
STRAP1 J7 STRAP0 [MISC2_ROM] ROM_CS_N H5 ROM_SI GC6_FB_EN_R 1 6 R4328 *short_4 +3V_MAIN
STRAP1 ROM_SI GC6_FB_EN <4,14>
STRAP2 J6 H7 ROM_SO
STRAP3 J5 STRAP2 ROM_SO R4341 R4342
STRAP4 J3 STRAP3 R4329 EV@0_4
+3V_GFX STRAP4 EV@2.2K_4 EV@2.2K_4 GFx SMBus Isolation
+3V_GFX 5
L2 GPU_BUFRST R4343 *EV@10K_4
R4344 *EV@10K_4 MULTISTRAP_REF_GND J1 BUFRST_N GFX_SCL 4 3
MULTISTRAP_REF_GND 2ND_MBCLK <7,31>
5
Q4300B *EV@ME2N7002DKW-G_115MA
R4345 M1 GPU_OVT# GPU_EVENT#_D 4 3 R4335 *short_4 2

Rx EV@40.2K/F_4 OVERT DGPU_EVENT# <4>
GFX_SDA 1 6
R4336 EV@0_4 2ND_MBDATA <7,31>
B2A
D D
Q4302
EV@ME2N7002DKW-G_115MA
+3V_GFX
PEGX_RST# <14>
5
R4346 GPIO12_ACIN 4 3
+3V_GFX <14,16,31,42> <32> GPU_THROTTING# dGPU_OPP# <31>
GPU_OVT# 1 6 dGPU_OTP#
+3V_MAIN <14,15,16>
*EV@0_4 Q4301B
EV@ME2N7002DKW-G_115MA Q4301A
dGPU_OTP# <31>
GPIO12 AC detect EV@ME2N7002DKW-G_115MA
AC high
B2A PROJECT : ZAA
DC low Size Document Number Rev
1A
N16 - 4/5 (MISC)
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
U3002G
VDD/XVDD : 43A SP@N16P-GT
A2 D2 +VGPU_CORE
+VGPU_CORE AA17 GND_1 GND_101 D31
U3002F +VGPU_CORE AA18 GND_2 [GPU GND] GND_102 D33
SP@N16P-GT AA20 GND_3 GND_103 E10
AA12 U1 AA22 GND_4 GND_104 E22 C4400 EV@1U/6.3V_4
AA14 VDD_001 XVDD_001 U2 AB12 GND_5 GND_105 E25 C4401 EV@1U/6.3V_4
AA16 VDD_002 [GPU VDD] XVDD_002 U3 AB14 GND_6 GND_106 E5 C4402 EV@1U/6.3V_4
AA19 VDD_003 XVDD_003 U4 AB16 GND_7 GND_107 E7 C4403 EV@1U/6.3V_4
PLACE UNDER GPU
AA21 VDD_004 XVDD_004 U5 AB19 GND_8 GND_108 F28 C4404 EV@1U/6.3V_4
AA23 VDD_005 XVDD_005 U6 AB2 GND_9 GND_109 F7 C4405 EV@1U/6.3V_4
A A
AB13 VDD_006 XVDD_006 U7 AB21 GND_10 GND_110 G10 C4406 EV@1U/6.3V_4
AB15 VDD_007 XVDD_007 U8 A33 GND_11 GND_111 G13 C4407 EV@1U/6.3V_4
AB17 VDD_008 XVDD_008 V1 AB23 GND_12 GND_112 G16
AB18 VDD_009 XVDD_009 V2 AB28 GND_13 GND_113 G19 C4408 EV@4.7U/6.3V_4
AC12 VDD_012 XVDD_012 V5 AB5 GND_16 GND_116 G25 C4411 EV@4.7U/6.3V_4
AC14 VDD_013 XVDD_013 V6 AB7 GND_17 GND_117 G28 C4412 EV@4.7U/6.3V_4
AC16 VDD_014 XVDD_014 V7 AC13 GND_18 GND_118 G3
AC19 VDD_015 XVDD_015 V8 AC15 GND_19 GND_119 G30
AC21 VDD_016 XVDD_016 W2 AC17 GND_20 GND_120 G32 C4413 SP@4.7U/6.3V_4
AC23 VDD_017 XVDD_017 W3 AC18 GND_21 GND_121 G33
B2A
M12 VDD_018 XVDD_018 W4 AA13 GND_22 GND_122 G5
M14 VDD_019 XVDD_019 W5 AC20 GND_23 GND_123 G7 C4414 EV@4.7U/6.3V_4
M16 VDD_020 XVDD_020 W7 AC22 GND_24 GND_124 K2 C4415 EV@4.7U/6.3V_4
M19 VDD_021 XVDD_021 W8 AE2 GND_25 GND_125 K28 C4416 EV@4.7U/6.3V_4
M21 VDD_022 XVDD_022 Y4 AE28 GND_26 GND_126 K30
M23 VDD_023 XVDD_026 Y5 AE30 GND_27 GND_127 K32
N13 VDD_024 XVDD_027 Y6 AE32 GND_28 GND_128 K33 C4417 SP@4.7U/6.3V_4
N15 VDD_025 XVDD_028 Y7 AE33 GND_29 GND_129 K5
B2A
N17 VDD_026 XVDD_029 Y8 AE5 GND_30 GND_130 K7
N18 VDD_027 XVDD_030 AE7 GND_31 GND_131 M13 C4418 EV@4.7U/6.3V_4
N20 VDD_028 AH10 GND_32 GND_132 M15
N22 VDD_029 AA15 GND_33 GND_133 M17
P12 VDD_030 AH13 GND_34 GND_134 M18 C4419 SP@4.7U/6.3V_4
P14 VDD_031 AH16 GND_35 GND_135 M20 C4420 *EV@4.7U/6.3V_4
B2A
P16 VDD_032 AH19 GND_36 GND_136 M22
P19 VDD_033 AH2 GND_37 GND_137 N12
B P21 VDD_034 AH22 GND_38 GND_138 N14 C4421 EV@4.7U/6.3V_4 B
P23 VDD_035 AH24 GND_39 GND_139 N16 C4422 EV@4.7U/6.3V_4
R13 VDD_036 AH28 GND_40 GND_140 N19
R15 VDD_037 AH29 GND_41 GND_141 N2
R17 VDD_038 AH30 GND_42 GND_142 N21
R18 VDD_039 AH32 GND_43 GND_143 N23
R20 VDD_040 AH33 GND_44 GND_144 N28 C4423 EV@10U/6.3V_4
R22 VDD_041 AH5 GND_45 GND_145 N30 C4814 EV@10U/6.3V_4
T12 VDD_042 AH7 GND_46 GND_146 N32 C44242 1 EV@22U/6.3V_6
T14 VDD_043 AJ7 GND_47 GND_147 N33 C44252 1 EV@22U/6.3V_6
T16 VDD_044 AK10 GND_48 GND_148 N5 C4426 EV@10U/6.3V_4
T19 VDD_045 AK7 GND_49 GND_149 N7 C4813 EV@10U/6.3V_4
T21 VDD_046 AL12 GND_50 GND_150 P13 C44272 1 EV@22U/6.3V_6
T23 VDD_047 AL14 GND_51 GND_151 P15 C44282 1 EV@22U/6.3V_6
U13 VDD_048 AL15 GND_52 GND_152 P17
B2A
U15 VDD_049 AL17 GND_53 GND_153 P18
U17 VDD_050 AL18 GND_54 GND_154 P20 C4429 2 1 EV@22U/6.3V_6
U18 VDD_051 AL2 GND_55 GND_155 P22
PLACE NEAR GPU
C4430 EV@4.7U/6.3V_4
U20 VDD_052 AL20 GND_56 GND_156 R12 C4431 EV@4.7U/6.3V_4
U22 VDD_053 AL21 GND_57 GND_157 R14
V13 VDD_054 AL23 GND_58 GND_158 R16
V15 VDD_055 AL24 GND_59 GND_159 R19 C4432 *EV@4.7U/6.3V_4
V17 VDD_056 AL26 GND_60 GND_160 R21
B2A
V18 VDD_057 AL28 GND_61 GND_161 R23
V20 VDD_058 AL30 GND_62 GND_162 T13
V22 VDD_059 AL32 GND_63 GND_163 T15 C4433 EV@4.7U/6.3V_4
W12 VDD_060 AL33 GND_64 GND_164 T17
W14 VDD_061 AL5 GND_65 GND_165 T18 C4434 EV@4.7U/6.3V_4
W16 VDD_062 AM13 GND_66 GND_166 T2
C W19 VDD_063 AM16 GND_67 GND_167 T20 C4435 330u/2V_7343 C
W21 VDD_064 AM19 GND_68 GND_168 T22
+
W23 VDD_065 AM22 GND_69 GND_169 AG11
Y13 VDD_066 AM25 GND_70 GND_170 T28
Y15 VDD_067 AN1 GND_71 GND_171 T32
Y18 VDD_068 AN10 GND_72 GND_172 T5
Y17 VDD_069 AN13 GND_73 GND_173 T7
Y20 VDD_070 AN16 GND_74 GND_174 U12
Y22 VDD_071 AN19 GND_75 GND_175 U14
VDD_072 AN22 GND_76 GND_176 U16
AN25 GND_77 GND_177 U19
AN30 GND_78 GND_178 U21
AN34 GND_79 GND_179 U23
AN4 GND_80 GND_180 V12
AN7 GND_81 GND_181 V14
AP2 GND_82 GND_182 V16
AP33 GND_83 GND_183 V19
B1 GND_84 GND_184 V21
B10 GND_85 GND_185 V23
+VGPU_CORE <41> GND_86 GND_186
B22 W13
B25 GND_87 GND_187 W15
B28 GND_88 GND_188 W17
B31 GND_89 GND_189 W18
B34 GND_90 GND_190 W20
B4 GND_91 GND_191 W22
B7 GND_92 GND_192 W28
C10 GND_93 GND_193 Y12
C13 GND_94 GND_194 Y14
C19 GND_95 GND_195 Y16
D GND_96 GND_196 D
C22 Y19
C25 GND_97 GND_197 Y21
C28 GND_98 GND_198 Y23
C7 GND_99 GND_199 AH11
GND_100 GND_200
C16
GND_OPT_1
W32
GND_OPT_2
PROJECT : ZAA
WWW.AliSaler.Com
1A
N16 - 5/5 (Power)
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
<15> VMA_DQ[63..0]
VMA_DQ[63..0]
For KB of GPUChannel CHANNEL A: 1G/2G GDDR5 X16

<15>
<15>
FBA_CMD[31:0]
FBA_DBI[7..0]
FBA_DBI[7..0]
Channel 0 0 Channel 1 Channel 1
<15> FBA_EDC[7..0]
FBA_EDC[7..0]
<0-31> <0-31> <32-63> <32-63>
MF=0 Non-mirrored MF=1 Mirrored MF=0 Non-mirrored MF=1 Mirrored
+1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX
VRAM3000 VRAM3004 VRAM3001 VRAM3005

M2 B1 M2 B1 M2 B1 M2 B1
M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3
N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12 N2 DQ30 | DQ6 VDDQ-B3 B12
T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1
T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3
U2 DQ26 | DQ2 VDDQ-D3 D12 U2 DQ26 | DQ2 VDDQ-D3 D12 U2 DQ26 | DQ2 VDDQ-D3 D12 U2 DQ26 | DQ2 VDDQ-D3 D12
A A
VMA_DQ23 M13 DQ24 | DQ0 VDDQ-D14 E5 VMA_DQ15 M13 DQ24 | DQ0 VDDQ-D14 E5 VMA_DQ55 M13 DQ24 | DQ0 VDDQ-D14 E5 VMA_DQ47 M13 DQ24 | DQ0 VDDQ-D14 E5
VMA_DQ22 M11 DQ23 | DQ15 VDDQ-E5 E10 VMA_DQ14 M11 DQ23 | DQ15 VDDQ-E5 E10 VMA_DQ54 M11 DQ23 | DQ15 VDDQ-E5 E10 VMA_DQ46 M11 DQ23 | DQ15 VDDQ-E5 E10
VMA_DQ21 N13 DQ22 | DQ14 VDDQ-E10 F1 VMA_DQ13 N13 DQ22 | DQ14 VDDQ-E10 F1 VMA_DQ53 N13 DQ22 | DQ14 VDDQ-E10 F1 VMA_DQ45 N13 DQ22 | DQ14 VDDQ-E10 F1
QD16~23 VMA_DQ20
VMA_DQ19
VMA_DQ18
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14 QD8~15
VMA_DQ12
VMA_DQ11
VMA_DQ10
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
QD48~55 VMA_DQ52
VMA_DQ51
VMA_DQ50
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
QD40~47 VMA_DQ44
VMA_DQ43
VMA_DQ42
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
VMA_DQ17 U13 G2 VMA_DQ9 U13 G2 VMA_DQ49 U13 G2 VMA_DQ41 U13 G2
VMA_DQ16 U11 DQ17 | DQ9 VDDQ-G2 G13 VMA_DQ8 U11 DQ17 | DQ9 VDDQ-G2 G13 VMA_DQ48 U11 DQ17 | DQ9 VDDQ-G2 G13 VMA_DQ40 U11 DQ17 | DQ9 VDDQ-G2 G13
F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3
F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12
E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3
E11 DQ13 | DQ21 VDDQ-K3 K12 E11 DQ13 | DQ21 VDDQ-K3 K12 E11 DQ13 | DQ21 VDDQ-K3 K12 E11 DQ13 | DQ21 VDDQ-K3 K12
B13 DQ12 | DQ20 VDDQ-K12 L2 B13 DQ12 | DQ20 VDDQ-K12 L2 B13 DQ12 | DQ20 VDDQ-K12 L2 B13 DQ12 | DQ20 VDDQ-K12 L2
B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13
A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1
A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3
VMA_DQ7 F2 DQ8 | DQ16 VDDQ-M3 M12 VMA_DQ31 F2 DQ8 | DQ16 VDDQ-M3 M12 VMA_DQ39 F2 DQ8 | DQ16 VDDQ-M3 M12 VMA_DQ63 F2 DQ8 | DQ16 VDDQ-M3 M12
VMA_DQ6 F4 DQ7 | DQ31 VDDQ-M12 M14 VMA_DQ30 F4 DQ7 | DQ31 VDDQ-M12 M14 VMA_DQ38 F4 DQ7 | DQ31 VDDQ-M12 M14 VMA_DQ62 F4 DQ7 | DQ31 VDDQ-M12 M14
VMA_DQ5 E2 DQ6 | DQ30 VDDQ-M14 N5 VMA_DQ29 E2 DQ6 | DQ30 VDDQ-M14 N5 VMA_DQ37 E2 DQ6 | DQ30 VDDQ-M14 N5 VMA_DQ61 E2 DQ6 | DQ30 VDDQ-M14 N5
QD0~7 VMA_DQ4
VMA_DQ3
VMA_DQ2
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3 QD24~31
VMA_DQ28
VMA_DQ27
VMA_DQ26
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3
QD32~39 VMA_DQ36
VMA_DQ35
VMA_DQ34
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3
QD56~63 VMA_DQ60
VMA_DQ59
VMA_DQ58
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3
VMA_DQ1 A2 P12 VMA_DQ25 A2 P12 VMA_DQ33 A2 P12 VMA_DQ57 A2 P12
VMA_DQ0 A4 DQ1 | DQ25 VDDQ-P12 P14 VMA_DQ24 A4 DQ1 | DQ25 VDDQ-P12 P14 VMA_DQ32 A4 DQ1 | DQ25 VDDQ-P12 P14 VMA_DQ56 A4 DQ1 | DQ25 VDDQ-P12 P14
DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1
VDDQ-T1 T3 VDDQ-T1 T3 VDDQ-T1 T3 VDDQ-T1 T3
VDDQ-T14 VDDQ-T14 VDDQ-T14 VDDQ-T14
FBA_CMD9 J5 FBA_CMD9 J5 FBA_CMD25 J5 FBA_CMD25 J5
FBA_CMD6 K4 RFU/A12/NC C5 FBA_CMD10 K4 RFU/A12/NC C5 FBA_CMD22 K4 RFU/A12/NC C5 FBA_CMD26 K4 RFU/A12/NC C5
FBA_CMD7 K5 A7/A8 | A0/A10 VDD-C5 C10 FBA_CMD11 K5 A7/A8 | A0/A10 VDD-C5 C10 FBA_CMD23 K5 A7/A8 | A0/A10 VDD-C5 C10 FBA_CMD27 K5 A7/A8 | A0/A10 VDD-C5 C10
FBA_CMD4 K10 A6/A11 | A1/A9 VDD-C10 D11 FBA_CMD1 K10 A6/A11 | A1/A9 VDD-C10 D11 FBA_CMD20 K10 A6/A11 | A1/A9 VDD-C10 D11 FBA_CMD17 K10 A6/A11 | A1/A9 VDD-C10 D11
FBA_CMD3 K11 A5/BA1 | A3/BA3 VDD-D11 G1 FBA_CMD2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 FBA_CMD19 K11 A5/BA1 | A3/BA3 VDD-D11 G1 FBA_CMD18 K11 A5/BA1 | A3/BA3 VDD-D11 G1
FBA_CMD1 H10 A4/BA2 | A2/BA0 VDD-G1 G4 FBA_CMD4 H10 A4/BA2 | A2/BA0 VDD-G1 G4 FBA_CMD17 H10 A4/BA2 | A2/BA0 VDD-G1 G4 FBA_CMD20 H10 A4/BA2 | A2/BA0 VDD-G1 G4
FBA_CMD2 H11 A3/BA3 | A5/BA1 VDD-G4 G11 FBA_CMD3 H11 A3/BA3 | A5/BA1 VDD-G4 G11 FBA_CMD18 H11 A3/BA3 | A5/BA1 VDD-G4 G11 FBA_CMD19 H11 A3/BA3 | A5/BA1 VDD-G4 G11
FBA_CMD11 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 FBA_CMD7 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 FBA_CMD27 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 FBA_CMD23 H5 A2 /BA0 | A4/BA2 VDD-G11 G14
FBA_CMD10 H4 A1/A9 | A6/A11 VDD-G14 L1 FBA_CMD6 H4 A1/A9 | A6/A11 VDD-G14 L1 FBA_CMD26 H4 A1/A9 | A6/A11 VDD-G14 L1 FBA_CMD22 H4 A1/A9 | A6/A11 VDD-G14 L1
A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4
VDD-L4 L11 VDD-L4 L11 VDD-L4 L11 VDD-L4 L11
VMA_WCK01 D4 VDD-L14 P11 VMA_WCK23 D4 VDD-L14 P11 VMA_WCK45 D4 VDD-L14 P11 VMA_WCK67 D4 VDD-L14 P11
<15> VMA_WCK01 WCK01 | WCK23 VDD-P11 WCK01 | WCK23 VDD-P11 <15> VMA_WCK45 WCK01 | WCK23 VDD-P11 WCK01 | WCK23 VDD-P11
<15> VMA_WCK01# VMA_WCK01# D5 R5 VMA_WCK23# D5 R5 <15> VMA_WCK45# VMA_WCK45# D5 R5 VMA_WCK67# D5 R5
B WCK01# | WCK23# VDD-R5 R10 WCK01# | WCK23# VDD-R5 R10 WCK01# | WCK23# VDD-R5 R10 WCK01# | WCK23# VDD-R5 R10 B
VMA_WCK23 P4 VDD-R10 VMA_WCK01 P4 VDD-R10 VMA_WCK67 P4 VDD-R10 VMA_WCK45 P4 VDD-R10
<15> VMA_WCK23 WCK23 | WCK01 WCK23 | WCK01 <15> VMA_WCK67 WCK23 | WCK01 WCK23 | WCK01
<15> VMA_WCK23# VMA_WCK23# P5 VMA_WCK01# P5 <15> VMA_WCK67# VMA_WCK67# P5 VMA_WCK45# P5
WCK23# | WCK01# A1 WCK23# | WCK01# A1 WCK23# | WCK01# A1 WCK23# | WCK01# A1
R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 R2 VSSQ-A1 A3
FBA_EDC2 R13 EDC3 | EDC0 VSSQ-A3 A12 FBA_EDC1 R13 EDC3 | EDC0 VSSQ-A3 A12 FBA_EDC6 R13 EDC3 | EDC0 VSSQ-A3 A12 FBA_EDC5 R13 EDC3 | EDC0 VSSQ-A3 A12
C13 EDC2 | EDC1 VSSQ-A12 A14 C13 EDC2 | EDC1 VSSQ-A12 A14 C13 EDC2 | EDC1 VSSQ-A12 A14 C13 EDC2 | EDC1 VSSQ-A12 A14
FBA_EDC0 C2 EDC1 | EDC2 VSSQ-A14 C1 FBA_EDC3 C2 EDC1 | EDC2 VSSQ-A14 C1 FBA_EDC4 C2 EDC1 | EDC2 VSSQ-A14 C1 FBA_EDC7 C2 EDC1 | EDC2 VSSQ-A14 C1
EDC0 | EDC3 VSSQ-C1 C3 EDC0 | EDC3 VSSQ-C1 C3 EDC0 | EDC3 VSSQ-C1 C3 EDC0 | EDC3 VSSQ-C1 C3
P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 P2 VSSQ-C3 C4
FBA_DBI2 P13 DBI3# | DBI0# VSSQ-C4 C11 FBA_DBI1 P13 DBI3# | DBI0# VSSQ-C4 C11 FBA_DBI6 P13 DBI3# | DBI0# VSSQ-C4 C11 FBA_DBI5 P13 DBI3# | DBI0# VSSQ-C4 C11
D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12
FBA_DBI0 D2 DBI1# | DBI2# VSSQ-C12 C14 FBA_DBI3 D2 DBI1# | DBI2# VSSQ-C12 C14 FBA_DBI4 D2 DBI1# | DBI2# VSSQ-C12 C14 FBA_DBI7 D2 DBI1# | DBI2# VSSQ-C12 C14
DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1
VSSQ-E1 E3 VSSQ-E1 E3 VSSQ-E1 E3 VSSQ-E1 E3
FBA_CMD12 G3 VSSQ-E12 E14 FBA_CMD15 G3 VSSQ-E12 E14 FBA_CMD28 G3 VSSQ-E12 E14 FBA_CMD31 G3 VSSQ-E12 E14
FBA_CMD15 L3 RAS# | CAS# VSSQ-E14 F5 FBA_CMD12 L3 RAS# | CAS# VSSQ-E14 F5 FBA_CMD31 L3 RAS# | CAS# VSSQ-E14 F5 FBA_CMD28 L3 RAS# | CAS# VSSQ-E14 F5
CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10
VSSQ-F10 H2 VSSQ-F10 H2 VSSQ-F10 H2 VSSQ-F10 H2
FBA_CMD14 J3 VSSQ-H2 H13 FBA_CMD14 J3 VSSQ-H2 H13 FBA_CMD30 J3 VSSQ-H2 H13 FBA_CMD30 J3 VSSQ-H2 H13
VMA_CLK0# J11 CKE# VSSQ-H13 K2 VMA_CLK0# J11 CKE# VSSQ-H13 K2 VMA_CLK1# J11 CKE# VSSQ-H13 K2 VMA_CLK1# J11 CKE# VSSQ-H13 K2
<15> VMA_CLK0# CK# VSSQ-K2 CK# VSSQ-K2 <15> VMA_CLK1# CK# VSSQ-K2 CK# VSSQ-K2
VMA_CLK0 J12 K13 VMA_CLK0 J12 K13 VMA_CLK1 J12 K13 VMA_CLK1 J12 K13
<15> VMA_CLK0 CK VSSQ-K13 CK VSSQ-K13 <15> VMA_CLK1 CK VSSQ-K13 CK VSSQ-K13
M5 M5 M5 M5
VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10
FBA_CMD0 G12 VSSQ-M10 N1 FBA_CMD5 G12 VSSQ-M10 N1 FBA_CMD16 G12 VSSQ-M10 N1 FBA_CMD21 G12 VSSQ-M10 N1
FBA_CMD5 L12 CS# | WE# VSSQ-N1 N3 FBA_CMD0 L12 CS# | WE# VSSQ-N1 N3 FBA_CMD21 L12 CS# | WE# VSSQ-N1 N3 FBA_CMD16 L12 CS# | WE# VSSQ-N1 N3
WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12
VSSQ-N12 N14 VSSQ-N12 N14 VSSQ-N12 N14 VSSQ-N12 N14
R4546 GKB@120/F_4 J13 VSSQ-N14 R1 R4549 GKB@120/F_4 J13 VSSQ-N14 R1 R4552 GKB@120/F_4 J13 VSSQ-N14 R1 R4555 GKB@120/F_4 J13 VSSQ-N14 R1
R4547 GKB@1K_4SEN_A0 J10 ZQ VSSQ-R1 R3 SEN_A1 J10 ZQ VSSQ-R1 R3 R4553 GKB@1K_4SEN_A2 J10 ZQ VSSQ-R1 R3 SEN_A3 J10 ZQ VSSQ-R1 R3
SEN VSSQ-R3 R4 R4550 GKB@1K_4 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 R4556 GKB@1K_4 SEN VSSQ-R3 R4
VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11
FBA_CMD13 J2 VSSQ-R11 R12 FBA_CMD13 J2 VSSQ-R11 R12 FBA_CMD29 J2 VSSQ-R11 R12 FBA_CMD29 J2 VSSQ-R11 R12
J1 RESET# VSSQ-R12 R14 J1 RESET# VSSQ-R12 R14 J1 RESET# VSSQ-R12 R14 J1 RESET# VSSQ-R12 R14
MF VSSQ-R14 +1.35V_GFX MF VSSQ-R14 MF VSSQ-R14 +1.35V_GFX MF VSSQ-R14
R4548 GKB@1K_4 U1 R4551 GKB@1K_4 U1 R4554 GKB@1K_4 U1 R4557 GKB@1K_4 U1
VSSQ-V1 U3 VSSQ-V1 U3 VSSQ-V1 U3 VSSQ-V1 U3
A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14
U5 Vpp,NC U5 Vpp,NC U5 Vpp,NC U5 Vpp,NC
16mils Vpp,NC1
VSS-B5
B5 16mils Vpp,NC1
VSS-B5
B5 16mils Vpp,NC1
VSS-B5
B5 16mils Vpp,NC1
VSS-B5
B5
VREFD_VMA1 A10 B10 VREFD_VMA2 A10 B10 VREFD_VMA3 A10 B10 VREFD_VMA4 A10 B10
U10 VREFD1 VSS-B10 D10 U10 VREFD1 VSS-B10 D10 U10 VREFD1 VSS-B10 D10 U10 VREFD1 VSS-B10 D10
VREFD2 VSS-D10 G5 VREFD2 VSS-D10 G5 VREFD2 VSS-D10 G5 VREFD2 VSS-D10 G5
C C
VSS-G5 G10 VSS-G5 G10 VSS-G5 G10 VSS-G5 G10
VSS-G10 H1 VSS-G10 H1 VSS-G10 H1 VSS-G10 H1
VSS-H1 H14 VSS-H1 H14 VSS-H1 H14 VSS-H1 H14
16mils VSS-H14
VSS-K1
K1 16mils VSS-H14
VSS-K1
K1 16mils VSS-H14
VSS-K1
K1 16mils VSS-H14
VSS-K1
K1
VREFC_VMA1 J14 K14 VREFC_VMA2 J14 K14 VREFC_VMA3 J14 K14 VREFC_VMA4 J14 K14
VREFC VSS-K14 L5 VREFC VSS-K14 L5 VREFC VSS-K14 L5 VREFC VSS-K14 L5
VSS-L5 L10 VSS-L5 L10 VSS-L5 L10 VSS-L5 L10
VSS-L10 P10 VSS-L10 P10 VSS-L10 P10 VSS-L10 P10
FBA_CMD8 J4 VSS-P10 T5 FBA_CMD8 J4 VSS-P10 T5 FBA_CMD24 J4 VSS-P10 T5 FBA_CMD24 J4 VSS-P10 T5
ABI# VSS-T5 T10 ABI# VSS-T5 T10 ABI# VSS-T5 T10 ABI# VSS-T5 T10
VSS-T10 VSS-T10 VSS-T10 VSS-T10
GKB@GDDR5 VRAM3000 GKB@GDDR5 VRAM3004 GKB@GDDR5 VRAM3001 GKB@GDDR5 VRAM3005
SAMSUNG GDDR5 5Gbps 4Gb K4G41325FC-HC03 LF+HF 256*16 AKG5PGDT505 B/S PN

HYNIX GDDR5 5Gbps 4Gb H5GC4H24AJR-T2C LF+HF 256*16 A-die AKG5PWUTW21 B/S PN
MICRON GDDR5 5Gbps 8Gb MT51J256M32HF-60:A LF+HF AKG5LGUTL04 B/S PN
VREF_VMA1_MOS VREF_VMA1_MOS
SAMSUNG GDDR5 5Gbps 8Gb K4G80325FB-HC03 LF+HF AKG5QGDT502B/S PN VREF_VMA3_MOS VREF_VMA3_MOS
VREF_VMA1_MOS
VREF_VMA3_MOS
+1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX
VMA_CLK0 VMA_CLK1
2
2
R4511 R4513 R4515 R4517 R4519 R4521 R4523 R4525
R4510 GKB@931/F_4 R4512 *GKB@931/F_4 R4514 GKB@931/F_4 R4516 *GKB@931/F_4 R4518 GKB@931/F_4 R4520 *GKB@931/F_4 R4522 GKB@931/F_4 R4524 *GKB@931/F_4
3
3
GKB@549/F_4 *GKB@549/F_4 GKB@549/F_4 *GKB@549/F_4 GKB@549/F_4 *GKB@549/F_4 GKB@549/F_4 *GKB@549/F_4
R4526 R4527
1
1
GKB@80.6/F_4 GKB@80.6/F_4 VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 Q4500 Q4501 VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4
2 2
GPIO10_VREF <17,19,20> GPIO10_VREF <17,19,20>
VMA_CLK0# VMA_CLK1# R4528 R4529 R4530 R4531 R4532 R4533 R4534 R4535
GKB@1.33K/F_4 *GKB@1.33K/F_4 GKB@1.33K/F_4 *GKB@1.33K/F_4 GKB@2N7002D GKB@2N7002D GKB@1.33K/F_4 *GKB@1.33K/F_4 GKB@1.33K/F_4 *GKB@1.33K/F_4
1
+1.35V_GFX <15,20,42>
D D
+1.35V_GFX
GDDR5 Mode H Mapping
< 0-31 > < 32-63 > Memory
+1.35V_GFX C4512 GKB@1u/6.3V_4 C4513 GKB@1u/6.3V_4 C4514 GKB@0.1u/16V_4 FBA_CMD14 R4538 GKB@10K_4 CMD0 CMD16 CS*
C4515 GKB@1u/6.3V_4 C4516 GKB@1u/6.3V_4 C4517 GKB@1u/6.3V_4 C4518 GKB@1u/6.3V_4 FBA_CMD30 R4541 GKB@10K_4 CMD1 CMD17 A3_BA3
C4519 GKB@1u/6.3V_4 C4520 GKB@1u/6.3V_4 C4521 GKB@1u/6.3V_4 C4522 GKB@1u/6.3V_4 CMD2 CMD18 A2_BA0
C4523 GKB@330u/2V_7343 C4524 GKB@1u/6.3V_4 C4525 GKB@1u/6.3V_4 C4526 GKB@1u/6.3V_4 C4527 GKB@1u/6.3V_4 CKE* is strap pin to set ODT value of memory chip CMD3 CMD19 A4_BA2
+
C4528 GKB@0.047u/10V_4 C4529 GKB@0.047u/10V_4 C4530 GKB@0.1u/16V_4 C4531 GKB@0.047u/10V_4 CMD4 CMD20 A5_BA1
C4532 GKB@0.1u/16V_4 C4533 GKB@0.047u/10V_4 C4534 GKB@0.047u/10V_4 C4535 GKB@0.1u/16V_4 C4536 GKB@0.047u/10V_4 CMD5 CMD21 WE*
C4537 GKB@10U/6.3V_6 C4538 GKB@0.1u/16V_4 C4539 GKB@0.1u/16V_4 C4540 GKB@0.1u/16V_4 C4541 GKB@0.1u/16V_4 FBA_CMD13 R4542 GKB@10K_4 CMD6 CMD22 A7_A8
C4542 GKB@10U/6.3V_6 C4543 GKB@0.1u/16V_4 C4544 GKB@0.1u/16V_4 C4545 *GKB@0.1u/16V_4 C4546 GKB@0.1u/16V_4 FBA_CMD29 R4543 GKB@10K_4 CMD7 CMD23 A6_A11
C4547 GKB@10U/6.3V_6 C4548 GKB@0.1u/16V_4 C4549 GKB@0.1u/16V_4 C4550 *GKB@0.1u/16V_4 C4551 GKB@0.1u/16V_4 CMD8 CMD24 ABI*
C4552 GKB@0.1u/16V_4 C4553 GKB@0.1u/16V_4 C4554 *GKB@0.1u/16V_4 C4555 GKB@0.1u/16V_4 CMD9 CMD25 A12_RFU
201201117 Add C764 for EMI suggestion. CMD10 CMD26 A0_A10 Quanta Computer Inc.
CMD11 CMD27 A1_A9
CMD12 CMD28 RAS* PROJECT : ZAA
RST PD place @ the end of daisy-chain. CMD13 CMD29 RST*
CMD14 CMD30 CKE* Size Document Number Rev
CMD15 CMD31 CAS* 1A
GDDR5x16-VRAM-A
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
<15> VMB_DQ[63..0]
VMB_DQ[63..0]
FBB_CMD[31:0] For KA of GPU CHANNEL A: 1G/2G GDDR5 X16

<15>
<15>
FBB_CMD[31:0]
FBB_DBI[7..0]
FBB_DBI[7..0]
Channel 0 Channel 0 Channel 1 Channel 1
<15> FBB_EDC[7..0]
FBB_EDC[7..0]
<0-31> <0-31> <32-63> <32-63>
MF=0 Non-mirrored MF=1 Mirrored MF=0 Non-mirrored MF=1 Mirrored
VRAM3003 VRAM3007 VRAM3002 VRAM3006

M2 B1 M2 B1 M2 B1 M2 B1
M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3 M4 DQ31 | DQ7 VDDQ-B1 B3
T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1 T2 DQ28 | DQ4 VDDQ-B14 D1
T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3 T4 DQ27 | DQ3 VDDQ-D1 D3
A A
VMB_DQ23 M13 DQ24 | DQ0 VDDQ-D14 E5 VMB_DQ15 M13 DQ24 | DQ0 VDDQ-D14 E5 VMB_DQ55 M13 DQ24 | DQ0 VDDQ-D14 E5 VMB_DQ47 M13 DQ24 | DQ0 VDDQ-D14 E5
VMB_DQ22 M11 DQ23 | DQ15 VDDQ-E5 E10 VMB_DQ14 M11 DQ23 | DQ15 VDDQ-E5 E10 VMB_DQ54 M11 DQ23 | DQ15 VDDQ-E5 E10 VMB_DQ46 M11 DQ23 | DQ15 VDDQ-E5 E10
VMB_DQ21 N13 DQ22 | DQ14 VDDQ-E10 F1 VMB_DQ13 N13 DQ22 | DQ14 VDDQ-E10 F1 VMB_DQ53 N13 DQ22 | DQ14 VDDQ-E10 F1 VMB_DQ45 N13 DQ22 | DQ14 VDDQ-E10 F1
QD16~23 VMB_DQ20
VMB_DQ19
VMB_DQ18
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14 QD8~15
VMB_DQ12
VMB_DQ11
VMB_DQ10
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
QD48~55 VMB_DQ52
VMB_DQ51
VMB_DQ50
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
QD40~47 VMB_DQ44
VMB_DQ43
VMB_DQ42
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
VMB_DQ17 U13 G2 VMB_DQ9 U13 G2 VMB_DQ49 U13 G2 VMB_DQ41 U13 G2
VMB_DQ16 U11 DQ17 | DQ9 VDDQ-G2 G13 VMB_DQ8 U11 DQ17 | DQ9 VDDQ-G2 G13 VMB_DQ48 U11 DQ17 | DQ9 VDDQ-G2 G13 VMB_DQ40 U11 DQ17 | DQ9 VDDQ-G2 G13
F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3 F13 DQ16 | DQ8 VDDQ-G13 H3
F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12 F11 DQ15 | DQ23 VDDQ-H3 H12
E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3 E13 DQ14 | DQ22 VDDQ-H12 K3
E11 DQ13 | DQ21 VDDQ-K3 K12 E11 DQ13 | DQ21 VDDQ-K3 K12 E11 DQ13 | DQ21 VDDQ-K3 K12 E11 DQ13 | DQ21 VDDQ-K3 K12
B13 DQ12 | DQ20 VDDQ-K12 L2 B13 DQ12 | DQ20 VDDQ-K12 L2 B13 DQ12 | DQ20 VDDQ-K12 L2 B13 DQ12 | DQ20 VDDQ-K12 L2
B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13 B11 DQ11 | DQ19 VDDQ-L2 L13
A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1 A13 DQ10 | DQ18 VDDQ-L13 M1
A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3 A11 DQ9 | DQ17 VDDQ-M1 M3
VMB_DQ7 F2 DQ8 | DQ16 VDDQ-M3 M12 VMB_DQ31 F2 DQ8 | DQ16 VDDQ-M3 M12 VMB_DQ39 F2 DQ8 | DQ16 VDDQ-M3 M12 VMB_DQ63 F2 DQ8 | DQ16 VDDQ-M3 M12
VMB_DQ6 F4 DQ7 | DQ31 VDDQ-M12 M14 VMB_DQ30 F4 DQ7 | DQ31 VDDQ-M12 M14 VMB_DQ38 F4 DQ7 | DQ31 VDDQ-M12 M14 VMB_DQ62 F4 DQ7 | DQ31 VDDQ-M12 M14
VMB_DQ5 E2 DQ6 | DQ30 VDDQ-M14 N5 VMB_DQ29 E2 DQ6 | DQ30 VDDQ-M14 N5 VMB_DQ37 E2 DQ6 | DQ30 VDDQ-M14 N5 VMB_DQ61 E2 DQ6 | DQ30 VDDQ-M14 N5
QD0~7 VMB_DQ4
VMB_DQ3
VMB_DQ2
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3 QD24~31
VMB_DQ28
VMB_DQ27
VMB_DQ26
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3
QD32~39 VMB_DQ36
VMB_DQ35
VMB_DQ34
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3
QD56~63 VMB_DQ60
VMB_DQ59
VMB_DQ58
E4
B2
B4
DQ5 | DQ29
DQ4 | DQ28
DQ3 | DQ27
DQ2 | DQ26
VDDQ-N5
VDDQ-N10
VDDQ-P1
VDDQ-P3
N10
P1
P3
VMB_DQ1 A2 P12 VMB_DQ25 A2 P12 VMB_DQ33 A2 P12 VMB_DQ57 A2 P12
VMB_DQ0 A4 DQ1 | DQ25 VDDQ-P12 P14 VMB_DQ24 A4 DQ1 | DQ25 VDDQ-P12 P14 VMB_DQ32 A4 DQ1 | DQ25 VDDQ-P12 P14 VMB_DQ56 A4 DQ1 | DQ25 VDDQ-P12 P14
DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1 DQ0 | DQ24 VDDQ-P14 T1
VDDQ-T14 VDDQ-T14 VDDQ-T14 VDDQ-T14
FBB_CMD9 J5 FBB_CMD9 J5 FBB_CMD25 J5 FBB_CMD25 J5
FBB_CMD6 K4 RFU/A12/NC C5 FBB_CMD10 K4 RFU/A12/NC C5 FBB_CMD22 K4 RFU/A12/NC C5 FBB_CMD26 K4 RFU/A12/NC C5
FBB_CMD7 K5 A7/A8 | A0/A10 VDD-C5 C10 FBB_CMD11 K5 A7/A8 | A0/A10 VDD-C5 C10 FBB_CMD23 K5 A7/A8 | A0/A10 VDD-C5 C10 FBB_CMD27 K5 A7/A8 | A0/A10 VDD-C5 C10
FBB_CMD4 K10 A6/A11 | A1/A9 VDD-C10 D11 FBB_CMD1 K10 A6/A11 | A1/A9 VDD-C10 D11 FBB_CMD20 K10 A6/A11 | A1/A9 VDD-C10 D11 FBB_CMD17 K10 A6/A11 | A1/A9 VDD-C10 D11
FBB_CMD3 K11 A5/BA1 | A3/BA3 VDD-D11 G1 FBB_CMD2 K11 A5/BA1 | A3/BA3 VDD-D11 G1 FBB_CMD19 K11 A5/BA1 | A3/BA3 VDD-D11 G1 FBB_CMD18 K11 A5/BA1 | A3/BA3 VDD-D11 G1
FBB_CMD1 H10 A4/BA2 | A2/BA0 VDD-G1 G4 FBB_CMD4 H10 A4/BA2 | A2/BA0 VDD-G1 G4 FBB_CMD17 H10 A4/BA2 | A2/BA0 VDD-G1 G4 FBB_CMD20 H10 A4/BA2 | A2/BA0 VDD-G1 G4
FBB_CMD2 H11 A3/BA3 | A5/BA1 VDD-G4 G11 FBB_CMD3 H11 A3/BA3 | A5/BA1 VDD-G4 G11 FBB_CMD18 H11 A3/BA3 | A5/BA1 VDD-G4 G11 FBB_CMD19 H11 A3/BA3 | A5/BA1 VDD-G4 G11
FBB_CMD11 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 FBB_CMD7 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 FBB_CMD27 H5 A2 /BA0 | A4/BA2 VDD-G11 G14 FBB_CMD23 H5 A2 /BA0 | A4/BA2 VDD-G11 G14
FBB_CMD10 H4 A1/A9 | A6/A11 VDD-G14 L1 FBB_CMD6 H4 A1/A9 | A6/A11 VDD-G14 L1 FBB_CMD26 H4 A1/A9 | A6/A11 VDD-G14 L1 FBB_CMD22 H4 A1/A9 | A6/A11 VDD-G14 L1
A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4 A0/A10 | A7/A8 VDD-L1 L4
VMB_WCK01 D4 VDD-L14 P11 VMB_WCK23 D4 VDD-L14 P11 VMB_WCK45 D4 VDD-L14 P11 VMB_WCK67 D4 VDD-L14 P11
<15> VMB_WCK01 WCK01 | WCK23 VDD-P11 WCK01 | WCK23 VDD-P11 <15> VMB_WCK45 WCK01 | WCK23 VDD-P11 WCK01 | WCK23 VDD-P11
<15> VMB_WCK01# VMB_WCK01# D5 R5 VMB_WCK23# D5 R5 <15> VMB_WCK45# VMB_WCK45# D5 R5 VMB_WCK67# D5 R5
B WCK01# | WCK23# VDD-R5 R10 WCK01# | WCK23# VDD-R5 R10 WCK01# | WCK23# VDD-R5 R10 WCK01# | WCK23# VDD-R5 R10 B
VMB_WCK23 P4 VDD-R10 VMB_WCK01 P4 VDD-R10 VMB_WCK67 P4 VDD-R10 VMB_WCK45 P4 VDD-R10
<15> VMB_WCK23 WCK23 | WCK01 WCK23 | WCK01 <15> VMB_WCK67 WCK23 | WCK01 WCK23 | WCK01
<15> VMB_WCK23# VMB_WCK23# P5 VMB_WCK01# P5 <15> VMB_WCK67# VMB_WCK67# P5 VMB_WCK45# P5
WCK23# | WCK01# A1 WCK23# | WCK01# A1 WCK23# | WCK01# A1 WCK23# | WCK01# A1
R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 R2 VSSQ-A1 A3 R2 VSSQ-A1 A3
FBB_EDC2 R13 EDC3 | EDC0 VSSQ-A3 A12 FBB_EDC1 R13 EDC3 | EDC0 VSSQ-A3 A12 FBB_EDC6 R13 EDC3 | EDC0 VSSQ-A3 A12 FBB_EDC5 R13 EDC3 | EDC0 VSSQ-A3 A12
C13 EDC2 | EDC1 VSSQ-A12 A14 C13 EDC2 | EDC1 VSSQ-A12 A14 C13 EDC2 | EDC1 VSSQ-A12 A14 C13 EDC2 | EDC1 VSSQ-A12 A14
FBB_EDC0 C2 EDC1 | EDC2 VSSQ-A14 C1 FBB_EDC3 C2 EDC1 | EDC2 VSSQ-A14 C1 FBB_EDC4 C2 EDC1 | EDC2 VSSQ-A14 C1 FBB_EDC7 C2 EDC1 | EDC2 VSSQ-A14 C1
EDC0 | EDC3 VSSQ-C1 C3 EDC0 | EDC3 VSSQ-C1 C3 EDC0 | EDC3 VSSQ-C1 C3 EDC0 | EDC3 VSSQ-C1 C3
P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 P2 VSSQ-C3 C4 P2 VSSQ-C3 C4
FBB_DBI2 P13 DBI3# | DBI0# VSSQ-C4 C11 FBB_DBI1 P13 DBI3# | DBI0# VSSQ-C4 C11 FBB_DBI6 P13 DBI3# | DBI0# VSSQ-C4 C11 FBB_DBI5 P13 DBI3# | DBI0# VSSQ-C4 C11
D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12 D13 DBI2 #| DBI1# VSSQ-C11 C12
FBB_DBI0 D2 DBI1# | DBI2# VSSQ-C12 C14 FBB_DBI3 D2 DBI1# | DBI2# VSSQ-C12 C14 FBB_DBI4 D2 DBI1# | DBI2# VSSQ-C12 C14 FBB_DBI7 D2 DBI1# | DBI2# VSSQ-C12 C14
DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1
FBB_CMD12 G3 VSSQ-E12 E14 FBB_CMD15 G3 VSSQ-E12 E14 FBB_CMD28 G3 VSSQ-E12 E14 FBB_CMD31 G3 VSSQ-E12 E14
FBB_CMD15 L3 RAS# | CAS# VSSQ-E14 F5 FBB_CMD12 L3 RAS# | CAS# VSSQ-E14 F5 FBB_CMD31 L3 RAS# | CAS# VSSQ-E14 F5 FBB_CMD28 L3 RAS# | CAS# VSSQ-E14 F5
CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10 CAS# | RAS# VSSQ-F5 F10
VSSQ-F10 H2 VSSQ-F10 H2 VSSQ-F10 H2 VSSQ-F10 H2
FBB_CMD14 J3 VSSQ-H2 H13 FBB_CMD14 J3 VSSQ-H2 H13 FBB_CMD30 J3 VSSQ-H2 H13 FBB_CMD30 J3 VSSQ-H2 H13
VMB_CLK0# J11 CKE# VSSQ-H13 K2 VMB_CLK0# J11 CKE# VSSQ-H13 K2 VMB_CLK1# J11 CKE# VSSQ-H13 K2 VMB_CLK1# J11 CKE# VSSQ-H13 K2
<15> VMB_CLK0# CK# VSSQ-K2 CK# VSSQ-K2 <15> VMB_CLK1# CK# VSSQ-K2 CK# VSSQ-K2
VMB_CLK0 J12 K13 VMB_CLK0 J12 K13 VMB_CLK1 J12 K13 VMB_CLK1 J12 K13
<15> VMB_CLK0 CK VSSQ-K13 CK VSSQ-K13 <15> VMB_CLK1 CK VSSQ-K13 CK VSSQ-K13
M5 M5 M5 M5
VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10 VSSQ-M5 M10
FBB_CMD0 G12 VSSQ-M10 N1 FBB_CMD5 G12 VSSQ-M10 N1 FBB_CMD16 G12 VSSQ-M10 N1 FBB_CMD21 G12 VSSQ-M10 N1
FBB_CMD5 L12 CS# | WE# VSSQ-N1 N3 FBB_CMD0 L12 CS# | WE# VSSQ-N1 N3 FBB_CMD21 L12 CS# | WE# VSSQ-N1 N3 FBB_CMD16 L12 CS# | WE# VSSQ-N1 N3
WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12 WE# | CS# VSSQ-N3 N12
VSSQ-N12 N14 VSSQ-N12 N14 VSSQ-N12 N14 VSSQ-N12 N14
R11089 GKA@120/F_4 J13 VSSQ-N14 R1 R11106 GKA@120/F_4 J13 VSSQ-N14 R1 R11075 GKA@120/F_4 J13 VSSQ-N14 R1 R11084 GKA@120/F_4 J13 VSSQ-N14 R1
R11090 GKA@1K_4SEN_B0 J10 ZQ VSSQ-R1 R3 SEN_B1 J10 ZQ VSSQ-R1 R3 R11083 GKA@1K_4SEN_B2 J10 ZQ VSSQ-R1 R3 SEN_B3 J10 ZQ VSSQ-R1 R3
SEN VSSQ-R3 R4 R11092 GKA@1K_4 SEN VSSQ-R3 R4 SEN VSSQ-R3 R4 R11069 GKA@1K_4 SEN VSSQ-R3 R4
VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11 VSSQ-R4 R11
FBB_CMD13 J2 VSSQ-R11 R12 FBB_CMD13 J2 VSSQ-R11 R12 FBB_CMD29 J2 VSSQ-R11 R12 FBB_CMD29 J2 VSSQ-R11 R12
J1 RESET# VSSQ-R12 R14 J1 RESET# VSSQ-R12 R14 J1 RESET# VSSQ-R12 R14 J1 RESET# VSSQ-R12 R14
MF VSSQ-R14 +1.35V_GFX MF VSSQ-R14 MF VSSQ-R14 +1.35V_GFX MF VSSQ-R14
R11068 GKA@1K_4 U1 R11096 GKA@1K_4 U1 R11073 GKA@1K_4 U1 R11071 GKA@1K_4 U1
A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14 A5 VSSQ-V14
U5 Vpp,NC U5 Vpp,NC U5 Vpp,NC U5 Vpp,NC
16mils Vpp,NC1
VSS-B5
B5 16mils Vpp,NC1
VSS-B5
B5 16mils Vpp,NC1
VSS-B5
B5 16mils Vpp,NC1
VSS-B5
B5
VREFD_VMB1 A10 B10 VREFD_VMB2 A10 B10 VREFD_VMB3 A10 B10 VREFD_VMB4 A10 B10
U10 VREFD1 VSS-B10 D10 U10 VREFD1 VSS-B10 D10 U10 VREFD1 VSS-B10 D10 U10 VREFD1 VSS-B10 D10
VREFD2 VSS-D10 G5 VREFD2 VSS-D10 G5 VREFD2 VSS-D10 G5 VREFD2 VSS-D10 G5
C C
VSS-G5 G10 VSS-G5 G10 VSS-G5 G10 VSS-G5 G10
VSS-G10 H1 VSS-G10 H1 VSS-G10 H1 VSS-G10 H1
VSS-H1 H14 VSS-H1 H14 VSS-H1 H14 VSS-H1 H14
16mils VSS-H14
VSS-K1
K1 16mils VSS-H14
VSS-K1
K1 16mils VSS-H14
VSS-K1
K1 16mils VSS-H14
VSS-K1
K1
VREFC_VMB1 J14 K14 VREFC_VMB2 J14 K14 VREFC_VMB3 J14 K14 VREFC_VMB4 J14 K14
VREFC VSS-K14 L5 VREFC VSS-K14 L5 VREFC VSS-K14 L5 VREFC VSS-K14 L5
VSS-L5 L10 VSS-L5 L10 VSS-L5 L10 VSS-L5 L10
VSS-L10 P10 VSS-L10 P10 VSS-L10 P10 VSS-L10 P10
FBB_CMD8 J4 VSS-P10 T5 FBB_CMD8 J4 VSS-P10 T5 FBB_CMD24 J4 VSS-P10 T5 FBB_CMD24 J4 VSS-P10 T5
ABI# VSS-T5 T10 ABI# VSS-T5 T10 ABI# VSS-T5 T10 ABI# VSS-T5 T10
VSS-T10 VSS-T10 VSS-T10 VSS-T10
GKA@GDDR5 VRAM3003 GKA@GDDR5 VRAM3007 GKA@GDDR5 VRAM3002 GKA@GDDR5 VRAM3006
VREF_VMB1_MOS VREF_VMB1_MOS VREF_VMB3_MOS VREF_VMB3_MOS

+1.35V_GFX <15,19,42>
VREF_VMB1_MOS
VREF_VMB3_MOS
+1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX
VMB_CLK0 VMB_CLK1
2
2
R11070 R11067 R11085 R11066 R11097 R11078 R11079 R11088
R11077 GKA@931/F_4 R11081 *GKA@931/F_4 R11101 GKA@931/F_4 R11074 *GKA@931/F_4 R11099 GKA@931/F_4 R11104 *GKA@931/F_4 R11095 GKA@931/F_4 R11082 *GKA@931/F_4
3
3
GKA@549/F_4 *GKA@549/F_4 GKA@549/F_4 *GKA@549/F_4 GKA@549/F_4 *GKA@549/F_4 GKA@549/F_4 *GKA@549/F_4
R11094 R11098
1
1
GKA@80.6/F_4 GKA@80.6/F_4 VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2 Q4509 Q4510 VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4
2 2
GPIO10_VREF <17,19,20> GPIO10_VREF <17,19,20>
VMB_CLK0# VMB_CLK1# R11105 R11103 R11091 R11102 R11100 R11076 R11093 R11087
GKA@1.33K/F_4 *GKA@1.33K/F_4 GKA@1.33K/F_4 *GKA@1.33K/F_4 GKA@2N7002D GKA@2N7002D GKA@1.33K/F_4 *GKA@1.33K/F_4 GKA@1.33K/F_4 *GKA@1.33K/F_4
1
+1.35V_GFX
D D

GDDR5 Mode H Mapping
< 0-31 > < 32-63 > Memory
+1.35V_GFX C4668 GKA@1u/6.3V_4 C4690 GKA@1u/6.3V_4 C4678 GKA@0.1u/16V_4 FBB_CMD14 R11086 GKA@10K_4 CMD0 CMD16 CS*
C4684 GKA@1u/6.3V_4 C4676 GKA@1u/6.3V_4 C4679 GKA@1u/6.3V_4 C4672 GKA@1u/6.3V_4 FBB_CMD30 R11072 GKA@10K_4 CMD1 CMD17 A3_BA3
C4688 GKA@1u/6.3V_4 C4697 GKA@1u/6.3V_4 C4675 GKA@1u/6.3V_4 C4703 GKA@1u/6.3V_4 CMD2 CMD18 A2_BA0
C4701 GKA@330u/2V_7343 C4683 GKA@1u/6.3V_4 C4692 GKA@1u/6.3V_4 C4691 GKA@1u/6.3V_4 C4693 GKA@1u/6.3V_4 CKE* is strap pin to set ODT value of memory chip CMD3 CMD19 A4_BA2
+
C4694 GKA@0.047u/10V_4 C4695 GKA@0.047u/10V_4 C4682 GKA@0.1u/16V_4 C4667 GKA@0.047u/10V_4 CMD4 CMD20 A5_BA1
C4705 GKA@0.1u/16V_4 C4669 GKA@0.047u/10V_4 C4708 GKA@0.047u/10V_4 C4671 GKA@0.1u/16V_4 C4696 GKA@0.047u/10V_4 CMD5 CMD21 WE*
C4706 GKA@10U/6.3V_6 C4704 GKA@0.1u/16V_4 C4670 GKA@0.1u/16V_4 C4686 GKA@0.1u/16V_4 C4702 GKA@0.1u/16V_4 FBB_CMD13 R11080 GKA@10K_4 CMD6 CMD22 A7_A8
C4689 GKA@10U/6.3V_6 C4699 GKA@0.1u/16V_4 C4698 GKA@0.1u/16V_4 C4709 *GKA@0.1u/16V_4 C4700 GKA@0.1u/16V_4 FBB_CMD29 R11065 GKA@10K_4 CMD7 CMD23 A6_A11
C4674 GKA@10U/6.3V_6 C4666 GKA@0.1u/16V_4 C4673 GKA@0.1u/16V_4 C4685 *GKA@0.1u/16V_4 C4681 GKA@0.1u/16V_4 CMD8 CMD24 ABI*
C4687 GKA@0.1u/16V_4 C4707 GKA@0.1u/16V_4 C4680 *GKA@0.1u/16V_4 C4677 GKA@0.1u/16V_4 CMD9 CMD25 A12_RFU
201201117 Add C764 for EMI suggestion. CMD10 CMD26 A0_A10 Quanta Computer Inc.
CMD11 CMD27 A1_A9
CMD12 CMD28 RAS* PROJECT : ZAA
RST PD place @ the end of daisy-chain. CMD13 CMD29 RST*
CMD14 CMD30 CKE* Size Document Number Rev
WWW.AliSaler.Com
CMD15 CMD31 CAS* 1A
GDDR5x16-VRAM-B
1 2 3 4 5 6 7 8
5 4 3 2 1
USB TYPE-C
<2,3,4,6,7,8,9,11,25,27,28,29,31,33,35,36,41> +3V_S5 +3V_S5
<30,33,36,37,38,39,41> +5V_S5
R819 *short_4 Close to connector <33> +5V_S5_V2 25810_FAULT# R11206 TYC@100K/F_4
USB2.0 ESD L69 *TYC@DLP11SN900HL2L

1 2 USB2_TYPC_7P_C
25810_LD_DET# R11208
25810_UFP# R11193
TYC@100K/F_4
*TYC@100K/F_4 Mount at page2

<6> USBP7+ +TYPEC_VBUS_C
4 3 USB2_TYPC_7N_C
<6> USBP7- Vendor suggest input cap 120u 25810_POL# R11203 TYC@100K/F_4
+5V_S5_V2 25810_AUO# R11197 TYC@100K/F_4
R818 *short_4 25810_DBG# R11194 TYC@100K/F_4
C4772 TYC@150U/6.3V_3528 U28 C4817 TYC_EMI@100p/50V_4
Type C1_HSIO_ ESD +3V_S5
+
D C4766 TYC@10U/6.3V/X5R_6 2 15 C4765 TYC@10U/6.3V/X5R_6 D
C4769 TYC@10U/6.3V/X5R_6 3 IN1 OUT 14 TYPEC_CHG R11205 TYC@100K/F_4
USB3_TYPC_TX2P_RE C4770 USB3_TYPC_TX2P_R R821 *short_4 4 IN1 OUT TYPEC_CHG_HI R11198 TYC@100K/F_4
TYC@0.1u/25V/X5R_4 5 IN2 11 25810_CC1
VAUX TI CC1 13
RP4 25810_CC2 EC_TypeC_EN_R R11278 TYC@10K_4
4 3 USB3_TYPC_TX2P_C EC_TypeC_EN_R 6 CC2
1 2 <31> EC_TypeC_EN_R EN TPS25810RVC 1
USB3_TYPC_TX2N_C 25810_FAULT#
TYPEC_CHG 7 FAULT# 20 25810_LD_DET#
*TYC@DLP11SN900HL2L *short_4 R11279 TYPEC_CHG_HI 8 CHG LD_DET# 19 25810_UFP#
USB3_TYPC_TX2N_RE USB3_TYPC_TX2N_R <31> EC_TypeC_CHG_HI CHG_HI UFP# 18 25810_POL#
C4771 R820 *short_4
TYC@0.1u/25V/X5R_4 25810_REF 10 POL# 17 25810_AUO#
REF AUDIO# 16 25810_DBG#
R11199 *short_4 R11204 25810_REF_RTN 9 DEBUG#
TYC@100K/F_4 12 REF_RTN 21
GND
GND
GND
GND
GND
GND
*TYC@DLP11SN900HL2L GND PwPd
USB3_TYPC_RX2P_RE 4 3 USB3_TYPC_RX2P_C
USB3_TYPC_RX2N_RE 1 2 USB3_TYPC_RX2N_C TYC@TPS25810RVCR(QFN)
22
23
24
25
26
27
RP2 25810_UFP# *short_4 R11280
PCH_TypeC_UPFb# <2>
R11196 *short_4
25810_FAULT# *short_4 R11281
USB_OC3# <6>
USB3_TYPC_TX3P_RE C4763 USB3_TYPC_TX3P_R R11202 *short_4

TYC@0.1u/25V/X5R_4
*TYC@DLP11SN900HL2L
1 2 USB3_TYPC_TX3P_C
4 3 USB3_TYPC_TX3N_C
RP5
USB3_TYPC_TX3N_RE C4762 USB3_TYPC_TX3N_R R11207 *short_4 +TYPEC_VBUS
TYC@0.1u/25V/X5R_4 Q6062 C4818 TYC_EMI@100p/50V_4
+TYPEC_VBUS_C TYC@AON7401 +TYPEC_VBUS
+TYPEC_VBUS C4768 TYC@0.1U/25V_4
1
C
5 2 C4764 TYC@0.1U/25V_4 C
R816 *short_4 3 EC51
TYC@AZ5725-01F
RP3 +5V_S5 C4767 R11200
USB3_TYPC_RX3P_RE 3 4 USB3_TYPC_RX3P_C CN2021
TYC@0.1U/25V_4 TYC@10K_4
4
USB3_TYPC_RX3N_RE 2 1 USB3_TYPC_RX3N_C 25810_UFP#_G2 A1 B12
R11201 R11195 TYC@100K/F_4 GND GND
*TYC@DLP11SN900HL2L TYC@10K_4 USB3_TYPC_TX2P_C A2 B11 USB3_TYPC_RX2P_C
TX1+ RX1+
3
R817 *short_4
USB3_TYPC_TX2N_C A3 B10 USB3_TYPC_RX2N_C
25810_UFP#_G1 Q17 TX1- RX1-
2 C4647 +TYPEC_VBUS A4
TYC@0.47u/25V_6 B9 +TYPEC_VBUS C4648 TYC@0.47u/25V_6
VBUS VBUS
TYC@2N7002K
3
25810_CC1 A5 B8 TYPEC_SBU2
CC1 SBU2 TP144
Q15 USB2_TYPC_7P_C A6 B7 USB2_TYPC_7N_C
1
25810_UFP# 2 D+ D-
USB2_TYPC_7N_C A7 B6 USB2_TYPC_7P_C
TYC@2N7002K D- D+
TYPEC_SBU1 A8 B5 25810_CC2
TP143 SBU1 CC2
1
C4649 +TYPEC_VBUS A9
TYC@0.47u/25V_6 B4 +TYPEC_VBUS C4650 TYC@0.47u/25V_6
VBUS VBUS
USB3 Re-Driver USB3_TYPC_RX3N_C
USB3_TYPC_RX3P_C
A10
A11
RX2- TX2-
B3
B2
USB3_TYPC_TX3N_C
USB3_TYPC_TX3P_C
A_EQ0 R258 *TYC@0_4 RX2+ TX2+
3V_LR
A_EQ1 R11211 *TYC@0_4 A12 B1
R11210 GND GND
*TYC@4.99K/F_4 B_EQ0 R206 *TYC@0_4 3 1
B_EQ1 R11212 *TYC@0_4 H-GND H-GND
4 2
A_DE0 R11213 *TYC@0_4 H-GND H-GND
A_EQ0
A_EQ1
A_DE0
A_DE1
A_DE1 R254 *TYC@0_4

TYC@USB_Type_C
B B_DE0 R11214 *TYC@0_4 ub31-dx07b024xj1ar1000-24p-smt B
B_DE1 R203 *TYC@0_4
32
31
30
29
28
U9 TYC@PTN36242LBS TST R617 *TYC@4.7K/F_4

39 40
A_EQ0
A_EQ1
A_DE0
A_DE1
REXT
38 GND GND 41
GND GND
C394 TYC@0.1U/16V_4_X7R USB3_TYPC_RX2N_C_RE 1 27 USB3_TYPC_RX2N_RE
<6> USB3_RXN2 2 A1_OUTn A1_INn 26
C4781 TYC@0.1U/16V_4_X7R USB3_TYPC_RX2P_C_RE USB3_TYPC_RX2P_RE
<6> USB3_RXP2 3 A1_OUTp A1_INp 25
GND VDD 24 3V_LR
C4780 TYC@0.1U/16V_4_X7R USB3_TYPC_TX2N_C_RE 4 USB3_TYPC_TX2N_RE
<6> USB3_TXN2 5 B1_INn B1_OUTn 23
C369 TYC@0.1U/16V_4_X7R USB3_TYPC_TX2P_C_RE USB3_TYPC_TX2P_RE
<6> USB3_TXP2 6 B1_INp B1_OUTp 22 TST R11209 *TYC@4.7K/F_4
C4777 TYC@0.1U/16V_4_X7R USB3_TYPC_RX3N_C_RE 7 I2C_EN TST 21 USB3_TYPC_RX3N_RE
<6> USB3_RXN3 8 A2_OUTn A2_INn 20
C4776 TYC@0.1U/16V_4_X7R USB3_TYPC_RX3P_C_RE USB3_TYPC_RX3P_RE
<6> USB3_RXP3 9 A2_OUTp A2_INp 19
3V_LR VDD GND 18 U4513
C4779 TYC@0.1U/16V_4_X7R USB3_TYPC_TX3N_C_RE 10 USB3_TYPC_TX3N_RE
<6> USB3_TXN3 11 B2_INn B2_OUTn 17 U4509 1 9
C4778 TYC@0.1U/16V_4_X7R USB3_TYPC_TX3P_C_RE USB3_TYPC_TX3P_RE USB2_TYPC_7P_C USB2_TYPC_7N_C
<6> USB3_TXP3 B2_INp B2_OUTp 33 USB3_TYPC_TX2P_C 1 9 USB3_TYPC_TX2N_C 2 LINE-1 LINE-2 8
B_EQ0
B_EQ1
B_DE0
B_DE1
36 GND 34 USB3_TYPC_RX2P_C 2 LINE-1 LINE-2 8 USB3_TYPC_RX2N_C LINE-3 LINE-4

PD#
37 GND GND 35 LINE-3 LINE-4 3

GND GND 3 GND
GND TYPEC_SBU1 4 7 TYPEC_SBU2
12
13
14
15
16
USB3_TYPC_TX3P_C 4 7 USB3_TYPC_TX3N_C 25810_CC1 5 LINE-6 LINE-5 6 25810_CC2

USB3_TYPC_RX3P_C 5 LINE-6 LINE-5 6 USB3_TYPC_RX3N_C LINE-8 LINE-7
LINE-8 LINE-7
TYC@AZ1045-08F
B_EQ0
B_EQ1
B_DE0
B_DE1
TYC@AZ1043-08F
Quanta P/NAMAZING P/NUSD保保保保

A_EQ0 A_EQ1 A_DE0 A_DE1 BC104308Z00AZ1043-08F.R7G0.08TX RX ( USB3.0 GEN1 5G )
L4209 TYC@BLM18PG181SN1D_0.5A
+3V_S5
R0603
3V_LR
B_EQ0 B_EQ1 B_DE0 B_DE1 BC104508Z00AZ1045-08F.R7G0.08D+ D- SBU1 SBU2 CC1 CC2
A
C4775
C4774 BC005725Z00AZ5725-01F.R7G0.009 PD 5V ( follow ZAA) A
TYC@10U/6.3V_6_X5R TYC@0.1U/16V_4_X7R 0 0 9dB 0 0 -3.5dB

C4773
0 1 3dB 0 1 no de-emphasis
TYC@0.1U/16V_4_X7R
1 0 6dB 1 0 -7dB
1 1 7.5dB 1 1 -5dB
TST : Low = Normal LFPS swing / Hight =Turn down LFPS swing Quanta Computer Inc.
PROJECT :ZAA
Type-C 3 of 3 1A

5 4 3 2 1
5 4 3 2 1
DP TO VGA
Close to CPU side of CAP.

R10842 *short_4 CRT_TXP0
<2> DDI2_TXP0
R10843 *short_4 CRT_TXN0
<2> DDI2_TXN0
R10844 *short_4 CRT_TXP1
D <2> DDI2_TXP1 D
R10845 *short_4 CRT_TXN1

<2> DDI2_TXN1
<2> PCH_DP_HPD R10846 *short_4 CRT_HPD
R10847 *short_4 CRT_AUXN

<2> DDI2_AUXN
R10848 *short_4 CRT_AUXP
<2> DDI2_AUXP
R11190 *0_4
<7,12,13,29> CLK_SDATA
R11189 *0_4
<7,12,13,29> CLK_SCLK
Power C4752
0.1U/16V_4
CIIC_SDA
CIIC_SCL
CRT_HPD
+3V +3V
VGA
+3V
L4 AVCC33 L4208 VDD_DAC_33
C C
60ohm@100MHz_6 60ohm@100MHz_6 VCCK_V12
C4751 DDCDAT
33
32
31
30
29
28
27
26
25
DDCDAT <23>
U13 C4754
0.1U/16V_4 2.2U/6.3V_4
XI
EXT1.2V_CTRL
SMB_SCL
PVCC_33
VCCK_12
SMB_SDA
LDO_RSTB
EPAD
HPD
DDCCLK DDCCLK <23>
HSYNC HSYNC <23>

AVCC33 1 24
AVCC_33 GND
AUX_CH_P 2 23 CRT_RED VSYNC VSYNC <23>
AUX_P RED_P
AUX_CH_N 3 22 CRT_GRE
AUX_N GREEN_P
VCCK_V12
LANE0_P
4
5
AVCC_12
LANE0_P
RTD2166 VDD_DAC_33
BLUE_P
21
20
CRT_BLU
VDD_DAC_33
VDD_DAC_33
C4748 C4750
CRT_AUXN C343 0.1U/16V_4 AUX_CH_N 0.1U/16V_4 LANE0_N 6 19 HSYNC
LANE0_N HSYNC 0.1U/16V_4 CRT_RED CRT_RED <23>
CRT_AUXP C341 0.1U/16V_4 AUX_CH_P LANE1_P 7 18 VSYNC +5V
LANE1_P VSYNC
POL1/SPI_CEB
LANE1_N 8 17 CRT_GRE CRT_GRE <23>
LANE1_N HVSYNC_PWR
VGA_SDA
VGA_SCL
C4749
SPI_CLK
VCC_33
CRT_BLU
SPI_SO
C4753 CRT_BLU <23>
SPI_SI
CRT_TXP0 C335 0.1U/16V_4 LANE0_P
POL2
0.1U/16V_4 4.7U/6.3V_4
CRT_TXN0 C331 0.1U/16V_4 LANE0_N

9
4.7K_4 10
11
12
13
14
15
16
B +3V +3V B
RTD_PIN12
CRT_TXP1 C329 0.1U/16V_4 LANE1_P

RTD_PIN11
DDCDAT
DDCCLK
R11188
+3V R11187
CRT_TXN1 C315 0.1U/16V_4 LANE1_N 4.7K_4
+3V
R11285 R11286
4.7K_4 *4.7K_4
RTD_PIN11 RTD_PIN12
TP4376
Note:
1- C1,C3,C4,C5,C11,C16, C21 should be placed close to chip
2- C5 shold be X5R material
3- R6, R7, R8 should be 75 ohm with +/-1%
4- Suggest to connect Pin 29 and Pin 30 to PCH SMBUS for debug purpose.
5- This configuration is for internal ROM mode and using embedded LDO mode.
A A
+3V <2,4,6,7,8,9,12,13,14,16,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>
+5V <23,24,26,27,29,33,40>

PROJECT : ZAA
WWW.AliSaler.Com
1A
RTD2166-CG
5 4 3 2 1
5 4 3 2 1
CRT +5V
CRTVDD5
C304 *0.1u/16V_4
R11267 *short_4 CRTHSYNC_B R11268 47_4 Q21
C720 +5V 3 1
IN OUT 2 CRTVDD5 CN7
16
U40 0.1u/16V_4 GND
AP2331SA-7
1 5 6
OE# VCC L7 BLM15BB220SN1D_6 CRT_R1 1 11 CRT_11
<22> CRT_RED TP75
7
HSYNC 2 4 R11269 *33_4 CRTHSYNC L6 BLM15BB220SN1D_6 CRT_G1 2 12 DDCDAT DDCDAT <22>
<22> HSYNC A Y <22> CRT_GRE
8
L5 BLM15BB220SN1D_6 CRT_B1 3 13 CRTHSYNC
<22> CRT_BLU
3 9
GND 4 14 CRTVSYNC
C337 C334 C320 C319 C333 C336 10
D D
*M74VHC1GT125DF2G R222 R219 R213 5 15 DDCCLK DDCCLK <22>
75/F_4 75/F_4 75/F_4 5.6p/16V_4 5.6p/16V_4 5.6p/16V_4 *5.6p/16V_4 *5.6p/16V_4 *5.6p/16V_4
+5V CRT CONN
17
DDCDAT 2.2K_4 R620 CRTVDD5
R11270 *short_4 CRTVSYNC_B R11271 47_4 DDCCLK 2.2K_4 R601
C713
U36
U37 0.1u/16V_4 CRTHSYNC 1 10 CRTHSYNC C305 *0.22u/6.3V_4
CRTVDD5 2 1 10 9 CRTVDD5
1 5 3 2 9 C300 *220p/50V_4
OE# VCC CRTVSYNC 4 GND_3/8 7 CRTVSYNC
DDCCLK 5 4 7 6 DDCCLK C301 0.1u/16V_4 CRTVDD5
VSYNC 2 4 R11272 *33_4 CRTVSYNC 5 6
<22> VSYNC A Y *RClamp0524P C716 *33P/50V_4 CRTVSYNC
3 U38 C718 *33P/50V_4 CRTHSYNC

GND CRT_R1 1 10 CRT_R1
CRT_G1 2 1 10 9 CRT_G1 C714 *10p/50V_4 DDCCLK
*M74VHC1GT125DF2G 3 2 9
DDCDAT 4 GND_3/8 7 DDCDAT C724 *10p/50V_4 DDCDAT
CRT_B1 5 4 7 6 CRT_B1
5 6 +5V <22,24,26,27,29,33,40>
+3V <2,4,6,7,8,9,12,13,14,16,22,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>
*RClamp0524P
VIN <26,27,32,33,34,35,36,37,38,39,40,41,42>
2,nd
LCD CONNECTOR LCD Power AL005245000
VIN TP_PWR CCD_PWR
+3V
C7 C9 C577 C578 C27 C16

AL002821000
C41 U1 LCDVCC
4.7u/25V_8 1000p/50V_4 0.1u/16V_4 0.1u/10V_4
C 1000p/50V_4 1000p/50V_4 1u/6.3V_4 6 1 LCDVCC C
IN OUT
4 2 C33 C29 C35 C34 C30
IN GND
R37 *short_4 EDP_VDD_EN_R 3 5 *0.1u/16V_4 *2.2u/10V_8 0.1u/16V_4 0.01u/50V_4 22u/6.3V_8
<2> EDP_VDD_EN ON/OFF GND
+3V 1A-5 VIN AP2821KTR-G1
R38
R15 *short_8 LVDS_CONN
MAX 1.5A
G_5
R447 *100K_4 EDP_AUX_C R448 *100K_4 R14 *short_8 V_BLIGHT
R450 *100K_4 EDP_AUX#_C R449 *100K_4 40 100K_4
TP_RST# R444 *TSI@10K_4 39
38
LCDVCC C580 C581 37
*1u/6.3V_4 *1u/6.3V_4 36
R28 *short_8 LCDVCC_R 35
R11 *short_6 CCD_PWR 34
2013/12/12 change eDP pin define +3V 33
32
colayout FHD Panel for A2 stage R16 0_6 TP_PWR 31 G_4 Touch screen level shift I2C(reserve) +3V
+5V 30
+3V R19 *0_6 TP_RST#
29
PCH_BRIGHT 28
Prevent ESD/EOS Layout near device <2> PCH_BRIGHT 27
BL_ON
R457 33_4 EDP_HPD_R 26
<2> EDP_HPD 25 R10 *TSI@0_4 R9 R12
EDP_AUX C4 .1U/16V_4 EDP_AUX_C 24 *TSI@10K_4 *TSI@10K_4 S0
<2> EDP_AUXP 23
C804 EDP_AUX# C2 .1U/16V_4 EDP_AUX#_C
180P/50V_4
<2> EDP_AUXN 22 S5 Q2
TPD->100kHz,TS=400Khz
EDP_TXP1 C10 .1U/16V_4 EDP_TXP1_C 21
<2> EDP_TXP1 20
Intel design guide suggestion
eDP FHD <2> EDP_TXN1 EDP_TXN1 C8 .1U/16V_4 EDP_TXN1_C <4> I2C1_SDA 6 1 I2C1_SDA_C MCP PIN 10u.
19
18 Per inch 3u TS=3x5inch
EDP_TXP0 C13 .1U/16V_4 EDP_TXP0_C 2 400kHz10~100u =2.4~0.4k.
<2> EDP_TXP0 17 +3V
EDP_TXN0 C12 .1U/16V_4 EDP_TXN0_C
<2> EDP_TXN0 16 100Khz 10~100u=9k~1k.
I2C1_SCL_C R6 *TSI@0_4 R2 *short_4 USBP6+_R 15 3 4 I2C1_SCL_C
B Touch Panel-I2C I2C1_SDA_C R5 *TSI@0_4
<6> USBP6+
R1 *short_4 USBP6-_R 14 <4> I2C1_SCL B
CCD-USB <6> USBP6- 13 5
USBP5+ R4 TSU@0_4 12
<6> USBP5+ 11
Touch Panel-USB <6> USBP5- USBP5- R3 TSU@0_4
10 G_1 *TSI@2N7002DW
EDP_TXP2 C3224 .1U/16V_4 EDP_TXP2_C 9 R13 *TSI@0_4
<2> EDP_TXP2 8
<2> EDP_TXN2 7
eDP 4k*2k TS_EN R442 *short_4 TS_EN_R
<31> TS_EN 6
EDP_TXP3 C3227 .1U/16V_4 EDP_TXP3_C
<2> EDP_TXP3 5
<2> EDP_TXN3 4
R441 33_4 BOARD_ID4_TOUCH_S 3 +3VPCU
<8> Board_ID4 2
TP_INT
1
G_0
S5 C803 CN5
180P/50V_4
R53
Prevent ESD/EOS Layout near device *100K_4
+3V LID# LID# <31>

LID591#,EC intrnal PU
TS_EN R443 *0_4 TP_INT
D1
R52 R58 1N4148WS
1C1-2 2014/03/11 Add R698 for TS_EN short TP_INT,
for issue debug. 10K_4 10K_4
R67 *short_4 PCH_BLON_C BL_ON
+3V
Hall Sensor (HSR) <31>
<2> PCH_BLON
PCH_BLON_R R66 *short_4 R65

BL#
3
LID# R11129 *short_4 LID#15
Rev:D +3VPCU 100K_4
2
change to 2
EC_FPBACK# <31>
D23
R7
shortpad R435 *100K_4 *VPORT_6 Q4
Touch Panel interrupt
*TSI@10K_4 Q3 DTC144EUA
1
2
2N7002DW
1
A R434 A
1
3 1 D28
TP_INT *short_6
<4> TP_INT_PCH *VPORT_6
Q1 1 2 1 2 LID#15
S5 *TSI@2N7002K S0
R8 *TSI@0_4 1B-3 2013/12/10 change Q3.3 from +3V to +3VPCU.
C556
3
4.7U/6.3V_4 MR1
AH9249NTR-G1

AL009132001 (default)
AL008132004 PROJECT : ZAA
AL008251000 Size Document Number Rev
1A
CRT/LVDS/CAMERA/LID
5 4 3 2 1
5 4 3 2 1
D D
+3V
HDMI_MB_HPD
HDMI_DDCDATA_MB +3V +3V
HDMI_DDCCLK_MB HDMI_EQ0 R11274 *10K_4 HDMI_EQ1 R11275 10K_4
+3V R11277 0_4 R11276 *0_4
C4609
0.1U/16V_4_X7R C4784
0.1U/16V_4_X7R
U18
24
23
22
21
20
19
18
17
PTN3366BS
HPD_SNK
SDA_SNK
SCL_SNK
GND
TERM_EN
DDC_EN
VDD
OE_N
HDMI_DDCDATA_SW
<2> HDMI_DDCDATA_SW
HDMI_DDCCLK_SW
<2> HDMI_DDCCLK_SW
INT_HDMITX0P C405 0.1u/16V_4 INT_HDMITX0P_C_R 25 16 INT_HDMITX0P_C

<2> INT_HDMITX0P IN_D1- OUT_D1-
INT_HDMITX0N C398 0.1u/16V_4 INT_HDMITX0N_C_R 26 15 INT_HDMITX0N_C
<2> INT_HDMITX0N IN_D1+ OUT_D1+
From PCH <2>
<2>
INT_HDMITX1P
INT_HDMITX1N
INT_HDMITX1N C406 0.1u/16V_4 INT_HDMITX1N_C_R 28 IN_D2-
IN_D2+
OUT_D2-
OUT_D2+
13 INT_HDMITX1N_C
<2> INT_HDMITX2P IN_D3- OUT_D3-
INT_HDMITX2N C408 0.1u/16V_4 INT_HDMITX2N_C_R 30 11 INT_HDMITX2N_C
<2> INT_HDMITX2N IN_D3+ OUT_D3+
INT_HDMICLK+ C389 0.1u/16V_4 INT_HDMICLK+_C_R 31 10 INT_HDMICLK+_C
<2> INT_HDMICLK+ IN_D4- OUT_D4-
INT_HDMICLK- C387 0.1u/16V_4 INT_HDMICLK-_C_R 32 9 INT_HDMICLK-_C
<2> INT_HDMICLK- IN_D4+ OUT_D4+
C C
33 37
HPD_SRC
SDA_SRC
SCL_SRC
CEN_PAD GND 36
GND
REXT
35
GND
VDD
EQ1
EQ0
GND 34
GND
1
2
3
4
5
6
7
8
+3V
HDMI_DDCDATA_SW
HDMI_DDCCLK_SW
HDMI_MB_HPD_R
+3V
HDMI_EQ1
HDMI_EQ0
12.4K/F_4
C4783
0.1U/16V_4 C4785 C4608 C4607 C4786 C386 C413 C4787
0.1U/16V_4_X7R 0.1U/16V_4_X7R 0.1U/16V_4_X7R 0.1U/16V_4_X7R 0.1U/16V_4_X7R 0.1U/16V_4_X7R 0.1U/16V_4_X7R
R11273
+3V R322 2.2K_4 HDMI_DDCCLK_SW
R319 2.2K_4 HDMI_DDCDATA_SW
D31 RB501V-40 R316 2.2K_4

HDMI_5V 2 1 HDMI_DDCCLK_MB
B
D30 RB501V-40 R317 2.2K_4

HDMI connector B
2 1 HDMI_DDCDATA_MB
CN12
20
INT_HDMITX2P_C 1 SHELL1
2 D2+
INT_HDMITX2N_C 3 D2 Shield
INT_HDMITX1P_C 4 D2-
5 D1+
INT_HDMITX1N_C 6 D1 Shield
INT_HDMITX0P_C 7 D1-
+3V +3V 8 D0+
INT_HDMITX0N_C 9 D0 Shield 23
INT_HDMICLK+_C 10 D0- GND
11 CK+ 22
R722
EMI INT_HDMICLK-_C 12
13
CK Shield GND
CK-
S5-input S0 CE Remote
2
*1M_4 14
INT_HDMITX2P_C +5V HDMI_DDCCLK_MB 15 NC
1 3 HDMI_MB_HPD_R HDMI_DDCDATA_MB 16 DDC CLK
<2> INT_HDMI_HPD DDC DATA
R315 *120/F_4 Q26 17
Q41 3 1 HDMI_5V 18 GND
*2N7002K INT_HDMITX2N_C IN OUT 2 19 +5V
GND HDMI_MB_HPD R721 *short_4 HP_DET_CN HP DET 21
*short_4 R718 R11064 INT_HDMITX1P_C AP2331SA-7 C383 D6 SHELL2
1
100K_4 *220p/50V_4 *AZ5125-01J HDMI connector
R314 *120/F_4
DDS AL002331000 R720
INT_HDMITX1N_C 20K_4
2
INT_HDMITX0P_C
R312 *120/F_4
A A
INT_HDMITX0N_C
INT_HDMICLK+_C
R303 *120/F_4
+3V <2,4,6,7,8,9,12,13,14,16,22,23,25,26,27,28,29,31,33,34,35,36,37,40,41,42>
+5V <22,23,26,27,29,33,40>
INT_HDMICLK-_C
+1.5V <9,26,28,40>

PROJECT : ZAA
WWW.AliSaler.Com
1A
HDMI (PTN3366BS)
5 4 3 2 1
5 4 3 2 1
+3V <2,4,6,7,8,9,12,13,14,16,22,23,24,26,27,28,29,31,33,34,35,36,37,40,41,42>
LAN & Card reader Combo (LAN) +3VPCU
+3V_S5
<6,9,11,23,26,27,28,29,31,32,33,40,41,42>
<2,3,4,6,7,8,9,11,21,27,28,29,31,33,35,36,41> Card Reader (CRD)
Giga LAN (LAN)

10p/50V_4 C4606 LAN_XTALI
2'nd source
-->DFHS11FR170
2
1
D Y1 SP8 D
CN4
25MHZ C4603 *10P/50V_4
SP1 R11254 *short_4 SP1=SD_D1 SP7=SD_WP=MS_BS 11
4
3
LAN_XTAL2 TP4333 SP2 R11253 *short_4 SP2=SD_D0=MS_D1 SP8=SD_CD# 10 WP 16
10p/50V_4 C4605 SP3 R11255 *short_4 SP3=SD_CLK=MS_D0 SP6=SD_D2=MS_CLK 9 CD NC 17
PCIE_LAN_WAKE#_R SP4 R11136 *short_4 SP4=SD_CMD=MS_D2 SP1=SD_D1 8 DATA2 NC
SP2=SD_D0=MS_D1 7 DATA1
SP5 R11137 *short_4 SP5=SD_D3=MS_D3 6 DATA0
TP4336 SP6 R11138 *short_4 SP6=SD_D2=MS_CLK SP3=SD_CLK=MS_D0 *short_4 R11141 SD_CLK_R 5 VSS2
VDD10 TP44 TP4335 CLK
+3V3_SD_SW +3V3_SD_SW reserve for EMI 4
TP4334 SP7 R11139 *short_4 SP7=SD_WP=MS_BS 3 VDD
R11264 2.49K/F_4 RSET SP4=SD_CMD=MS_D2 2 VSS1
GND
GND
GND
GND
C4604 *10P/50V_4 SP8 R11256 *short_4 SP8=SD_CD# SP5=SD_D3=MS_D3 1 CMD
10 mils CD/DATA3
LANVCC SD-CARD
12
13
14
15
C4618
48
47
46
45
44
43
42
41
40
39
38
37
U15 C4617
Share Pin 4.7u/6.3V_4 0.1u/16V_4 R6308
LED1/GPO
RSET
LV_CEN
LED_CR
CKXTAL2
CKXTAL1
MS_CD#
SD_CD#
LED0
LED2
HV_GIGA
LANWAKEB
49 *2K/F_4
E_PAD
SP1 SD_D1
SP2 SD_D0 MS_D1
SP3 SD_CLK MS_D0
SP4 SD_CMD MS_D2
+3V SP5 SD_D3 MS_D3
VDDREG SP6 SD_D2 MS_CLK EMI
MDI_0+ 1 36 REGOUT SP7 SD_WP MS_BS
MDI_0- 2 MDIP0 REG_OUT 35 R11266 *short_8 LANVCC SP8 SD_CD# SP3=SD_CLK=MS_D0
3 MDIN0 VDDREG 34 ENSWREG R11258 *short_4 R11263
VDD10 SP9 MS_INS#
MDI_1+ 4 AVDD10 ENSWREG 33 1K_4
MDIP1 VDD1 VDD10
MDI_1- 5 32 R11259 *short_4 LANVCC
MDIN1 VD33 C4616
MDI_2+ 6 31 ISOLATEB
MDI_2- 7 MDIP2 ISOLATEBPIN 30
MDIN2 PERSTBPIN 10P/50V_4
VDD10 8 29 PCIE_REQ_LAN#_R SP1=SD_D1 C4611 *10p/50V_4
MDI_3+ 9 AVDD10 CLKREQBPIN 28 SP7 R11262
MDI_3- 10 MDIP3 QFN48 MS_BS/SD_WP# 27 VDD33/18 15K_4 SP2=SD_D0=MS_D1 C4612 *10p/50V_4
11 MDIN3 DV33_18 26 PCIE_RX5-_LAN_C C4602 0.1U/16V_4
LANVCC HV_GIGA HSON PCIE_RX5-_LAN <6>
+3V 12 25 PCIE_RX5+_LAN_C C4601 0.1U/16V_4 SP4=SD_CMD=MS_D2 C4614 *10p/50V_4
VDD3 HSOP PCIE_RX5+_LAN <6>
SP5=SD_D3=MS_D3 C4613 *10p/50V_4
SD_CMD/MS_D2
SD_CLK/MS_D0
SD_D2/MS_CLK
SD_D0/MS_D1
SD_D3/MS_D3
SP6=SD_D2=MS_CLK C4615 *10P/50V_4

REFCLK_N
CARD_3V3
REFCLK_P
C C
R11260 IOAC@0_4
VDDTX
SD_D1
IOAC_RST# <28,31>
HSIN
HSIP
R11261 NAC@0_4 PLTRST# <8,14,27,28,31>

+3V3_SD_SW
13
14
15
16
17
18
19
20
21
22
23
24
SP1
SP2
CLK_PCIE_LANN <6>
SP3
CLK_PCIE_LANP <6>
SP4 PCIE_TX5-_LAN <6>
SP5 PCIE_TX5+_LAN <6>
SP6
EVDD10
LANVCC
40 mils (Iout=1A)
Tramsformer
Leakage circuit (MPC) C354 C370 C365 C361
DB0LL1LAN00 --> Main
B Layout:All termination B
+3V +3V 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 *4.7U/6.3V_4 DB0Z06LAN00 --> 2'nd signal should have 30
DB0X81LAN00 --> 2'nd mil trace
+3V For RTL8411B
R281 R277 U42
CLK_PCIE_REQ4# have PU 10k. Place 0.1uF CAP close to each VDD33 pin-- 11, 32,48 1 24 LAN_MCT0
*10K/F_4 10K/F_4
TCT1 MCT1
2
MAIN POWER(3V_S0) MDI_3+ 2 23 LAN_MX3+

MDI_3- 3 TD1+ MX1+ 22 LAN_MX3-
3 1 PCIE_REQ_LAN#_R TD1- MX1-
S0 <6> CLK_PCIE_LAN_REQ#
Q25 MDI_2+
4
5 TCT2
TD2+
MCT2
MX2+
21
20
LAN_MCT1
LAN_MX2+
RJ45 Connector
2N7002K RTL8411B (LDO mode) close to each VDD10 pin-- 3, 8, 33, 46 close to each VDD10 pin-- 20 MDI_2- 6 19 LAN_MX2-
R276 *0_4 TD2- MX2-
REGOUT (reserve) 7 18 LAN_MCT2 CN11
LANVCC VDD10 MDI_1+ 8 TCT3 MCT3 17 LAN_MX1+
MDI_1- 9 TD3+ MX3+ 16 LAN_MX1- 9
FAE suggest to 40 mils (Iout=1A) 40 mils (Iout=1A) TD3- MX3- 9
R246
change to 1K *short_8 10 15 LAN_MCT3 10
MDI_0+ 11 TCT4 MCT4 14 LAN_MX0+ LAN_MX0+ 1 10
GND
R702 C363 C760 C762 C757 C355 C758 C761 MDI_0- 12 TD4+ MX4+ 13 LAN_MX0- LAN_MX0- 2 0+
IOAC@1K_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 *1U/6.3V_4 *0.1u/16V_4 TD4- MX4- LAN_MX1+ 3 0-
1+
75/F_8
75/F_8
75/F_8
75/F_8
TRANSFORMER LAN_MX2+ 4
25
2+
2
EC_PCU LANVCC LAN_MX2- 5

C364 LAN_MX1- 6 2-
R713 NAC@0_4 3 1 PCIE_LAN_WAKE#_R 0.01U/50V_4 LAN_MX3+ 7 1-
<8,28> PCIE_LAN_WAKE# 3+
LAN_MX3- 8
3-
R269
R262
R11265
R251
R715 IOAC@0_4 Q39
<31> IOAC_LAN_WAKE#
IOAC@2N7002K 11
11
12
R709 NAC@0_4 12
Reserve IOAC No Stuff
TERM9
RJ45
Q24 IOAC@AO3413 LANVCC +3V_S5
VDD10 EVDD10 VDDREG
1 3 +3V_LAN R248 R247 NAC@2.2_8
30 mils 40 mils 4/20 REV:D add TP85 ~TP100 for AZ chip ICT/ATE Capacitor test
+3VPCU 10 mils
C4782 IOAC@0_8 R11257 C746
R260 C366 C367 C350 C377 VDD33/18 *short_6 1000P/3KV_1808
2
*IOAC@0.1U/16V_4 *IOAC@100K_4 10u/6.3V_6 0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 C4600 C4599

C4596 C244 4.7U/6.3V_4 0.1U/16V_4
C4597 C4598
A A
1U/6.3V_4 0.1U/16V_4
<31> LANPWR# R259 *4.7u/6.3V_4 0.1U/16V_4
IOAC@10K_4 C368
*IOAC@1000p/50V_4
Place close to pin 27
Close to Pin20 Place connect to Pin35

PROJECT : ZAA
1A
LAN_CRD_COMBO_RTL8411
5 4 3 2 1
5 4 3 2 1
Codec(ADO) DC-DET circuit(ADO) Rev:D change to shortpad

R338 *short_6
+5V
HP-R2 VIN
3 1 PVDD
HP-L2
+5V C456 Q28
LINE1-VREFO-L R345 *10u/6.3V_4 *AO3404
2
*1M_6
LINE1-VREFO-R
MIC2-VREFO
Close to Codec R343
3
*100K_4
CODEC_VREF C535 2.2U/6.3V_4 ADOGND
DC-DET R344 *0_4 2 Q27
INT_AMIC-VREFO C534 10u/6.3V_4 *DTC144EU
D ADOGND +5VA D
C527
C528
C530
R397 100K_4
1
10u/6.3V_4
1U/6.3V_4
1U/6.3V_4
C536
C532
0.1u/16V_4 10u/6.3V_4
+AZA_VDD Far away rubber +3V

Place next to pin 26
+3V D-Mic (MIC) C373
C371
*10u/6.3V_4
*0.1u/16V_4
C356 10u/6.3V_4 C376 *10p/50V_4
36
35
34
33
32
31
30
29
28
27
26
25
+1.5VA
U23 C353 0.1u/16V_4
ADOGND C360 10p/50V_4 U16
CPVEE
HP-OUT-L
LINE1-VREFO-L
MIC2-VREFO
LDO1-CAP
AVDD1
AVSS1
CPVDD
CBN
HP-OUT-R
LINE1-VREFO-R
VREF
C520 1 3 DMIC_CLK_L1
C524 U17 VDD CLK
10u/6.3V_4 0.1u/16V_4 1 3 DMIC_CLK_L_R0 R11186 *short_4 DMIC_CLK_L 2 4 DMIC_DAT_L1
ADOGND 37 24 VDD CLK LR DATA
CBP LINE2-L
D4
D5
C378
C379
2 4 DMIC_DAT_L_R0 R11185 *short_4 DMIC_DAT_L 5 7
LR DATA GND GND
1
38 23 6 8
AVSS2 LINE2-R GND GND
D2
C357
C374
ADOGND 5 7
GND GND
D3
Place next to pin 40 C529 10u/6.3V_4 39 22 LINE1-L 6 8 R270 R11047 *KBL17@KMM40301026-18DS
LDO2-CAP LINE1-L GND GND
*TVS/6pF_4
*TVS/6pF_4
*10p/50V_4
*10p/50V_4
*0_4 *0_4 DUAL SECOND
2
Analog 40 21 LINE1-R Rev:D change to shortpad KMM40301026-18DS
AVDD2 LINE1-R
TVS/6pF_4
*10p/50V_4
*10p/50V_4
Single DMIC DMIC_CLK_L_R1 R11179 *0_4 DMIC_CLK_L1
TVS/6pF_4
Digital L13 +5V_PVDD 41 20 R388 *short_6
PVDD +3VPCU
2
PVDD1 NC analog digital DMIC_DAT_L_R1 DMIC_DAT_L1
PBY160808T-600Y-N(60,3A) DUAL MAIN R11180 *0_4
L_SPK+ 42 19 C519 10u/6.3V_4
SPK-L+ MIC-CAP ADOGND
C510 C509
10u/6.3V_4 0.1u/16V_4
L_SPK- 43
SPK-L-
ALC255 MIC2-R/SLEEVE
18 SLEEVE trace width of SLEEVE & RING2 Close to Codec R11181 R11182
R_SPK- 44 17 RING2 are required at least 40mil and *0_4 *0_4 +3V
SPK-R- MIC2-L/RING2 its length should be asshort as possible
Close to Codec Low is power down
R_SPK+ 45
SPK-R+ MONO-OUT
16 C4734 *10u/6.3V_4
C4735 *0.1u/16V_4
amplifier output 46 15 DMIC_CLK_L2 C4733 *10p/50V_4
PVDD2 SPDIFO/FRONT JD
GPIO0/DMIC-DATA
PD# 47 14 DMIC_DAT_L2
GPIO1/DMIC-CLK
Placement near Audio Codec U4512
C C501 C500 PDB MIC2/LIN2 JD 1 3 DMIC_CLK_L2 C
48 13 SENSEA R383 200K_4 HP_JD# VDD CLK
TP34 SPDIF-OUT SDATA-OUT HP/LINE1 JD
LDO3-CAP
10u/6.3V_4 0.1u/16V_4 2 4 DMIC_DAT_L2
SDATA-IN
DVDD-IO
LR DATA
PCBEEP
RESETB
BIT-CLK
R378 100K_4 +3V
DVDD
SYNC
C4737
D4013
C4736
D4012
49
DVSS
5 7
DGND GND GND
1
Analog 6 8
GND GND
Digital *KBL15@KMM40301026-18DS
1
10
11
12
*TVS/6pF_4
*TVS/6pF_4
*10p/50V_4
*10p/50V_4
DUAL SECOND
2
DMIC_DAT
DMIC_CLK
C481
+AZA_VDD
DC-DET

Change 47K to 22K for PCBEEP
1.6Vrms
R350
+3V R367 *short_6 +AZA_VDD Single DMIC and Dual DIMC same PN: AL403010A00
10u/6.3V_4
PCBEEP C476 0.1u/16V_4 BEEP_1 R352 22K_4 D9 1N4148WS

SPKR <4>
C477 D10 1N4148WS
PCBEEP_EC <31>
2'nd -->AL403010000 (KMM40301026-18DZ)
*short_4
C485 C484 100p/50V_4 R354

0.1u/16V_4 10u/6.3V_4
10K_4
+3V +1.5V
CPU 3.3V
Rev:D change to shortpad PCH_AZ_CODEC_RST# <4> Rev:E change connect to +3V
R365 0_4
DMIC_DAT_L R371 *short_4 PCH_AZ_CODEC_SYNC <4>
Tied at one point only DMIC_CLK_L R370 22_4 DVDD_IO R366 *0_4
under Rev:E change to 0402
the codec or near the codec
R394 *0_4 C488 ACZ_SDIN R359 33_4 C492 C489
R393
R399
*0_4
*0_4
10p/50V_4
PCH_AZ_CODEC_SDIN0
PCH_AZ_CODEC_BITCLK
<4>
<4> 0.1u/16V_4 10u/6.3V_4 Universal Audio Jack HEADPHONE/MIC/LINE combo (ADO)

R400 *0_4
R375 *0_4 C493 *22p/50V_4
R750 *short_4 Close to Codec MIC2-VREFO
C537 *1000p/50V_4 PCH_AZ_CODEC_SDOUT <4> Place next to pin 9 R407 2.2K_4
R420& R422 change to 62 ohm -> 3/11
C538 *0.1u/16V_4 R424 2.2K_4 Combo Jack
B B
SLEEVE R408 *short_4 SLEEVE_R
SLEEVE_R <30>
ADOGND
RING2 R425 *short_4 RING2_R
RING2_R <30>
Cap need near AVDD1 and
AVDD2 HP-L2 R422 62/F_4 HP-L3
HP-L3 <30>
power source input +3VPCU <6,9,11,23,25,27,28,29,31,32,33,40,41,42>
HP-R2 R420 62/F_4 HP-R3
+3V <2,4,6,7,8,9,12,13,14,16,22,23,24,25,27,28,29,31,33,34,35,36,37,40,41,42> HP-R3 <30>
+1.5V <9,28,40>
HP_JD#
HP_JD# <30>
R423 R417
+5V <22,23,24,27,29,33,40>
LINE1-L C552 4.7U/6.3V_4 *10K_4 *10K_4 C547 C554 C553 C550
LINE1-VREFO-L R421 4.7K_4 100p/50V_4 100p/50V_4 100p/50V_4 100p/50V_4
LINE1-VREFO-R R418 4.7K_4
Codec PWR 5V(ADO) Mute(ADO)

+AZA_VDD +1.5V
LINE1-R C549 4.7U/6.3V_4 ADOGND
To small/B
R372
1K_4
2
DIGITAL ANALOG
PD# D15 *RB500V-40 3 1 PCH_AZ_CODEC_RST#
L16 HCB2012KF220T60/6A/22ohm_8
+5V +5VA R369
3
U25
IN OUT
4
*10K_4 C494
*1u/10V_4
Q29
*PJA138K Codec PWR 1.5V(ADO)
2 D16 RB500V-40
GND AMP_MUTE# <31>
C523 C526
1 5 R395 *29.4K/F_4
SHDN SET *10u/6.3V_6 *0.1u/16V_4 +1.5VA
*G923-330T1UF
C525 C515 R390 DIGITAL ANALOG
A *10K/F_4 A
*0.1u/16V_4 *10u/6.3V_6 ADOGND
Internal Speaker +1.5V L18 HCB1608KF-121T30_3A
R401 *0_4
40mil for each signal 4 ohm : 40mil for each signal C541
ADOGND SPK_CONN_4P 1U/6.3V_4

1003 change 0603type
R_SPK+ R419 *short_6 R_SPK+_1
R_SPK- R414 *short_6 R_SPK-_1 1
L_SPK- R406 *short_6 L_SPK-_1 2
L_SPK+ L_SPK+_1 3 5
C730, C787 close U37 pin3 and L65 R404 *short_6
4 6
CN18 Quanta Computer Inc.
C551 C548 C546 C545
*68p/50V_4 *68p/50V_4 *68p/50V_4 *68p/50V_4 PROJECT : ZAA
1B-2 2013/12/04 Change PN and footprint. Size Document Number Rev
WWW.AliSaler.Com 5 4 3
1B-5 2013/12/17 Change CN14 pin define
2
Date:
ALC255/HP/SPK
Friday, February 05, 2016
1
Sheet 26 of 48
1A
5 4 3 2 1
+5V <22,23,24,26,29,33,40>
+3V <2,4,6,7,8,9,12,13,14,16,22,23,24,25,26,28,29,31,33,34,35,36,37,40,41,42>
2.5" SATA HDD (HDD) +3VPCU <6,9,11,23,25,26,28,29,31,32,33,40,41,42>

SATA ODD Connector +3V_S5 <2,3,4,6,7,8,9,11,21,25,28,29,31,33,35,36,41>
CN14
23
GND23 +3V_LDO_EC <7,31,33>
1
GND1 2 SATA_TXP0_C C522 0.01u/50V_4
RXP SATA_TXP0 <6>
3 SATA_TXN0_C C513 0.01u/50V_4 SATA_TXN0 <6> CN9
RXN 4 14
GND2 5 SATA_RXN0_C C507 0.01u/50V_4 GND14
TXN 6 SATA_RXN0 <6> 1
SATA_RXP0_C C504 0.01u/50V_4
TXP SATA_RXP0 <6> GND1
7 2 SATA_TXP1_C C751 0.01u/50V_4 SATA_TXP1 <6>
GND3 RXP 3 SATA_TXN1_C C749 0.01u/50V_4
RXN SATA_TXN1 <6>
4
D 8 GND2 5 SATA_RXN1_C C744 0.01u/50V_4 D
3.3V 9 DEVSLP0_R DEVSLP0 TXN 6 SATA_RXP1_C SATA_RXN1 <6>
R351 *0_4 DEVSLP0 <6> C743 0.01u/50V_4
3.3V TXP SATA_RXP1 <6>
10 7 C802 180P/50V_4
3.3V 11 GND3 SSD_ID <6>
R217 33_4
GND ODD_PRSNT# <4>
12 R216 10K_4 Prevent ESD/EOS Layout near device
GND +5V +3V
13 1B-4 8 ODD_PRSNT#_C C330 *15p/50V_4
GND 14 DP 9 +5VODD R657 *short_8
5V 15 +5V_HDD 60mil R339 *short_8 +5V 10
+5V_ODD
5V 16 +5V 11 C726 C721 C733 C730 C737 C740
+
5V 17 C437 C436 C435 C453 C438 C457 RSVD 12
GND 18 + GND 13 0.01u/50V_4 0.01u/50V_4 *0.1u/16V_4 *0.1u/16V_4 10u/6.3V_6 *100u/6.3V_3528
RSVD 19 0.01u/50V_4 0.01u/50V_4 *0.1u/16V_4 *0.1u/16V_4 10u/6.3V_6 *100u/6.3V_3528 GND
GND 20 15
12V 21 GND15
12V 22 C185Q2-11311-L
12V EC_ODD_EJ# <31>
24
GND24 1A-8
HDD_CONN(on board) R326 *0_4 ACCEL_INT2 ACCEL_INT2 <29> R209 10K_4 +3V
Connect to G-sensor INT2
ODD Power (SATA) +3VPCU

VIN +5V
Q34
IOAC@AO6402A +5V_ODD
+5V
1
6
C C
R695 5 4 R672 NAC@0_8
IOAC@100K 2
1 R673
Reserve IOAC Power No Stuff IOAC@22_8
2
R686
3
ODD_EN_Q 2 1
MOD_EN_5V
IOAC@100K
3
<31> ODD_POWER R704 IOAC@0_4 ODD_EN
ODD_EN_Q 2
1
<2> PCH_ODD_EN R703 *IOAC@0_4

C752 Q36
R692 IOAC@0.1u/25V_4 IOAC@DMN601K-7
2
*IOAC@100K
1
2
IOAC@2N7002DW
Q37
4
POA(FPD) for Intel Base plateform POA_PWR +3V

POA_PWR
SEL OE# Y+ Y- +3VPCU R11297 *FPD_SP@0_4

B B
X H Hi-Z Hi-Z Spec define: High Active C3001 *FPD@2.2u/16V_6
TPM NPCT650 (TPM) L L M+ M-
but USBON# is Low Active
+3V_LDO_EC R11289 *FPD_SP@0_4
R11287 FPD_SP@0_4
1
+3V3_TPM_VSB
H L D+ D-
Q75
+3V_S5 +3V3_TPM FPD@AO3413
+3V_S5 R2854 2 R11296
<31> POA_FP_PWREN#
R745 *short_6 FPD@10K_4 *FPD_SP@0_4
C776 TPM@10u/6.3V_6 R725 *short_6
C775 TPM@0.1u/16V_4 C4819
C774 TPM@0.1u/16V_4 C767 TPM@10u/6.3V_6
3
C768 TPM@0.1u/16V_4 C766 TPM@0.1u/16V_4 *1000p/50V_4
20mil V_POA_Q R2855 *short_4 20mil
22
14
U44 C3000
8
C3002
VDD3
VDD2
VDD1
VSB
FPD@4.7u/6.3V_4
FPD@0.01u/50V_4 CN95
V_POA_R 1 10
USBP8+_R 2 9
LPC_LAD3 15 4 TPM_PP USBP8-_R 3
<7,28,31> LPC_LAD3 LAD3 PP TP4358
LPC_LAD2 18 3 GPX 4
<7,28,31>
<7,28,31>
LPC_LAD2
LPC_LAD1
LPC_LAD1
LPC_LAD0
21
24
LAD2/SPI_IRQ
LAD1/MOSI
GPX/GPIO2
GPIO1
30 TP4359
TP4360 USBP8+
Co-layout
R11290 *FPD_SP@0_4 USBP8+_PI3 <31> POA_EN#
R11292
R11293
FPD_SP@0_4
FPD_SP@0_4
5
6
<7,28,31> LPC_LAD0 LAD0/MISO <6> USBP8+ <31> POA_PWR_INT#
LPC_LFRAME# 20 29 USBP8- R11291 *FPD_SP@0_4 USBP8-_PI3 R11294 FPD_SP@0_4 7
<7,28,31> LPC_LFRAME# LFRAME/SCS GPIO0/XOR_OUT TP4361 <6> USBP8- <31> POA_AUTH_ERR
IRQ_SERIRQ 27 6 TPM_BADD R729 *TPM@10K_4 R11295 FPD_SP@0_4 8
<7,31> IRQ_SERIRQ SERIRQ GPIO3/BADD <31> POA_POWERREQ
PCLK_TPM 19 5 R11298 FPD_SP@0_4 USBP8+_R_COM
<7> PCLK_TPM LCLK/SCLK TEST R11299 FPD_SP@0_4 USBP8-_R_COM FPD@CONN_AOP
CLKRUN# R743 *short_4 TPM_CLKRUN# 13 2
<7,31> CLKRUN# CLKRUN/GPIO04 NC1
PLTRST# R742 *short_4 TPM_LRESET# 17 7
<8,14,25,28,31> PLTRST# LRESET/SPI_RST NC2
LPCPD 28 10
LPCPD NC3 U1006
11 USBP8+_R
26 NC4 12 USBP8-_R
31 NC7 NC5 25 BADD SELECTION +3VPCU USBP8+_PI3 1 4 TP4396
NC8 NC6 Y+ M-
GND1
GND2
GND3
GND4
A 0 EEh - EFh USBP8-_PI3 2 5 TP4397 A

B.M.
Y- M+
3/4 EMI request add 33p near TPM IC 1 7Eh - 7Fh 3
GND D-
6 USBP8-_R_PI3 EC52 EC53
R2870 *short_4 R2868 *FPD_SP@10_4 9 7 USBP8+_R_PI3 *AZ5725-01F *AZ5725-01F
C807 10 VCC D+ 8
TPM@NPCT620/650_QFN32 R2872 *short_4
33
9
16
23
32
CLKRUN# '1' - pin is left open. C3007 C3008 SEL OE#

'0' - pin is pulled down. EMI
+3V3_TPM *FPD_SP@0.01u/50V_4 *FPD_SP@0.1U/16V/X7R_4 *FPD_SP@PI3USB102
TPM@33P/50V_4
LPCPD R744 *TPM@4.7K_4
USBP8+_R_PI3
USBP8-_R_PI3
R11302 *FPD_SP@0_4 USBP8+_R
USBP8-_R
R11303 *FPD_SP@0_4
<8,31> MAINON
USBP8+_R_COM R11300 FPD_SP@0_4
PROJECT : ZAA
USBP8-_R_COM R11301 FPD_SP@0_4 Size Document Number Rev
1A
Co-layout Date:
HDD/ODD/TPM NPCT650
Friday, February 05, 2016 Sheet 27 of 48
5 4 3 2 1
5 4 3 2 1
NGFF_M.2 WiFi & BT (NGF)

CN10
Leakage circuit (MPC)
+WL_VDD +WL_VDD
NGFF +WL_VDD Stuff
1 2 +3V +WL_VDD +WL_VDD +3V
USBP4+ 3 GND 3.3Vaux 4 C340 10u/6.3V_6 +3V
<6> USBP4+ USB_D+ 3.3Vaux
USBP4- 5 6 C755 0.1u/16V_4 R237 NAC@0_8
<6> USBP4- USB_D- LED#1
7 8 C753 0.1u/16V_4
9 GND PCM_CLK 10 C735 0.1u/16V_4
SDIO CLK(O) PCM_SYNC R245 R242
11 12 C731 0.1u/16V_4 APU Internal PU 2N7002DW R241 C347 C346 C338 C339
13 SDIO CMDIO) PCM_IN 14 APU External nu-PU 4.7K_4 4.7K_4
*10K_4 *10u/6.3V_6 *0.1u/16V_4 **0.1u/16V_4 **0.1u/16V_4
15 SDIO DAT0(IO) PCM_OUT 16 5
SDIO DAT1(IO) LED#2
IOAC S0
17 18
19 SDIO DAT2(IO) GND 20 WLAN_CLKREQ# 4 3
D 21 SDIO DAT3(IO) UART Wake 22 S0 PCIE_CLKREQ_WLAN# <6> D
23 SDIO Wake(I) UART Rx 24
25 SDIO Reset Key 5 26 2
KEY1 Key 6
IOAC
27 28 EC_PCU
29 KEY2 Key 7 30 WLAN_WAKE_R# 1 6 Low Mini card +3V power enable Q22 IOAC@AO3413 +WL_VDD
31 KEY3 Key 8 32 S0 IOAC_WLAN_WAKE# <31>
33 KEY4 UART Tx 34 Q23 1 3+3V_WLAN R221
<6> PCIE_TX6+_WLAN
PCIE_TX6+_WLAN 35 GND UART CTS 36 High Mini card +3V power disable +3VPCU
*short_8
PCIE_TX6-_WLAN 37 PETp0 UART RTS 38 R243 *0_4 R244 C345
<6> PCIE_TX6-_WLAN PETn0 Clink RESET
39 40 R253 *0_4 R231
PCIE_LAN_WAKE# <8,25>
2
PCIE_RX6+_WLAN 41 GND CLink DATA 42 WIFI_SUSCLK *IOAC@0.1U/16V_4
<6> PCIE_RX6+_WLAN PERp0 CLink CLK
PCIE_RX6-_WLAN 43 44 *0_4 *IOAC@100K_4
<6> PCIE_RX6-_WLAN
45 PERn0 COEX3 46 C821 180P/50V_4
IOAC No Stuff S0
CLK_PCIE_WLANP 47 GND COEX2 48 WLANPWR#
<6> CLK_PCIE_WLANP REFCLKP0 COEX1 <31> WLANPWR#
<6> CLK_PCIE_WLANN CLK_PCIE_WLANN 49 50 R680 IOAC@0_4 WIFI card reset (IOAC) R230
REFCLKN0 SUSCLK(32KHz) IOAC_RST# <25,31>
51 52 WLAN_RST# R671 NAC@0_4 PLTRST# WIFI card reset (non-IOAC) IOAC@10K_4 C344
GND PERST0# PLTRST# <8,14,25,27,31>
WLAN_CLKREQ# 53 54 BT_EN BT_EN <31>
WLAN_WAKE_R# 55 CLKREQ0# W_DISABLE#2 56 RF_EN *IOAC@1000p/50V_4
PEWake0# W_DISABLE#1 RF_EN <31>
57 58 Reserve only for Intel module no need to stuff by default 11/24
59 GND NFC I2C SM DATA 60 Reserve IOAC No Stuff
61 PETp1 NFC I2C SM CLK 62
63 PETn1 NFC I2C IRQ 64 LPC_LAD0_C R688 *short_4 LPC_LAD0
GND NFC Reset# LPC_LAD0 <7,27,31> +3V_S5
65 66 LPC_LAD1_C R690 *short_4 LPC_LAD1 U43 +WL_VDD
PERp1 RESERVED3 LPC_LAD1 <7,27,31>
67 68 LPC_LAD2_C R693 *short_4 LPC_LAD2
PERn1 RESERVED4 LPC_LAD2 <7,27,31>
69 70 LPC_LAD3_C R696 *short_4 LPC_LAD3 R716 **10K_4 1 5
<7> CLK_PCI_LPC CLK_PCI_LPC R694 *0_4 CLK_PCI_LPC_C 71 GND RESERVED5 72
LPC_LAD3 <7,27,31> +3V_S5 NC VCC Reserver +1.5v for WIFI module
1
LPC_LFRAME# R699 *0_4 LPC_LFRAME#_C 73 Reserved1 3.3Vaux 74 +WL_VDD Rev:D change to shortpad R714 Q38 *IOAC@AO3413
<7,27,31> LPC_LFRAME# Reserved2 3.3Vaux
75 <6> SUSCLK SUSCLK 2 C763 *10K_4
GND A *0.1u/16V_4 1 3+3V_WLAN
+1.5V
2
For Debud Card use WLAN_NGFF CONN 3 4 WIFI_SUSCLK C759
GND Y R712
2
**IOAC@0.1U/16V_4
*74AUP1G07GW **IOAC@100K_4
WLANPWR#
R710
*IOAC@10K_4 C756
**IOAC@1000p/50V_4
No Stuff
C C
+3V3_SATA_N1 +3V
C1162 *150u/6.3V_3528 R948 C1163 10u/6.3V_6

+ *short_8 C1164 0.1u/10V_4 CN23
C1165 10u/6.3V_6 +3V3_SATA_N1
C1166 0.1u/10V_4
C1167 0.1u/10V_4 1
NGFF 2
+3V <2,4,6,7,8,9,12,13,14,16,22,23,24,25,26,27,29,31,33,34,35,36,37,40,41,42>
GND 3.3V +3VPCU <6,9,11,23,25,26,27,29,31,32,33,40,41,42>
C1168 0.1u/10V_4 3 4
C1169 0.1u/10V_4 5 GND 3.3V 6
PERn3 NC +3V3_SATA_N1_N +3V3_SATA_N1 +3V_S5 <2,3,4,6,7,8,9,11,21,25,27,29,31,33,35,36,41>
7 8
PERp3 NC +1.5V <9,26,40>
9 10 TP108
11 GND DAS 12 R951
13 PETn3 NOTCH/3.3V 14 *short_8
15 PETp3/NOTCH NOTCH/3.3V 16
17 GND/NOTCH NOTCH/3.3V 18
19 PERn2/NOTCH NOTCH/3.3V 20
21 PERp2/NOTCH NC 22
23 GND/CONFIG_0 NC 24
25 PETn2 NC 26
27 PETp2 NC 28
R959 *short_4 SATA_RXN3/PEG_RXN9_L0_N 29 GND NC 30
<6> SATA_RXN3/PEG_RXN9_L0 PERn1 NC
<6> SATA_RXP3/PEG_RXP9_L0 R958 *short_4 SATA_RXP3/PEG_RXP9_L0_N 31 32
33 PERp1 NC 34
C1176 0.1u/10V_4 SATA_TXN3/PEG_TXN9_L0_N 35 GND NC 36
<6> SATA_TXN3/PEG_TXN9_L0 PETn1 NC
<6> SATA_TXP3/PEG_TXP9_L0 C1177 0.1u/10V_4 SATA_TXP3/PEG_TXP9_L0_N 37 38 DEVSLP_N1 R956 *short_4 SATA_DEVSLP2 <6>
39 PETp1 DEVSLP 40 R957 *10K_4
R11061 *short_4 SATA_RXP3/PEG_RXP10_L1_N 41 GND NC 42
<6> SATA_RXP3/PEG_RXP10_L1 PERn0/SATA-B+ NC
<6> SATA_RXN3/PEG_RXN10_L1 R11062 *short_4 SATA_RXN3/PEG_RXN10_L1_N 43 44
45 PERp0/SATA-B- NC 46
C4664 0.1u/10V_4 SATA_TXN3/PEG_TXN10_L1_N 47 GND NC 48
<6> SATA_TXN3/PEG_TXN10_L1 PETn0/SATA-A- NC
<6> SATA_TXP3/PEG_TXP10_L1 C4665 0.1u/10V_4 SATA_TXP3/PEG_TXP10_L1_N 49 50 NGFF1_RST#_SSD R960 *short_4 PLTRST#
51 PETp0/SATA-A+ PERST# 52 PCIE_CLKREQ_NGFF_SSD#_R R11110 *short_4
B GND CLKREQ# PCIE_CLKREQ_NGFF_SSD# <6> B
<6> NGFF_SSD_CLK#
53 54
55 REFCLKn PEWake# 56 TP109
<6> NGFF_SSD_CLK REFCLKp N/C
57 58 TP150
+3V 59 GND N/C 60
61 NOTCH NOTCH 62
R11284 10K_4 63 NOTCH NOTCH 64
<6> NGFF_SATA_DET NOTCH NOTCH +3V3_SATA_N1
R961 1M_4 65 66
67 NOTCH NOTCH 68 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD8 PAD7 PAD10 PAD9 PAD11
3
NGFF3_PEDET 69 NC SUSCLK(32KHz) 70 *SPAD-ZAB-1NP *SPAD-ZAB-2NP *SPAD-RE157X488NP *SPAD-RE157X1282NP *SPAD-ZAB-3NP *SPAD-C298NP *SPAD-C298NP *spad-re157x491np *SPAD-RE157X1267NP *SPAD-C276NP *SPAD-RE531X205NP
Q59 71 PEDET 3.3V 72
R968 73 GND 3.3V 74
2 75 GND 3.3V
GND
GND
GND
*0_4
1
1
2N7002K SSD@SSD_NGFF_CONN
76
77
1
HOLE23 HOLE24
*HG-C315D134P2 *HG-C315D134P2
HOLE1 HOLE2 HOLE3 HOLE4 PAD12 PAD13 PAD14 7 6 7 6
14” DFHS75FR307 ( TH=5.0 a-test) *HG-C354D134P2 *HG-C354D134P2 *HG-C354D134P2 *HG-C354D134P2 *SPAD-RE157X315NP *SPAD-C197NP *o-zab-1 8 5 8 5
15”/ 17” DFHS75FR299 ( TH=4.8 a-test) 7
8
6
5
7
8
6
5
7
8
6
5
7
8
6
5
9 4 9 4
9 4 9 4 9 4 9 4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
HOLE6 HOLE7 HOLE13 HOLE14 HOLE15
*o-zab-2 *hg-tc354ic236bc236d118p2 HOLE8 HOLE9 HOLE10 HOLE11 HOLE12 H-C256D161P2 H-C256D161P2 H-C256D161P2
6 7 6 H-C236I156D140P2 H-C236D140P2 *H-TC236IC236BC256D161P2 *H-TC236IC236BC256D161P2 *H-TC236IC236BC256D161P2
5 8 5
4 9 4
1
2
3
1
2
3
1
1
1
A A
GPU
M.2
HOLE19 HOLE20 HOLE21 HOLE22
HOLE25 HOLE16 HOLE17 HOLE18 *H-ZAB-5 *H-C87D87N *H-O146X87D146X87N *O-ZAA-1
*H-C217D217N H-TC217IC197BC197D126P2 *hg-zab-2 *hg-zab-2
7 6 7 6
8 5 8 5
9 4 9 4
1
1
1
1
2
3
1
2
3
PROJECT : ZAA
K/B
WWW.AliSaler.Com
1A
Mini-Card/WL/3G/SIM
5 4 3 2 1
5 4 3 2 1
For 17"
TOUCHPAD BOARD CONN (TPD I2C/PS2 co-lay) 1C-2 2014/01/13 Change TP power rail from +3V_S51C-4 2014/01/15 reserve TP power rail +3V_S5.
KEYBOARD (KBC) CN2019
1 MX0
to +3V_SUS.
R752 0_6 1C1-1 2014/02/17 Add Q47 for PTP
CN20 <EMI> 2 MX1 power EN and soft up R694\C713.
1 MX0 3 MX2 TPD->100kHz,TS=400Khz R402 *short_4 *AO3413 and C712\C686.
MX0 <31> +3V_S5
2 MX1 MX4 C4788 *220p/50V_4 4 MX3 Intel design guide suggestion +3V_S5 L19 *short_6 1 3
MX1 <31>
3 MX2 MX5 C4789 *220p/50V_4 5 MX4 MCP PIN 10u.
MX2 <31>
4 MX3 MX6 C4790 *220p/50V_4 6 MX5 Per inch 3u TS=3x5inch C781 Q42 C790 + C783
MX3 <31>
5 MX4 MX7 C4791 *220p/50V_4 7 MX6 400kHz10~100u =2.4~0.4k. R416 R415
MX4 <31>
2
6 MX5 MY3 C4792 *220p/50V_4 8 MX7 0.1u/16V_4 0.22u/10V_4 0.1u/16V_4
7 MX6
MX5 <31>
MY2 C4793 *220p/50V_4 9 MY17
100Khz 10~100u=9k~1k. 10K_4 10K_4
MX6 <31>
8 MX7 MY1 C4794 *220p/50V_4 10 MY16 R754 *0_4 C786 *1000p/50V_4 50mil CN17
MX7 <31> <31> PTP_PWR_EN#
9 MY17 MY0 C4795 *220p/50V_4 11 MY15 +TPVDD 8
D MY17 <31> D
10 MY16 MY7 C4796 *220p/50V_4 12 MY14 R411 *short_4 TPCLK_R 7
MY16 <31> <31> TPCLK
11 MY15 MY6 C4797 *220p/50V_4 13 MY13 R412 *short_4 TPDATA_R 6
MY15 <31> <31> TPDATA
12 MY14 MY5 C4798 *220p/50V_4 14 MY12 5
MY14 <31>
13 MY13 MY4 C4799 *220p/50V_4 15 MY11 +TPVDD I2C_TP_SDA_R 4
MY13 <31>
14 MY12 MY11 C4800 *220p/50V_4 16 MY10 R405 *short_4 I2C_TP_SCL_R 3
MY12 <31>
15 MY11 MY10 C4801 *220p/50V_4 17 MY9 TPD_INT# 2 9
MY11 <31> *TDI@2N7002DW
16 MY10 MY9 C4802 *220p/50V_4 18 MY8 *2.2K_4 R409 C787 C788 TPD_EN 1 10
MY10 <31>
17 MY9 MY8 C4803 *220p/50V_4 19 MY7 *0.1u/16V_4 *0.1u/16V_4
18
19
MY8
MY7
MY9
MY8
<31>
<31>
MX0
MX1
C4804
C4805
*220p/50V_4
*220p/50V_4
20
21
MY6
MY5
S5 1 6 S5 *2.2K_4 R410 TP_CONN
MY7 <31>
20 MY6 MX2 C4806 *220p/50V_4 22 MY4 <4> I2C0_SDA 2 I2C_TP_SDA_R I2C PU at CPU side
MY6 <31>
21 MY5 MX3 C4807 *220p/50V_4 23 MY3 <4> I2C0_SCL I2C_TP_SCL_R
MY5 <31> <31> TPD_EN
22 MY4 MY15 C4808 *220p/50V_4 24 MY2
MY4 <31>
23 MY3 MY14 C4809 *220p/50V_4 25 MY1 4 3
MY3 <31>
24 MY2 MY13 C4810 *220p/50V_4 26 MY0 1A-5 2013/10/18 Change CN21 Pin8 for
MY2 <31> <4,31> TPD_INT#
25 MY1 MY12 C4811 *220p/50V_4 27 5 I2C/PS2 TPD idendify.
MY1 <31>
26 MY0 28
MY0 <31> Q43
27 R11107 33_4 NBSWON# 2013/10/29 Change CN21 power rail to S5
28 29 R403 *short_4 change Q42 direction and net name,
R776 33_4 NBSWON# 30 +3V_S5 1A-12 reseve PS2 PU to +3V.
NBSWON# <11,31>
1
29
30 +3VPCU KBL17@KB_CONN
1
D4002
KBL15@KB_CONN C805 *VPORT_6
D34 180P/50V_4 RP1 *10K_10P8R CPU FAN (THM)
2
*VPORT_6 10 1 MX3 Prevent ESD/EOS
Prevent ESD/EOS MX4 9 2 Layout near
2
For 15" Layout near MX6 8 3 MX2 device

MX5 7 4 MX0
device 6 5 MX1
C MX7 C
+3V
+3V
R609
KB_BL LED (KBC) R218
+5V 10K_4
*10K_4
+5V +5V
2
C321
<31> FAN1_RPM
C187 KBL@2.2u/6.3V_4 2.2U/6.3V_4
R148 U12 30mils CN8
1
1
2 3 TH_FAN_POWER
KBL@10K_4 Q18 VIN
VO 5 1
1 GND 6 2
KBL@AO3413 <7> SMB1ALERT#
2
2 /FON GND 7 C723 C728 C719 3
4 GND 8 FAN_3P
<31> FAN1_DAC VSET GND 2.2U/6.3V_4 .01U/50V_4 *.01U/50V_4
1
3
APL5606AKI
20mil 20mil
3
2 +5V_KB R119 *short_4 +5V_KB_R

<31> KB_BL_LED
For 17"+ 15"
FANPWR = 1.6*VSET
Q19 C169 C170 AL005606002
KBL@DTC144EU KBL@KB_backlight
1
KBL@4.7u/6.3V_4 KBL@0.01u/50V_4
4 +3VPCU <6,9,11,23,25,26,27,28,31,32,33,40,41,42>
3 6 +3V_S5 <2,3,4,6,7,8,9,11,21,25,27,28,31,33,35,36,41>
2 5 +5V <22,23,24,26,27,33,40>
B 1 +3V <2,4,6,7,8,9,12,13,14,16,22,23,24,25,26,27,28,31,33,34,35,36,37,40,41,42> B
CN6
R436 *1M_4 +3VPCU Blue 71.5 ohm CS07152FB15 BB 5/18 ReB E

POWER LED(UIF) R426 *1M_4 +3V Amber 130 ohm CS11302FB15 BB 5/18 ReB E
R427 *1M_4 +3VPCU
G-sensor(ACS) Power LED

D26 1 2 *5.5V/25V/410P_4
R318 *short_6 +G_SEN_PW

Blue
LED1
+3V
R432 71.5/F_4 2 3 R438 *short_4 +3VPCU
<31> PWRLED#
U19
C428 C412 1 2 R433 130/F_4 1
Vdd_IO NC <31> SUSLED# +3VPCU
GS@0.1U/16V_4 14 3 R440 *0_4 +3V_S5
GS@10u/6.3V_6 VDD NC LED_AMBER/BLUE
Rev:E change Amber
1 2
D27 *5.5V/25V/410P_4 C555
10 39P/50V_4
GS@RB500V-40 D8 ACCEL_INTA_R 11 RESERVED 15
to CPU <4> ACCEL_INTA INT1 RESERVED
to SATA HDD<27> GS@RB500V-40 D35 ACCEL_INT2_R 9 R428 *1M_4 +3VPCU
ACCEL_INT2 INT2
R337 *short_4 7 R429 *1M_4 for ESD
CLK_SDATA R336 *short_4 G_MBDATA_R 6 SA0 5
<7,12,13,22>
<7,12,13,22>
CLK_SDATA
CLK_SCLK CLK_SCLK R329 *short_4 G_MBCLK_R 4 SDA
SCL
GND
GND
12 Battery D24 1 2 *5.5V/25V/410P_4
13
A
ACCEL_INTA +G_SEN_PW 8 GND 16 Blue
LED2
A
+G_SEN_PW CS GND R430 71.5/F_4 2 3 R437 *short_4 +3VPCU
<31> BATLED0#
G_MBDATA_R C454 *33P/50V_4
GS@LIS3DHTR R431 130/F_4 1
<31> BATLED1#
C425 G_MBCLK_R C431 *33P/50V_4 R439 *0_4 +3V_S5
*22P/50V_4 LED_AMBER/BLUE
+G_SEN_PW R334 *4.7K_4 G_MBDATA_R

Rev:E change Amber
1 2
R333 *4.7K_4 G_MBCLK_R D25 *5.5V/25V/410P_4
PROJECT : ZAA
KB/TP/FAN 1A

5 4 3 2 1
5 4 3 2 1
USB Charger to 3.0 (UBC) USBPWR0
+5VPCU
80 mils (Iout=2A)
U22 CTL1 CTL2 CTL3 ILIM_SEL
1 12 80 mils (Iout=2A)
IN OUT 15 ILIM_LO (RILIM_LO 1.2A)
C483 ILIM_LO
ILIM_HI
16 ILIM_HI SDP 1 1 1 0
+
(RILIM_HI 2.3A)
1U/10V_4 17 C497 C496
GND_PAD R376 C487
9
STATUS GND_PAD
14
18
R377
39K/F_4
100u/6.3V_1206
470P/50V_4 0.1u/16V_4 CDP 1 1 1 1
GND_PAD 20K/F_4
13 19
<6> USB_OC0# 4 FAULT GND_PAD 20
<31> USB_BC_ON ILIM_SEL GND_PAD 21 DCP 0 1 1 X
GND_PAD 22
5 GND_PAD iPAD charging current is about 2.1A so set on 2.3A
D <31> USB_CHARGE_ON EN 1.2A current limit of USB 3.0 SDP mode D
R364 100K_4 11 USBP0-_C
6 DM_IN 10 USBP0+_C
<31> USB_CLT1 CTL1 DP_IN
+5VPCU R360 10K_4 CTL2 7 2
8 CTL2 DM_OUT 3 USBP0- <6>
R356 10K_4 CTL3
CTL3 DP_OUT USBP0+ <6>
TPS2544RTER RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:
1. ILIM_SEL is always set high
2. Load Detection - Port Power Management is not used
GMT:AL003703000(G3703) 3. Mouse / Keyboard wake function is not used
If conditions 1 and 2 are met but the mouse / keyboard wake function is also desired, it is recommended to use
TI:AL002544001(TPS2544) RILIM_LO < 80.6 kΩ.
Silergy: AL055544000 (SLGC55544VTR) The following equation programs the typical current limit:
+5VPCU <27,33,34,40,42> (1) IOS_typ(mA) = 50,250/{RILIM_XX(KΩ)+0.1}
+5V_S5 <21,33,36,37,38,39,41> RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.
+3V <2,4,6,7,8,9,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,35,36,37,40,41,42>
USB 3.0 Connector (UB3)

USBP0-_C R385 *short_4 USBP0-_R
USBP0+_C R386 *short_4 USBP0+_R
+5V_S5 USBPWR0
CN16 USBPWR0
USB3.0 CONN
1 U24
2 1 VBUS
USB3_TXP0_R 1
C424 USBPWR1 2 D- I/O 1
U20 C518 *1.6P/50V_4 3 10 USB3_TXN0_R
1u/6.3V_4 4 3 D+ 2 I/O 6
Close USB3.0 4 GND VDD
5 1 R392 *short_4 USB3_RXN0_R 5 9
IN OUT <6> USB3_RXN0 5 SSRX- GND_2
R387 *short_4 USB3_RXP0_R 6 C502 3
2 <6> USB3_RXP0 7 6 SSRX+ NC_1 8
0.1u/16V_4
GND C517 *1.6P/50V_4 8 7 GND USBP0-_R 4 NC_2
USBON# 4 3 C451 C450 C452 9 8 SSTX- I/O 2 7 USBP0+_R
<31> USBON# /EN /OC 9 SSTX+ 5 I/O 5
470P/50V_4 0.1u/16V_4 100U/6.3V_1206 USB3_RXP0_R
13
12
11
10
GND_1
I/O 3 6 USB3_RXN0_R
C C
G524B2T11U I/O 4
13
12
11
10
<6> USB_OC1#
11
Enable: Low Active /2.5A C499 0.1u/16V_4 USB3_TXN0_C R384 *short_4 USB3_TXN0_R
<6> USB3_TXN0
C498 0.1u/16V_4 USB3_TXP0_C R381 *short_4 USB3_TXP0_R
BCD:AL002822000 <6> USB3_TXP0
USB30_ESD_AZ1065-06F.R7G
GMT:AL000524007
C511 C505 USB protection diodes for ESD.
*1.6P/50V_4 *1.6P/50V_4
as close as possible to USB connector pins.
USB3.0 conn, 2'nd : DFHS09FR679

R342 *short_4 USBP1-_R
<6> USBP1-
R348 *short_4 USBP1+_R
+5V_S5 <6> USBP1+ USBPWR1
USB2.0 DB (UB2)
USBPWR1
CN13 U21
USB3.0 CONN USB3_TXP1_R 1
1 I/O 1 10 USB3_TXN1_R
C4714 USBPWRD2 1 VBUS I/O 6
U4511 2 2
3 2 D- VDD 9
1u/6.3V_4 Close USB3.0 C475 *1.6P/50V_4
5 1 4 3 D+ C462 3 GND_2
IN OUT R355 *short_4 USB3_RXN1_R 5 4 GND 0.1u/16V_4 NC_1 8
2 <6> USB3_RXN1 6 5 SSRX- 4 NC_2
R353 *short_4 USB3_RXP1_R USBP1-_R
GND <6> USB3_RXP1 6 SSRX+ I/O 2
7 7 USBP1+_R
USBON# 4 3 C4713 C4715 C4712 C469 *1.6P/50V_4 8 7 GND USB3_RXP1_R 5 I/O 5
GND_1
/EN /OC 470P/50V_4 0.1u/16V_4 100U/6.3V_1206 9 8 SSTX- I/O 3 6 USB3_RXN1_R
9 SSTX+ I/O 4
13
12
11
10
G524B2T11U
13
12
11
10
11
<6> USB_OC2#
B Enable: Low Active /2.5A B

USB30_ESD_AZ1065-06F.R7G
BCD:AL002822000 C461 0.1u/16V_4 USB3_TXN1_C R341 *short_4 USB3_TXN1_R
<6> USB3_TXN1
GMT:AL000524007 <6> USB3_TXP1
C459 0.1u/16V_4 USB3_TXP1_C R340 *short_4 USB3_TXP1_R USB protection diodes for ESD.
as close as possible to USB connector pins.
C460 C458
*1.6P/50V_4 *1.6P/50V_4
USBPWRD2
CN2020
+
1 C4711
2 100u/6.3V_12
3
4
5
6
7 USBP2+
8 USBP2+ <6>
USBP2-
USBP2- <6>
9
10
11 USBP3+
USBP3+ <6>
12 USBP3- For 17" DB use
13 USBP3- <6>
14
HP_JD# <26>
15
16
17
18 SLEEVE_R <26>
19
20
21 RING2_R <26>
A 22 A
23
HP-L3 <26>
24
27 25
28 26 HP-R3 <26>
DB_CONN
ADOGND

PROJECT : ZAA
WWW.AliSaler.Com
1A
USB3/Charger/USB2 DB
5 4 3 2 1
5 4 3 2 1
11/11 FAE suggestion pin106
+3V_RTC change to +3VPCU_EC
EC(KBC) +3V_LDO_EC
L12 +A3VPCU
BLM15AG121SN1D(120,500MA)_4 +3VPCU_ECPLL L22 +3VPCU_EC
C495 BLM15AG121SN1D(120,500MA)_4
0.1u/16V_4 C772 (For PLL Power) VSTBY_FSPI R11118 +3V_S5 NBSWON# R730 10K_4
VSTBY_FSPI 0_4
ECAGND 0.1u/16V_4 R11119 +3V_LDO_EC S5_ON R741 10K_4
*0_4
R747 2.2/F_6
12 mils +3VPCU_EC SB_ACDC <8>
+3V_LDO_EC POA_EN# <27>
BT_EN
BT_EN <28>
C514 C771 C770 C777 C780 C508 +3V_GFX
+3VPCU_EC and +3V_RTC POA_PWR_INT# <27>
minimum trace width 12mils. 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4
POA_POWERREQ <27> DGPU_OTP#
Prevent ESD/EOS Layout near device R740 EV@10K_4
+3V_EC EC_TypeC_CHG_HI <21>
DGPU_OPP# R382 EV@10K_4
USBON# <30>
R190 33_4
TPD_EN <29>
D +3V R361 *2.2/F_6 +3V_EC D
USB_BC_ON <30>
+3V_S5 R779 2.2/F_6
USB_CHARGE_ON <30>
C482 C796
CLKRUN# <7,27>
180P/50V_4
<7,27,28> LPC_LAD0
0.1u/16V_4 MAINON R389 100K_4
<7,27,28> LPC_LAD1
114
121
106
127
U45
11
26
50
92
74
84
83
82
19
20
99
98
97
96
93
<7,27,28> LPC_LAD2
3
SUSON R739 100K_4
<7,27,28> LPC_LAD3 10 110 MBCLK
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY(PLL)
EGCLK/GPE3
EGCS#/GPE2
EGAD/GPE1
L80HLAT/BAO/GPE0
L80LLAT/GPE7
GPH7
ID6/GPH6
ID5/GPH5
ID4/GPH4
ID3/GPH3
CLKRUN#/ID0/GPH0
VCC
VSTBY_FSPI
AVCC
LAD0/GPM0(3) SMCLK0/GPB3 MBCLK <32>
C822 180P/50V_4 9 111 MBDATA VRON R463 100K_4
LAD1/GPM1(3) SMDAT0/GPB4 MBDATA <32>
8 SM BUS 115 2ND_MBCLK 2ND_MBCLK <7,17>
+3V_LDO_EC 7 LAD2/GPM2(3) SMCLK1/GPC1 116 2ND_MBDATA PCH_SPI_SI_EC R735 *10K_4
LAD3/GPM3(3) SMDAT1/GPC2 2ND_MBDATA <7,17>
R749 *short_4 PLTRST#_EC 22 117 EC_PECR_R R738 43_4 H_PECI <2>
<8,14,25,27,28> PLTRST# 13 LPCRST#/GPD2 PECI/SMCLK2/GPF6(3) 118 R460 33_4 LID# PCH_SPI_SO_EC R736 *10K_4
<7> CLK_PCI_EC LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3) LID# <23>
6
<7,27,28> LPC_LFRAME# LFRAME#/GPM5(3) C801 180P/50V_4 Prevent ESD/EOS Layout near device
PROCHOT_EC 17 CY000220Z00 / CY402220B00
LPCPD#/GPE6
2
D4015 2 1
D12 SIO_A20GATE 126 PS/2 VARISTOR_4
R368 SDMK0340L-7-F
<7,27>
TP77
IRQ_SERIRQ
5
15
GA20/GPB5(3)
SERIRQ/GPM6(3) PS2CLK0/CEC/TMB0/GPF0
85
86
IOAC_RST# <25,28>
SM BUS PU(KBC)
100K_4 LPC
<8> PCH_SUSPWRACK ECSMI#/GPD4(3) PS2DAT0/TMB1/GPF1 EC_FPBACK# <23>
23 89
<2> SIO_EXT_SCI# TPCLK <29>
1
WRST# 14 ECSCI#/GPD3 PS2CLK2/GPF4 90

WRST# GPIO PS2DAT2/GPF5 TPDATA <29> +3V_LDO_EC
4
<7> SIO_RCIN# KBRST#/GPB6(3)
16
C491
1u/6.3V_4
<28> IOAC_WLAN_WAKE# PWUREQ#/BBO/SMCLK2ALT/GPC7(3)
IT8987E/CX PWM0/GPA0
PWM1/GPA1
24
25
PWRLED#
BATLED1#
<29>
<29> Battery module
MBCLK
MBDATA
R731
R732
4.7K_4
4.7K_4
<29>
<8>
KB_BL_LED
DNBSWON#
113
123 CRX0/GPC0
CTX0/TMA0/GPB2(3) CIR
LQFP PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
28
29
30
31
SUSLED#
SUSLED#
BATLED0#
MAINON
<29>
<29>
<8,27>
+3V_S5
PWM5/GPA5 USB_CLT1 <30>
R751 33_4 TS_EN_C
<23> TS_EN 2ND_MBCLK
PWM R733 2.2K_4
EC_TypeC_EN 80 UMA& VGA SKU 2ND_MBDATA R734 2.2K_4
C800 180P/50V_4 119 DAC4/DCD0#/GPJ4(3) 47
<8,11,33> SUSB#
33 DSR0#/GPG6 TACH0A/GPD6(3) 48
FAN1_RPM <29> Need Stuff
Prevent ESD/EOS Layout near device <8> EC_PWROK GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) POA_AUTH_ERR <27>
88
<23> PCH_BLON_R 81 PS2DAT1/RTS0#/GPF3 120
<29> FAN1_DAC DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3) SUSON <8>
87 124
<25> IOAC_LAN_WAKE# PS2CLK1/DTR0#/GPF2 TMRI1/GPC6(3) DGPU_OTP# <17>
C 109 C
<4> ME_WR# TXD/SOUT0/GPB1
108
<26> AMP_MUTE# RXD/SIN0/GPB0
71 107 NBSWON#
<27> ODD_POWER ADC5/DCD1#/GPI5(3) PWRSW/GPE4 NBSWON# <11,29>
72 UART port 18
<32> ACIN ADC6/DSR1#/GPI6(3) RI1#/GPD0(3) SUSC# <8,11>
73 WAKE UP 21 HWPG
<32> TEMP_MBAT# ADC7/CTS1#/GPI7(3) RI2#/GPD1 HWPG <8> H_PROCHOT# <2,32,37>
35
<28> WLANPWR# RTS1#/GPE5
3
34
<26> PCBEEP_EC 122 PWM7/RIG1#/GPA7 112 Q30
<36> DDR4_SUSON_2V5 DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 RSMRST# <8>
Prevent ESD/EOS Layout near device <34> +1V_S5_ON 95
+1V_S5_ON CTX1/SOUT1/GPH2/SMDAT3/ID2
R746 33_4 EC_ODD_EJ#_R 94 Prevent ESD/EOS Layout near device PROCHOT_EC 2
<27> EC_ODD_EJ# CRX1/SIN1/SMCLK3/GPH1/ID1
PCH_SPI_CLK_EC 105 R774 33_4
<7> PCH_SPI_CLK_EC 101 FSCK/GPG7 RF_EN <28>
C799 180P/50V_4 R380 2N7002K
<7> SPI_CS0#_UR_ME FSCE#/GPG3
102 EXTERNAL SERIAL FLASH ICMNT
<7> PCH_SPI_SI_EC ICMNT <32>
1
103 FMOSI/GPG4 66 C798 100K_4
<7> PCH_SPI_SO_EC FMISO/GPG5 ADC0/GPI0(3) 67 C516 10u/6.3V_6 ECAGND 180P/50V_4
CLK_PCI_EC 56 ADC1/GPI1(3) 68
<29> MY16 57 KSO16/SMOSI/GPC3(3) ADC2/GPI2(3) 69 DGPU_OPP# <17>
<29> MY17 KSO17/SMISO/GPC5(3) ADC3/GPI3(3) VRON <8>
TS_EN_C 32 70
PWM6/SSCK/GPA6 ADC4/GPI4(3) LANPWR# <25>
R373 S5_ON 100 A/D D/A
<33,40> S5_ON SSCE0#/GPG2
125 SPI ENABLE
<29> PTP_PWR_EN# SSCE1#/GPG0 76
*22_4
TACH2/GPJ0(3) POA_FP_PWREN# <27>
36 77 SYS_HWPG
<29> MY0 KSO0/PD0 GPJ1(3) SYS_HWPG <33>
37 78
<29> MY1 KSO1/PD1 DAC2/TACH0B/GPJ2(3) PCH_PWROK <8>
38 79
<29> MY2 KSO2/PD2 DAC3/TACH1B/GPJ3(3) CLR_CMOS <6>
C490 39
<29> MY3 40 KSO3/PD3
*10p/50V_4 +3V
PCH_SPI_CLK_EC
<29>
<29>
MY4
MY5
41
42
KSO4/PD4
KSO5/PD5
HWPG(KBC)
<29> MY6 KSO6/PD6 KBMX DDR=1.5V, D1 DNP and D2 POP
43
<29> MY7
44 KSO7/PD7 DDR=1.35V, D1 POP and D2 DNP R374
<29> MY8 45 KSO8/ACK# 10K_4
<29> MY9 KSO9/BUSY
C4726 46
<29> MY10 KSO10/PE
*22p/50V_4 51 2 R11283 *short_4 D18 RB500V-40 HWPG
<29> MY11 KSO11/ERR# GPJ7 SYS_SHDN# <2,33,40> <40> HWPG_1.5V
KSI3/SLIN#
KSI1/AFD#
52 128
KSI0/STB#
KSI2/INIT#
CLOCK R349 33_4

<29> MY12 KSO12/SLCT GPJ6 TPD_INT# <4,29>
EMI 53 D11 *RB500V-40
VCORE
<29> MY13 54 KSO13 <40> HWPG_1.8VS5

AVSS
Prevent ESD/EOS Layout near device

KSI4
KSI5
KSI6
KSI7
<29> MY14 KSO14

VSS
VSS
VSS
VSS
VSS
B 55 C797 D20 *RB500V-40 B

<29> MY15 KSO15 <36> HWPG_VDDR
180P/50V_4
IT8987/CX SM BUS ARRANGEMENT TABLE D17 *RB500V-40
<34> HWPG_1VS5
58
59
60
61
62
63
64
65
27
49
91
104
ECAGND 75
12
SM Bus 1 Battery SYS_HWPG D4014 *RB500V-40

<29> MX0
C778 D14 *RB500V-40
<29> MX1 AJ089870F02 IT8987E/CX <35> HWPG_+VCCOPC
R782
<29> MX2 SM Bus 2 PCH/VGA

Output for TPS 2580 type-C enable 0.1u/16V_4 D4001 *RB500V-40
<29> MX3 <36> HWPG_2.5V
*0_4 R783
*0_4 R784
*0_4 R785
EC_GND
<29> MX4
EC_TypeC_EN R11153 *short_4 SM Bus 3
EC_TypeC_EN_R <21> <29> MX5
L11
<29> MX6
*short_4
<29> MX7
BLM15AG121SN1D(120,500MA)_4 SM Bus 4
Rev:D Add
Battery Detect Switch Reset SW (FSW)

SW4 R756 *0_4 +3V_RTC
+3V_LDO_EC Reserve switch for test R757 *0_4
(MP remove) 3 2
+3VPCU Reserve no stuff
4 1
+3V_RTC R717
*10K_4
R753
10K_4 WRST#
1
<32> BI BI R11282 *0_4

SW2 R719
C764
*POWER_SW 100K_4
*0.1u/16V_4
3
NBSWON# 1 3
2 4 Vgs = 1.5V
2
C785 2 BI_GATE
Option either one
5
A A
*0.1u/16V_4
Vgs = 1.5V
SW1
1
6
PJA138K C765
3
4
BI_SW
1
Q40 *0.1u/25V_4 6
2
Q56
5 *PJ4N3KDW
4

1
2
PROJECT : ZAA
1A
KBC IT8587
5 4 3 2 1
5 4 3 2 1
Double Check ADP-In Type
VA VA1 PQ22 VA2 PR213 PQ1

PD8 AON6414AL 0.01/F_0612 VIN AON6414AL
Power conn SV1040
1 3 3
4 3 5 2 1 2 5 2
3 2 1 1
2
1
P4SMAFJ20A
47n/50V_6
*0.01u/50V_4
PC136
PR209 10_4 24780_ACN
0.1u/50V_6
4
PC133
PD3
PC1
PC13
PJ3 PC141 PC140
D 1n/50V_4 0.1u/50V_6 2200p/50V_6 D
PR210 10_4 24780_ACP
2
PC128 PC124
0.1u/50V_6 2200p/50V_6
PR165 PR166
4.02K/F_4 4.02K/F_4
PR185
*short_6
24780_ACP
24780_ACN PR186 10/F_6
PC115 PC5 PC2

0.1u/50V_6 0.1u/50V_6 0.1u/50V_6
24780_CMSRC
1
PR5 3 18 24780_BATDRV
ACN
ACP
20_1206 CMSRC BATDRV
17 24780_BATSRC VIN
BATSRC
C 24780_ACDRV 4 REGN6V C
PR168 ACDRV
REGN6V 866K/F_4 24780_VCC 28
VCC 24
PC116 REGN PC122
0.47u/25V_6 2.2u/10V_6 PC117 PC118
2200p/50V_6 10u/25V_8
PR1 PR3
100K/F_4 137K/F_4
5
24780_ACDET 6 25 24780_BST *short_6
ACDET BTST PR173 PC119
PR167 *short_4 5 47n/50V_6
<31> ACIN ACOK
MBDATA PR177 *short_4 11 26 24780_DH 4
SDA HIDRV PQ20 PR169
PR4 MBCLK PR178 *short_4 12 AON7410 0.01/F_0612 BAT-V
100K/F_4 SCL PU5 PL1
3
2
1
ICMNT PR170 *short_4 7 BQ24780SRUYR 6.8uH_7X7X3
<31> ICMNT IADP 27 24780_LX 1 2 BAT-V
D/C# PR171 *short_4 8 PHASE
TP4366 IDCHG
UMA-(GT2)> 45 W adapter PR342 CS31542FB14 15.4K 1/16W +-1% (0402) For 78W
5
PMON PR172 *short_4 9
<37> PMON PMON
100P/50V_4
100P/50V_4
*100P/50V_4
PC7
PC6
PC3
UMA-(GT3)> 65 W adapter PR342 CS31272FB17 12.7K 1/16W +-1% (0402) For 95W PR2
PR342 no stuff *4.7_6
Dis -65W adapter> PR342 CS31272FB17 12.7K 1/16W +-1% (0402) For 95W SP@12.7K/F_4 23 24780_DL 4 PR176 PR175
LDODRV PQ21 *short_4 *short_4
Dis -90W adapter> PR342 CS31002FB26 10K 1/16W +-1% (0402) For 116W AON7410
+3VPCU 24780_BM# 16
3
2
1
PR16 10K_4 TB_STAT PC130 24780_SRP PC121 PC120 PC127
PC126 24780_CMPOUT 14 0.1u/25V_4 PC4 2200p/50V_6 10U/25V_8 10U/25V_8
0.1u/50V_6 PR179 *10K_4 CMPOUT 20 PR183 10/F_6 24780_SRP *680p/50V_6 24780_SRN
B 24780_ILIM 21 SRP B
ILIM PC131
PROCHOT
PC125 PR14 24780_CMPIN 13 0.1u/25V_4
BATPRES
*100p/50V_4 316K/F_4 CMPIN
19 PR184 10/F_6 24780_SRN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PAD
SRN
BAT-V PC132
35
36
37
38
10
15
22
29
30
31
32
33
34
0.1u/25V_4
PR15 PR11
BI <31>
100K/F_4 100K_4
50458-00801-V01
PR10 *0_4
9 8
7
*short_4
6 PR8 100/F_4 TEMP_MBAT#
5 TEMP_MBAT# <31> Power charger circuit reserBe 2N7002 for GPU throtting
*0_4
4 PC123
3 0.01u/50V_4
2 +3VPCU GPU_THROTTING# <17>
PR9 1M_4
10 1
PR12
PR13
3
PJ1
TEMP_MBAT#
PR6 PR7 24780_CMPOUT 2

100/F_4 100/F_4 PQ40
*EV@2N7002K
REGN MAX voltage 6.5V
Double Check BATT-In Type
V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
1
MBCLK <31> H_PROCHOT#
=0.793V for 3.965A current limit
H_PROCHOT# <2,31,37>
A A
MBDATA <31> PR174
ILIM=0.793V
*100K_4 Rsr = 0.01ohm
1
PC8 PC9
*47p/50V_4 *47p/50V_4
+VCCIO
2
PD1 PD2
PDZ5.6B PDZ5.6B Check PU high with HW side PROJECT : ZAA
1A
Charger (BQ24780S)
5 4 3 2 1
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5 4 3 2 1
<31> SYS_HWPG
PR6130 *short_6
SYS_SHDN# +3VPCU VL 3V_LDO

<2,31,40> SYS_SHDN#
PR6280
10K/F_4
VIN VIN
10u/6.3V_6
0.1u/25V_4
4.7u/6.3V_6
1
+
PC6212 PC6220 PC6218 PC6214 PC6216
*33u/25V_6x4.5 10u/25V_8 2200p/50V_4 PR6278 PR6283 2200p/50V_4 10u/25V_8
2
*short_4 *short_4 PR6284
10K/F_4
PC6219
PC6100
51225_VIN
PC6098
+5VPCU
5
PQ6054 +3VPCU
PR6297 AON7410 +3VPCU
D
+5VPCU 100K_4 3.3 Volt +/- 5%
D
5 Volt +/- 5% PQ6056
13
12
TDC : 6.58A
3
AON6978 4
TDC : 10A PEAK : 8.77A
VIN
VREG5
VREG3
2
PEAK : 13.4A 7 6 SYS_SHDN# OCP : 11A
D1
D1
D1
3
2
1
PGOOD EN2
OCP : 16A Width : 280mil
51225_EN1 20 10 51225_DH2
Width : 400mil EN1 DRVH2 PR6286 PC6213
PL6013 G1 1 51225_DH1 16 9 51225_VBST2 PL6012
1uH_7X7X3 PC6215 PR6287 DRVH1 VBST2 2.2uH_7X7X3
51225_SW1 9 S1/D2 51225_VBST1 17 8 51225_SW2 1/F_6 0.1u/50V_6
VBST1 PU6010 SW2
0.1u/50V_6 1/F_6 51225_SW1 18 RT6575AGQW 11 51225_DL2
SW1 DRVL2
5
G2 8
PR6281 51225_DL1 15 4 51225_FB2 PR6279
15.8K/F_4 DRVL1 VFB2 6.49K/F_4
51225_FB1 2 21 PR6289
S2
S2
S2
+ PR6288 VFB1 GND 4 *4.7_6 +
PC6227 PC6226 *4.7_6 14 22 PC6225 PC6224
5
6
7
VO1 GND
VCLK
220u/6.3V_6X4.2 0.1u/50V_6 0.1u/50V_6 220u/6.3V_6X4.2
GND
GND
GND
GND
CS1
CS2
PQ6053
3
2
1
AON7752 PC6222
PR6120 *680p/50V_6 PR6121
19
26
25
24
23
10K/F_4 PC6221 10K/F_4
*680p/50V_6
51225_CS1
51225_CS2
PR6125 *short_6
113K/F_4
Rds(on)=14.5m ohm
49.9K/F_4
OCP:11A
OCP:16A L(ripple current)
L(ripple current)
Rds(on)=4.9m ohm
=(9-3.3)*3.3/(2.2u*0.355M*9)
=(9-5)*5/(1u*0.3M*9) ~2.676A
=7.407A Iocp=11-(2.676/2)=9.662A
PR6124
PR6122
Iocp=18-(7.407/2)=12.296A Vth=(9.662A*14.5mOhm)+1mV=141.099mV
Vth=(12.296A*4.9mOhm)+1mV=61.252mV R(Ilim)=(141.099mV*8)/10uA
C
R(Ilim)=(61.252mV*8)/10uA =112.88K C
~49K Power auto recovery
3V_LDO
+3V_LDO_EC
+3VPCU PR6296 0_6
PR6295 *0_6
+5VPCU +5VPCU +3VPCU +3VPCU
TDC : 3.38A TDC : 3.6A TDC : 1.65A TDC : 3.15A

PEAK : 4.5A PEAK : 4.8A PEAK : 2.2A PEAK : 4.2A
Width : 140mil Width : 160mil Width : 80mil Width : 140mil
PC90 PC83 PC137 PC106
1u/25V_4 1u/25V_4 1u/25V_4 1u/25V_4
1
7
+5V_S5 +5V +3V_S5 +3V
VIN1
VIN1
VIN2
VIN2
VIN1
VIN1
VIN2
VIN2
13 8 13 8
14 VOUT1 OUT2 9 14 VOUT1 OUT2 9
VOUT1 OUT2 VOUT1 OUT2
+5V_S5_V1 for PC97 PC85 PC91 PC105 PC173 PC108 PC114 PC174
10U/6.3V_6 0.1U/16V_4 11 0.1U/16V_4 10U/6.3V_6 10U/6.3V_6 0.1U/16V_4 11 0.1U/16V_4 10U/6.3V_6
USB2.0/3.0 Port PU11 GND PU10 GND
APL3523A 15 APL3523A 15
PR6282 *short_4 4 GND PR6292 *short_4 4 GND
+5VPCU VBIAS +5VPCU VBIAS
PC88 PC111
B B
0.1U/16V_4 0.1U/16V_4
S5_ON PR6285 *short_4 3 5 PR6291 *short_4 MAINON_R S5_ON PR6293 *short_4 3 5 PR6294 *short_4 MAINON_R
<31,40> S5_ON
CT1
CT2
CT1
CT2
ON1 ON2 ON1 ON2 MAINON_R <8,36,40>
PC84 PC87 PC107 PC112

12
10
12
10
*0.1U/16V_4 *0.1U/16V_4 *0.1U/16V_4 *0.1U/16V_4
PC175 PC98 PC177 PC176

1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4
Soft-Start Soft-Start
+5VPCU
TDC : 3A
PEAK : 4A ZRW Rev:E Reserve only no stuff
Width : 120mil +5VPCU
PC185 B2A
1u/25V_4
S0->S5 & S0->S3
1
+5V_S5_V2 Power off sequence under 200us PR6290

VIN1
VIN1
VIN2
VIN2
SUSB# -> VCCIO *10K_4

13 8 MAIND
14 VOUT1 OUT2 9 MAIND <34,36,40>
VOUT1 OUT2
+5V_S5_V2 for PC208 PC189
10U/6.3V_6 0.1U/16V_4 11
PD Charger GND
3
PU20
APL3523A 15
PR6300 *short_4 4 GND
+5VPCU VBIAS
PC180 <8,11,31> SUSB# 2 2
A A
PQ6057 PQ6058
0.1U/16V_4 *2N7002K *2N7002K
S5_ON PR6299 *short_4 3 5
1
1
CT1
CT2
ON1 ON2
PC214
12
10
*0.1U/16V_4
PC210
1000P/50V_4
Soft-Start Quanta Computer Inc.

PROJECT : ZAA
1A
SYSTEM 5V/3V (RT6575AGQW)
5 4 3 2 1
5 4 3 2 1
VIN
PU15
8
IN
9
2200p/50V_6
10u/25V_8
*0.1U/25V_4
IN
PC269
PC237
PC238
7 22
+5VPCU PR88 NC IN
10/F_6 24 Fsw=550KHz
+1V_S5
D IN D
G5335-VCC-1 21
VCC 1.0 Volt +/- 5%
G5335QT2U PR97 PC271 TDC : 6.82A
PC243 73.2K/F_4 *0.01U/25V_4
+3V 10U/6.3V_6 6 G5335-TON-1 PEAK : 9.1A
TON
Width : 280mil
PR295 20 G5335-BST-1 +1V_S5
100K/F_4 BST
PR99 PC267
2.2/F_6 0.1U/25V_6 PL15
PR94 *short_4 G5335-PWRGD-1 1 0.68uH_7X7X3
<31> HWPG_1VS5 PGOOD 10 G5335-LX-1 1 2
+5VPCU LX 11
LX 16
PR93 *0_4 LX 17
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
0.1U/16V_4
*22U/6.3V_6
*22U/6.3V_6
LX
PC239
PC234
PC245
PC242
PC248
PC236
PC268
PC250
18
PR87 *short_4 G5335-PFM-1 3 LX 25
G5335-AGND-1 PFM LX R1
PR98
Pulse-Skipping mode *4.7_6
PR86 PC235
5.1K/F_4 *1000P/50V_4
PC270
PR83 *short_4 G5335-EN-1 2 *680p/50V_6
<31> +1V_S5_ON EN 12
PGND
PC272 13
*0.047U/10V_4 PGND
C
14
R2 C
PGND
G5335-AGND-1 15 PR92 Vo=0.8*(R1+R2)/R2
PGND
19
20K/F_4 =1V
G5335-SS-1 23 PGND
SS
4 G5335-AGND-1
AGND G5335-AGND-1
PC89
0.047U/10V_4
5 G5335-FB-1 VFB=0.8V
G5335-AGND-1 FB
PR82 *short_4
G5335-AGND-1
B VIN +1V_SUS VIN +1V_S5 +1V_S5 B
PR141 PR139 PR142
5
1M_6 22_8 1M_6
3
SUSD 2 MAIND 4
<33,36,40> MAIND
PQ26
3
MDV1528Q
PQ23
3
2
1
2 AO3404
<8,36> SUSON_R
1
2 2
+1V_SUS
PR140 PQ7 PQ8
+VCCIO
1
PQ6 1M_6 2N7002K 2N7002K

DTC144EU PC101
TDC : 0.18A
1
*2.2n/50V_4 PC6230
22u/6.3V_6 PEAK : 0.24A PC6231 TDC : 2.36A
Width : 20mil
*22u/6.3V_6 PEAK : 3.14A
ZRW Rev F Add Width : 100mil
ZRW Rev F Add

A A

PROJECT : ZAA
1A
+1V_S5 (G5335QT2U)
5 4 3 2 1
WWW.AliSaler.Com
5 4 3 2 1
+3V_S5
PR292 +VCCOPC Power only for 2+3e CPU

*short_4
D D
+VCCOPC_3V3
PC230 +VCCOPC
*GT3@1u/10V_4 TDC : 4.5A
PEAK : 6A
10
Width : 200mil
*GT3@2200P/50V_4
1
*GT3@0.1U/25V_4
3V3
VIN VIN
*GT3@10u/25V_8
*GT3@10u/25V_8
PC99
PC228
PC100
PC229
PC231 *GT3@0.1u/50V_6
9 +VCCOPC_VBST
BST PR291 *short_6
PL13
*GT3@0.68uH_7X7X3
8 +VCCOPC_SW PR6306 *short_8
SW +VCCOPC
PR136 *short_4 +VCCOPC_EN 5
<8,37> VRON_R EN PR6307 *short_8
+3V_S5 +VCCEOPIO
+VCCOPC_MODE 7 PU14 12 PR344 *GT3@10/F_4
*GT3@0.1u/16V_4
**GT3@100K/F_4
*GT3@22uF/6.3V_6
*GT3@22uF/6.3V_6
*GT3@22uF/6.3V_6
MODE *GT3@NB681GD-Z
VOUT
PR135
PC226
PC222
PC225
PC223
C C
*GT3@100K/F_4
PR289
R697 2 +VCCOPC_SRC <5>
**GT3@10K_4 PGND
PR280 *short_4 PR288 *short_4 +VCCOPC_LP# 6 3 VCCOPC_VID1_C PR286 *short_4 VCCOPC_VID1

<9> LPM_ZVM_N LP# C1
4 VCCOPC_VID0_C PR287 *short_4 VCCOPC_VID0
C0
AGND
PR290 *short_4 13
<31> HWPG_+VCCOPC PG
+3V_S5
*GT3@100K/F_4
11
PR293
PR294
*short_6
R705 R708
*GT3@10K_4 **GT3@10K_4
+3V 681_AGND <5>
B B
VCCOPC_VID0
VCCOPC_VID1
Mode VR Rail LP# C1 C0 Vo

R706 R707
**GT3@10K_4 *GT3@10K_4
0 ohm VCCIO 0 X X 0V
Floating PRIMCORE 1 0 0 0.8V(MSM)
100K EDRAM/EOPIO 1 0 1 0.95V

VCCEDRAM
150K Other 1 1 0 1.0V
1 1 1 1.05V
A A
<5> +VCCOPC
<23,26,27,32,33,34,36,37,38,39,40,41,42> VIN
<2,4,6,7,8,9,12,13,14,16,22,23,24,25,26,27,28,29,31,33,34,36,37,40,41,42> +3V PROJECT : ZAA
<2,3,4,6,7,8,9,11,21,25,27,28,29,31,33,36,41> +3V_S5
1A
+VCCOPC (NB681GD-Z)
5 4 3 2 1
5 4 3 2 1
+3V
PR107
100K/F_4
PR267 *short_4 <23,26,27,32,33,34,35,37,38,39,40,41,42> VIN

<31> HWPG_VDDR
<21,30,33,37,38,39,41> +5V_S5
<12,13> DDR_VTTREF
PR263 *short_4 <12,13> +VDDQ
<8,34> SUSON_R
D <3,5,12,13> +1.2VSUS D
PC203
*0.1U/16V_4 Ilimit=9A
+1.2VSUS
VIN
PR250 1.2 Volt +/- 5%
1P35V_PGOOD
PR257 *short_4 232K/F_4 Fsw=500KHz
<8,33,40> MAINON_R
TDC : 5A
1P35V_CS
1P35V_S3
1P35V_S5
PC196 PR261 PEAK : 6.67A
*0.1U/16V_4 1P35V_TON OCP : 9A
10u/25V_8
10u/25V_8
2200P/50V_4
0.1U/25V_4
0.1U/25V_4
Width : 200mil
PC285
PC213
PC181
PC286
PC283
499K/F_4
10
13
7
9
TDC : 0.45A
5
PQ24 +1.2VSUS
CS
PGOOD
TON
S3
S5
PEAK : 0.6A DDR_VTTREF AON7410
Width : 20mil 20
VTT 17 1P35V_UGATE 4
2 UGATE
PC207 VTTSNS PR251 PC202
10U/6.3V_6 18 1P35V_BOOT
TDC : 0.38A
3
2
1
1 BOOT1 PL11
+VDDQ VTTGND
PEAK : 0.5A PU21 16 1P35V_PHASE
2.2/F_6 0.1u/50V_6 1uH_7X7X3
Width : 20mil PHASE
*330u/2.5V_6X4.2
RT8231BGQW
PR269
0.1U/16V_4
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
4 15 1P35V_LGATE
VTTREF LGATE
PC215
PC194
PC219
PC216
PC205
PC284
100/F_4 +
19 12 1P35V_VDD *short_4 +5V_S5 PR90 PR254
PC212 PC218 VLDOIN VDD PR274 *4.7_6 *short_4
*10U/6.3V_6
PC198
0.1U/16V_4 0.033U/10V_4 4
PC217
C PGND C
VDDQ
1U/6.3V_4 PQ25 PC197
GND
PAD
3
2
1
VID
AON7752 *680p/50V_6
+1.2VSUS FB
3
11
14
1P35V_S3 PR6303 *0_4 1P35V_S5 21

PR281 *short_4
1P35V_VID
1P35V_FB
Rds(on)=14.5mohm
PR6302 *0_4 1P35V_S3
<3> DDR_VTTT_PG_CTRL
+5V_S5 PR264 *short_4 1P35V_VDDQ
PR258
PR265 *0_4
7.87K/F_4
VID Ref. Voltage PR266

10K/F_4
High 0.675V
Low 0.75V
S3 S5 VDDQ VTTREF VTT
OCP=9A
L ripple current S0 1 1 ON ON ON
=(19-1.2)*1.2/(1u*500k*19)
=2.248A S3 (mainon off) 0 1 ON ON OFF
Vtrip=9-(2.248/2)*14.5mohm DDR=1.2V
=114.202mV PR258=7.87K/F_4
S4/S5 0 0 OFF OFF OFF
B
Rlimit=114.202mV/5uA*10=228.4Kohm PR266=10K/F_4 B
+2.5VSUS Power Rail For DDR4 10/26 Reserve +2.5V for DDR4 VDDSPD
+2.5V_SUS
+2.5V_SUS
+2.5V_SUS <12,13>
2.5Volt +/- 5%
+3V_S5 PR285 *short_6 TDC : 0.75A
+3V
PEAK : 1A
3
PC244
4.7U/6.3V_6
Width : 40mil
Check PU high with HW PR314 2
+2.5V_SUS <33,34,40> MAIND
100K/F_4
PQ6065
4
PU16 *AO3404
VIN
PL17
1
<31> HWPG_2.5V PR306 *short_4 5 3 G5719LX2.5V
PG LX 2.2uH/1.85A_2.5X2X1.2
+2.5V
PR273 *short_4
SUSON_R PR304 *0_4 PR271 10K_4 1 2
EN GND +2.5V <12,13,40>
PC233 PC232 PC241
FB
A A
10u/6.3V_6
*10u/6.3V_6
0.1U/16V_4
PC240
TDC : 0.16A
0.47uF/4V_4
PR307 *short_4 G5719CTB1U

<31> DDR4_SUSON_2V5
6
R1 PEAK : 0.21A
PR278 Width : 20mil
47.5K/F_4
PR302
R2 15K/F_4
Vo=(0.6(R1+R2)/R2) Quanta Computer Inc.
PROJECT : ZAA
Size
Date:
Document Number
DDR4_+1.2VSUS (RT8231B)
Friday, February 05, 2016 Sheet
1
36 of 48
Rev
1A
5 4 3 2 1
Check PU high with HW

GT2 : PR19 Unstuff GT3 : PR19 CS41003F932 100K
GT2 : PR6301 CS00002JB38 0 ohm GT3 : PR6301 Unstuff
+1V_VCCST
GT2 : PC17 Unstuff GT3 : PC17 CH3224K1B01 0.022U/25V
SVID near PU1 +5V_S5
GT2 : PC18 Unstuff GT3 : PC18 CH3224K1B01 0.022U/25V
1000P/50V_4
PC6228
PR198 SP@88.7K/F_4
ZRW REV:F add 1000p PR341 PR340 VIN GT2 : PR192 CS12802FB00 280 ohm GT3 : PR192 CS13402FB00 340 ohm
45.3/F_4 100/F_4 GT2 : PC134 CH4104K9B03 0.1uF/25V GT3 : PC134 CH4152K9B02 0.15uF/10V
IMVP8 Vcore Controller
1/F_6
D
PC22 330P/50V_4 PR40 10_4 ISL95857_SDA
GT2 : PR198 CS38872FB18 88.7K GT3 : PR198 CS39312FB15 93.1K D
Close to <5> H_CPU_SVIDDAT
PR212 GT2 : PR202 CS38872FB18 88.7K GT3 : PR202 CS39762FB12 97.6K
VCCGT MOS
<5> VR_SVID_ALERT#_VCORE *short_8
PR227 GT2 : PR194 CS21912FB13 1.94K GT3 : PR194 CS22552FB01 2.55K
PR204
PR225 13.7K/F_4 PR35 49.9/F_4 ISL95857_SCLK
470K_4_4700NTC
<5> H_CPU_SVIDCLK
GT2 : PR203 CS37872FB15 78.7K GT3 : PR203 CS38872FB18 88.7K （1 phase）
Rail A（）：VCORE
PR226 27.4K/F_4
GT2 : PR207 CS41622FB11 162K GT3 : PR207 CS41402FB14 140K
PC21 33P/50V_4
+3V +VCCIO
GT2 : PR201 CS21372FB19 1.37K GT3 : PR201 CS21502FB14 1.5K （2 phase）
Rail B（）：VCCGT
GT2 : PR211 CS12372FB00 237 ohm GT3 : PR211 CS12672FB02 267 ohm
（1 phase）
Rail C（）：VCCSA
PR197
PR200
PC129 PR195
10K/F_4
*10K/F_4
3300P/50V_4 3K/F_4 PC40 PR48
PR32 ISL95857_VR_HOT
<2,31,32> H_PROCHOT#
*short_4
2K/F_4
0.1u/25V_4
0.1u/25V_4
63.4K/F_4
SP@78.7K/F_4
PR24
PR23
PR206
PR203
PC35
PC32
PR30 2200p/50V_4 1K/F_4
1K/F_4
ISL95857_VR_READY
ISL95857_PROG1
ISL95857_PROG2
<2> IMVP_PWRGD
*short_4
ISL95857_VCC
+VCCGT
ISL95857_VIN
Close to
SP@1.91K/F_4
PR194
PR220 VCCSA Choke
PR28 ISL95857_VR_EN ISUMN_C <39>
<8,35> VRON_R
PC11 *short_4
220p/50V_4
470P/50V_4
PC16
PC15
PR187 475/F_4
*10_4
PR196
*10K/F_4
no stuff *0.01U/50V_4 PR242
<32> PMON
40
39
38
37
36
35
34
33
32
31
10K/F_4_3435NTC
1
0.1u/25V_4
0.015u/50V_4
VCC
VIN
VR_HOT#
ALERT#
PROG1
PROG2
VR_ENABLE
VR_READY
SCLK
SDA
2
PC43
PC39
PR25 +3V
<5> VCCGT_SENSE PR191 *short_4 *short_4 PC38 PR219
PC12 Rail C 0.047U/10V_4 11K/F_4
1
<5> VSSGT_SENSE PR181 *short_4 *0.01U/50V_4
2
ISL95857_PSYS 1 30 ISL95857_PWM_C PR47 *short_4 PR218
PSYS PWM_C PWM_C <39>
C 2.61K/F_4 C
ISL95857_IMON_B 2 29 ISL95857_FCCM_C PR46 *short_4
IMON_B FCCM_C FCCM_C <39>
2
ISL95857_NTC_B 3 28 ISL95857_ISUMN_C
NTC_B ISUMN_C
no stuff PR180 ISL95857_COMP_B 4 27 ISUMP_C <39>
*10_4 PC10 COMP_B ISUMP_C
PU1
1u/6.3V_4 ISL95857_FB_B 5 26 ISL95857_RTN_C
FB_B RTN_C
ISL95859HRTZ-T
ISL95857_RTN_B 6 25 ISL95857_FB_C
RTN_B FB_C
7 24 ISL95857_COMP_C
<38> ISUMP_B ISUMP_B COMP_C
8 23
PR45
ISL95857_ISUMN_B ISL95857_IMON_C
301/F_4
ISUMN_B IMON_C
PR216
2.49K/F_4
2.05K/F_4
9 22 ISL95857_PWM_A
330P/50V_4
33P/50V_4
*2K/F_4
ISEN1_B PWM_A
2
2.61K/F_4
10 21 +VCCSA
PR193
PR44
ISL95857_FCCM_A
SP@0.1u/25V_4
ISEN2_B FCCM_A
PC46
2
PR21 PC19
1000P/50V_4
0.022u/25V_4
ISUMN_A
ISUMP_A
PWM1_B
PWM2_B
COMP_A
FCCM_B
1
IMON_A
41
PR22
PC134
PC20
PR207
SP@162K_4
PC42
11K/F_4
NTC_A
RTN_A
1
EP
FB_A
PR51
2200P/50V_4
1K/F_4 2200P/50V_4 Rail A *0.01U/50V_4
*680P/50V_4
*10_4 no stuff
2
PC36
PC37
PR217
1
PC41
PC139
PR241
11
12
13
14
15
16
17
18
19
20
10K/F_4_3435NTC PR43 *short_4
Close to PWM_A <38>
VCCGT Choke PR42 *short_4
ISL95857_ISUMN_A
ISL95857_PWM1_B
ISL95857_PWM2_B
ISL95857_COMP_A
FCCM_A <38>
ISL95857_FCCM_B
PR192
ISL95857_IMON_A
ISL95857_NTC_A
ISL95857_RTN_A
PR50 *short_4
ISL95857_FB_A
<38> ISUMN_B VSA_SENSE <5>
PC44
SP@267/F_4 *0.01U/50V_4 PR52 *short_4 VSASS_SENSE <5>
PC34 PR41
PC14 PC18 *GT3@0.022U/25V_4 2200p/50V_4 1K/F_4

0.1U/25V_4 ISEN1_B <38>
PC45
B Close to PR49 B
PC17 *GT3@0.022U/25V_4 ISEN2_B <38> PR211 Vcore Choke *10_4 no stuff
ISUMN_A <38>
PR6301 SP@0_4 +5V_S5 0.01U/50V_4
SP@237/F_4
PR243
0.1u/25V_4
PC33
<38> FCCM_B PR26 *short_4 10K/F_4_3435NTC
1
PR27 *short_4
0.1u/25V_4
<38> PWM1_B
2
PC31
PR208
<38> PWM2_B PR29 *short_4 PC30 11K/F_4
1
10n/50V_4
1
PR205
2
2.61K/F_4
Rail B
470K_4_4700NTC
2
PR36
2K/F_4
499/F_4
Skylake-U U23e 15W/28W
ISUMP_A <38>
PR34
27.4K/F_4
PR201 SP@1.37K/F_4
4.87K/F_4
PR199
(1+2+1+1 Phase)
330P/50V_4
VCCGTU merge to VCCGT

+VCCCORE
PC25
1000P/50V_4
PR235
PR236
PC26
SP@88.7K/F_4
PR202
33P/50V_4
2200p/50V_4
560P/50V_4
VCORE VCCGT VCCSA VCCGTU *0.01u/50V_4 PR31
*10_4 no stuff
PC23
Close to
Icc TDC PL2：23A Icc TDC PL2：40A Icc TDC PL2：5A VCORE MOS
PR33 *short_4
13.7K/F_4
Icc Max：29A Icc Max：64A Icc Max：5A VCORE_SENSE <5>

PR224
PC24
PC135
PC28
PC27 PR38 *short_4

*0.01u/50V_4 VCORESS_SENSE <5>
A
OCP：35A OCP：A OCP：6A A
Fsw：800KHz Fsw：800KHz Fsw：800KHz PC29

PR39
*10_4 no stuff
：
VCORE L/L：：
VCCGT L/L：：
VCCSA L/L： 0.01u/50V_4
R_DC_LL：2.1mV/A R_DC_LL：2mV/A R_DC_LL：10.3mV/A Quanta Computer Inc.

PROJECT : ZAA
R_AC_LL：2.1mV/A R_AC_LL：2mV/A R_AC_LL：10.3mV/A Size Document Number Rev
1A
CPU_CORE (ISL95859HRTZ-T)
5 4 3 2 1
5 4 3 2 1
GT2 : PR19 Unstuff GT3 : PR19 CS41003F932 100K
VCORE
VIN VCORE
*33U/25V_6x4.5
1
10u/25V_8
10u/25V_8
2200P/50V_6
PR55 *short_6
0.1U/50V_6
+5V_S5
Icc TDC PL2：23A
PC155
PC52
PC154
PC51
PC6229
D
+ D
4.7U/10V_6
PC149
PU8 AOZ5049QI
Icc Max：29A
2
6
VCORE_VCC 23 VIN 22
24 PVCC VIN
VCC OCP：35A
Rail A GH
4
3 VCORE_VBST PR231 +VCCCORE Fsw：800KHz
PR237 *short_4 1 BOOT *short_6
<37> PWM_A PWM
PR238 *short_4 2 PC144
<37> FCCM_A FCCM 0.1u/50V_6 PL4 ：
VCORE L/L：
5 0.15uH_7X7X4
VSWH 13 VCORE_PHASE 1 2 DCR=0.66mOhm
VSWH R_DC_LL：2.1mV/A
PGND
PGND
19
4
GL 20
GL PR60 + +
R_AC_LL：2.1mV/A
330u/2V_7343
330u/2V_7343
2.2/F_6
21
0.1u/16V_4
22u/6.3V_8
22u/6.3V_8
PC161
PC164
PC168
PC162
PC59
PC58
1000P/50V_4
<37> ISUMP_A PR215 3.65K/F_6
<37> ISUMN_A
PR214 10/F_6
VCCGT
C C
+VIN_VCCGT
+5V_S5 PR61 *short_6 PR6304 VIN

*short_37
4.7U/10V_6
33U/25V_6x4.5
1
10u/25V_8
10u/25V_8
PC146
2200P/50V_6
0.1U/50V_6
PC47
PC148
PC150
PC48
PC138
PU13 AOZ5049QI +
6
VCCGT_VCC1 23 VIN 22 VCCGT
2
24 PVCC VIN
VCC
Rail B
GH
4
+VCCGT
Icc TDC PL2：40A
3 VCCGT_VBST1 PR223
PR228 *short_4 1 BOOT *short_6
<37> PWM1_B PWM Icc Max：64A
PR229 *short_4 2 PC142
<37> FCCM_B FCCM 0.1u/50V_6 PL2
5 0.15uH_7X7X4 OCP：A
VSWH
VSWH
13 VCCGT_PHASE1 1 2 DCR=0.66mOhm
Fsw：800KHz
PGND
PGND
330u/2V_7343
19
0.1u/16V_4
22u/6.3V_8
22u/6.3V_8
3
4
GL
PC159
PC170
PC172
PC163
20 +
GL
PR57
：
VCCGT L/L：
21
2.2/F_6
PC55 R_DC_LL：2mV/A
1000P/50V_4
R_AC_LL：2mV/A
<37> ISUMP_B PR20 3.65K/F_6
GT2 : PR19 Unstuff
GT3 : PR19 CS41003F932 100K
ISEN1_B PR19 *GT3@100K/F_6
GT2 : PR19 Unstuff

GT3 : PR19 CS41003F932 100K
PR18 *GT3@100K/F_4
B
VCCGT = 1 phase for U22 , 不不不 <37> ISUMN_B
PR17 10/F_6 ISEN2_B <37>
B
VCCGT = 2 phase for U23e , 不不 2015/10/2 FAE Suggestion
+VIN_VCCGT
+5V_S5 PR62
*short_6
*GT3@4.7U/10V_6
PC147
*GT3@10u/25V_8
*GT3@10u/25V_8
*GT3@2200P/50V_6
PU7 *GT3@AOZ5049QI
*GT3@0.1U/50V_6
PC49
PC152
PC153
PC50
6
VCCGT_VCC2 23 VIN 22
24 PVCC VIN
VCC
Rail B GH
4
3 VCCGT_VBST2 PR230 +VCCGT
PR233 *GT3@0_4 1 BOOT *short_6
<37> PWM2_B PWM
FCCM_B PR234 *GT3@0_4 2 PC143
FCCM *GT3@0.1u/50V_6 PL3
5 *GT3@0.15uH_7X7X4
VSWH
VSWH
13 VCCGT_PHASE2 1 2 DCR=0.66mOhm
PGND
PGND
*GT3@330u/2V_7343
19
*GT3@0.1u/16V_4
*GT3@22u/6.3V_8
*GT3@22u/6.3V_8
3
GL
PC160
PC166
PC167
PC158
20 PR58 +
GL *GT3@2.2/F_6
21
PC56
*GT3@1000P/50V_4
ISUMP_B PR190 *GT3@3.65K/F_6
ISEN2_B PR189 *GT3@100K/F_6

A A
GT2 : PR19 Unstuff
GT3 : PR19 CS41003F932 100K
ISUMN_B PR188 *GT3@100K/F_4
PR182 *GT3@10/F_6 ISEN1_B <37>
2015/10/2 FAE Suggestion
<5,37> +VCCCORE
<23,26,27,32,33,34,35,36,37,39,40,41,42> VIN
<5,37> +VCCGT
PROJECT : ZAA
WWW.AliSaler.Com
<21,30,33,36,37,39,41> +5V_S5
1A
VCORE/VCCGT (ISL95808HRZ-T)
5 4 3 2 1
5 4 3 2 1
D D
VCCSA
+5V_S5 PR56 *short_6

VIN
4.7U/10V_6
VCCSA
PC151
2200P/50V_6
10u/25V_8
10u/25V_8
0.1U/50V_6
PC54
PC157
PC156
PC53
PU9 AOZ5029QI-5
VIN
6 Icc TDC PL2：5A
VCCSA_VCC 23 22
C
24 PVCC VIN C
VCC Icc Max：5A
Rail C 4
GH
BOOT
3 VCCSA_VBST PR232
+VCCSA
OCP：6A
PR239 *short_4 1 *short_6
<37> PWM_C PWM
<37> FCCM_C PR240 *short_4 2
FCCM
PC145 Fsw：800KHz
0.1u/50V_6 PL5
5 0.47uH_7X7x3
VSWH 13 VCCSA_SW 1 2 DCR=4.2mOhm
VSWH ：
VCCSA L/L：
PGND
PGND
19
0.1u/16V_4
22u/6.3V_8
22u/6.3V_8
3
4
GL
PC171
PC169
PC165
20
GL R_DC_LL：10.3mV/A
PR59
21
2.2/F_6
R_AC_LL：10.3mV/A
PC57
1000P/50V_4
B B
<37> ISUMP_C PR222 3.65K/F_6
<37> ISUMN_C
PR221 10/F_6
<5,37> +VCCSA
<23,26,27,32,33,34,35,36,37,38,40,41,42> VIN
<21,30,33,36,37,38,41> +5V_S5
A A

PROJECT : ZAA
1A
VCCSA (ISL95808HRZ-T)
5 4 3 2 1
5 4 3 2 1
+5VPCU +5VPCU
Check PU high with HW Check PU high with HW

PR81 PR68
*short_4 *short_4
PR73 100K_4 +3V PR53 100K_4 +3V
D PC79 1u/6.3V_4 PU6 PC81 1u/6.3V_4 PU2 D
YB1282PSP8 YB1282PSP8
PC77 *1u/16V_6 4 1 PC70 *1u/16V_6 4 1
VPP PGOOD HWPG_1.8VS5 <31> VPP PGOOD HWPG_1.5V <31>
S5_ON PR69 *short_4 2 6 PR1249 *short_8 +1.8V_S5 MAINON_R PR37 *short_4 2 6 PR1247 *short_8 +1.5V
<31,33> S5_ON VEN VO <8,33,36> MAINON_R VEN VO
PR1250 *short_8 3 PR1248 *short_8 3
+3VPCU VIN +3VPCU VIN
8 PR156 8 PR121
GND R1 GND R1
ADJ
ADJ
9 5 43.2K/F_4 9 5 30K/F_4
GND NC GND NC
PR75 PC80 +1.8V_S5 PR54 PC71 +1.5V
7
100K_4 10u/6.3V_6 1.8Volt +/- 5% 100K_4 10u/6.3V_6 1.5Volt +/- 5%
VFB=0.8V TDC : 0.08A VFB=0.8V TDC : 0.49A
PR133 PR119
PC76 PC78 PC75 34K/F_4 PEAK : 0.06A PC65 PC74 PC61 34K/F_4 PEAK : 0.66A
10u/6.3V_6 0.1u/50V_6 *0.1u/50V_6 R2 Width : 20mil 10u/6.3V_6 0.1u/50V_6 *0.1u/50V_6 R2 Width : 20mil
Vo =0.8(1+R1/R2) Vo =0.8(1+R1/R2)
=1.8V =1.5V
PR153 Change to
C 220 ohm for bo bo C
sound issue.
VIN VIN
VIN +3V +5V +VCCIO +2.5V
Thermal protection
PR148
PD4 PR151 PR137 PR153 PR138 PR6298 1M_6
DA2J10100L 1M_6 *22_8 *220_8 22_8 *22_8
Need fine tune
MAIND
for thermal protect point MAINON_ON_G MAIND <33,34,36>
3
Note placement position
3
3
TEMP=85C
PR152 PR150 2
1M_6 1 MAINON_R 2 PQ11 1M_6 2 2 2 2 PC103
DTC144EU PQ3 2200p/50V_4
PQ12 PQ4 PQ10 PQ5 PQ6066 2N7002K
AO3409 *2N7002K *2N7002K 2N7002K *2N7002K
1
2 PR147
1
*100K/F_6 ZRW Rev:D Stuff
3
S5_ON 2
PQ13 PR154
1
DTC144EU *short_6
B VL VL B
SYS_SHDN# <2,31,33>
PR144 PC104 PR155

PR146 200K/F_4 0.1u/50V_6 200K_6
3
1.47K/F_4
8
PR262
10K/F_4_3435NTC 2.469V 3
+ 1 2
LM393_PIN2 2
- PQ14
3
PU4A 2N7002K
4
AS393MTR-E1 PC102
1
0.1u/50V_6
S5_ON 2
PR145
PQ9 200K/F_4
2N7002K
1
5
+ 7
6
-
PU4B
A AS393MTR-E1 A
For EC control thermal protection (output 3.3V)

PROJECT : ZAA
1A
+1.8V/+1.5V/Thermal Protect
5 4 3 2 1
WWW.AliSaler.Com
5 4 3 2 1
+5V_S5
PR143
D
Double Check OCP SETTING *short_6 VIN D
*EV@33U/25V_6x4.5
EV@10u/25V_8
EV@10u/25V_8
EV@0.1u/50V_6
EV@2200p/50V_4
1
PR96
EV@2.2/F_6 +
PC86
PC184
PC251
PC254
PC224
18 1658R-PVCC
PR270 EV@13K/F_4 PR268 EV@24.9K/F_4 1658R-BOOT1
1
1658R-EN 1658R-VREF PQ33 PQ41
2
PC195 EV@AON6414AL EV@AON6414AL
EV@1u/10V_4 PC253
5
PC227 *EV@0.01U/50V_4 EV@0.22u/25V_6
PR276 1 2
EV@100K/F_4 PU19
PR275 1 1658R-BOOT1 1658R-UGATE1 4 4
PVCC
VIN PR260 *EV@1/F_4 1658R-OCS/CB 9 BOOT1
OCS/CB 2 1658R-UGATE1
1
2
3
1
2
3
PR345 *short_4 *EV@499K/F_4 UGATE1 PL9
<16,42> 3V_MAIN_PWGD
20 1658R-PHASE1 EV@0.36uH_10X10X4 DCR=1.2m ohm
PR253 *EV@0_4 1658R-EN 3 PHASE1 1658R-PHASE1
<4> VGPU_EN EN +VGPU_CORE
19 1658R-LGATE1
LGATE1
5
DGPU_PSI PR255 *short_4 1658R-PSI 4 PR89
<17> DGPU_PSI PSI
EV@UP1658RQKF EV@2.2/F_6
+ +
EV@330u/2V_7343
EV@330u/2.5V_6X4.2
PWM-VID PR256 *short_4 1658R-VID 5 15 1658R-BOOT2 1658R-LGATE1 4 4
EV@0.1u/16V_4
EV@10u/6.3V_8
<17> PWM-VID VID BOOT2
PC191
PC190
PC201
PC328
14 1658R-UGATE2
1
2
3
1
2
3
1 2 1658R-VREF 8 UGATE2 PC188
PC206 EV@1u/10V_4 VREF 16 1658R-PHASE2 EV@1000p/50V_6
PHASE2 PQ27 PQ42
1658R-REFADJ 6 17 1658R-LGATE2 EV@AON6752 EV@AON6752
Check PU High with HW side REFADJ LGATE2 1 2 +3V
PR259 EV@10K_4
7
C +3V_S5 +3VPCU R1 PR113 REFIN 13 1658R-PG PR252 *short_4 C
PR106 EV@20K/F_4
R2 PGOOD GPU_PWR_GD <14>
RDSon=2.5mohm
1658R-REFIN
*EV@0.01U/50V_4
EV@20K/F_4 12 1658R-COMP
PC178
COMP
GND
EV@4700P/25V_4
PR104 PR101 10
FB
FBRTN
1
*EV@10K_4 *EV@10K_4
PC199
1
11
21
DGPU_PSI PR115
C R3
EV@22P/50V_4
2
PC200 EV@2K/F_4 TP4362
1658R-FBRTN
2
1
EV@2700P/50V_4
PC221
EV@16K/F_6
1658R-FB
PR95
PR102 EV@2.2/F_6
PR118
VIN
2
*EV@0_4 1658R-BOOT2
PQ30
EV@10u/25V_8
EV@10u/25V_8
EV@0.1u/50V_6
EV@2200p/50V_4
TP4363 EV@AON6414AL PQ43
PC182 EV@AON6414AL
PC209
PC179
PC220
PC211
5
5
PR114 EV@0.22u/25V_6
EV@18K/F_4
R4
Phase Number of Operation
*EV@22P/50V_4
1
PR277 PR279 1658R-UGATE2 4 4

PR105
PC110
*short_4 *short_4
*EV@5.1K/F_4
2
1
2
3
1
2
3
PL10
PR112 EV@0.36uH_10X10X4 DCR=1.2m ohm
PWM-SVID : Config B EV@0_4
R5 1658R-PHASE2 +VGPU_CORE
Check PWM-SVID by SKU
3
5
PR91
EV@2.2/F_6 + +
EV@330u/2.5V_6X4.2
2
EV@330u/2V_7343
PQ18 1658R-LGATE2 4 4
EV@0.1u/16V_4
EV@10u/6.3V_8
*EV@2N7002K
PC193
PC192
PC186
PC204
1
B B
Standby
1
2
3
1
2
3
PC187 PQ34 PQ44 PC183
1
Function *EV@1u/10V_4 EV@AON6752 EV@AON6752 EV@1000p/50V_6

2
+VGPU_CORE
PR84
*EV@100_4 RDSon=2.5mohm
Component Value Config B
N16P-GX(40W/GDDR5)
PR163 *short_4
<14> VGA_VCCSENSE
PR162 *short_4 R1 20K OpenVR Config:B
<14> VGA_VSSSENSE
PR85 R2 20K +VGPU_CORE

*EV@100_4 Countinue current:51.1A
R3 2K Peak current:87A
Parallel
OCP:112A
R4 18K FSW:300KHz
L/L=0mV/A
A A
R5 0-ohm
C 2.7nF
PROJECT : ZAA
1A
+VGPU_CORE(UP1658RQKF)
5 4 3 2 1
5 4 3 2 1
<14,15,16> +1.05V_GFX
<14,16,17,31> +3V_GFX
<15,19,20> +1.35V_GFX
Check PU High with HW side

+1.05V_GFX
+3V
TDC : 2.18A
PEAK : 2.9A
Width : 100mil
PR318
*EV@100K/F_4 PC304 PR319
+1.05V_GFX
TP76 *EV@2200P/50V_4 *EV@2.2/F_6
D D
HWPG_1.05VGFX PR317 554PG_0.95V PU18
*short_4 PL14
4 1 554LX_0.95V
PG NC EV@1uH_7X7X3 554FB_0.95V_S
EV@0.1U/16V_4
EV@22U/6.3V_6
*short_4
9 2 PR311
+3VPCU PVIN LX
PC303
PC302
PC301
10 3 *EV@22P/50V_4
PVIN LX PR310
7 554NC_0.95V PC247
R1
PR312 EV@7.5K/F_4
EV@10/F_6 NC *EV@68P/50V_4
554SVIN_0.95V 8 6 554FB_0.95V
SVIN FB
EV@0.01U/50V_4
EV@10U/6.3V_6
11 5 554EN_0.95V
EV@1U/6.3V_4
PR321
GND EN
PC246
PC249
*short_4 R2 PR309
Vo=0.6*(R1+R2)/R2
PC252
EV@10K/F_4
EV@RT8068AZQW
PC300
*EV@0.1u/16V_4 3V_MAIN_PWGD
3V_MAIN_PWGD <16,41>
VIN +3V_GFX VIN +3VPCU
PR159 PR164 PR161
3
EV@1M_6 EV@22_8 EV@1M_6
DGPU_D 2
3
C C
3
PQ19
PR157 EV@AO3404
+3V_GFX
1
PR160 *short_4 2 EV@1M_6 2 2 +3V_GFX
<4> DGPU_PWR_EN PC113 TDC : 0.26A
1
PQ17 PQ16 *EV@2.2n/50V_4
PQ15 EV@2N7002K EV@2N7002K PEAK : 0.34A
1
PC109 PR158 EV@PDTC143TT
Width : 20mil
1
*EV@1u/10V_4 EV@100K_4
2
+1.35V_GFX for GDDR5
VIN
PU22
8
IN
9
EV@2200p/50V_6
EV@10u/25V_8
*EV@0.1U/25V_4
IN
PC291
PC276
PC277
7 22
+5VPCU PR111 NC IN
EV@10/F_6 24 Fsw=550KHz
+1.35V_GFX
IN
G5335-VCC 21
VCC 1.35 Volt +/- 5%
EV@G5335QT2U PR116 PC292 TDC : 8.55A
PC280 EV@73.2K/F_4 *EV@0.01U/25V_4
+3V EV@10U/6.3V_6 6 G5335-TON PEAK : 11.4A
TON
B Width : 360mil B
PR296 20 G5335-BST +1.35V_GFX

EV@100K/F_4 BST
PR123 PC289
EV@2.2/F_6 EV@0.1U/25V_6 PL18
<16> HWPG_1.35VGFX PR110 *short_4 G5335-PWRGD 1 EV@0.68uH_7X7X3
PGOOD 10 G5335-LX 1 2
+5VPCU LX 11
LX 16
PR103 *EV@0_4 LX 17
EV@22U/6.3V_6
EV@22U/6.3V_6
EV@22U/6.3V_6
EV@22U/6.3V_6
EV@22U/6.3V_6
EV@0.1U/16V_4
*EV@22U/6.3V_6
*EV@22U/6.3V_6
LX
PC278
PC273
PC281
PC279
PC282
PC275
PC288
PC287
18
PR109 *short_4 G5335-PFM 3 LX 25
G5335-AGND PFM LX R1
PR120
Pulse-Skipping mode *EV@4.7_6
PR108 PC274
EV@14K/F_4 *EV@1000P/50V_4
PC290
PR122 *short_4 G5335-EN 2 *EV@680p/50V_6
<14> FBVDDQ_EN EN 12
PGND
PC293 13
*EV@0.047U/10V_4 PGND
14
R2
PGND
G5335-AGND 15 PR100 Vo=0.8*(R1+R2)/R2
PGND
19
EV@20K/F_4 =1.35V
G5335-SS 23 PGND
SS
4 G5335-AGND
AGND G5335-AGND
PC92
EV@0.047U/10V_4
5 G5335-FB VFB=0.8V
G5335-AGND FB
A A
PR117 *short_4
G5335-AGND

PROJECT : ZAA
Date:
+1.35V_GFX/+1.05V_GFX/+3V_GFX
Friday, February 05, 2016
1
Sheet 42 of 48
1A
1 2 3 4 5 6 7 8
VGA power up sequence
+3VPCU
SKYLAKE
PCH +3V_MAIN
MOSFET +3V_GFX
DGPU_PWR_EN
GPP_B17 MOSFET
A A
3V_MAIN_EN (GPU GPIO5)
3V_MAIN_PWGD
PG
+1.05V_S5
MOSFET +1.05V_GFX
3V_MAIN_PWGD
PWM-VID (GPU GPIO11)
VIN
B
+VGPU_CORE B
3V_MAIN_PWGD VIN +1.35V_GFX

PWM
PWM
VGPU_PWRGD
OR FBVDDQ_EN HWPG_1.35VGFX
Gate DGPU_PWROK
VGPU_PWRGD
EC_FB_CLAMP(EC)
GC6_FB_EN (GPU GPIO0 )
C C
GPP_B19
VGA Reset
PLTRST# All 3.3V

PEGX_RST#
PCH DGPU_HOLD_RST# t>0
NVVDD
PXE_VDD
+1.05V
PEX_RST timing t>0
FBVDDQ
D D
N15x Power on sequance

I/O 3.3V
Notes: -All 3.3V includes all rails powered at 3.3V
-PEX_VDD 1.05V inculdes all rails that are shared
PEX_RST
Trise >= 1uS Tfail <=500nS Quanta Computer Inc.

PROJECT : ZAA
1A
GPU PWR CRL
1 2 3 4 5 6 7 8
5 4 3 2 1
Battery Mode 3
VIN 1
3
1
+3VPCU +5VPCU
VIN BAT-V
Non Deep Sx 3V/5V VL
5V_LDO 2
11 2 VR
3 +5VPCU +5V_S5
+15V
CHARGER Battery
EN2
EN1
D
+3VPCU S5 PWR +3V_S5 10 4 D
3
3
S5_ON 8 NBSWON# +3VPCU or +3V_S5
1 VIN Delay DSW power well 10ms DSW PWR

+1V_S5
PWR 6 DPWROK DPWROK
VCCPRIM PWR
DDR VDDQ +1.35VSUS 18 BTN 13 RSMRST# +1V_S5
RSMRST#
VR 7 14 ACPRESENT VCCMPHY PWR
+VDDQ 19 EC ACPRESENT +1.8V_S5
30 DNBSWON#
15 PWRBTN#
HWPG SUSC# 16 SPI PWR
+VDDQ_VTT 23 SLP_S4# V1_MPHY
SUSB# 20 SLP_S3#
HSIO PWR
PCH_SUSACK# SUSACK V1_MPHY
HWPG_VDDR 24
PG PCH_SUSPWARN# SUSWRAN
PLL PWR
S5
S3
PCH_SLP_SUS# SLP_SUS# +1V_S5
31a
VCCST_PWRGD PCH
DDR_VTTT_PG_CTRL VCCST_PWRGD CORE PWR
C
21 31b PCH_PWROK
+1V_S5 C
MAINON
22 31C EC_PWROK PCH_PWROK VCCSRAM PWR
PCH_CLK +1.5V
35
SUSON PLTRST# HDA PWR
VRON
SUSON
S5_ON
MAINON
EC_PWROK
+1V_S5_ON
PLTRST#
17 38 VCCPGPPA PWR +3V_S5
+3VPCU 24 HWPG_VDDR IMVP_PWRGD VCCPGPPB PWR
3 36 SYS_PWROK VCCPGPPC PWR
SYS_PWROK VCCPGPPD PWR
26 HWPG_1V_S5 EC_PWROK VCCPGPPE PWR
+1.5V 12 31C
VCCPGPPG PWR
VCCPGPPF PWR
1.5V +1.8V_S5
HWPG_1.5V 31C 32b 21 17 9 8
VR
PLTRST#
29 29 38
HWPG_1.5V
PG
EN
+VCCIN
MAINON CORE PWR

21 +1.35VSUS
RESET#
CPU
VDDQ PWR
+1V_VCCST
RUN PWR +1VSUS
+1V_VCCST PROCPWRGD
B
3 +5VPCU +5V 28 VCCST PWR B
MOS1
SM_PG_CNTL1
VCCST_PWRGD
0 ohm
3 +3VPCU +3V 27
VR_READY
MOS2
VR_EN
EC_PWROK 10K ohm
SVID
9 +1V_S5 +VCCIO 31C
MOS3 29
G
HWPG_1VS5
1 VIN 12
MAINON 33
VRON
DDR_PG_CTRL
21 +VCC_CORE
IMVP_PWRGD
VCCST_PWRGD_EN
SVID
PCH_PWROK VCCST_PWRGD_EN
IMVP +VCCSA 33 31b
VIN
1 9 VR +VCCGT
33 SYS_PWROK
+1V_S5 36
+1V_S5
VR 34 HWPG+1ms
12 IMVP_PWRGD 37 22 34 32a
HWPG_1VS5 PG
EN
PG
EN
A A
8 SVID VRON 32a

+1V_S5
37
CPU Quanta Computer Inc.

PROJECT : ZAA
WWW.AliSaler.Com
1A
Power Sequence
5 4 3 2 1
5 4 3 2 1
Skylake U Non-Deep Sx Platform

Power on sequence
D D
C C
B B
A A

PROJECT : ZAA
2A
Power on Sequence
5 4 3 2 1
5 4 3 2 1
實實實defult
虛實實reserve VGPU_PWRGD
+5V_S5
SYS_HWPG S5_ON PWRGD
VIN Vin
VGPU Core Vout
+VGPU_CORE
APL3523A up1658
SYS_SHDN# PWRGD
+5VPCU +5V EN
D D
EN1 5V S5_Vout
3V_MAIN_PWGD
TPS51225
MAINON_R
EN1
3V
HWPG_1.35VGFX
Vin S3_Vout +3VPCU
+3V_S5
VIN PWRGD
S5_ON
VIN Vin
+1.5V_GFX Vout
RT8237
+1.35V_GFX
APL3523A
EN
+3V FBVDDQ_EN
MAINON_R
IMVP_PWRGD
RT8068AZQW +1.05V_GFX
C
PWRGD
VIN Vin C
3V_MAIN_PWGD
VIN Vin
+VCC_CORE Vout
ISL95859HRTZ-T AOZ5029QI
+VCCCORE
AO3404 +3V_GFX EN
VRON
dGPU_PWR_EN
SVID PWM_A
PCH FCCM_A
IMVP_PWRGD
HWPG_1VS5 PWRGD
VIN Vin
MDV1528Q
VIN Vin
+VCCSA AOZ5029QI Vout
+VCCIO ISL95859HRTZ-T
+VCCSA
PWRGD
EN
VIN +1.0V_S5 MAIND
Vin Vout +1V_S5 VRON
RT8237CZQW
B B
EN SVID PWM_C
FCCM_C
+1V_S5_ON AO3404 +1V_SUS
EC IMVP_PWRGD
SUSON
PWRGD
VIN Vin
EC
VIN Vin
+VCCGT ISL95808 Vout
ISL95859HRTZ-T
+VCCGT
EN
HWPG_VDDR VRON
G5719 +2.5V_SUS SVID PWM1_B
FCCM_B
SUSON PWRGD
+1.2VSUS SUSON
EC S5 EN
S5_Vout HWPG_1.5V
+1.2VSUS +VDDQ_VTT
G5316RZ1D
MAINON HWPG_1.8VS5 PWRGD
A
EC A
S3 EN +3V_PCU +1.5V
Vin S3_Vout +VDDQ Vin Vout +1.5V
DDR_VTTT_PG_CTRL G9661
PWRGD
EN
PCH +3V_S5 +1.8V_S5
Vin Vout +1.8V_S5 MAINON_R
G9661
EN
VIN S5_ON
PROJECT : ZAA
1A
SKL PCH PWR CONTROL
5 4 3 2 1
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1 2 3 4 5 6 7 8
+3V_S5 +3V
SDRAM
2.2K 2.2K 2.2K 2.2K
+3V
R7 SMB_PCH_CLK CLK_SCLK
A 2N7002DW A
R8 SMB_PCH_DAT Level shift CLK_SDATA G-Sensor
XDP
Skylake U
+3V_S5
2.2K 2.2K
B B
R9 VGA_MBCLK
W2 VGA_MBDATA
+3V_S5
*2.2K *2.2K
+3V_S5
W3 SMB_ME1_CLK
*2N7002DW
V3 SMB_ME1_DAT Level shift
+3V_S5 +3V_GFX
C 0 0 C
2.2K 2.2K 2.2K 2.2K
+3V_MAIN
115 2ND_MBCLK
2N7002DW GFX_SCL
Level shift VGA
116 2ND_MBDATA GFX_SDA
EC
+3VPCU
IT8987CX
D D
4.7K 4.7K
110 MBCLK
111 MBDATA CHARGER

PROJECT : ZAA
1A
SMBUS Block Diagram
1 2 3 4 5 6 7 8
5 4 3 2 1
Model Date CHANGE LIST
B-CHANGE
B0. Change FP from 0201 to 0402; C689,C688,C683,C194,C241,C227,C216,C242,C205,C252 for RDC request.
B1. Change CN95, CN6, CN20,CN2019, CN7,JDIM1, JDIM2,CN10 of foot-print
B2. Page 33 Mount PR6296, remove PR6295 for EC can't boot issue
B3. Page 12 Delete R11170, mount R11133 for DDR4's SPD
B4. Page 13 Delete R11174, mount R11134 for DDR4's SPD
D B5. Page 27 Change POA IC U1006's P/N. (AL000103006) D
B6. Page 28 Change CN23's P/N--- 5H; Reserve R11284

B7. Page 25 change R247 value from 0 to 2.2 Ohm (CS-2204FA00); Change R251, R262, R269, R11265 footprint from 0603 to 0805 (LAN)--(CS07504FA11)
B8. Page 2 Mount R485 for THRMTRIP#
B9. Page 17 Change R4314 & R4306 of value for KA/KB
B10. Page 6 Mount Q6060 for CMOS issue
B11. Page 31 Swap U45 Pin81 & Pin32 for DAC Fan; Add D4015 for ESD; Reserve R11282 for battery
B12. Page 6 R512 Change P/N from 5% to 1 % (CS22702FB14)
B13. Page 8 IOAC setting change into none IOAC R598 mount , R599 remove.
B14. Page 29 Delete R328,R11109,R327,R347,R346,C4716,C4718,C4717,C4558 & Q6061; Add C321,C723,C728,C719,R218 & U12 for DAC Fan; Change CN8's P/N
B15. Page 29 Change KB/BL connector CN's FP,P/N. (DFFC04FR111) & remove CN2018 for ME request
B16. Page 29 Chage CP1~CP6 into 0402 size, from C4788~C4811
B17. Page 26 Change Speaker connector CN18's FP,P/N. (DFHD04MR176)
B18. Page 26 Modify U16,U4512 pin2 to +3V , then off U16 & U4512
B19. Page 15 Change C4117,C4118 from 22U into 10U, and Add C4815, C4812 (10U-0402) for layout speace.
B20. Page 18 Change C4423,C4426 from 22U into 10U, and Add C4813, C4814 (10U-0402) for layout speace.
B21. Page 31 Change SW4's P/N & FP; Add R1283 for EC AUTO RECOVERY.
B22. Page 28 Change Hole16's P/N & FP, Add Hole25, Hole26 for ME modify ; Add R11284
B23. Page 5 Change C202 value from 47U to 22U & add C4816
B24. Page 23 Change R11268,R11271 from 33 to 47 Ohm ; Change L5,L6,L7's P/N; Not mount C718,C716,C319,C333,C336
B25. Page 32 Change PJ3's FP
B26. Page 30 Change U22's FP
B27. Page 24 Change CN12's FP
B28. Page 4 Change C739 from 10 to 22P & mount for EMI request
B29. Page 21 Add C4817 & C4818 for EMI request
C B30. Page 2 Change R577 & R152 power to +3V_S5 for leakage C
B31. Page 8 Change R211 power to +3V_S5 for leakage

B32. Page 22 Add R11285, R11286(reserve)
B33. Page 21 Cancle co-layout R11225,R11226,R11227,R11228,R11229,R11230,R11231 & R11232.
B34. Page 14 Change C356 & 362 for vendor recommend
B35. Page 24 Mount R11277, Remove R11274 change to -4db
Power-CHANGE
B36. Page 33 Delete JP18, JP20 ,PR248,PR249,PR6127,PR6219,PR345,PR244,,PR247,PR246,PR266,PR272
B37. Page 34 Delete JP9
B39. Page 36 Delete JP22,JP29
B40. Page 37 Change PR225,PR224's value from 10k to 13.7K; Add SP@ at PR194,PR203,PR207,PR202
B41. Page 38 Delete JP24, change JP25 to PR6304
B43. Page 40 Delete PR6298,PQ6066,PR137,PQ4,PR153,PQ10; Change PU2 & PU6's P/N for ESD.
B45. Page 42 Delete JP10,JP35
B46. Change DDR solution to RT8231B
Change +1V_S5 solution to G5335
Change +1.35V_GFX solution to G5335
Revise LDO P/N to AL001282000 (YB1282PSP8)
LDO (PU2 & PU6) Pin4 adding 1u/6.3
B47. Page 37 Change PC10, PC20, PR192,PC28,PR211,PR220 & PC39 of value.
B48. Page 25 Add R6308
B B
C-CHANGE
C1. Change 0 Ohm to short pad & remove JP,
R11,R14,R15,R28,R66,R67,R11129,R102,R194,R224,R229,R235,R790,R791,R792,R11111,R11112,R11113,R11140,R112,R135,R179,R180,R182,R185,R187,
R188,R192,R193,R198,R240,R252,R11131,R164,R246,R339,R350,R11185,R11186,R550,R657,R718,R721,R782,R11153,R11283,R795,R796,R797,R816,
R817,R818,R819,R820,R821,R11196,R11199,R11202,R11207,R11279,R11280,R11281,R948,R951,R956,R958,R959,R960,R11061,R11062,R11110,R11133,
R11134,R11136,R11137,R11138,R11139,R11141,R11253,R11254,R11255,R11256,R11267,R11270,PR257,PR263,PR267,PR274,PR281,PR82,PR83,PR94.
PR87,PR254,PR264,PR109,PR110,PR117,PR122,JP8,JP10,JP14,JP15,JP17,JP22,JP33,JP19,JP21
R4328,R4335,R2855,R2870,R318,R221,R403,R405,R742,R743,R725,R745,L19,R2872
C2. Page 31 remove SW2 -- power bottom
C3. Page 29 Change CN20 & CN2019 K/B connector of P/N
C4. Page 27 Delete Q76, R11288; Add C4819, R11290 ,R11291,R11298,R11299,R11302,R11303,R11300,R11301,R11292,R11293,R11294,R11295 for co-layout POA & PBA ; Reseeve EC52,EC53,R11289 & R11287
C5. Page 21 remove R11193, double mount at type-C
C6. Page 32 for power request change short pad to 10 Ohm, location PR209 & PR210; Change PC115 of value
C7. Page 8 remove R618, it can't mount, because none device.
C8. Page 38 mount PC138 -- power request.
A A
U12,Q31,PR192

PROJECT MODEL : ZWA APPROVED BY: DATE:
PROJECT : ZAA DOC NO.
1A
Change list PART NUMBER: DRAWING BY: REVISON:
5 4 3 2 1
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Acer Aspire E5-575 735T DAZAAMB16E0 Quanta ZAA-x16 - Ironman - SK (ZAA) & Captain - SK (ZAAA) - 2016-0203-C-Gerber

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Acer Aspire E5-575 735T DAZAAMB16E0 Quanta ZAA-x16 - Ironman - SK (ZAA) & Captain - SK (ZAAA) - 2016-0203-C-Gerber

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5 4 3 2 1

ZAA Serials SKL ULT SYSTEM BLOCK DIAGRAM

USB3-1 & USB3-2

TPS51225R ISL95859HRTZ-T UP1658RQKF

AJ0QKKQVT00 -->CPU(1356P)KBL 1.7G QKKQ(FCBGA) -----no use

1K_4 R529 CPU_THRMTRIP# H_PECI (50ohm)

5/29 XDP_TCK0 R558 Stuff

Quanta Computer Inc.

Change Data and DQS to interleave.

SKL ULT (DDR3L) SKL ULT (DDR3L)

M_A_A[13:0] *100K_4 M_B_A[13:0]

R621 *10K_4 1 3 DDR_VTTT_PG_CTRL <36>

For Sx ,stuff Q? in DDR_VTT_CNTL

SM_RCOMP_0 120/F_4 R685

CPU_DRAMRST# R670 *short_4 DDR3_DRAMRST# <12,13>

SKL ULT (SIDEBAND ) GPIO

H_PWRGOOD (50ohm) VGPU_EN AN8 +3V_S5

high UMA Only

+3V R667 33_4 HDA_SYNC_R BA22

SPI0_MOSI Reserved RSMRST# (iPU 15 ~ 40K)

SPI0_MISO Reserved RSMRST# (iPU 15 ~ 40K)

SPI0_IO2 Reserved RSMRST# (iPU 15 ~ 40K)

A SPI0_IO3 Reserved RSMRST# (iPU 15 ~ 40K) A

0 = *Enable security in the Flash

GPP_E19 0 = *Port B is not detected (iPD 20K)

Backside cap A30

G32 Primary side cap

Backside cap Primary side cap

+VCCEOPIO Backside cap +VCCOPC_SRC

U35M SKL_ULT +VCCGT H_CPU_SVIDCLK

Primary side cap

Primary side cap

Primary side cap SP@SKL_ULT/BGA

C176 VSA_SENSE <37>

Primary side cap

Primary side cap 1U/6.3V_4

Quanta Computer Inc.

<25> CLK_PCIE_LANN CLKOUT_PCIE_N4 RTCX2

<28> CLK_PCIE_WLANN CLKOUT_PCIE_N5

CLK_PCIE_REQ0# R234 10K_4

CLK_PCIE_REQ1# R215 10K_4 1. AHL03003057 DBV CR2032

CLK_PCIE_REQ5# R223 10K_4 100K_4

+3V_LDO_EC R11126 *0_6 +3V_PCH_ME +3V

R649 1K_4 SPI_WP_IO2_ME

R602 *short_4 PCH_SPI_CS0#

R591 10K_4 SPI_CS0#_UR_ME

Quanta Computer Inc.

VCCST_PWRGD B65 PROCPWRGD I SLP_LAN# BB17 PCH_SLP_WLAN#

A36 C37 +3V_S5

BOARD_ID4 No touch panel touch panel

Rev:D change to shortpad

EC_PWROK R131 *0_4 SYS_PWROK_R

For platforms not supporting Deep B2A

TC7SH08FU R214 U8 Rev:D change netmane for HWPG

100K_4 *TC7SH08FU R130

Quanta Computer Inc.

VCCPRIM_1P0 & VCCPRIM_CORE Short GPIO Group Power Plane

Pin Name Strap description Configuration Note

CFG[1] Reserved Configuration lane

CFG[3] Reserved Configuration lane

1 = Disabled (iPU 3K) CFG4

00 = 1x8, 2x4 PCI Express*

APS1 R289 0_6 APS3 R272 0_6 APS7

EC39 120P/50V_4 EC36 120P/50V_4 C1325 1U/6.3V_4 C1311 1U/6.3V_4 +1.2VSUS

EC48 120P/50V_4 EC47 120P/50V_4 C1309 1U/6.3V_4 C1310 1U/6.3V_4

EC42 120P/50V_4 EC43 120P/50V_4 C1318 1U/6.3V_4 C1319 1U/6.3V_4