TDTS01

Computer Aided Design

of Electronics

Lab Compendium

version 4.1 (2011)

January 2011

1
 Chapter 1
Introduction

This lab aims to let students get familiar with the techniques for computer-aided design,
synthesis and test. In order to understand the design flow (see Figure 1), students will be
given an example of a hardware design in the tutorial with the following steps:

♦ preliminary hardware specification

♦ behavioral design on the system level
♦ simulation of the behavioral design
♦ high-level synthesis (HLS) of the design to the register-transfer level (RTL)
♦ simulation of the structural design
♦ logic synthesis of the design to the gate level
♦ test pattern generation for the gate-level netlist
A hardware description language VHDL is used for the behavioral and structural design.
Several computer-aided design tools from Mentor Graphics are used for the simulation,
synthesis, and test pattern generation (see Figure 1). Students are required to follow the
above steps to make their own designs and write final reports.

Parts of this tutorial are copyright  Mentor Graphics Corporation 1996-2000. All rights
reserved.

1
 Specification
Description of
----
Basic Specifications
----

Behavioral Design

VHDL Code of
----
---- Behavioral Design

ModelSim Simulation

High-Level Synthesis

---- VHDL Code of

---- Structural Design
ModelSim Simulation

Leonardo
Spectrum Logic Synthesis

Gate-Level Netlist

FlexTest Test Pattern Generation

----
---- Test Patterns

Figure 1. Design flow for the lab

2
 Chapter 2
Preparation for the Lab

Before starting the lab for hardware design, you have to set up the lab environment.

Please use TERMINAL other than CONSOLE for the lab!

2.1 Setting Up the CAD Tool Environment

1. Open a terminal (not a console window). Load a module called prog/mentor/C.2
which is used by Mentor Graphics tools ModelSim, Leonardo Spectrum, and
FlexTest.

First of all, check if this module has already been loaded with the following
command (note that % is used in this tutorial to denote the command prompt):

% module list

If you cannot find the module prog/mentor/C.2 in the module list, you can issue
the following command to initially add the module to the login setup file .login :

% module initadd prog/mentor

Then load this module for your present terminal:

% module load prog/mentor

2. Initially load a module called prog/mentor/fpgadv which is used by Mentor

Graphics synthesis tool LeonardoSpectrum, if it has not been loaded yet, with the
following command:

% module initadd prog/mentor/fpgadv

Then load this module for your present shell:

% module load prog/mentor/fpgadv

Make sure that the module prog/mentor/C.2 is always loaded BEFORE

the module prog/mentor/fpgadv !

3
2.2 Setting Up Environment Variables
In this step you will set environment variables for your shell.

1. Set the environment variable MGC_HOME which should point to the location of the
most recent release of Mentor Graphics tools.

First, use the following command

% echo $MGC_HOME

to check if the environment variable MGC_HOME is equal to:

/sw/mentor/C.2/mentor

If not, set MGC_HOME with the desired value:

% setenv MGC_HOME /sw/mentor/C.2/mentor

2. Set the environment variable MODEL_TECH which should point to the bin directory
of the most recent release of the ModelTech tools, including ModelSim.

First, check if the command

% echo $MODEL_TECH

prints the following result:

/sw/mentor/C.2/fpgadv/4.0/Modeltech/bin

If not, set MODEL_TECH with the desired value.

3. Check and/or set the environment variable PATH :

PATH should include at the beginning the path $MGC_HOME/bin which contains the
executable files for Mentor Graphics applications, and the path $MODEL_TECH
which contains executable files for ModelSim. If this is not the case, use the
following command to set the PATH variable accordingly:

% setenv PATH /sw/mentor/C.2/mentor/bin:/sw/mentor/C.2/

fpgadv/4.0/Modeltech/bin:$PATH

Make sure that version 4.0 of Modeltech is specified first in PATH and not
version 6.2 !

4
2.3 Copying Files for Tutorial
1. Move to the directory where you want to create a copy of the tutorial data (it can be
your root directory) and execute the commands below

% mkdir hls

% mkdir hls/src

% cp /home/TDTS01/hls_tutorial/std_arit.vhd hls/src/.

% cp /home/TDTS01/hls_tutorial/array_acc_behavioral.vhd
hls/src/.

% cp /home/TDTS01/hls_tutorial/tb_array_acc_behavioral.vhd
hls/src/.

% cp /home/TDTS01/hls_tutorial/array_acc_structural.vhd
hls/src/.

% cp /home/TDTS01/hls_tutorial/tb_array_acc_structural.vhd
hls/src/.

% cp /home/TDTS01/hls_tutorial/c35_CORELIB.atpg hls/src/.

2. Move to the created hls/src directory and check if all files are correctly copied.
Please note that the following files should be observed:

♦ std_arit.vhd -- source file of the standard binary-component library

♦ array_acc_behavioral.vhd and array_acc_structural.vhd -- source files of the
behavioral and structural design, respectively
♦ tb_array_acc_behavioral.vhd and tb_array_acc_structural.vhd -- source files of
the test bench for behavioral and structural design, respectively
♦ c35_CORELIB.atpg -- AMS c35 ATPG library with scan flip-flops

5
 Chapter 3
Tutorial of System-Level
Design and Simulation

In this chapter, you will learn to:

♦ write a specification for the design

♦ generate a VHDL description for the behavioral design
♦ compile the VHDL source file into a library used for simulation
♦ use a simulator called ModelSim to verify the functionality of the behavioral design

6
3.1 Design Specification for Array Accumulator
An Array Accumulator (ARRAY_ACC) can accumulatively add up the value of each
element in an input array X and output the sum value to an output port SUM. In order to
show a hardware design which has the capability to run concurrent operations, the
value of each element in array X is added with that of another input array Y, and each
sum value is assigned to the corresponding element of an array variable Z (not a
output port).

Figure 2 shows the logic symbol for the ARRAY_ACC design, where CLK is the clock
port, and RST is the reset port. X and Y are two input arrays with L elements. SUM is
the output port for the sum value, and DV is the data valid port. Note that only when DV
outputs ‘1’, the sum value at the port SUM becomes valid.

CLK
SUM
RST
ARRAY_ACC
X(0 to L-1)
L
DV
Y(0 to L-1)
L

Figure 2. Logic symbol for the ARRAY_ACC design

7
3.2 Behavioral Design in VHDL
The VHDL description of the behavioral design of ARRAY_ACC is shown below:

1 -- Array Accumulator Behavioral Description

2 -- VHDL Pre-synthesis Behavioral Model
3
4 package ARRAY_ACC_PKG is
5 type UI16 is range 0 to 2 ** 16 - 1;
6 type ARRAY_UI16 is array ( UI16 range <> ) of UI16;
7 end;
8 use work.ARRAY_ACC_PKG.all;
9
10 entity ARRAY_ACC is
11 generic ( ARRAY_LEN : UI16 := 10 );
12 port ( X : in ARRAY_UI16 ( 0 to ARRAY_LEN - 1 );
13 Y : in ARRAY_UI16 ( 0 to ARRAY_LEN - 1 );
14 CLK : in bit;
15 RST : in bit;
16 SUM : out UI16;
17 DV : out bit );
18 end ARRAY_ACC;
19
20 architecture BEHAVIORAL of ARRAY_ACC is
21 Begin
22 P_MAIN : process
23 variable SUM_VAR : UI16;
24 variable IDX_VAR : UI16;
25 variable Z_VAR : ARRAY_UI16 ( 0 to ARRAY_LEN – 1 );
26 begin
27 SUM_VAR := 0;
28 IDX_VAR := 0;
29 while ( IDX_VAR < ARRAY_LEN ) loop
30 SUM_VAR := SUM_VAR + X( IDX_VAR );
31 Z_VAR( IDX_VAR ) := X( IDX_VAR ) + Y( IDX_VAR );
32 IDX_VAR := IDX_VAR + 1;
33 end loop;
34 SUM <= SUM_VAR;
35 DV <= '1';
36 end process P_MAIN
37 end BEHAVIORAL;

Figure 3. VHDL description of the behavioral design of ARRAY_ACC

8
Below are the explanations for the behavioral description:

♦ Lines 4-8: Type definition of the unsigned integer and the array of unsigned integer.
For simplicity we only use unsigned integers in this design.
♦ Lines 10-18: Declaration of the entity ARRAY_ACC which has four input ports and
two output ports. Input ports consists of X, Y, CLK, and RST. X and Y are two input
arrays, CLK is the clock port, and RST is the reset port. Output ports include SUM
and DV. SUM is the sum of element values of array X, and DV outputs the data valid
signal.
♦ Lines 20-26: The architecture of ARRAY_ACC contains one process. Three variables
SUM_VAR, IDX_VAR, and Z_VAR are created to store temporary values. SUM_VAR
is used to store the present sum value of the calculated elements in array X.
IDX_VAR stores the present index value for array X, used for addressing the
element which should be currently calculated. Z_VAR is an array which stores the
sum of each pair of elements with the same index value in arrays X and Y.
♦ Lines 22-36: Definition of main body of the algorithm. SUM_VAR and IDX_VAR are
initialized with the value 0 (lines 27 and 28).
♦ Lines 29-33: In the WHILE loop, all the elements in the arrays X and Y are explored.
The value of each element in array X is accumulatively added to the variable
SUM_VAR. The values of each pair of elements in X and Y are added and the sum
value is stored in the corresponding element in array Z. The index IDX_VAR is
incremented at every iteration step and is used for quitting the loop when it gets
equal to the right bound value of the arrays.
♦ Lines 34-35: Output the value of SUM_VAR and set the data valid port DV to ‘1’
when the WHILE loop is terminated.

9
3.3 Compiling Your Design for Simulation
In this section, you will create a work library called work in order to compile the VHDL
source codes of the ARRAY_ACC design for simulation. You will use the ModelSim
commands vlib, vmap, and vcom.

1. Go to the directory where the source file array_acc_behavioral.vhd is located,

and create a working directory work with the command vlib :

% $MODEL_TECH/vlib work

2. Use vmap command to map the Mentor Graphics ieee and mgc_hls resource
libraries (logical libraries) to the directories where the physical libraries are stored.

% $MODEL_TECH/vmap ieee $MODEL_TECH/../ieee

% $MODEL_TECH/vmap mgc_hls $MGC_HOME/pkgs/hls_pkgs/mgc_hls

Examine the modelsim.ini file to verify that the mapping was created:

% $MODEL_TECH/vmap

The mappings should exist in the first few lines.

The modelsim.ini file records the mapping from each logical library to
its physical location. When the mapping from a logical library to its
physical location is created, users can place their work libraries to any
desired location while still make them visible to ModelSim.

3. Compile std_arit.vhd into the work library with the vcom command:

% $MODEL_TECH/vcom -93 std_arit.vhd

Be aware of the warning and error messages in the transcripts

4. Compile the ARRAY_ACC behavioral design into the work library

% $MODEL_TECH/vcom array_acc_behavioral.vhd

5. Compile the test bench tb_array_acc_behavioral for the behavioral design

into the work library.

% $MODEL_TECH/vcom tb_array_acc_behavioral.vhd

10
3.4 Simulation of Behavioral Design
1. Invoke the ModelSim simulator:

% $MODEL_TECH/vsim &

2. Close the welcome screen by pressing the button Done. On the pop-up Load
Design window, select the test bench of the behavioral design to be loaded for
simulation:

3. In ModelSim Main Window, click the mouse pointer after the prompt, and enter:

VSIM> view *

4. Move the cursor to the Signals window and execute the following pull-down menus:
View → Wave → Signals in Design. The signals listed in the Signals window are
added to the Wave window.

5. Move the cursor to the Signals window, then execute the following pull-down
menus: View → List → Signals in Design. The signals listed in the Signals
window are added to the List window

6. Expand the Wave window to the full width of the screen for the convenience of
observing the waveforms.

11
7. Move the cursor to the ModelSim Main Window and execute the following pull-
down menu: Run → Run 100 ns

8. From the wave window, execute the pull-down menu Zoom → Full. Place the
mouse pointer on the blue cursor, hold down the Select mouse button (the left
button) and slide the cursor across the window to examine the results. The
expected results in the Wave window are shown below:

Observe the simulation results and the behavior of your VHDL model.
Check if the sum was correctly calculated for each element in the input
array.

Notice that the DV port was set to ‘1’ at the beginning of the simulation.
Compare the time that DV port is set to ‘1’ in the simulation of the
behavioral design and the structural design. Explain the reason of the
observed difference in your final report.

9. From the main ModelSim window, execute the menu File → Quit.

12
 Chapter 4
Tutorial of High-Level Synthesis

In this chapter, you will learn to use high-level synthesis techniques to synthesize the
behavioral design to a structural design on the register-transfer level. You will see the
following steps in this tutorial:

♦ derivation of Control/Data-Flow Graph (CDFG)

♦ operation scheduling
♦ resource allocation and binding
♦ derivation of RTL data-path structure
♦ description of finite state machine (FSM)
♦ VHDL description for data-path structure
♦ writing a test bench for simulation
♦ simulation of the structural design

13
4.1 Control/Data-Flow Graph
In this section, you will lean to derive a Control/Data-Flow Graph (CDFG) from the behavioral
description of ARRAY_ACC desgin. In this tutorial, the fastest solution is taken as an
example, with the given constraints of available components for use.

Control/Data-Flow Graphs are widely used for representing register-transfer level designs
(structural designs). In a CDFG, an operation such as comparison, addition, or multiplication
is represented by a node, meaning that this operation is implemented by a particular
hardware component, such as a comparator, adder, or multiplier, and the operation is bind to
the component for execution. A data flow is represented by an arrow with a solid line which
connects two nodes, meaning that from the source node to the destination node, there exists
a data dependency. When a data flow arrow exists between two nodes, the represented
operations can be executed only sequentially. Similarly, a control flow in a CDFG is
represented by an arrow with a dashed line. When a control-flow arrow connects two nodes,
it means that there is a control dependency between the source and destination nodes, and
these two operations can only be executed sequentially. Note that when two nodes have a
data dependency, they must also have the control dependency in the same direction. So in
this case, the control-flow arrow is omitted by default for the clearness of the CDFG. When
two nodes have neither data dependency nor control dependency, the two operations can be
bind to two arbitrary components for concurrent execution, if the two operations arrive at the
same time.

Figure 4 shows the CDFG for the fastest solution where adequate hardware components are
provided for the design. The CDFG is derived from the behavioral description in Figure 3.
The comparison operation < corresponds to line 29 where the index value is compared to the
right bound of the arrays. The addition +x corresponds to line 30 where the value of an
element in array X is added to the variable SUM_VAR. The addition +y corresponds to line 31
where the value of an element in array X is added with the value of the element which is of
the same index value in array Y. The addition +i corresponds to line 32 where the index value
increments. The assignment operation := corresponds to line 34 where the sum value is
output to the port SUM.

14
 N
<
Y

+X +Y

+i

:=

Figure 4. CDFG derived from the behavioral description (the fastest solution)

15
4.2 Operation Scheduling
Operation scheduling deals with the assignment of each operation to a control step which is
a time slot such as a clock cycle or bus cycle. A schedule will be generated such that the
data/control dependencies captured by the CDFG derived from the behavioral description
are kept and the resource constraint is satisfied. Here we use the As-Soon-As-Possible
(ASAP) scheduling for the fastest solution.

Control
Step

1 N
<
Y

2
+X +Y

3
+i

4
:=

Figure 5. Scheduled CDFG (the fastest solution)

16
4.3 Resource Allocation and Binding
In this section, you allocate and bind hardware components in some given libraries to the
operations illustrated in the scheduled CDFG. Resource allocation is the process of deciding
how many and which kind of resources can be used in a given implementation. Binding
assigns the instance of an allocated hardware resource to a given data-path node. Different
data-path operations can share the same hardware resource if they are not executed at the
same time.

As the fastest solution is employed, we decide to use one comparator, three adders, and
some registers and multiplexers, according to the CDFG derived from the behavioral
description and the component libraries.

In the case that you have to write your own components, you can refer to two
source files resources.vhd and primitives.vhd in
/home/TDTS01/hls_tutorial. There are source codes for basic components
like adder, multiplier, and multiplexer etc. You are entitled to modify the design
of those components for you own use.

17
4.4 Derivation of RTL Data-Path Structure
After the binding of adders, comparators, multiplexers, and registers, a RTL data-path
structure illustrated in Figure 6 is derived from the scheduled CDFG (see Figure 5).

X(0 to L-1) Y(0 to L-1)

0 0
MS_SEL MX_SEL MY_SEL MI_SEL
MUX_SUM MUX_X MUX_Y MUX_IDX

MS_OUT MX_OUT MY_OUT MI_OUT

RS_ENB RX_ENB RY_ENB RI_ENB

REG_SUM REG_X REG_Y REG_IDX

RS_OUT RX_OUT RY_OUT RI_OUT

L 1

ADDER_SX ADDER_XY COMP_IL ADDER_I1

ASX_OUT AXY_OUT GTE_OUT AI1_OUT

Z(IDX)
SUM DV

Figure 6. RTL Data-Path Structure (the fastest solution)

In the illustrated data-path graph, the multiplexer MUX_IDX is used to select either the value
0 (only used for the initialization when the selection signal MI_SEL is set to ‘0’) or the newest
index value fed back from the adder ADDER_I1 (when MI_SEL is set to ‘1’). Similarly, the
multiplexer MUX_SUM select either the value 0 or the newest sum value fed back from the
adder ADDER_SX to be output to the signal MS_OUT, according to different values in the
selection signal MS_SEL. The selection signals MX_SEL and MY_SEL come from the signal
RI_OUT which is of the current index value stored in the register REG_IDX.

The multiplexers MUX_X and MUX_Y select different elements from the input arrays X and Y,
respectively. The comparator COMP_IL compares the index value in the signal RI_OUT to
the right bound (L) of the arrays and generates an signal GTE_OUT. When MI_OUT is less
than L, GTE_OUT equals ‘0’, otherwise it equals ‘1’. The value assigned to the output port
DV means that the data at the output port SUM is invalid until the port DV gets the value ‘1’.

The signals MI_OUT, MS_OUT, MX_OUT, and MY_OUT which are output in respective from
the multiplexers MUX_IDX, MUX_SUM, MUX_X, and MUX_Y are respectively sent to the
register REG_IDX, REG_SUM, REG_X, and REG_Y which stores the current index value of
the arrays X and Y, the current sum value of the calculated elements in array X, the value of
currently indexed element in arrays X and Y, respectively. These registers are enabled by
signals RI_ENB, RS_ENB, RX_ENB, and RY_ENB in respective. Note that only when the
enable signal is set to ‘1’, the input data are latched into the register, otherwise the old data
are kept.

There are three adders in the data-path graph, denoted with ADDER_I1, ADDER_SX, and
ADDER_XY. ADDER_I1 increments the index value, ADDER_SX adds the value of the
currently indexed element in array X with the sum value stored in the register REG_SUM,
18
and ADDER_XY adds the value of the currently indexed element in array X and Y. The
adders output signals AI1_OUT and ASX_OUT are respectively fed back to the input ports of
multiplexers MUX_IDX and MUX_OUT, for the next round of calculation. The signal
AXY_OUT is assigned to elements in the array variable Z.

19
4.5 Generation of Finite State Machine
In order to control all operations in the desired order, a Finite State Machine (FSM) is
required. From the scheduled CDFG, we can easily derive the finite state machine by
creating every state from the control steps. Figure 7 shows the FSM of the Array
Accumulator.

S1 GTE_OUT = '1'

GTE_OUT = '0'

S2

S3

S4

Figure 7. Finite State Machine (FSM)

Below is the explanations for the operations at every state and how the control flow goes
through different states.

♦ State S1:
RX_ENB <= '0';
RY_ENB <= '0';
RS_ENB <= '0';
RI_ENB <= '0';
MS_SEL <= 1;
MI_SEL <= 1;
SUM <= ASX_OUT;
DV <= GTE_OUT;

At state S1, values are assigned to signals MX_OUT, MY_OUT, MS_OUT and MI_OUT but
none of them are latched into the registers since the register are not write-enabled at this
moment. The value of signal GTE_OUT is used for selecting the next state: if GTE_OUT
equals '1', the next state is S4, otherwise S2.

20
♦ State S2:
RX_ENB <= '1';
RY_ENB <= '1';
RS_ENB <= '1';
RI_ENB <= '0';
MS_SEL <= 1;
MI_SEL <= 1;
SUM <= ASX_OUT;
DV <= GTE_OUT;

At state S2, the values of signals MX_OUT, MY_OUT and MS_OUT are latched into
registers REG_X, REG_Y, and REG_SUM, respectively. Additions are executed on adders
ADDER_SX and ADDER_XY and the output of ADDER_SX is fed back to the input of
register REG_SUM through multiplexer MUX_SUM. The value of signal MI_OUT is not
latched into register REG_IDX as its write-enable signal is ‘0’. Thus the output of adder
ADDER_I1 remains unchanged. The control goes to state S3.

♦ State S3:
RX_ENB <= '0';
RY_ENB <= '0';
RS_ENB <= '0';
RI_ENB <= '1';
MS_SEL <= 1;
MI_SEL <= 1;
SUM <= ASX_OUT;
DV <= GTE_OUT;

In state S3, registers REG_X, REG_Y and REG_SUM hold their present data, while the
value of signal MI_OUT is latched into register REG_I1. Thereafter, adder ADDER_I1
increments the value of signal RI_ENB. The output signal AI1_OUT is then fed back to the
input of register REG_IDX through multiplexer MUX_IDX. Multiplexers MUX_SUM and
MUX_IDX select the high inputs. The next state becomes S1.

♦ State S4:
RX_ENB <= '0';
RY_ENB <= '0';
RS_ENB <= '0';
RI_ENB <= '0';
MS_SEL <= 0;
MI_SEL <= 0;
SUM <= ASX_OUT;
DV <= '1';

In state S4, all registers are set to hold the current data. The sum value in signal ASX_OUT
is assigned to the primary output port SUM and ‘1’ is assigned to DV.

Please note that EVERY output port of the FSM should be assigned a value at
EVERY state, even when the value at the port remains unchanged!

Please pay attention to the clock edge used in your design. You can ONLY use
a single edge for a clock signal (port) in your design, either the raising edge or
the falling edge. Using inconsistent edges for a clock signal (port) violates the
design rule!

21
Below is the complete VHDL description of the FSM

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.all;
use work.ARRAY_ACC_PKG.all;

entity FSM is
port ( CLK : in bit;
RST : in bit;
ASX_OUT : in UI16;
GTE_OUT : in bit;
MS_SEL : out UI16;
MI_SEL : out UI16;
RS_ENB : out bit;
RI_ENB : out bit;
RX_ENB : out bit;
RY_ENB : out bit;
SUM : out UI16;
DV : out bit
);
end FSM;

architecture CONTROLLER of FSM is

-- FSM state declaration
type STATE_TYPE is ( S1, S2, S3, S4 );
signal PRESENT_STATE : STATE_TYPE;
signal NEXT_STATE : STATE_TYPE;
begin -- FSM controller
STATE_REGISTER : process ( RST, CLK )
begin
if ( RST = '1' ) then
PRESENT_STATE <= S1;
elsif ( CLK'EVENT and CLK = '0' ) then
PRESENT_STATE <= NEXT_STATE;
end if;
end process STATE_REGISTER;

OUTPUT_DECODE_LOGIC : process ( PRESENT_STATE, ASX_OUT, GTE_OUT )

begin
MS_SEL <= 0;
MI_SEL <= 0;
case PRESENT_STATE is
when S1 =>
RX_ENB <= '0';
RY_ENB <= '0';
RS_ENB <= '0';
RI_ENB <= '0';
MS_SEL <= 1;
MI_SEL <= 1;
SUM <= ASX_OUT;
DV <= GTE_OUT;
when S2 =>
RX_ENB <= '1';
RY_ENB <= '1';
RS_ENB <= '1';
RI_ENB <= '0';
MS_SEL <= 1;
MI_SEL <= 1;
SUM <= ASX_OUT;
DV <= GTE_OUT;

22
 when S3 =>
RX_ENB <= '0';
RY_ENB <= '0';
RS_ENB <= '0';
RI_ENB <= '1';
MS_SEL <= 1;
MI_SEL <= 1;
SUM <= ASX_OUT;
DV <= GTE_OUT;
when S4 =>
RX_ENB <= '0';
RY_ENB <= '0';
RS_ENB <= '0';
RI_ENB <= '0';
MS_SEL <= 0;
MI_SEL <= 0;
SUM <= ASX_OUT;
DV <= '1';
end case;
end process OUTPUT_DECODE_LOGIC;

STATE_DECODE_LOGIC : process ( PRESENT_STATE, GTE_OUT )

begin
case PRESENT_STATE is
when S1 =>
if( GTE_OUT = '1' ) then
NEXT_STATE <= S4;
else
NEXT_STATE <= S2;
end if;
when S2 =>
NEXT_STATE <= S3;
when S3 =>
NEXT_STATE <= S1;
when S4 =>
NEXT_STATE <= S4;
end case;
end process STATE_DECODE_LOGIC;
end CONTROLLER;

23
4.6 VHDL Description for the Structural Design
Below is the complete VHDL description of the structural design of ARRAY_ACC:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.all;
use work.ARRAY_ACC_PKG.all;

entity ARRAY_ACC_STRUCTURAL is
generic ( ARRAY_LEN : UI16 := 10 );
port ( X : in ARRAY_UI16 ( 0 to ARRAY_LEN - 1);
Y : in ARRAY_UI16 ( 0 to ARRAY_LEN - 1);
CLK : in bit;
RST : in bit;
SUM : out UI16;
DV : out bit
);
end ARRAY_ACC_STRUCTURAL;

architecture STRUCTURAL of ARRAY_ACC_STRUCTURAL is

-- data path component declarations

component MUX2_UI16
port ( D0 : IN UI16;
D1 : IN UI16;
SEL : IN UI16;
DOUT : OUT UI16
);
end component;

component MUX_UI16
generic ( INPUT_ELEM_NUM : UI16 );
port ( INPUT : IN ARRAY_UI16 ( 0 to INPUT_ELEM_NUM - 1 );
SEL : IN UI16;
DOUT : OUT UI16
);
end component;

component REG_UI16
port ( DIN : IN UI16;
ENB : IN bit;
SET : IN bit;
RST : IN bit;
CLK : IN bit;
DOUT : OUT UI16
);
end component;

component GTE_UI16
port ( A : IN UI16;
B : IN UI16;
GTE : OUT bit
);
end component;

24
component ADDER_UI16
port ( A : IN UI16;
B : IN UI16;
O : OUT UI16
);
end component;

component FSM
port ( CLK : in bit;
RST : in bit;
ASX_OUT : in UI16;
GTE_OUT : in bit;
MS_SEL : out UI16;
MI_SEL : out UI16;
RS_ENB : out bit;
RI_ENB : out bit;
RX_ENB : out bit;
RY_ENB : out bit;
SUM : out UI16;
DV : out bit
);
end component;

-- signal declarations
signal MS_SEL : UI16 := 0;
signal MS_OUT : UI16 := 0;

signal MI_SEL : UI16 := 0;

signal MI_OUT : UI16 := 0;

signal RS_ENB : bit := '0';

signal RS_SET : bit := '0';
signal RS_RST : bit := '0';
signal RS_OUT : UI16 := 0;

signal RI_ENB : bit := '0';

signal RI_SET : bit := '0';
signal RI_RST : bit := '0';
signal RI_OUT : UI16 := 0;

signal MX_OUT : UI16 := 0;

signal MY_OUT : UI16 := 0;

signal RX_ENB : bit := '0';

signal RX_SET : bit := '0';
signal RX_RST : bit := '0';
signal RX_OUT : UI16 := 0;

signal RY_ENB : bit := '0';

signal RY_SET : bit := '0';
signal RY_RST : bit := '0';
signal RY_OUT : UI16 := 0;

signal ASX_OUT : UI16 := 0;

signal AXY_OUT : UI16 := 0;
signal AI1_OUT : UI16 := 0;
signal GTE_OUT : bit := '0';

signal ARRAY_LEN_SIG : UI16 := ARRAY_LEN;

signal UI0_CON : UI16 := 0;
signal UI1_CON : UI16 := 0;
signal BIT0_CON : bit := '0';
signal BIT1_CON : bit := '0';

25
begin

-- component instantiations
MUX2_SUM : MUX2_UI16
port map ( UI0_CON, ASX_OUT, MS_SEL, MS_OUT );

MUX2_IDX : MUX2_UI16
port map ( UI0_CON, AI1_OUT, MI_SEL, MI_OUT );

REG16_SUM : REG_UI16
port map ( MS_OUT, RS_ENB, RS_SET, RST, CLK, RS_OUT );

REG16_IDX : REG_UI16
port map ( MI_OUT, RI_ENB, RI_SET, RST, CLK, RI_OUT );

COMP : GTE_UI16
port map ( RI_OUT, ARRAY_LEN_SIG, GTE_OUT );

MUX16_X : MUX_UI16
generic map ( ARRAY_LEN )
port map ( X, RI_OUT, MX_OUT );

MUX16_Y : MUX_UI16
generic map ( ARRAY_LEN )
port map ( Y, RI_OUT, MY_OUT );

REG16_X : REG_UI16
port map ( MX_OUT, RX_ENB, RX_SET, RST, CLK, RX_OUT );

REG16_Y : REG_UI16
port map ( MY_OUT, RY_ENB, RY_SET, RST, CLK, RY_OUT );

ADD16_SX : ADDER_UI16
port map ( RS_OUT, RX_OUT, ASX_OUT );

ADD16_XY : ADDER_UI16
port map ( RX_OUT, RY_OUT, AXY_OUT );

ADD16_I1 : ADDER_UI16
port map ( RI_OUT, UI1_CON, AI1_OUT );

FSM1 : FSM port map

( CLK ,
RST ,
ASX_OUT ,
GTE_OUT ,
MS_SEL ,
MI_SEL ,
RS_ENB ,
RI_ENB ,
RX_ENB ,
RY_ENB ,
SUM ,
DV
);

-- constants
UI0_CON <= 0;
UI1_CON <= 1;
BIT0_CON <= '0';
BIT1_CON <= '1';

end STRUCTURAL;

26

As it is more convenient to use a single design file for the logic synthesis with
LeonardoSpectrum, put the descriptions of all components and the structural
design in one file when you finish the design.

The complete structural-design diagram is depicted in Figure 8.

X(0 to L-1) Y(0 to L-1)

0 0
MS_SEL MX_SEL MY_SEL MI_SEL
MUX_SUM MUX_X MUX_Y MUX_IDX

MS_OUT MX_OUT MY_OUT MI_OUT

RS_ENB RX_ENB RY_ENB RI_ENB

REG_SUM REG_X REG_Y REG_IDX

RS_OUT RX_OUT RY_OUT RI_OUT

L 1

ADDER_SX ADDER_XY COMP_IL ADDER_I1

ASX_OUT AXY_OUT GTE_OUT AI1_OUT

Z(IDX)

CLK

FSM

RST
SUM
DV

Figure 8. Complete structural-design diagram

27
4.7 Writing a Test Bench for Simulation
When finishing the structural design, write a test bench to verify the design by simulation.
Below is the test bench for the structural design of ARRAY_ACC.
use work.ARRAY_ACC_PKG.all;

entity TB_ARRAY_ACC_STRUCTURAL IS
end TB_ARRAY_ACC_STRUCTURAL;

architecture TEST_BENCH_STRUCTURAL of TB_ARRAY_ACC_STRUCTURAL is

-- Input data
constant ARRAY_LEN_CON : UI16 := 10;
constant A_CON : ARRAY_UI16 ( 0 to ARRAY_LEN_CON - 1 )
:= ( 6, 5, 7, 91, 9, 35, 112, 17, 75, 9 );
constant B_CON : ARRAY_UI16 ( 0 to ARRAY_LEN_CON - 1 )
:= ( 9, 25, 49, 29, 10, 65, 65, 18, 123, 255 );

-- define clock period

constant PERIOD : time := 10 ns;

signal X_SIG : ARRAY_UI16 ( 0 to ARRAY_LEN_CON - 1 );

signal Y_SIG : ARRAY_UI16 ( 0 to ARRAY_LEN_CON - 1 );
signal CLK_SIG : bit;
signal RST_SIG : bit;
signal SUM_SIG : UI16;
signal DV_SIG : bit;

component ARRAY_ACC_STRUCTURAL
generic ( ARRAY_LEN : UI16 := ARRAY_LEN_CON );
port ( X : in ARRAY_UI16 ( 0 to ARRAY_LEN - 1 );
Y : in ARRAY_UI16 ( 0 to ARRAY_LEN - 1 );
CLK : in bit;
RST : in bit;
SUM : out UI16;
DV : out bit
);
end component;

begin
-- Component instantiation
ARRAY_ACC_STRUCTURAL_1 : ARRAY_ACC_STRUCTURAL
generic map ( ARRAY_LEN_CON )
port map ( X_SIG, Y_SIG, CLK_SIG, RST_SIG, SUM_SIG, DV_SIG );

P_CLOCK : process ( CLK_SIG )

begin
CLK_SIG <= ( not CLK_SIG ) after PERIOD;
end process P_CLOCK;

P_DATAINPUT : process ( RST_SIG )

begin
if ( RST_SIG = '0' ) then
X_SIG <= A_CON;
Y_SIG <= B_CON;
end if;
end process P_DATAINPUT;

end TEST_BENCH_STRUCTURAL;

28
4.8 Simulation of the Structural Design
1. Compile the structural design into the work library:

% $MODEL_TECH/vcom array_acc_structural.vhd

Pay attention to warnings and errors in the transcripts.

2. Compile the test bench into the work library:

% $MODEL_TECH/vcom tb_array_acc_structural.vhd

3. Invoke ModelSim:

% $MODEL_TECH/vsim &

4. Finish the rest steps as you did in the simulation of behavioral design.

29
 Chapter 5
Tutorial of Logic Synthesis

LeonardoSpectrum is a suite of high-level design tools for a Complex Programmable

Logic Device (CPLD), Field Programmable Gate Array (FPGA), or Application Specific
Integrated Circuit (ASIC). LeonardoSpectrum offers design capture, VHDL and Verilog
entry, register-transfer level debugging for logic synthesis, constraint-based
optimization, timing analysis, encapsulated place-and-route, and schematic viewing. In
this tutorial, you will use LeonardoSpectrum to synthesize the structural design to a
gate-level net list.

1. In order to invoke LeonardoSpectrum correctly, you have to load the module

prog/mentor/fpgadv

Use the following command to see loaded modules:

% module list

If the required module has not been loaded yet, load it with the following command:

& module load prog/mentor/fpgadv

2. Invoke LeonardoSpectrum:

% leonardo &

Select LeonardoSpectrum Level 3 and click OK on the dialogue box:

30
 Then the main window of LeonardoSpectrum will be displayed:

3. In the main window, click the menu Tools → FlowTabs to enter the advanced
setup mode:

31
4. Click the Technology tab and select the technology ASIC → AMS →
c35_CORELIB. Then click Load Library button to load the specified technology
library. Observe the transcripts in the upper-right text window.

5. Click the Input tab and press the Open button to load the structural design source
file array_acc_structural.vhd. Then press the Read button. See the transcripts to
make sure that no errors occurred and the pre-optimization succeeded

32
6. Click the Elaborate tab at the bottom-left corner of the main window. Select the
Top level designs as ARRAY_ACC_STRUCTURAL and the Architecture as
STRUCTURAL. Then press the Elaborate button.

7. Click Optimize tab. Choose the Target Technology as AMS – c35_CORELIB,

and select Run Type as Optimize. Click the Optimize button

33
8. Click Output tab. Choose Format as EDIF. Specify the file name as
array_acc_structural.edf and press the Write button to save the netlist file

34
 Chapter 6
Tutorial of Test Pattern Generation

In previous chapters, you have learned how to synthesize a design down to the gate
level. In this chapter you will learn to use FlexTest to generate test patterns
automatically.

1. Invoke FlexTest:

% flextest &

1. On the Welcome Window, specify where the Design File (the netlist file
array_acc_structural.edf) and ATPG Library are located. Choose the Format of
the netlist file as EDIF. Click Invoke FlexTest.

35
 Two windows will pop up, the one on the left is FlexTest Main Window and the
other is FlexTest Control Panel.

2. In FlexTest Control Panel, click Clocks. In the Setup Circuit Clocks window, add
all Primary Input Clocks and choose the off-state for each. Click OK when ALL
primary input clocks have been added

36

Usually there are two primary pins that you may want to define as circuit
clocks, CLK (clock) and RST (reset). Here a primary clock pin means that
you use the rising or falling edge of the clock signal coming from this
primary input port to trigger an event.

The off-state of a primary input clock should be defined as ‘0’ if you use
its raising edge, or ‘1’ when using the falling edge.

3. Then click Done With Setup. In the pop-up FlexTest - Session Purpose window,
click Pattern Generation.

4. In FlexTest Control Panel, click Fault Universe. On the pop-up dialogue box, click
Typical. In FlexTest Control Panel, click Test Generation, and then click Run
With Existing Settings on the pop-up window.

37
 FlexTest ATPG Run Statistics window will pop up, and you can see the test
coverage that has been reached. Click Dismiss to close the window.

Please make a screen shot for the above statistic result window and put it
in your final report. On a Solaris workstation, an application called
“SnapShot” can be used to capture screen shots.

5. In FlexTest Main Window, click menu File → Save → Patterns. In the pop-up
Save Test Patterns window, check the first option Save the Pattern Set to a File,
specify the file name, select the pattern format as desired, and click OK to save the
test patterns.

38
 Chapter 7
Lab Assignments

Students are supposed to do their own projects by following the same design and test
flow as they did in the tutorial. Projects can be assignments provided on the course
webpage or can be defined by students themselves. Two students should work
together in a team on their project.

In the lab, students are supposed to follow the steps bellow:

♦ preliminary hardware specification

♦ behavioral design
♦ simulation of behavioral design
♦ high-level synthesis of the design to the register-transfer level (RTL)
♦ simulation of structural design
♦ logic synthesis of the design to the gate level
♦ test pattern generation for the gate-level net list

You should discuss with the lab assistant on what project you have
selected. A short written description of your project proposal is required
to be sent to the lab assistant before you start the project.

When your project is approved, you should not modify the project
proposal except that you have discussed with the lab assistant and the
modification has been approved.

By the last lab session, each group should have demonstrated their
project interactively.

The project proposal, interactive demonstration, and final reports are

obligatory in order to get the points of the lab

39