Metallic Cabinet Ass'y Front Glass (DISPLAY) Rernote Controller Ass'y

(A01-1618-12) (810-0897-04) (A70-0180-05)

Knob (POWER) Panel Ass'y (TRAY) Panel Ass'y

(K29-2516-04) (A29-0112-04) (A20-5343-02)

I
Phone Jack (PHONES)
I
Knob (OUTPUT LEVEL)
Knob (+IO, +20. +30, +40, +50)
(K29-2648-04) X 5
(El 1-0162-05) (K29-2648-04) X 2

I Power Cord Bushing

Knob (DIGITAL OUTPUT) (J42-0083-05)
(-7-1 514-04)

Insulator Ass'y
Phono Jack (COAXIAL)
(El 3-01 31 -05)
1
Electric Circuit Module (OPTICAL)
R: (J02-0356-05) X 2 Cap (~02-0784-05)
L: (JO2-0357-05) X 2 (809-0068-05) Cap
(809-0063-05)

Phono Jack (LINE OUTPUT) AC Power

(El 3-0485-05) (E30-)

in cornpliance w'th Federal Regulations, fol- KENWOOD-Corp. certifies this equipment

lowing are reproductions of labels on, or
Inside the product relating to laser product
safety.
conforms to DHHS Regulations No. 21
CFR 1040. 1 O, Chapter 1, Subchapter J.
DANGER: Laser radiation when open
and i Refer to parts list on page 85.
AVO
 CONTENTS
TRANSPORTATION SCREW.. . . . . . . . . . . . . . . . . . . . . . . . . . 2
DISASSEMBLY FOR REPAIR . . . . . . . . . . . . . . . . . . . . . . . . . 3
SYSTEM CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CONTROLS AND INDICATORS. . . . . . . . . . . . . . . . . . . . . . . 5
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Description of components.. . . . . . . . . . . . . . . . . . . . . 9
Set Mode Flowchart.. . . . . . . . . . . . . . . . . . . . . . . . . . .11
Test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
. Transistor array
Microprocessor
pPD7521 6ACW-051 (X32-1170-00: ICI 0). . . . . . . 17
RF amplifier
CXA1081 M (X29-1870-00: ICI) . . . . . . . . . . . . . . . . 20
Servo signal processor
CXAI 244s (X32-1170-00: I C I ) . . . . . . . . . . . . . . . . . 26
Digital signal processing LSI
CXDl l25QZ (X32-1170-00: IC6) . . . . . . . . . . . . . . . 30
Static RAM
CXK5816SP-12L (X32-1170-00: IC7) . . . . . . . . . . . 51
Reset IC
M51951ASL (X32-1170-00: ICI 1 ) . . . . . . . . . . . . . 52
Transportation screw
Before operation, remove the two red screws attached to
the bottom of the unit used during transport from the
factory. Remove both screws using a coin, etc. and, after
removing, retain them together with the Warranty card and
other documents. When the unit isso be transported again,
be sure replace the two screws to their original position:
DA Converter
PCM56P-K (X25-3050-00: ICI, IC2). . . . . . . . . . . . . 53
Digital filter
SM5804D (X25-3050-00: IC14). . . . . . . . . . . . . . . . . 5 4
D/A distortion correct
TC17G005AF-0048 (X25-3050-00: ICI 5) . . . . . . . 5 8
Hexa D Flip-flop
TC74HC174F (X25-3040-00: IC2). . . . . . . . . . . . . . .5 8
TD62003AP (X25-3040-00: IC3). . . . . . . . . . . . . . . . 59
2-channel analog switch IC
pPD4053BC (X32-1170-00: IC2) . . . . . . . . . . . . . . . .5 9
ADJUSTMENT/REGLAGE/ABGLElCH . . . . . . . . . . . . . . . . 6 0
PC BOARD (Component Side View) . . . . . . . . . . . . . . . . . . 67
PC BOARD (Foil Side View) . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SCHEMATIC DIAGRAM.. . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
EXPLODED VlEW (MECHANISM) . . . . . . . . . . . . . . . . . . . . 83
EXPLODED VlEW (UNIT).. . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4
PARTS LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5
SPEClFlCATlONS . . . . . . . . . . . . . . . . . . . . . . . . . . . Back cover
Before transport: tighten the transportation
screws
Before transporting this unit, be sure to tighten the two
transportation screws o r the bottom of the unit.
1. Turn ON the power switch when no disc is loaded.
2. Wait a few seconds until the disc OUT indicator cornes
"ON". Then turn "OFF" the power.
 DISASSEMBLY FOR REPAIR
Mechanism assernbly removal procedure
1. Rernove the screw (a) retaining the ground lug frorn
the rnechanism assernbly.
(0).
2. Rernove the three connectors
3. Rernove the four screws (O) retaining the mechanisrn
assernbly.

4. Rernove the rnechanism assernbly by pulling out in the

(0
direction of the arrow 1.
 SYSTEM CONNECTIONS
Connection precautions
Always turn OFF the power before making connections.
Incorrect connections can cause damage to your audio system. Heed the precautions and follow the directions
carefully.

To AC outlet

O DO not connect to other than the

DIGITAL IN jack. It could darnage the

Use these stereo output jacks for connection to a

typical amplifier or receiver. Note:
@ variable output (VARIABLE): outputvoltage
1. If your amp has both optical and coax digital inputs. use
O- 2Vrms variable only one or the other. Connection to both creates a loop
which can cause undesirable oscillation.
'Ou adjust.the Output level from jacks t0 2. Be careful never to kink, twist or bend the optical fiber cable
match the signal level of other sources connected to excessively.
your amplifier Or receiver. als0 be used 3. Thi's unit is not necessarily compatible with the optical fiber

DIGITAL OUT, COAXIAL) successful. consult your dealer or service representa-

Connection to amplifier or receiver

(The following three methods are possible.)

Conventional amplifier connection:

Connect the CD player's LlNE OUTPUT (FIXED or
P I U ~in the AC power cord for the CD piayer and
amplifier.
i
VARIABLE) to the AUX or CD input jacks on the rear
panel of the amp or receiver. Use the supplied cord.
Be sure to connect the left (L) and right (R) jacks on
the CD player to the corresponding jacks on the
amplifier or receiver.

Connection to an amplifier equipped with digital

input:
Use a single coaxial cable to connect the CD player's
DIGITAL OUT jack to the digital input jack on the
amplifier.

Connection to a component equipped with optical

fiber cable (OPTICAL INPUT) terminal:
Use an optical fiber cable to connect the CD player's
(DIGITAL OUT) OPTICAL terminal to the optical input
terminal on the other component.
 CONTROLS AND INDICATORS
O
- POWER switch
- (B Numeric keys (1 - 0)
Used to specify first digit in a number when
@ DIGITAL OUTPUT indicator selecting a tune or setting a time.
This illuminates when the digital output switch
IS on. (b Numeric keys ( + I O -
+50)
Adds ten to a number. Used with the numeric
@ DIGITAL OUTPUT switch keys.
This switches digital output on and off.
@ EDlT key
O PHONES jack Used to automatically fit tracks into a program
Plug stereo headphones into this jack. of a specified time length.
Q Dyna-pneumatic suspension SPACE key
Designed to safeguard sound quality by isolat-
This causes play to pause for about four
ing the player from adverse external vibrations.
seconds between tunes. useful when taping.
Note:
To rnaintain the effectiveness of the Dyna-pneurnatic
@ TlME DISPLAY key
suspension. do not place other cornponents or items This switches the time display.
weighing more than 5kg on top of this unit. @ CLEAR key
@ REMOTE SENSOR window This erases the last tracks in a program.
This picks up infrared signals from the remote @ DISPLAY
control.
Q) CHECK key
O OUTPUT LEVEL adjustment keys Press to check program contents.
These DOWN/UP keys simultaneously adjust
both the rear panel VARIABLE output signal @ TO key
level and headphone volume. When programming, this lets you input a
The output level setting is shown by the number of consecutive tunes starting at a
indicators on the right side of the display: particular track number.

8 OPEN/CLOSE key ( A )
Press once to open the disc tray. Press again
l
O
l
4D
1 1 1 1 1 1 1 1 1 1 1 @ A b 4 B repeat key
This key lets you define the beginning (A)
and end (B) points of a section of music
to close.
that you want played repeatedly.
@ INDEX keys ( a INDEX El )
Used to specify index numbers within Display window
tracks. @ REPEAT key
@ Disc indicator (DISC) @ SPACE indicator 1-)( Used for repeated play.
(b Manual search keys ( 44 , bb )
These keys let you move quickly forward Confirms that a disc is in the tray.
@ Emphasis indicator (EMPHASIS) @ Disc tray
or backward across the disc. @ Disc out indicator (m) This confirms that the disc in play
Q) Music skip keys ( 4 4 , bbl ) This illuminates (red) when there is was recorded with high frequency
Used to skip forward to the start of the no disc in the tray. emphasis.
next track or back to the start of the
current or preceding track.
0 A-B repeat indicator (mm) 0 Edit indicator (ml)

(D STOP key (W)

@ REPEAT indicator ((REPEATI) @ Program check indicator (m)
Lights up when you check program
Press to stop play. ' @ Time counter (TOTAL TIME, SIN-
r------- -r--1
t
contents.
GLE TIME)
@Play indicator ( b )

@ PLAY/PAUSE key ( D II )
8 Maximum track number indica-
tor (MAX TNo.) 88 BE
1 2 3
7 8 9
4
-
511LEEI
,o/!:g1
I
@ Index number (INDEX)/program
number (PNO.)
Shows the current index number
Press to begin play. Press during play to
pausr- or resume play.
Shows the highest track number
'7% ;Es
I
wxTm. 111
- '
12 13 14 1 5 ! 1 2 s
1
1 1 3 ~

I within the track. Shows the number

found on the current disc.
-3-gj3338 88 I'16 17 1 1
L -----T-
le 200'3
A l L r A
of tracks during programming or
@ Pause indicator ( Il ) Music calendar (1 - 20) I
I
I l l
when checking program contents.
(B PLAY MODE keys lndicates the track (selection) num- I I I I I 1 @ Track number display
Used to select the play mode: TRACK, bers on the disc. or shows which 00 0 8 @ O (TRACK NO.)
PROGRAM, TIME, or SINGLE. selections are programmed for play. Shows the track number (according
OUTPUT LEVEL indicator to the order of the selections on the
Six LEDs show the output level (of disc).
the signal from the VARIABLE jacks
on the rear panel.) This can be ad-
justed by remote control or output
level adjustment screw on the
roarnanol
BLOCK DIAGRAM
 CIRCUIT DESCRIPTION
Description of components
Display Unit (X25-3040-51)
Cornponent UselFunction Operation/Condition/Cornpatibility
ICI BX1408 1 Rernote control signal receiving Converts the infrared signal from the remote control into logic signal

IC2 TC74HC174F 1 D-type flip-flop 1 Controls larnps and LEDs for each mode
IC3 TD62003AP Transistor array 1 Transistor array drives larnps and LEDs for each mode

DAC Unit (X25-3050-00)

Cornponent UseIFunction Operation/Condition/Cornpatibility
ICI .2 PCM56P-K 1 D/A converter Resistance ladder type D/A converter; converts digital data into the volume of analog
( data.
IC3.4 NJM5532D-D ( 1-V converter 1 (1/2) Converts current output of D/A converter into voltage.
1 (2/2) Generates offset voltage for distortion compensation.
IC5-8 NJM5532D-D 1 Op amp 1 Consists GIC (general irnpedance converter) in LPF
IC9.10 NJM5532D-D Op amp Buffer amp and output arnp
IC13 M5220P OP amp Error arnp for f15 V constant power supply
ICI4 SM5804D Digital filter 4 times oversampling digital filter
ICI 5 TC1 7Q005AF- D/A distortion compensator D/A distortion compensation. 2SB detection circuit
0048
ICI 6 M5F79M06L 3-pin regulator -6 V (-VCC) power supply for D/A converter circuit
ICI 7 M5F78M06L 3-pin regulator +6 V (+VCC) power supply for D/A converter circuit
IC22 M5F79M05L 3-pin regulator -5 V (-VL) power supply for D/A converter circuit
IC23 M5F78M05L 3-pin regulator +5 V (+VL) power supply for D/A converter circuit
IC24 M51951ASL Reset lC . Reset IC for digital filter
02 2SD1266(P) Ripple filter Ripple filter for +15 V constant power supplv
Q3 2SB941 (P) Ripple filter Ripple filter for -1 5 V constant power supply
0 1O DTC114YFF Switch Relay driver for deemphasis
QI1 DTC114YFF Switch Relay driver for muting
Q12 DTC143EFF Switch Muting photocoupler driver
Q13 DTC143EFF Switch Photocoupler driver for deernphasis
QI4 2SA733(A) Transistor For power supply of photocoupler output
(OS)
D l7 E-102 Constant current diode ( Constant current diode for +-15 V constant power supply

Control Circuit Unit (X29-1870-00)

Cornponent Use/Function Operation/Condition/Cornpatibility
ICI CXA1081 M RFarnp Focus error signal generation. tracking error signal generation. RF signal generation and
phase compensation. and auto symrnetry compensation circuit
IC2 TC74HCOOP NAND gate EFMT signal waveform detection. auto syrnmetry signal detection
01 2SC2878 Switch Focus error amp bias select switch
 CIRCUIT DESCRIPTION
CD Player Unit (X32-1170-00)
Cornponent UseIFunction OperationlConditionICompatibility
ICI CXA1244S Servo lC Various pulse generation for focus servo. tracking servo. and feed servo.
(CX20108 shrink type)
IC2 pPD4053BC Analog switch Receives scratch detection signal (DFCT signal frorn pin 21 of CXA1081 M) and turns
focus and tracking servo OFF when scratches are present.
IC3 M5218P-K Op amp (1/2) For focus servo phase compensation
(2/2) For trackina servo hase corn~ensation
IC4 NJM4558D Op arnp (1/2) For VARIABLE volume motor drive
(2/2) For tray rnotor drive
IC5 M5218P-K Op amp (1/2) PLL compensation circuit (LPF+amp)
(2/2) CLV corn~ensationcircuit (LPF+level shifter)
IC6 CXD1125QZ Digital signal processing LSI Executes al1 digital signal processing including EFM data decoding, error correction,
interpolation. PLL circuit. CLV servo and digital out, etc.
1C7 CXK5816SP Static RAM Signal processing RAM (16K)
IC9 TC74HC08P AND gate Buffer arnp for digital out. and reset signal generator when power is ON/OFF
ICI O pPD75216 Microprocessor Display, each key input processing and servo IC control.
ACW-05 1
ICI 1 M51951ASL Reset lC Generates reset signal when power is ON/OFF
ICI 2 LB1344N Linear scale level rneter IC Outputs VARIABLE volume position indication
IC13- 17 LB1294 FL driver IC IC for drivina FL disolav
ICI 8 M5F78M05L 3-pin regulator +5 V power supply for digital and servo circuits
ICI 9 M5218L OP arnp Headphone amp
IC20 NJM558D Op amp (1/2) Rising and trailing control for +5 V and - 5 V power supply
(2/2) S u o ~ l i e s+5 V for ALPC. and controls laser ON/OFF
QI 2SC2878 1 Switch 1 Focus gain select
O2 2SC3940A Driver Focus actuator driver
Q3 2SA1534A Driver Focus actuator driver
Q4 2SC3940A Driver Trackina actuator driver
05 2SA1534A 1 Driver 1 Tracking actuator driver
Q6 2SC3940A Driver Feed motor driver
Q7 2SA1534A Driver Feed motor driver
O8 2SC3940A Driver Trav motor driver
1 09 2SA1534A 1 Driver 1 Tray rnotor driver
QI0 2SC3940A Driver Disc motor driver
QI 1 2SA1534A Driver Disc motor driver
Q12 2SD1266 Driver VARIABLE volume rnotor driver
1 QI3 2SB772 1 Driver 1 VARIABLE volume rnotor driver 1
Q I4 2SC1685 1 Ripple filter 1 Power supply for FL driver (+6.6 V)
O1 5 2SC945(A) 1 Switch 1 FL driver switch
(0.P)
QI6 2SA733(A) Level shifter Level shifter for FL driver
i0.P)
0 17 2SC3940A Ripple filter Power supply for larnps and LEDs foreach mode (+7.5 V)
018 2SA954 Ripple filter Power supply for FL reference voltage (-32 V)
O1 9 2SA1127NC Ripple filter -5 V power supply
Q20 2SC3940A R i ~ ~filter
le +5 V ~ o w e sr u ~ ~(for
l vALPC)
Q21.22 2SC3940A Driver Headphone amp driver
023.24 2SA1534A Driver Headphone amp driver
Q25 DTAl24EN Digital transistor switch Controls focus offset voltage by the MUTE signal
Q26 DTAl24EN Digital transistor switch Selects focus gain by the FGSW signal
 CIRCUIT DESCRIPTION
Set Mode Flowchart
(Simplified flowchart
after power ON) Q POWER O N

r - i500ms Wait

Dise Motor
rotation start

u Tray close

Returns pickup
to inside

Laser ON u Tracking ON

ldDunl
or more

a
Focus Lens

u
Feed Motor

350ms Wait

9 Focus Lens
a
IF 15 sec
failure
TOC read-out

1
1
Searches start
of 1 st track
and starts play

signal "H"
Disc Motor
brake
SENSE signal
chattering

ii
rernoval. 500 us
"DISC OUT"
indicated Disc Motor
I I
A

. If 1.2 sec
failure
 CIRCUIT DESCRIPTION
Test mode
I f the TEST pins are short-circuited when the power is
turned ON, the microprocessor enters test mode. With the
microprocessor set t o test mode, each operation can be
easily checked after making a repaire or adjustment.
With the DP-1 100SG. the microprocessor can be set to
test mode by short-circuiting pin 6 and pin 7 of the CD
PLAYER UNIT (X32-1170-00).
Note': "Set mode" shows the normal status.
c, ,
the TEST pin
short-
circuited?

"01" is
dirplayed.
,,
OPENICLOSE

1 - 1
key.

Effective keys in the Test mode and their functions 6Set mode

No. Input k.y Function Track No. display

(1) Focus servo . . . . . . . . . . . . . . ON. TRACK NO.

(2) Tracking servo . . . . . . . . . . . . . ON. 1-1

(3) Feedsewo. . . . . . . . . . . . . . . ON. I I , 1
1 PLAY When the key is pressed i n the Stop mode. the servoes are switched 1
ON automatically in the order from (1 ) t o (3). Displayed for a few seconds after ( 1) t o (3).

1
Disc's Track No. is displayed.
(1) Focus s e ~ o. ............. ON. TRACK NO.

2 CHECK (2) Tracking servo ............ OFF. 1-1 J'

(3) Feedsewo. .............. OFF. I I , 1
(1) FOCUS
servo .............. ON. TRACK NO.

3 CLEAR (2) Tracking servo . . . . . . . . . . . . ON. 1-1 I I

(3) Feed servo. . . . . . . . . . . . . . . OFF. L I 1
(1) FocusSewo .............. OFF. TRACK NO.

4 STOP (2) Tracking servo ............ OFF. 1-1 1

(3) Feed servo . . . . . . . . . . . . . . . OFF. I l 1
(1) Tray open
TRACK NO
(2) Laser.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ON.
1-1
r-1
5 REPEAT
When the tray is closed by pressing it. +10 function will be released.
The TRACK NO. display shows "01 ".
I I
I n Stop mode : Moves the PU slightly t o the outer tracks.
6 bb
With feed servo ON : Switches the tracking gain t o "H".
I n Stop mode : Moves the PU slightly t o the inner tracks.
7 44
With feed servo ON : Switches the tracking gain t o "L".
Jumps the number of tracks as follows:

Key 1 1 2 1 3 1 4 1 5
Numeric (digit) Number of tracks 1 1 4 1
16 1
3 2 11000
8 Direction Outward
keys (0-9)
Key 6 1 7 1 8 1 9 1 0
Number of tracks 1 1 4 1 16 132 11000
Direction lnward

When the tray is opened and the closed again in test mode, TRACK
12 9 OPEN/CLOSE NOS. 2, 17. 2. 6. 7. 8. 10. 13 and 22 are automatically programrned
Opening the tray again will cause the unit to enter set mode.
 CIRCUIT DESCRIPTION
Flow chart of test mode
Flow chart from tray OPEN status sfter power ON

7 Power O N

Tray
CLOSE
i
1

5 sec.
elapsed?

FI Cancellation

data store

utward
feed of PU

01 displayed
e
?l]
S L T : "Lu?

Outward feed
YES
Cancellation
5 sec.
elapsed?

YES

9
in T N O of tray

9 SLT : "H"?
S L T : "H"?

CLOSE key
pressed?

1 YES l
S L T : Pickup start lirnit switch
CLS : Tray clore detect switch
OPEN : Tray open detect switch

Acceptance of key
 CIRCUIT DESCRIPTION
Focus warch & focus servo ON

1 .Osec

h Focus UP

SENSE :

Focus
servo ON

4 I

Disc motor
ON
& b

C
 CIRCUIT DESCRIPTION
Tracking sewo ON Disc rnotor stop

I Trac k ing servo

ON 1 NO

4 0-j) FOK terminal 1 v 2

Disc motor
Disc motor
brake 4OP
>
l

YES
("SENSE")
3 sec.
elapsed?

2 sec.

Q 200rns WAlT
1 YES
Disc motor

OFocus search
Ga
 CIRCUIT DESCRIPTION
a From loading of Q data to display Flow chart from the time the tray opens until the STOP
indicator lights, after pressing the tray.

< START

m4
START

t
Tray
CLOSE

NO

Y ES -1

Loading of al1 of @
96 bit data

Focus servo O N
after focus search

. i
Tracking
,
A
servo ON
NO b

4
Feed servo
ON

4
I TOC load
I
4
STOP display
NO
1

1 Stop of PU 1 I a Disc stop

Microprocessor pPD75216ACW-051 (X32-1170-00 : I C I 0)
Terminal connection diagram

(Top View)

Pd VDD (+5v)
Pc Pe
Pb Pf
Pa pg
SENSE Ph
WFCK pl
SUBQ pi
CRCF GND
FiCI GND
SCOR Pk
FOK PI
GFS G14
RMUTE G13
EMPH G12
DlRC G11
MUTG G10
FGSW G9
SLTSW G8
OPNSW G7
CLSSW G6
K1 G5
K2 G4
K3 G3
K4 G2
DATA G1
XL T RESET
CLK VRUP
LDC VRWWN
XRST CLSM
(4.23MHz) X I OPNM
X2 NC
GND NC
 CIRCUIT DESCRIPTION
Pin Function Table
Pin No. I/O 1 Pin Name 1 Functions
O 1 Pd- Pa 1 FL display segment indication and key scan signal output
I 1 SENSE 1 Sensing signal input (from CXDl125QZ. CXA1244S)
I WFCK O data read-off clock input (from CXD112502)
l SUBO Q data input (from CXDl125QZ)
I CRCF O data CRC OK rH")input (from CXD1125QZ)
I RCI Remote control signal input
I SCOR Q data sync signal input (from CXDl125QZ)
I FOK Focus OK ("Ha')input (from CXA1081 M)
I GFS 1 EFM sync OK ("Ha')input (from CXD1125QZ)
O 1 RMUTE 1 Relay mute ON/OFF ("L"/..H")
O EMPH Emphasis ON/OFF ("H"/"L")
O DlRC DlRC signal output (to CXAl244S)
O MUTG MUTG signal output: Mute ON/OFF ("Hm/"L) (to CXD1125Q.Z)
O FGSW Focus gain switch signal output
I SLT SW Start limit switch signal input (SW ON = "L")
I OPN SW Tray open switch signal input (SW ON = "L")
1 CLS SW Tray close switch signal input (SW ON = "L")
I K1

l* Key input for frontpanel

O DATA Control data signal output (to CXD1125QZ. CXA1244S)

O X LT Control data latch signal output (toCXDl12502. CXAl244S)
O CLK Control data clock signal output (to CXD112502. CXA1244S)
O LDC Laser ON/OFF ("H"/"L") signal output
O XRST Control reset signal output (to CXD1125O.Z. CXAl244S)
I X1 Clock input pin (1/2 clock of CXD1125QZ)
O X2 (Oscillating frequency 4.2336 MHz)
- Vss GND (ground)
Tray open/close signal output
O OPNM
Normal (OPNM = "Y, CLSM = " L )
Open (OPNM = "H". CLSM = "L")
O CLSM Close (OPNM = "Y, CLSM = "HM)

O 1 VRDOWN 1 Motor volume level down signal output

O 1 VRUP
-
1 Motor volume level up signal output
RESET I RESET Reset signal input
O G1 - G14 FLdisplay digit indication output
O PI FL display segment indication output
O Pk (Pt is also used for key scan)
I VLOAO GND (ground)
I VPRE GND (ground)
O Pj- Pe FLdisplay segment indication and key scan signal output
I VDO +5 V power supply
 CIRCUIT DESCRIPTION
RF amplifier CXAl081 M (X29-1870-00 : I C I )
The CXA1081 M supplies the following functions as
required for controlling the RF'amp in the compact disc
player.
RFamp
Focusing error amp
Tracking error amp
APC circuit
Auto asymmetry control amp
Focus OK detection circuit
Mirror detection circuit
Defect detection circuit
EFM comparator

Block diagram
VI
L 5
-
14
O
O a w m Y
U
Z E z
W VI
O
O
m
U
a
U
0
4;i w
l-
Y
LL
W
2'
U
U

-
LL
K
O
LL
a
O
LL
K
.
Z
O
D
J
O
O
-
O
O
N
O
U
>
W O
Y
-
W
K
>
N
V
U
 CIRCUIT DESCRIPTION
Explanation of terminals
Terminal No. Terminal name 110 Function
1 RF1 I Input pin of the Ccoupled signal output from the RF summing amp.
2 RF0 O Check point of eye pattern for the RF sumrning amp output pin.
3 RF I RF summing amp feedback input pin.
4 PIN I P-subIL-subselect pin of LD. (DC voltage: in N-sub mode)
5 LD O APC L D amp output pin. (DC voltage: PD open in Nsub mode)
6 PD I APC PD amp input pin. (DC voltage: open)
7 PD1 I RF 1-V amp (1) invert input pin. Current input by connecting t o PIN diode A + C.
8 PD2 I RF 1-V amp (2) invert input pin. Current input by connecting to PIN diode B + D.

- Connected t o GND when using a positive ( + )lnegative (-) dual-voltage power supply.
9 VC
Connected t o VR (pin 14) when using a single-voltage power supply.
1O F I . F 1-V arnp invert input pin. Current input by connecting t o PIN diode F.
11 E 1 E 1-V amp invert input pin. Current input by connecting to PIN diode E.
12 €0 O E 1-V amp output pin.
13 El I E 1-V arnp feedback input pin. For E 1-V amp gain adjustment.
14 VR O DC voltage output pin of (Vcc + V E E ) / ~ .
15 CC2 I Input pin of the Ccoupled signal output from the defect bottom hold.
16 CC 1 O Defectbottom hold output pin.

- Connected to the negative power supply when using a positive ( + Ilnegative (-) dual-voltage power
17 VEE
supply. Connected t o GND when using a single-voltage power supply.
18 FE BlAS I Bias pin at the focus error amp non-invert side. For CMR adjustment of the focus error amp.
19 FE O Focus error amp output pin.
20 TE O Tracking error arnp output pin.
21 DEFECT O Defect comparator output pin. (DC voltage: connected to a 1 0 k n load).
22 MlRR O Mirror comparator output pin. (DC voltage: connected to a l O k n load).
23 CP I Mirror hold capacitor output pin. Mirror comparator non-invert input.
24 CB I Defect bottom hold capacitor connect pin.

- Connected t o GND when using a positive ( + Ilnegative (-) dual-voltage power supply. Connected to
25 DGND
GND (VEE) when using a single-voltage power supply.
26 ASY I Auto asymmetry control input pin:
27 EFM O EFM comparator output pin. (DC voltage: connected t o a l O k n load).
28 FOK O FOK comparator output pin. (DC voltage: connected to a 1 0 k n load).
-
29 L D ON I L D ONIOFF select pin. (DC voltage: when L D ON).

I 30 Vcc 1 - 1 Positive power supply. 1

 CIRCUIT DESCRIPTION
Explanation of function The low frequency component of the RF0 output
RFamp voltage, VRFO is represented by the following equation:
The photodiode current input to the input pins (PD1,
= 2.2 x (VA+ VB)
VRFO
PD2) is converted to a voltage by an equivalent resistance
of 58kS2 in RF 1-V amp (1) and (2) respectively. The = 127.6k C2 x (ipni +ipnz)

voltage which is converted from the current of the photo-

diode (A + B + C + D) is added in the RF summing amp and
is output from the R F 0 pin. The eye pattern can be check-
ed at this pin.

VCC

! l!l k I-V AMP (. 1. ). 1 LI

, 5aK
Y1 R F SUMMING AMP

10K
1b
IP02 I VB

RF I - V amplifier

Focus error amp

The difference between the R F 1-V amp (1) output
(VA) and the RF 1-V amp (2) output (VB) is calculated,
and the current of the photodiode (A + C - B - D) is
converted to a voltage and output.
The FE output voltage (low frequency) is represented by
the following equation:

-IB+D) FE
-(A+C)
VA FOCUS
ERROR
C 2 25P- 164 K AMP
 CIRCUIT DESCRIPTION
Tracking error amp The difference between the E 1-V amp and the F 1-V
The current from the side spot photodiodes is input to amp is calculated by the tracking error amp, and the photo.
pins E and F and is converted to a voltage by the E 1-V diode (E-F) current is converted to a voltage and output.
arnp and F 1-V arnp respectively. That is:
VTE= (VE- VF) X 3.2
V~=iFX403kQ
= (iE-iF) X 1290k Q
V ~ = i E x 2 6 0 k!2 X +
R A / ( R B + ~ ~(RA
~ )+260k)

Focus OK circuit
The focus OK circuit creates a timing window, turning
the focusing servo ON with the focus search status.
While the RF signal is present at pin 2, its HPF output
is present at pin 1. At the same time, the LPF output
C34 is used to determine the time constants of the EFM
comparator, the HPF in the mirror circuit, and the LPF
in the focus OK amp. Normally, C34 = O.01pF is selected,
with fc = 1kHz. This will prevent degradation of the block
error rate due to an RF envelope lack caused by cracks, etc.

~~~~~~~
(opposite phase) of the focus OK amp is obtained. on the disc.
The focus OK output is inverted when VRFI -VRFO
= -0.37V.

1 From summing amplifier.

'% 15 K QK FOK

0.625V

1 FOCUS OK AMP FOCUS OK 1

I CCUPARATOR 1
L,,----,---,,,----,,,J
 CIRCUIT DESCRIPTION
Mirror circuit
In the mirror circuit, after the RF1 signal is amplified,
both peak and bottom holds are held by a time constant
which can follow a traverse of 30kHz. while only the
bottom hold is held by a time constant which can follow a
cyclic period envelope variation respectively.
These peak/bottom hold signals, H and I are differ-
entially amplified to obtain the DC-reproduced envelope
signal J.
This signal is compared with signal K, that the 2/3 level
of the peak value is peak held by a large time constant so H
that the mirror output is obtained. That is, the mirror (PEAK HOLD) n / v \ o v
output goes "L" on the disc tracks and goes "H" between

Oo
tracks (mirror section). In addition, the output goes "H"
I
when -a defect is detected. The time constant of the mirror (BOTTOM
hold should be quite larger when compared with the HOLD)
traverse signal.

I
I
I 0.033~

I
I
MIRROR AMP
I
I

i
- - - - - - - - - -h - Ji
MlRRoR
I
b
CowARAToR DGNo
 CIRCUIT DESCRIPTION
EFM comparator
The EFM comparator converts the RF signal into a
binary coded signal. Since asymmetry caused by disper-
sion when manufacturing the discs cannot be reduced by
AC coupling only, the reference voltage of the EFM com-
parator is controlled using the characteristics that the
present probability of a 1 or O is 50% each for the binary
coded EFM signal.
The EFM comparator is designed as a current switching
type, and the "H" and "L" levels are not equal to the
power voltages. Therefore, feedback is required via a
CMOS buffer.
R9. RIO, C3 and C8 constitute a LPF to obtain the DC
cornponent of (Vcc+DGND)/2 (VI. If the cut-off frequency
(fc) is set to more than 500Hz. leakage of the EFM low fre-
quency signals will be greatly increased and will result in
a degradation of the block error rate.

AUTO ASYMMETRY

RF1
I
L-------- ,,,- --------
EFM COMMRATOR
-----A
1

Defect circuit
After inverting the RF1 signal, the defect circuit bottom
a
holds with the two long/short time constants. The bottom
hold with a shorter time constant responds to a mirror
defect of more than 0.1 msec on the disc, and the bottom b
hold with a longer time constant holds the mirror level
obtained immediately before the defective section. These
signals are C-coupled, then differentiated with level shift-
BOTTOM
ing. The signals are compared with each other to generates Broken line CC2
the rnirror defect detecting signals. Continuous
n n H
line CC1
e 2- -LL
1 Amsec M A X

EFECT BOTTOM
DEFECT AMP
 CIRCUIT DESCRIPTION
Servo signal processor CXAl244S
(X32-1170-00 : I C I )
CXA1244S is a bipolar IC developed for servo of com-
pact disc (CD) players, and it provides the following func-
-
Terminal connection diagram

29 TG 1
tions. TAO
OTracking control (servo ONIOFF, single track jump, TAO
multiple track jump, gain control, phase compensation SENSE DlRC
V) SL@
control, brake circuit)
0 Sled control (servo ONIOFF, fast forward, fast
XRST 3N SLO
DATA S LO
reverse)
sX 21
FE@
F EO
CLK 10 O
MlRR 11 20 FE
TZC 12 19 ATSC
TE 13 18 FS3
ISET 14 17 VEE
VCC 15 16 SRCH

Block diagram

TG2 TA@ TE0 TE@ SENSE C.OUT XRST DATA XLT CKL MlRR TZC TE ISET VCC
 CIRCUIT DESCRIPTION

Terminal No. Terminal name If0 Functiom

1 TG2 Tracking amplifier gain switching terminal. GND level.
7 TA a Non-inverted inout of ooerational amolifier 2.
3 TE0 . Output of operational amplifier 4.
4 TE lnverted input of operational amplifier 4.
5 SENSE O Output o f SSP interna1 status that corresponds t o ADDRESS of CPU -+ SSP.
- (Changes i n accordance with ADDRESS content of internal serial register.) See Note 1 .
6 C. OUT O Signal output for counting number of tracks at the time of high speed access.
7 X RST I All interna1 registers are cleared when CPU + SSP "L".
Connected with CPU RESET. See Note 2.
8 DATA I Serial data transmission of CPU -t SSP. Input is made from LSB. DO-D7.
9 XLT I Latch o f serial data of CPU + SSP. (The contents of interna1 serial register are transmitted t o each
address decoded latch.) Transmission at "L". Change t o "H" occurs immediately after execution
because no edge trigger is produced.
1O CLK I CPU -t SSP serial data transmission block. Data is read at falling.
"H" level before and after transmission.
11 MlRR I Mirror signal input from RF amplifier.
12 TZC I Tracking error signal is input with C couple. The time constant is determined by one single track
jump, but it is usually around 2kHz.
13 TE I Tracking error signal input.
14 ISET Setting o f current level for determining focus search voltage,
tracking jump voltage and thread feed voltage.
15 Vcc / Power supply terminal. Normally +5V.
16 1 SRCH 1 The condenser for determining the time constant of chargeldischarge waveform for focus search
- is connected.
17 VEE Power supply terminal. Normally -5V.
18 FS3 Focus amplifier gain switching terminal. GND level.
19 ATSC Such information that a mechanical shock was applied t o the player is input. Simply, a trakcing
error is input through BPF. I n this equipment it is connected t o GND level and is not used.
20 FE I Input of focus error signal.
21 FE0 O Output of operational amplifier 1.
22 FE O I lnverted input of operational amplifier 1.
23 S LO O Output of operational output 3.
24 SL I lnverted input of operational amplifier 3.
25 SL @ I Non-inverted input of operational amplifier 3.
26 D l RC I Used at the time of one track jump. Normally "H". The direction of the track jump pulse is
reversed with "L". Setting is made in the normal tracking mode by changing t o "H".
"L" for a fixed length of time with detection of activation, deactivation of TZC.
27 TAO O Output of operational amplifier 2.
28 TA O O lnverted input of operational amplifier 2.
29 TG 1 Tracking amplifier gain switching terminal. GND level.

1 30 GND 1 1 GND terminal of IC. 1

Note 1 : SENSE terminal output
Note 2 : Digital unit timing chart
Explanatien

I 1 "H" when focus zero

cross. Focus erro volL
Tage is O\/ or higher.
I l
FOCUS PULL opera-
tion.
Data is loaded at activation
"H" when the ATSC

k
input level exceeds the
wind camparatbr level CLK
CONTROL IVTH = 'Vcc x 13%).
1 1 1 1 But fhis is no1 used in 1
fhis equipmenl.
t w c k w twck
1 1 Judoement output of
positive or negative ol w
1Ifck
tracking zero cross.
tracking error.
When used at the timr
TRACKING
TZC of ringle track lump.
MODE
DlRC ir reduced 10
"Ln on defection of , 1 ,

Execution of instruction
TZC t . in FWD JUMF
or on derection of +
1
tWL
1 27
TZC 1 in R E V JUMP
 CIRCUIT DESCRIPTION
Systern control

*
ADDRESS DATA
COMMAND SENSE
D7 D6 D5 D4 D3 D2 Dl DO
FS4 FS3 . FS2 FS1
FOCUSCONTROL O O O O FOCUS GAlN SEARCH SEARCH FZC
ON DOWN ON UP
ANTl BREAK TG2 TG1 *
TRACKINGCONTROL O O O 1 AS
SHOCK ON GAIN SET
TRACKING* SLED*
TRACKINGMODE O O 1 O TZC
MODE MODE

GAlN SET* TG1, TG2 may be set independently.

In the case of ANTl SHOCK = 1 (0001I X X X ) , both T G l , TG2
are inverted when ANTl SCHOCK = "Hu.

TRACKING MODE * SLED MODE *

ID~/DO(
1 1 ;1 ;1
1

OFF
SERVO ON SERVOON
FWD JUMP FWD MOVE
REV JUMP

Note : The antishock circuit is not used in

this equipment.
 CIRCUIT DESCRIPTION
Serial data truth value table Hexa-
Serial data Function

FOCUS CONTROL FS = 4321

00000000 SOO O000
00000001 SO 1 O001
0000001O S02 O01O
O0000011 S03 O01 1
O00001O0 S04 O100
O0000 1O 1 S05 O101
O00001 1O S06 O1 10
O00001 11 S07 O1 11
O0001O00 S08 1O00
O0001O0 1 S09 1001
00001O1O SOA 1010
O0001O1 1 SO B 1011
000011O0 SOC 1100
O0001 1O1 SOD 1101
O0001 110 SOE 1110
O0001 111 SO F 1111

D2 AS=O AS = 1 AS : ANTI SHOCK

TRACKING
CONTROL (Brake) TG=2 1 TG=2 1
O001O000 S1O O OO OO
O001O001 SI 1 O O 1 01
O001O010 512 O 1O 1O
O0010011 S13 O 11 11
O001O100 SI 4 1 O0 O0
O001O1O1 SI 5 1 O 1 O1
000101 10 SI 6 1 1O 1O
O001O1 11 SI 7 1 11 11
O001 1O00 S18 O OO 11
O001 1O01 SI9 O O 1 1O
00011010 SI A O 1O 01
00011011 SI B O 11 0O
O001 11O0 SIC 1 OO 11
O001 1101 SI D 1 O 1 1O
00011110 S1 E 1 1O O1
00011111 S1 F 1 11 OO

- -

TRACKING
MODE

000010 O01010 00001 1

O1@O00 01 1O00 100001
100000 101O00 100001
000001 O001O0 00001 1
O0001 1 O0011 O 00001 1
010001 010100 1O0001
100001 1O01O0 100001
O00 1O0 O01O00 00000 1
O001 1O O01O1O 00001 1
010100 O1 1O00 100001
100100 101000 1O000 1
O01000 000100 O000 11
001010 O001 10 00001 1
O1 1O00 O1O1O0 100001
1O1O00 100100 100001
DC : DlRC input terrnin
 CIRCUIT DESCRIPTION
Digital signal processing LSI CXD1125QZ Interpolation with average value or by holding the pre-
(X32-1170-00 : IC6) vious value.
Demodulaiton of sub code signal or error detection of
The CXDl125QZ is the digital signal processing LSI for
sub code O.
the compact disc player, and has the following functions.
Spindle motor CLV servo.
All the digital signals for reproduction can be processed in-
8-bit tracking counter.
ternally with this one-chip design.
CPU interface with a serial bus.
Bit clock reproduction by an EFM-PLL circuit.
Sub code O register.
EFM data demodulation.
DIA interface output.
Frame sync signal detection, protection and insertion.
Powerful error detection and correction.

Block diagram L Y VI
U O
C, Y V mI
W
VI

1
subcoae
Sync Detector
1 1 ~ubcode
Demodulotor
~ u b c o r ~O
Regis ter
e

VOO
GFS
VOD
LOC K
TEST
FSW
XRST
M DP
MUTG
MDS
MD1
MON
MD2
VCOO MD3
PSSL
SLOB
vss
VSS

XTAO

X'TAL circuit
XTA l
timing generoior

I
w
!
(:xo:::z3
Digit01 Filter

WDCK
LRCK

CNlN DOTX
 CIRCUIT DESCRIPTION
Explanation of terminais
Terminal No. Terminal name I/O Function
1 FSW O Time constant switching output of output filter of spindle motor.
2 MON O ONIOFF control output of spindle motor.
3 M DP O Drive output of spindle motor. Rough speed control in CLV-S mode and phase control in CLV-P mode.
4 M DS O Drive output of spindle motor. Speed control in CLV-P mode.
5 EFM I EFM signal input from RF amplifier.
6 AS Y O Output for controlling the slice level of EFM signal.
Samples the GFS signal with WFCKI16, and outputs "H" when the level is high.
7 LOCK O When it is "L" for eight times, in arow, outputs "L".
8 VCOO O VCO output. f = 8.6436MHz when locked t o EFM signal.
9 VCOl I VCO input.
1O TEST l (OV)
11 PD0 O Phase cornparison output of EFM signal and VC012.
12 Vss - GND (OV)
13 CLK I Serial data transmission clock input from CPU. Data is latched at rising edge of a dock.
14 X LT I Latch input from CPU. Data (serial data from CPU) from the 8 bit shift register is latched in each

15 DATA I Serial data input from CPU.

16 XRST I System reset input. Reset at "L".

- 17 CNlN I Input of tracking pulse.

18 SENSE O Output of interna1 status i n correspondence t o the address.
19 MUTG I Muting input. I n the case where ATTM of interna1 register A is "L".
normal status when MUTG is "L" or soundless state when i t is "H".
20 CRCF O Output of result of CRC check of sub code O.
21 EXCK I Clock input for sub code serial output.
22 SBSO O Sub code O read-off clock.
23 SUBQ O Sub code Q output.
24 SCOR O Sub code sync SO + S I output.
25 WFCK O Write Frame Clock output. f = 7.35kHz when the frame sync is locked.
28 CFS O Output of display of lock status of frame sync.
 CIRCUIT DESCRIPTION

-
Notes: PLCK : VC0/2 output. f = 4.3218MHz when locked t o the EFM
ClFI
C l F2
:}Error correction status rnaiitor output for C l decode.
signal.
UGFS : Non-protected frarne sync pattern output.
GTOP : Frarne sync protect status display output.
C2F1
C2F2
i
} ~ r r o rcorrection status rnonitor output for C2 decode. RAOV : 14 frarne jitter absorption R A M overflow and underflow
C2PO : C2 pointer signal. display output.
C2F L : Correction status output. Goes "H" when the currently C4LR : Strobe signal. 176.4kHz.
-
corrected C2 series data cannot be corrected. C210 : C210 invert output.
RFCK : Read frarne clock output. 7.35MHz when locked t o the C210 : Bit clock output. 2.1 168MHz.
crystal line. D A T A : Audio signal serial data output.
WFCK : Write frarne clock output. 7.35MHz when locked t o the
crystal line.
 CIRCUIT DESCRIPTION
Explanation of functions
CPU interface
1) Data input
Each register may be set by input of 4 bit address, and
4 bit data from LSB in the timing that is shown in Fig. 6-2
k- Data
DATA
terminal
CLK
terminal
X LT
terminal
Registers
A-E
Timing chart for data input
2) Registers
0 Register 9 - New function control
Controls the new functions added to the CX23035.
0 3 : ZCMT Switches the zero cross mute function ON/
OFF. Detai ls are described in "lnterpola-
tion and Mute, Attenuate".
D2 : HZPD One of the defect countermeasures. Switches
ONIOFF the function which rnakes the PD0
pin a high impedance (Z) for a maximum of
0.55ms from the rising edge of GFS. Details
are described in "Countermeasures to de-
fects".
D l : NCLV Switches between the old CLV-P servo and
the new CLV-P servo by comparison with
newly added base counter. Details are de-
scribed in "CLV servo control".
DO : CRCQ Switches ON/OFF the function which out-
p u t ~the CRCF data to the SUBQ pin from
the rising edge of SCOR to the trailing
edge of SQCK. Details are described in
"5) Subcode output".
0 Register A - Sync. protection, attenuator control
1
D3 : GSEM Provided for switching framesynk. protection
D2 : GSEL characteristics in correspondence t o the time
D l : WSEL of playback and time of access. Details
DO : ATTM will be described in the paragraph of "EFM
demodulation".
DO : ATTM Used for attenuating audio signals by 12dB,
and the details will be described in the para-
graph of "DIA interface".
ORegisters B and C - Counter set, more significant 4
bits (register C) and less significant 4 bits (register B)
these registers are used for setting the tracking count
value. the data of registers B and C are preset in the counter
through the 4 bit buffer register assigned by address.
to three terminals, XLT, CLK and DATA. The address
and data of each terminal are as shown in Table 6-2, and
their functions are as follows. The contents of each register
become entirely O when XRST = "L".
Address -CI
Valid
Accordingly, when data of either register B or C is input,
the contents of both registers are preset in the counter
simultaneously as 8 bit data (either buffer register is of
"OLD" data.)
D3 : DIV The dividing ratio of RFCK and WFCK in
CLV-P mode is fixed, and the phase is com-
pared with RFCKl4 or WFCK/4 respectively,
regardless of the status of D3, then output
from the MDP pin.
0 Register D-CLV control
D3 : DIV Used for setting the frequency dividing ratio
of RFCK, WFCK in the CLV-P mode. When
D3 = O,, phase comparison of RFCK/4 and
WFCKl4 is made, and when 0 3 = 1, phase
comparison of RFCK/8 and WFCK/8 is
made, and output is made out of MDP ter-
minal in each case.
D2 : TB Used for determining the period of bottom
hold in the CLV-S and CLV-H modes.
Bottom hold is made in the period of RFCK
132 when D2 = O or in the period of RFCK/
16 when D2 = 1.
D l : Tp Used for setting the period of peak hold in
the CLV-S mode. Peak hold is made in the
period of RFCK/4 when D l = O or in the
period of RFCK/2 when D l = 1.
DO : GAIN Used for setting the gain of MDP terminal
output in the CLV-S and CLV-H modes.
It is -12dB (time of 314 out of the period of
RFCK/2 is of high impedance) when DO = O
or is OdB when DO = 1.
 CIRCUIT DESCRIPTION
0 Register E-CLV mode
It is as shown in Table 6-2.
The details of each mode will be described in the paragraph
o f C L V servo control.

Register Addl~g Data SENSE

Command
name D7-D4 D3 D2 D l DO terminal
9"' New function control 100 1 ZCMT HZPD NCLV CRCQ Z
A
2i Sync protection,attenuator control 1 O 1 O GSEM GSEL WSEL A T T M Z
B Counter set, Less significant 4 bits 1 O1 1 Tc3 Tc2 Tc1 Tc0 COMPLETE
C Counter set, More significant 4 bits 1 1 OO Tc7 Tc6 Tc5 Tc4 COUNT
DI3 CLV control 1101 DIV TB Tp GAIN Z
E*4 C L V mode 1110 CLV mode Pw 1 6 4 ,
+ l Register 9

Dn=O Dn= 1
ZCMT 03 Zero-cross MUTE off Zero-cross MUTE on
HZPD D2 PDC pin is always active PDC pin is "Z" at the trailing edge of GFS
NCLV Dl CLV-P servo for the frame sync signal CLV-P servo for the base coanter
CRCQ DO CRCF is not superimposed on SUBQ SUBQ = CRCF at the raising edge of SCOR

+2 Register A

GSEM GSEL Frame WSEL Clock

1 13

*3 Register D

DIV D3
O 1 RFCK/4 & WFCK/4 Phase comparison frequency
1 1 RFCKl8 & WFCK/8 in CLV-P mode
O RFCK/32 Bottom hold period in
TB D2
1 RFCK/16 CLV-S. CLV-H mode
O RFCK/4 Peak hold frequency i n
Tp Dl
1 RFCKl2 CLV-S mode
O -12dB Gain at MDP terminal in
GAlN DO
1 OdB CLV-S. CLV-H mode

+4 Register E
1 Mode 1 D3-DO 1 MDP terminal 1 MDS terminal IFSW terminal 1 MON terminal 1
STOP 10000 1 L Z L L

r
KICK 11000 1 H Z L H
BRAKE 1 0 10 L Z L H
CLV-S 1 11O C LV-S Z L H
CLV-H 1 10 0 CLV-H Z i H
CLV-P 1 1 1 1 1 1 CLV-P 1 CLV-P Z H
CLV-A 0 110 CLV-S or CLV-P Z or CLV-P L or Z H
Z : High impedance

List of registers
 CIRCUIT DESCRIPTION
3) Trakcing counter
This counter is provided for facilitating track jump.
Load the number of tracks t o be jumped in register B and
C. Count of CNlN pulses is started at raising edge of XLT
after it was loaded in either register B or C.
When n (n = 256 is meant when register B = register C =
O) is loaded in registers and the address is set at "6".
a signal (COMPLETE) that is of HlGH level up to "n"
pulses an.3 is of LOW level after "n" pulses is output of
SENSE terminal. When the address is set at "C", signal
(m) of CNINl2n ( H z ) is output.
The tracking counter timing chart is shown in Fig. 6-3.

Register
B,C X n ( n = 256 when "O" is loaded)

X L T terminal

l
I
C N l N terminal

COMPLETE
X I

I
I
I

COUNT
X I
I I I 1
Tracking counter timing chart

4) SENSE when the pulse width after bottom hold is over

The following signals are output from SENSE terminal
depend ing on the address of D7-D4.
1. COMPLETE : Address is "B"; Shown in Fig. 6-3.
2 . COUNT : Address is "C"; Shown in Fig. 6-3.
3. PWZ64 : Address is "E"; this signal is of LOW level
63, and is of HlGH level otherwise. It is used
for detection of a drop in the speed of the
spindle motor after braking and so on.
Note : Address setting is determined only by the data that
corresponds to D4-D7 which can be input from
DATA terminal shown in Fig. 6-2.

D7-D4 B E Others
I l I
I I I
l l I Z : High impedance
SENSE terminal COMPLETE

Timing chart of SENSE terminal

 CIRCUIT DESCRIPTION
(CI Timing of SCOR, CRCF, SQCK, SUBQ
SQEX= "H" level

SQCK

SUBQ 1 *5 X Q4 X 03 )( 0 2 )( Q1 X Q8 X a77 X
'5 : CRCF when CRCQflag is "1". undefined when " 0 .
SQEX= "L" level

so SI
SQCK

SUBQ X *6 XQlx Q 2 )( 03 X 04 X 05 xQ96 x Q97x x

'6 : CRCF when CRCQ flag is "1", 0 9 8 . 0 1 when "O".

(2)Timing chart of sub code outputs

80bit shift register SUBQ terminal

4-bit replacement

SQCK terminal

SQEX terminal
 CIRCUIT DESCRIPTION
EFM demodulation made by TRI STATE out of PD0 terminal. The mean value
1) Playback of bit clock by EFM-PLL circuit of PD0 terminal is about 112 VDD if synchronized, but

-
The EFM signal read out of the optical block contains
a clock cornponent of 2.16MHz. Therefore, it is possible to
take out a bit clock (PLCK) of 4.32MHz synchronized
with this clock by the EFM-PLL circuit.
At each edge of EFM signal, phase comparison is made
with PLCK, which is 112 of VCO, is made and output is
the mean value drops when VCO becomes higher. On the
other hand, the mean value increases when VCO becornes
less.
The timing charts of EFM terminal, EFMO, PLCK and
PD0 are shown in Fig. 6-7.

(a) When EFM signal ahd VCO are synchronized

E F M terminal 1I l

EFMO 1
1
1
l l I l
PLCK
I I 1I I
l
1 1l II I II
,
l I
.l I I
P D 0 terminal - -- - n-
I I
I ;----
- Z
l I
-u-- I
l

Z : High irnpedance

(b) When VCO is higher than EFM signal

E FM terminal

EFMO

I I !
PLCK

! I
1
I
1
I
I I I I
1
I
I
I
I
I
I

P D 0 terminal

Z : High irnpedance

(c) When VCO is less than EFM signal

E F M terminal
I I
EFMO 1I
I
I 1
I
1 I I
PLCK
I
I
I
l
I
l
1 I I I
I
1
I
I
I I
I I I
P D 0 terminal - J
L
-
I I
- I I
I I I

u---- I - 1

Z : High impedance
Timing charts of EFM-PLL circuit
 CIRCUIT DESCRIPTION
2) Detection, protection and interpolation of frame
synchronizing signals
There are cases during recording where the same pattern
is detected in the data due to the influence of drop-out
and jitter, even if a pattern that is same as the synchroni-
zing signal will not appear.
On the other hand, there also are cases where original
frame synchronizing signal is not detected. Therefore,
protection and interpolation are required besides detection.
The edge portion only of EFM signal (EFMO) latched
with PLCK is converted to "1" and the rest to "O", and
then input is to a 23 bit shift register and a frame synchro-
nizing signal is detected.
In order to protect a frame synchronizing signal, a
window is provided and the same patterns outside of this
window are removed. This width can be selected with
WSEL. If no frame synchronizing signal is located in this
window, interpolation is made with a signal produced by
588-mal counter (4.3218MHzl588 = 7.35kHz)
A 4 bit counter for counting the number of these frarnes
t o be interpolated is provided, and when its count reaches
the level selected with GSEL, GSEM, the window is ignored
and the 4 bit counter is reset with the next frame synchro-
nizing signal. the GTOP terminal is of "H" while this opera-
tion is performed. Further, GFS terminal is of "H" when
the frame synchronizing signal generated by the 588-mal
counter for making interpolation is synchronized with the
frame synchronizing signal from the disc.
The frarne synchronizing signal before passage through
the window or the wondow is output out of UGFS (DA05
terminal at the time when PSSL = L.)
GSEM GSEL
C-i
WSEL Window width
Number of frames t o
be interpolated
13 clock
17 clock
UGFS (PSSL= "L")
O O 2 frames Window
O 1 4 frames Window
Frame synchronizing signal before
1 O 8 frarnes
Passage through window.
1 1 13 frarnes Window
The timing for write request signal (WREQ), Write
Frarne Clock (WFCK), etc. is generated based on the pro-
tected and interpolated frame synchronizing signal.
3) EFM demodulation
14 bit data is taken out of the 23 bit shift register and is
demodulated to 8 bit data through 14 + 8 conversion
circuit composed of array logics. Then a write request
(WREQ) signal is output to the RAM interface block,
and the data is then output to the data bus (DB08-
DBO1) terminals) of the RAM in accordance with the
OENB signal transmitted from said block.
Sub code demodulation
1) Sub code demodulation
synchronizing signals SO, SI of 14 bit sub codes are
detected out of the 23 bit shift register. and sampling is
made in the timing that is synchronized with WFCK.
After delay of $0 by one frame, SO + SI is output out
of SCOR terminal and SO . SI is output out of SBSO ter-
minal (only when SCOR = H.)
Data (P-W) of sub' codes only is input to the register
in the timing synchronized with WFCK after EFM demo-
dulation; and sub code Q is output out of SUBQ terminal,
and at the same time, i t is loaded in the 8 bit shift register
and is output out of SBSO terminal in correspondence to
a clock from EXCK terminal.
The detials of this timing will be shown in the paragraph
of CP.U interface.
2) Sub code O error detection
The CRC sub code result is output from the CRCF pin
in synchronism with the SCOR pin. I t goes "L" when an
error is detected. A t the same time as the CRCQ flag is
"l", the CRCF flag is output frorn the SUBQ pin during
the time frorn the rising edge of the SCOR pin to the
trailing edge of the SUBQ pin. This timing is detialed in
"CPU interface".
 CIRCUIT DESCRIPTION
RAM interface (generation of external R A M address)
1) Request from EFM demodulation block (Write RAM
request)
When one symbol of demodulation is complete in the
EFM demodulation block, the EFM demodulation block
requests to write data to the external RAM to the RAM
interface block. This request is WREQ signal. This block
gives priority orders to requests from other blocks and
processes these requests.
When EFM write request is received, an address is
generated to the RAM and Write Enable state is produced.
Furthermore, a data output instruction is issued against
the EFM demodulation block. This instruction is OENB
signal.
Clocks of .PLL system are used for EFM block and for
requests (WREQ) from EFM block, but clocks of X'Tal
system are used for processing thereafter.
2) Request from DIA converter output circuit (Read to
DIA request)
This is a de-interleaved data request issued out of the
timing generator in this block. This request is of the
highest priority among al1 requests, and addresses of three
types are generated against this request.
This request is generated once every 24 periods based
on the period of system clock C212 (8.4672MHzl4).
The data output out of the RAM is C2 pointer first, less
significant 8 bits out of 16 bits and finally more signifiant
8 bits.
3) Request from error correction block (ClIC2 correction,
pointer RMI)
The error correction block requests the data located
on the system (Cl/C2) to be corrected. Furthermore,
there is a request to rewrite incorrect data to correct data.
In addition, there is a request for pointer R/W which in-
dicates reliability of data.
These requests are made by the 8 bit data directed to
the RAM interface block from the error correction block.
The requests from the error correction unit are of the
lowest priority among requests of three types. After
acceptance of a request, data from RAM is directed to the
3rd clock of C212.
The data of acceptance of a request is output to the
error correction block as a PREN signal. This block
generates the address of the requested data, and controls
R/W of the RAM at the same time.
4) Address generation
The data after EFM demodulation is data subjected to
interleave processing. This interleave processing is subjected
to data lag by the unit of a frame. Data of 108 frames
are required for de-interleave. In other words, for obtaining
one frame of audio data played in a certain length of time,
data of 108 frames after EFM dernodulation are required.
Further, the system data of C l /C2 is of the systern in the
process of application of interleave, and therefore, is
included in 108 frames.
Data in practice are generated continuously. That is,
de-interleave should be updated by the unit of a frame.
Therefore, Read~Write base counters are required. This
base counter performs counting by the unit of a frarne.
The writer base counter is used only at the time of EFM
data writer. The address directed to the external RAM is
deterrnined by the relative lag value to EFM demodulation
data and their number of frames.
5) Priority of address generation request
The system control block determines priority of address
generation requests made t o the RAM interface block.
The priority order is as follows beginning with higher
priority.
1. Read to DIA request
2. Write t o RAM request
3. C l lC2 request
The number of times of requests is as follows.
1. Requests of 12 times in the frame section
The number of times of address generation t o i t i s 36
times.
2. Requests of 32 times in the frame section
.The number of times of address generation to it is
32 times.
3. Maximum number of times of request ( C l Double
error correction, C2 pointer copy)
Read R/W 64 times, Pointe R/W 65 times in one
frame section
The number of tirnes of address generation to it is
129 times.
288 C212 (clocks) are included in a frame. and the
number of times of operation of the RAM in it is 197
tirnes at maximum. In the system control block, against
request 1, the 'timing of its occurrence is reserved in
advance. Requests 2, 3 are not accepted in this timing.
When requests 2, 3 are generated simultaneously, priority
is given to request 2, and if a requestis generated during
execution of either request, priority is given to the job
in execution.
 CIRCUIT DESCRIPTION
6) Jitter rnargin 8) The flow of data with the external RAM is as follows.
The EFM demodulation data is synchronized with data's
playback system (PLL) as described earlier. Accordingly,
i t includes disturbance (wow.flutter, etc.) of disc rotation A data request is made frorn the correction block
servo, etc. It is loaded t o the external RAM. As the data to the RAM interface block.
taken out of the RAM is synmchronized with the clock of
X'Tal system, this RAM is subjected t o time axis correc-
tion.
However, the limit of time axis correction is determined
by the capacity of the RAM. In this system, other data The RAM interface block accepts the request with
is destroyed when readlwrite frames are spaced apart by the operating situation of the entire system ob-
115 frames. In such a status how the playback sound is served. The address of the requested data is gene-
cannot be guaranteed. The base counter monitor is pro- rated t o the external RAM.
vided in order t o avoid it.
In other words, when the difference between read base
counter and write base counter exceeds 114 frames, the
write base counter is set in the value of the read base
counter. As a result, there is no case where data without ReadANrite of the correction block and RAM data
error correction is output to the DIA. are enabled.
The RAOV signal is of "H" for one frame (WFCK)
section when the difference between base counters ex- 9) When PSSL is set at "L", a signal that is capable of
ceeded + 4 frames. monitoring error correction is output. C l F I . C l F2,
C2F2 output t o DA01 -DA04 are these monitor signals.
Error correction This signal is reset t o "L" when a period of minimuni
1) The error correction block makes correction up t o 472 ns has elapsed since deactivation of RFCK.
double errors with each of C l correction and C2 correc- The levels and meanings of these signals at the time of
tion. deactivaiton of RFCK are as follows.
2 ) This system adopts a unique pointer erasure method in
order t o minimize erroneous correction. Accordingly,
ClFl C1F2 Cl correction status
the external 16k RAM stores these pointer data in
addition to audio data. O O No Error
3 ) The pointer generated in C l correction is called C l 1 O Siiigle error correction
pointer and the pointer generated in C2 correction is O 1 Double error correction
called C2 pointer. 1 1 Irretrievable errcir
4) When the data of C l system is judged as reliable, a
C l pointer is set in this systern.
5) During C2 correction, whether correction is to be made
or not t o be made and whether the data is reliable or C2F 1 C2 F2 C 2 FL C2 correction status
unreliable are judged from .the error location, locations O O O No Error
and number of C l pointers obtained through computa- 1 O O Single error correctioii
tion. A C2 pointer is set against an unreliable word O 1 O Double error correctiori
(16 bits).
1 1 1 Irretrievable error
6) The word in which a C2 pointer was set is subjected t o
previous value hold or mean value interpolation when it
is output out of this LSI.
7) Terminal C2FL becomes "H" when one or more C l
pointers are set in the data included in the C2 system
at the time of C2 correction. C2FL is reset to "L"
when a period of minimum 472ns after deactivation of
terminal RFCK. C2FL is the AND of C2F1 and C2F2.
Note : 47211s : One period of 2.1 168MHz
 CIRCUIT DESCRIPTION
CLV servo control 1 ) STOP : Register E = 0000'6 (B means binary)
The spindle motor revolution is controlled with one Mode for stopping the spindle motor.
selected out of the following seven modes in accordance MDP = FSW = MON = "L", MDS = "Z"
with a cornmand from the CPU. CLV is the abbreviation of 2) KlCK : Register E = 1000'6
Constant Linear Velocity. The output is composed of MDP Mode for running the spindle motor in forward
terminal for controlling synchronization of velocity and direction.
phase, MDS terminal for controlling synchronization of MDP = MON = "H", MDS = "Z", FSW = "L",
velocity, FSW terminal for making selection of filter 3) BRAKE: Register E = 1010'6
constant and MON terminal for controlling motor ON/ Mode for running the spindle motor in reverse
OFF. direction.
MDP = FSW = "L", MDS = "Z", MON = "H".

MON
-
"1" in CLV-S mode
"1" in CLV-P mode

FSW "Z" at the time' ,,L" or ,.Z,, at the'time

uH,,, ,,L,t or ,,Z,, of-12dBinCLV-Smode
"H" or "L" at
in Ci-v.' or at the tirne
the time of O ~ B
of OdB
J P
'
MDP ----. - - - -- - -
,.,,,, or ,,L,, in "Z" in

MDS
"CLV-P mode

- - - - - -- - - - - .- - - - - - -
/
CLV-S mode

-----

Cornmand from CPU :

STOP KICK CLV-A CLV-H CLV-A BRAKE STOP

A t the time of high speed access

Automatic switching between CLV-S and CLV-P

Activation i s made quicker by applying Rotation is quickly stopped by apply ing
forward rotational torque t o the motor. reverse rotational torque to the motor.

Z : High impedance

Typical control of spindle motor

 CIRCUIT DESCRIPTION
TP : RFCKl2 or RFCK14 in the case of CLV-S.
F8M1256 in the case of CLV-H
TB : RFCK116 or RFCKl32 in the case of
CLV-S, CLV-H

'

\
I
II
Peak hold Initial StatUS Initial status II
I1
II
FF
(22 and up) 1 O F, JJi
I
14-
FF
(23 and up) ,
\ 1 -
<L

\
Bottom hold

FF
(22 and UP)
O
1
Initial status

1
[,\ 1 7
Initial status

1
(1

FF
t
- 1
O\
1
!'
,

9 ( 1

--
(23 and up) ' 1

TP

Latch

F
(22
F and up)

FF
(23 and up)
\\\
\
\,1 &$

j G

4 TB c

Timing chart in CLV-S, CLV-H mode (2)

 CIRCUIT DESCRIPTION
4) CLV-S : Register E = 1 100'8
Rough servo mode used at the time of start of
rotation, at the time of track jump and also
when the EFM-PLL circuit is unlocked due to
another reason. When the period of VCO's
oscillation frequency 8.6436MHz is expressed
as "T", the pulse width of a frame synchro-
nizing signal is "22T" during specified revolu-
tion, and i t is the maximum pulse width in a
period of RFCK. In practive, however, there are
pulses having widths over "22T" due to drop-
off of EFM signal due t o other reasons, and the
frame synchronizing signal cannot be correctly
detected unless such pulses are removed. There-
fore, the maximum value (peak) of the pulse
width of EFM signal is detected (called peak
hold) in the period of RFCK/2 or RFCK/4,
than the minimum value in this peak is detect-
ed (called bottom hold) in the period of RFCK/
16 or RFCK/32, and this value is used as the
frarne synchronizing signal. "Lu is produced
out of MDS termipal while the frame synchro-
nizing signal is "21T" or less, "Z" when i t is
"22T", or "H" when it is "23T" or more.
Either OdB or 12dB can be selected as its gain.
MDS = "Z", FSW = "Lu, MON = "H",
a and
(22 t up) h l-+'"-/
RFCK terminal
MDP terminal
(when OdB)
MDP terminal
(when -12dB)
Timing chart in CLV-S. CLV-H mode (11
5) CLV-P: Register E = 11 11'8
PLL servo mode.
When the NCLV of register 9 is "O", the phase
of the WFCKl4 signal and the phase of the
RFCK/4 signal are compared and output to the
MDP pin. When NCLV = "lu, 114 of the base
counter frame frequencies at the Write side and
the Read side are phase-compared and output
to the MDP pin. I t goes "H" when WFCK is
slow, "L" when i t is fast, and is "Z" when
synchronized. I f the 8.467212MHz period is
T, and the time when WFCK is "H" is tHW,
then the MDS pin outputs a signal which goes
"H" during the time from the trailing edge of
WFCK to the time represented by (~Hw-279T)
X 32, and then goes "L" until the next trailing
edge of WFCK.
MDS 5 "H" when tHW = 279T.
MDS = "L" when tHW 2 279T.
The MDS pin varies between 32T and 544T. in
32T steps, when 280T 5 5
~ H W 296T. For
example, when synchronized (rotating at the
standard speed), that is when tHW = 288T, a
7.35kHz signal, with a duty cycle of 50% is
output.
FSW = " Z " , MON = "H".
 CIRCUIT DESCRIPTION
6) CLV-P : Register E = 1111'B
PLL servo mode.
Phase comparison of signals WFCK/4 and
RFCK/4 or WFCK/8 and RFCKl8 is made, and
output is made out of MDP terminal. "H" when
WFCK has delayed, "L" when WFCK is fast,
and "Zn when synchronized. When the period
of 8.467212MHz is expressed at T and the
length of time when WFCK is "H" is expressed
at tHW,. such a signal that is of "Hu during
(tHW-279T)
x 32 with 7.35kHz as a period and that is "L"
during the remaining time is produced out of
MDS terminal. MDS = "L" when tHW 5 279T.
MDS = "H" when tHW 5 297T. When 280T ' :
tHW 5 296T, the MDS terminal changes in
32T steps from 32T to 544T. When synchro-
nized, for instance, that is, when tHW = 288T,
a signal of 7.35kH.z of DUTY 50% is producerl
FSW = "Z", MON = "H".

MDP terminal

WFCK14 i 1
(or WFCKl8) I I

Z : High impedance

MDS terminal (The Period of 4.2336MHz is expressed as "TM.)

(1 ) When rotating a t specified velocity

1- 288T

WFCK
I 1
I
I
l
I 288~+
I
M DS
I
(2) When rotation becomes fast
2 8 0 ~

WFCK
I I I l
I I

(3) When rotation becomes slow

WFCK
I I I l
I

Timing chart in CLV-P mode

 CIRCUIT DESCRIPTION
7) CLV-A: Register E = 01 10'B
The mode used for normal play status.
The GFS signal ("H" when locked, "L" when
unlocked), after frame sync detection, protec-
tion and insertion block, is sampled at WFCK/
16, and functions in CLV-P mode when the
signal is "H". When the "L" signal continues
for 8 times, the mode is automatically
changed to CLV-S mode. When in the CLV-S
mode, setting of the peak hold period, and set-
ting of the period and gain of the bottom hold
of the CLV-S and CLV-H are performed in
register D, and the selection of each mode is
perfomred in register E. The description of
these registers are detialed in "CPU interface".
Note: When PSSL = "Lw, DA07 pin outputs
WFCK/4 or WFCK/8 as FCKV, and DA08 out-
p u t ~EFCKl4 or EFCKW as FCKX.
8 Interpolation and DIA converter interface.
1) Interpolation circuit block
3 byte data can be obtained with a Read to DIA
request. They are C2 pointer, less significant 8 bits and
more significant 8 bits. The total 16 bits constitute the
data generated per sampling (2's complement.)
The C2 pointer expresses the reliability of this 16 bit
data. Therefore, data with C2 pointer is subject to inter-
polation in this block.
O : Without C2 pointer
X : With C2 pointer
Mean value interpolation
1
B = (A+C)
2 NOTE : When the MUTG is set to "H" level with the NCLV
1 : When pointers are continuous
H= - (E+I)
2 well as the muting.
Previous value hold
F=G=E
8) CLV-A' : Register E = 0101'8
New auto servo mode added t o the CX23035.
The difference between CLV-A. and CLV-A
is in the rough servo system. With the old
rough servo system, the EFM pattern is meas-
ured by a crystal and the servo is applied so
that the width of the sync pattern is a fixed
value, and the rotation speed of the spindle
motor is roughly fixed. In this case, if the value
is out of the VCO capture range, the VCO never
locks with the EFM. With the new rough servo
system, a VCO is used for rneasurement instead
of a crystal. If the VCO center is shifted from
true center the VCO tends t o lock, since the
rotation of the spindle motor varies in the same
direction.
The new rough servo functions'only in CLV-A'
mode. The rough servo in CLV-A mode and
CLV-S mode is the old rough servo.
16 bit data is alternately output to L-ch and R-ch,
R-ch data is output in the section in which LRCK is "L"
and L-ch data is output in the section in which LRCK is
"H". C2PO signal outputs C2 pointer to the 16 bit data
directed to DAO1-DA16 (PSSL = H), DA16 (PSSL = L).
In other words, it means that the 16 bit data that is output
when C2PO is "H" is interpolated data.
2) Explanation of muting and attenuator
In the muting block i t is possible to mute (- dB) or
attenuate (-12dB) the audio signal in accordance with
the MUTG terminal and ATTM signal of the CPU interface
block.
-12dB
--dB See Note
-12dB See Note
flag set to "O", the read base counter value is con-
tinuously loaded into the write base counter as
Except at CLV-A, CLV-P, CLV-S, or CLV-A' with
the NCLV flag set to "l", the base counter is
loaded.
 CIRCUIT DESCRIPTION
Mode setting
The various kinds of mode can be set by combining the
following pins. (Refer to the table below.)
MD1 pin : Mainly for selection of the oscillator clock at
the XTAl or XTAO pin.
MD2 pin : Mainly for selection of the digital out func-
tion.
(Note)
8M/16M : Selection of clock, X T A L or XTAO. 8.4672MHzI
16.9344MHz
DO OFF/ON : Digital out OFFION
D F OFFION : Digital filter OFFION
1) Selection of clock
The oscillator clock for XTAl and XTAO is available
at 16.9344MHz and 8.4672MHz. However, when digital
out is used, the clock must be set t o 16.9344MHz.
2) Selection of digital out (Refer to "DIA interface")
When digital out is set to ON, a signal conforming to
the DIA interface format is output from the DOTX pin.
When i t is set t o OFF, the DCTX pin outputs the WFCK
signal. In the DP-969, this function is fixed t o ON.
3) Selection of digital filter
When the digital filter function is set to ON, the DAC
interface signal are al1 set t o double speed.
4) Selection of parallel outputlserial output
When the parallel output is selected, DAO1 to DA16
pins output the 16-bit parallel data. When the serial output
is selected, DAO1 t o DA16 pin output the following signals
respectively.
1
DAO1 + C l F I : Error correction status monitor
DA02 + C l F2 : output at C l decode.
1
DA03 + C2F1 : Error correction status monitor
DA04 -* C2F2 : output at C2 decode.
DA05 + C2FL : Correction status output,
C2FL = C2FI.CZF2.
MD3 pin : Mainly for selection of the digital filter func-
tion.
PSSL pin : Mainly for selection between serial and
parallel output.
SLOB pin : Selection between offset binary and 2's
complement.
PIS : Parallel outputlserial output
OB/2's : Offset binary/2's cornplement
CD ROMIAUDIO : Compatible t o CD ROM/Compatible t o audio
DA06 + C2PO : C2 pointer signal.
DA07 + RFCK : Read frame clock signal, 7.35kHz
when locked t o the crystal line.
DA08 + WFCK : Write frame clock signal, 7.35kHz
- when locked.
DA09 + PLCK : 112 of the divided signal from the
VCO pin, 4.3218MHz when locked.
DA10 + UGFS : Non-protect frame sync signal.
DA1 1 + GTOP: Frame sync protect status display
signal.
DA12 + RAOV : Jitter margin over or underflow dis-
play signal.
DA13 + - C4LR : 4 times the LRCK signal.
DA14 + C210 : Bit clock (invert signal of C210).
D A I 5 + C210. : Interna1 system clock (4.2336MHz
when DF is ON, 2.1 168MHz when
CXD11250 or DF is OFF).
DA16 + DATA : Serial data output (MSB or LSB first
output).
 CIRCUIT DESCRIPTION
5) Selection of OFFSET BINARYIS'S COMPLEMENT
When the SLOB pin is "H", an offset binary signal is
output, and when it is "L", a 2's complement signal is out-
put.
6) Selection of CD ROMIAUDIO cornpatibility
When MD1 = MD2 = MD3 = "H", the player is compa-
tible with a CD ROM and outputs the C2 pointer for each
byte. At the same tirne, the average value interpolation and
the previous value holding operations are not perforrned.
For example, when there is an error in the upper 8 bits of
the 16 bits, only the C2 pointer corresponding to the upper
8' bits goes "Hu, and the lower 8 bits are processed as the
correct data.
DIA Interface
The player incorporates a DIA interface output (digital
output) and the digital signal is output frorn the DOTX pin.
The digital signal is output after passing through interpola-
tion, mute and attenuator circuits. The 4 control bits (IDO,
ID1, COPY, EMPHASIS) in the C-bit channel status per-
form a CRC check and are revised only when it's OK.
Timing chart
-
WDCK \ /
APTR r
APTL
Timing chart of audio output
Counterrneasuresto defect
To counter a defect, the PDC pin is set to "Hi-Z"
during the time until GFS goes "H" again after inverting
from "H" to 'IL" or after approx. 0.55rns has elapsed.
However, this operation is perforrned only when the HZPD
flag of register 9 is "1 ". When HZPD = "O", it will never be
set to "Hi-Z".
The signal switching between the rough servo in the
CLV-A or CLV-A' mode and the PLL servo is output from
the LOCK pin. After the GFS signal is sampled at WFCKI
16, and when the signal is "l", the LOCK pin goes "H",
when a "O" is present 8 times in a row, the LOCK pin goes
"LU.
This operation is sirnilar to that for the FSW pin. How-
ever, while the FSW outputs a fixed signal when not in
CLV-A' mode, the LOCK pin always output the above
signa 1.
7 /
/
*PSSL = "L"
 CIRCUIT DESCRIPTION

DAOI-DAM mf
l
4-P-
I 1 Min 47211s
)i lm)mA
DAOl -DA04 ( C I F I , C l F2, C2F1, C2F2) are cleared when a period
of minimum 472 ns has elapsed since RFCK was deactivated.
ANDing signal of C2F1 and C2F2 is output out of C2FL termnal.

WFCK \

I
l I
35 period with DA09
-(bA09 is of about 4.32MHz) A

WFCK 7 1 \

WFCK
\ 1 \ \

RFCK
1
\ \ / \ \

Timing chart of DAOl -DA1 6 output when PSSL="L"

 CIRCUIT DESCRIPTION

C4LR
I I
(DA13) \

WDCK
- /
L X
(DAlO) -/
DA16*
(DATA) X Lch (MÇB) 16

1 l I
C2PO (DA06')
when compatible
with audio
C2PO corresponding to the L c h 16-bit data
K
I I
C2PO (DA06')
C2PO corresponding t o the upper C2PO corre~pondingto the lower
when compatible
with a CD-ROM 8-bits of L-ch data 8-bits of L-ch data

I l
Timing chart of C2PO output (when PSSL="L")

'RAOV becomes "H" for one frame (synchronizedwith WFCK) when a jitter that exceeds
I 4 frarnes is generated between RFCK and WFCK.

w
RAOV F c K 3 ~ [ ~ [ ~ ~

Min 47211s

Timing chart of RAOV output

 CIRCUIT DESCRIPTION
Static R A M CXK5816SP-12L

Block Diagram
Vpr

GND

Ciiluniri D r c i i liv

Terminal connection diagram Explanation of terminalç

Terminal name Function
(Top View)
AO- A10 Address input
A7

A6
1/01
-
- 1/08 Data input/output
CE Chip enable input
A5 -
A4
WE Write enable input
-
A3 OE Outfit enable input
A2 Vcc +5v
Al
END Ground
AU

101

1 02

l 03

GND

51
 CIRCUIT DESCRIPTION
Reset IC: M51951ASL (X32-1170-00: ICI 1)

Output

Operating Waveform

Power voltage
 CIRCUIT DESCRIPTION
DA Converter: PCM56P-K
(X25-3050-00: I C l , lC2)
Block diagraml
Terminal connection diagram

OUT

Explanation of terminais
Terminal No. Terminal name Function Terminal No. Terminal name Function
1 -Vcc Analog negative power supply. 9 Vout Voltage output
2 DIG GND Digital ground. 1O RF Feedback resistor.
3 +VL Logic positive power supply. 11 S.J Surnrning junction (op arnp. input).
4 NC No connection. 12 ANA GND Analog ground.
5 CK Clock input. 13 lout Current output.
6 LEC Latch enable control input. 14 MSB ADJ MSB adjustment terminal.
7 DATA Data input. 15 V POT Potentiorneter terminal.
8 -V L Logic negative power supply 16 + Vcc Analog positive power supply.
1
 CIRCUIT DESCRIPTION
Digital filter: SM5804D
(X25-3050-00: I C I 4)
Block diagram
 CIRCUIT DESCRIPTION
Explanation of Pins
W i t h this LSI, the switching b e t w e e n the serial a n d parallel in- of t h e functions o f pins X I t o X I 6 a n d Yi to Y16 rnay b e
putsloutputs is perforrned b y the K L a n d K L pins. Some changed b y this switching.

AH the terrninals o f this unit function w i t h PlSL = H. Note: ip designates an input jack with a pull-up resistor.

- -
PlSL = H PISL = L
Pin No.
Function
Pin Name 110 Pin Name 110
-
SIMD iP Serial input mode switching.
1
X5 ip Parallel data input (Bit 5).
-
SIE0 iP B CH serial input enable.
2
X4 ip Parallel data input (Bit 4 ) .
-
SIEA [P A CH serial input enable.
3
X3 ip Parallel data input (Bit 3).
BCKl [P Serial input bit clock input.
4
X2 ip Parallel data input (Bit 2).
SID iP Serial input data
5
X1 ip Parallel data input (LSB).
6 44CI iP f-- ip 44 1 kHz sync clock input.
-
7 ABSL 1P ip -ABSL= H-44
ABSL=L-44
CI clock, HIL = A CHIE CH
CI clock, HIL = B CHIA CH.

8 TEST 1 1P ip Test input 1 (Normally Open).

9 TEST 2 iP ip Test input 2 (Normally Open).
- -
- . Normally 4SSL= H or Open. 4SSL= L when input is 16.9344
1O 4SSL ip IP
MHz or 17.2872 MHz.
-
- CKSL= H-External
- clock input.
11 CKSL 1P a ip CKSL= L-X'tal oscillation.
A ,
'
12 Vss a / GND power supply pin (O V).

13 XT l I
m=H-Clock input.
C m = L-X'tal oscillation input.
-
- CKSL= H-(Open).
14 XT O O
C m = L-X'tal oscillation output.

15 CKO O O Clock output

-
- System clock 96 fs-SCSL= H
16 SCSL 1P a ip
System clock 98 fs-== L.
17 m 1P ip Open.
-
- POMD=H-Normal parallel output mode.
-
18 POMD iP ip POMD= L-ln-phase parallel output mode
-
19 s'mm i~ ip m=
L with serial output.

-
-
. LSBO= H-MSB-first serial output.
LSBo -

-
20 1P t-- iP LSBO = L-LSB-fis serial output.

21 (NCI (NC)

-
22 (NC) (NC)
23 (NC) i (NC)
24 (NC) (NC)
25 DGA O O A CH deglitch control output.
26 DGB O O B CH deglitch control output.

SODA O A CH serial data output.

27 -
Y1 O Parallel output iinverted, LSB).

55
 CIRCUIT DESCRIPTION
- - d

PlSL = H PlSL = L
Pin No. Function
Pin Narne 110 Pin Narne 110
SODB O B CH serial data output.
28 -
Y2 O Parallel output iinverted, Bit 2).

29 (NC) lnternally short-circuited to VDO. Not to be connected externally.

BCKO O Serial output bit clock output.

30
-
Y3 O Parallel output (inverted, Bit 3).
CO 1 O Serial output control clock 1.
31
vf O Parallel output iinverted, Bit 4 ) .

CO2 O Serial output control clock 2.

32 -
Y5 O Parallel output iinverted, Bit 5 ) .

CO3 O Serial output control clock 3

33 -
Y6 O Parallel output (inverted, Bit 6).

CO4 O Serial output control clock 4.

34
Y7 O Parallel output iinverted, Bit 7).

(NC) Hz (NC)
35
Vg O Parallel output iinverted, Bit 8).

(NC) Hz iNCi
36
-
Y9 O Parallel output iinverted, Bit 9).

(NC) Hz (NC)
37 -
Y 1O O Parallel output (inverted, Bit 10).

iNC) Hz (NC)
38 -
Y1 1 O Parallel output (inverted, Bit 1 1).

(NC) Hz (NC)
39
v.7 O Parallel output (inverted, Bit 12).

(NC) Hz (NC)
40
n-3 O Parallel output (inverted, Bit 13).

(NC) Hz (NC)
41
-
Y 14 O Parallel output (inverted, Bit 14).

(NC) Hz (NC)
42
-
Y15 O Parallel output iinverted, Bit 15).

(NC) Hz (NC)
43 -
Y16 O Parallel output (inverted, MSB).

44
-
POSL i~ ip
m=
- H-Serial output systern.
POSL= L-Parallel output systern.
. KjFB= H-2's cornplernent display output.
45 YOFB 1P IP
mTFB= L-Offset binary display output.
46 Voo /
,- +ve power supply pin ( 5 V).

-
-
. XOFB= H-2's cornplernent display input.
47 x m IP IP
m B = L-Offset binary display input.

48 KL iP ip
m=H-Serial input systern.
P~SL
= L- parallei input systern.

49 (NC) iNCI

56
 CIRCUIT DESCRIPTION
- -
PlSL = H PlSL = L
Pin No. Function
Pin Name Il0 Pin Name 110
(NC) iP (NC)
50
XI6 ip Parallel data input (MSB).

(NC) iP INC)
51
XI5 ip Parallel data input (Bit 1 5 ) .
(NC) iP (NC)
52
XI4 ip Parallel data input (Bit 1 4 )
(NC) iP (NC)
53
XI3 ip Paraltel data input (Bit 13).
(NC) iP (NC)
54
XI2 ip Parallel data input (Bit 1 2 ) .
(NC) iP (NC)
55
XI 1 ip Parallel data input (Bit 11 ) .
(NC) iP (NC)
56
X 1O ip Parallel data input (Bit 1 0 ) .
(NC) ip (NC)
57
X9 ip Parallel data input (Bit 9)
(NCI i~ (NCI
58
X8 ip Parallel data input (Bit 8 )
(NC) iP (NC)
59
X7 ip Parallel data input (Bit 7 ) .
- LSBl=
LSBl 1P
- H- MSB-first serial input
60 LSBl = L- LSB-first serial input

X6 ip Parallel data input (Bit 6 ) .

-
Senal Output Timing (SOMD = L, SCSL = H, system clock = 4.2336 MHz)

PIN 4.n ,II dich 2nd ncn 3rd th 41h

@ SODA rn Illllllllllllllll
B C ~ i.1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ch 2nd
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
~ ç n 3rd
11111111111111111
B L ~ 411

@ soDe rn 11111111111111111 lllllllllllllllll 11111111111111111 I I I I I I l l 1 1 1 1 1 1 1 1 1 (4.2336

@) BCKO 1 MHZ)
0CO 1 7 I L ( 4 4 . 1 kHz)
@c02 1 1 1 J ~ ( 8 8 . 2 k H z )
@ CO3 A I I 1 r
@ CO4 1 1 1 1 1 1 L r L(I76.4kHz)
@$DGA I 1
@ DG0 1 I I r L
 CIRCUIT DESCRIPTION
DIA distortion correct TC1 7G005AF-0048
(X25-3050-00: I C I 5)
Explanation of terrninals

Crystal oscillator input terminal

Terminal connection diagram

Hexa D Flip-flop TC74HC174F

(X25-3040-00: IC2)
Block diagram Truth table

Vcc 6Q 6D 5D 5Q 4D 40 CLOCK lnputs Outpub

CLEAR 10 ID 2D 20 3D 30 GND
 CIRCUIT DESCRIPTION
Transistor array (X25-3040-00: IC3)
TD62003AP DARLINGTON DRIVER
Pin configuration

01 02 03 04 05 06 07 COMMON

COMMON
INPUT OUTPUT

I I
L - - - - - -- GND
Il 12 13 14 15 16 17 GND

pPD4053BC 2-channel analog switch IC Truth table

(X32-1170-00: IC2)
The pPD4053BC is a multiplexer cornposed of a level con-
verter and analog SWs. The switches corresponding t o
the required channels are turned o n according t o the digit-
al signal input to the control terminals.

Block diagram

H: "H" level..L: "L" level, X: H or L

 ADJUSTMENT
- 1 NPUT ALICNYENT
-
No. 1 TEM SETTl NC SETTINC SETTlNC POINT ALICN FOR
ien the porer is fra
Short-circuit 0.15 to 0.4mV. RF
pins TEST and turn evel is 1.OVp-p or
APPIY the sensor power on to enter iore, TE (servo open
1 LASER WVER section of the optical the Test mode. s 2.OVp-P or more
power meter on the Press the REPEAT ind the diffraction
pickup lens. key. the tray grating is aligned
opens and ,orrectlu. the picku
- the LO emits light is acceptable.
Short-circuit pins
LASER PICKUP Connect a DC ammeter TEST and turn pore -5.5mA current valus
lPERATlNC CURRENT across CN2 on to enter the abeld on the laser
2 (Only when the pin 6 and Test mode. Press pickup. If current
pickup seems the pattern. the REPEAT key. 6 40mA or more ove1
defective.) (X32-1110) the tray opens and .he above value. it'
- the LD emits light defect ive.

Connect a frequency Turn Power OFF,

3 VCO counter to CNll(P1CK) then ON again.
- - -
(X32-1110) Stop mode
Enter the test mod
Connect an osci 1loscopi by turning Power Check that
as follows. ON while shorting the diffraction
4 DIFFRACTION Test disk CHI: RF the Test Pin. grating is aligned
GRATlNC Type 4 (X29-1810 Test pin) Press the CHECK ke correctly.
CH2: TE and confirm that th :The grat ing cannot
- (X32-1170 pin 1) display is ' 0300' be adjusted.)
Enter the test mod
Connect an ose i 1loscop by turning Power
as follows. ON while shorting TE.BALANCE Symmetry between
TRACK l NC ERROR Test disk CHI: RF the Test Pin. VR3 upper and lower
5 BALANCE Type 4 (X29-1810 Test pin) Press the CHECK ke (X29-1870) pat terns.
CH2: TE and confirm that th or DC=OIO.O5V
- (X32-1110 pin 1) display is ' 0300'
Connect an oscilloscop
as follows. Press the PLAY
FOCUS ERROR Test disk CHI: RF key. and conf irm FE BALANCE
6 BALANCE Type 4 (X29-1810 Test pin) that the display VR4 lptimum eye pattern
CH2: TE is' 0500'. tx29-18io)
- (X32-1110 pin 1)
Test disc Type 4 Use a servo jig. or Turn Power OFF
iply 900Hz. 4OmVrm connect a 4TkR. 410pF then ON again. FOCUS CAlN
7 FOCUS CAlN gnal to CN3 pin 2 LPF to pin 1 of CN3. and press VRl
- ' PC board X32-111 (X32-1110) the PLAY key. (X29-1810) - -

Test disc Type 4 Use a servo jig. or

1p1y 900Hz. 4OmVrm connect a 4lkR. 470pF TRACK l NC CA 1 N
8 TRACK INC GAIN gnal to CN3 pin 4 LPF to pin 5 of CN3. PLAY VR2 4OmVrms
- ' PC board X32-117 (X32-1110) (X29-1810)

Test disk
9 DAC OUTPUT Type 4 to the output OdB signal 1.9-2.OVrms
-
Test disk
1O DAC DISTORTION Type 4 to the output -20dB signal Minimum distortion
-
Test disk
11 DAC DISTORTION Type 4 to the output OdB signal Minimun distortion
-
loti Type 4 disk: SONY )S-18 Test Oisk or !quivalent.
 REGLAGE
RECLACE 1 RECLACE 1
RECLACE DE LA 1 POINT 1
D' ENTREE DE SORTIE LECTURE ( D' ALIGNEMENT ALIGNEMENT POUR FIG
-
Court-circuiter les] Quand 1' alimentation
broches TEST et est de 0.15 à 0.4iX.
mettre sous tensio le niveau RF de
Appliquer la section pour passer dans 1.OVc-c ou plus.
dëtecteur du compteu le mode d' essai. TE (asservissement
1 PUISSANCE LASER - de puissance optique Appuyer sur ouvert) de 2.OYc-c 01 (a)
sur la lentille la touche REPEAT. plus et le reseau de
du capteur. le plateau s'ouvre diffraction aligne
et le LD emet de correctement. le cap
la lumiëre. teur est acceptable. -

broches TEST et +5.5mA de valeur de

courant de Raccorder mettre sous tensio courant indiquee sur
fonctionnement du un ampëremetre CC pour passer dans le capteur laser.
capteur laser en travers de le mode d' essai. Si le courant est de
2 (Uniquement quand la broche 6 de Appuyer sur 40mA ou bien (b)
le capteur semble CN2 et la forme. la touche REPEAT, supérieur à la
dëfect if.) (X32-1110) le plateau s' ouvre valeur ci-dessus.
et le LD émet de i l est défectif.
la lumiére.

1 1 VCO

1
Raccorder un
compteur de frëquence
à CNI1 (PLCK).
(X32-1110) 1
1
1' alimentation.

Mode d'arrêt
Entrer en mode de
test en mettant
Raccorder un 1' alimentation en Yerifier
r cil loscope comme suit circuit tout en que le réseau de
RESEAU DE Disque test CHI: RF court-circuitant diffraction est
4 DIFFRACTION Type 4 (X29-1810 broche test) la broche test. correctement aligné.
CH2: TE Presser la touche (Le réseau ne'peut
(X32-1110 broche 1) CHECK et s' assurer pas ëtre ajuste.)
que 1' aff ichage

Entrer en mode de
test en mettant
1 Raccorder un 1' alimentation en
>scilloscopecomme suit circuit tout en Symétrie entre les
BALANCE D' ERREUR Disque test CHI: RF court-circuitant TE BALANCE formes supërieure et
5 D' ALIGNEMENT Type 4 (X29-1810 broche test) la broche test. VR3 inférieure ou
CH2: TE Presser la touche (X29-1870) DC=Ot0,05V
(X32-1110 broche 1) CHECK et s'assurer
que l'affichage
1 est "0300'.
Raccorder un
)scilloscope comme suit. Presser la touche
BALANCE D' ERREUR Disque test CHI: RF PLAY et s'assurer FE BALANCE
6 DEMISEAUPOINT Type 4 (X29-1810 broche test) que l'affichage VR4 Forme optimum
CH2: TE est ' 0500 ' (X29-1810)
(X32-1110 broche 1)
Disque test Type 4
Appliguer un signal Utiliser un gabarit Couper CAlN DE
GAIN DE MlSE AU 900Hz. 40mYrms d' asservissement 1' alimentation et MlSE AU POINT
7 POINT â la troche 2 de ou raccorder un FPH de la redonner VRI
CN3 sur la plaquette 4'7kIi. 410pF puis presser (X29-1810)
X32-1110. la troche 1 de CN3. la touch PLAY.
Disque test Type 4
Apyliauer un signal Utiliser un gabarit
9OOHz. 40mVrms d' asservissement CAlN D' ALIGNEMENT
8 1 CAlN D'ALICNEMEN. â la troche 4 de ou raccorder un FPH de
CN3 sur la plaquette 41kQ. 410pF
PLAY VR2
(X29-1870)
1 1

1
132-1110. latroche5deCN3.
( Raccorder un voltmètre 1 Lire le signal 1
9 1 SORTIE DAC Disque test
Type 4
1 CA sur la borne de 1
sortie (FIXED).
IkHz. 0dB dans
la piste n' 2.
1
YRl: C
VR2: D
(X25-3050)
1 1.9-2.OYrms 1 (h)
Raccorder un voltmétre Lire le signal YR3: C
DISTORSrOti DAC Disque test CA sur la borne de IkHz. -20dB dans VR4: D Distortion minimum (h)
Type 4 sortie (FIXED). la piste n' 15. (125-3050)
Raccorder un voltmëtre Lire le signal YR5: C
DISTORTION DAC Disque tes1 CA sur la borne de 100Hz. OdB dans YR6: D Distortion minimum (hl
Type 4 1 sortie (FIXED). 1 la piste n. 4. 1 (X25-3050) 1
:Remarque)Disque de type :Disque test SONY YEDS-18 ou ëquivalent.
 El NCANGS- AUSGANCS- 1 SPIELER- 1 ABCLEICH- 1 1
NU. GEGENSTAND El NSTELLUN El NSTELLUNGE El NSTELLUNG PUNKT ABGLEICHUNG 1 ABB
1 DieStifteTEST 1 1 lenn bei einer .1
kurzschlieBen und Spannung von 0.15 bis
die Spannungsver- 0.4 n Y der RF-Pegel
Das Sensorteil sorguns einschalten. 1.OVs-s oder mehr.
des optiscben um den Test-Modus TE (Servo-Of fen)
1 LASERLEISTUNG Leistungmeters auf zu aktivieren. Die 2,OVs-s betragt und
die Aufnehnerlinse Taste REPEAT drücken das Beugungsgitter
ansetzen. dann offnet sich richtig ausgerichtet
der Trager. und die ist. ist der Abtaster
1 LD gibt Licht aus. 1 in Ordnung. 1
1 Die Stifte TEST (
kurzschlieBen und
die Spannungsver- Stromwert + 5.5mA
BETR 1 EBSSTROM DES Ein-Cleichstrom- sorguns einschalten. auf den Lasertonab-
LASERTONABNEHYERS Amperemeter zwischen um den Test-Modus nehmer markiert.
2 (Nur wenn der CN2 Stift 6 und zu aktivieren. Die - Venn der Strom 40mA
Tonabnehmer defekt iem Muster anschlieBen. Taste REPEAT drucken. oder mehr über den
zu sein scheint) (X32-1170) dann offnet sich obigen lert liegt.
der Trager. und die ist er defekt.
LD gibt Licht aus.
Einen Frequenzzahler Die Spannungsversor-
an CNll(PLCK) gung aus-und dann L9
anschlieBen. wieder einschalten. (X32-1170)
(X32-1170) Stop-Betriebsart
Den Testst ift kurz-
schlieBen und dabei
Ein Oszilloskop die Spannungsversor- Priifen.
rie folgt anschlieBen: gung einschalten. un ob das Beugungsgitte
Testdisc Kanal 1: RF den Testmodus zu akti- richtig ausgerichtet
(X29-1870 Teststift) vieren. Die CHECK- - ist.(Das Citter
TYP 4
Kanal 2: TE Taste driicken und kann nicht
(X32-1170 Stift 1) prufen. da0 ' 0300 " eingestellt werden.)
auf dem Display
1
angezeigt wird.
1 Den Testst ift kurz- 1
schl ieBen und dabei
Ein Oszilloskop die Spannungsversor-
wie folgt anschlieBen: gung einschalten. un Symmetrie zwischen
SPURHALTEFEHLER- Testdisc Kanal 1: RF den Testnodus zu akti- TE BALANCE oberen und umteren
5 AUSCLEI CH TYP 4 (X29-1870 Teststift) vieren. Die CHECK- VR3 Mustern oder (e)
Kanal 2: TE Taste driicken und (X29-1810) Cleichstrom
(X32-1170 Stift 1) prufen. da0 ' 0300 ' DC=OfO.O5V
auf den Display
angezeigt wird.
Ein Oazilloskop

1
rie folgt anschlie0en: Die PLAY-Taste FOKUS-
FOKUS- Testdisc Kanal 1: RF driicken und prüfen. FEHLERAUSCLEICH
6 FEHLERAUSCLEICH TYP 4 (X29-1810 Teststift) da0 ' 0500 ' VR4 Optimales Ausenmuste Cf)
Kanal 2: TE auf dem Display (X29-1870)
(X32-1110 Stift 1) angezeigt wird.
Testdisc Type 4 Eine Servo-Lehre v e r Die Spannungsversor-
Ein 900Hz. 40mVrns wenden oder ein 47kQ. gung aus-und dann FOKUSVERSTARKUNC
7 (
FOKUSVERSTARKUNC Signal an Stift 2 410pF TiefpaDfilter wieder einschalten. VR1 40mVrms (9)
von CN3 an platine an Stift 1 von CN3 dann die PLAY-Taste (X29-1810)
132-1110 anlegen. anschl ieBen. drueken.
Testdisc Type 4 Eine Servo-Lehre ver-
Ein 900Hz. 40mVrms wenden oder ein 47kP. SPUHALTE-
SPURHALTE- Signal an Stift 4 470pF TiefpaBf ilter PLAY VERSTARKUNG 4OmVrms (B)
VERSTARKUNC von CN3 an platine an Stift 5 von CN3 VR2
X32-1170 anlegen. anschlieBen. (X29-1810)
Ein lechselstroai-

9 1 DAC-AUSCANC
Testdisc.
TYP 4
Voltmeter an die Aus- Das IkHz. OdB Signal
gangsklemme(F1XED)
- -

anschl ie0en.
in Titel Nr. 2
wiedergeben.
VR1: L
VR2: R
(X29-1870)
Ein Yechselstrom-

4-
Testdisc Voltmeter an die Aus- Das 1kHz. -20dB Signal VR3: L
DAC-VERZERRUNC TYP 4 gangsklemme(F1XED) in Tite1 Nr. 15 VR4: R Minimale Verzerrung (b)
anschlieBen. wiedergeben. (X29-1810)
Ein lechselstrom-
Testdisc Voltmeter an die Aus- Das 100Hz. OdB Signal VR5: L
II 1
DAC-VERZERRUNC Type 4 gangsklemme(F1XED) in Titel Nr. 4 VR6: R Minimale Verzerrung Ch)
1 anschliesen. 1
wiedergeben. 1 (X29-1870) 1 1
(Hinveis) TYP 4 Disc: SQNY YEDS-18 Testdisc oder Aquivalent.
4. Description of Signal Waveforms, Connection of Measuring Instruments/Descriptiondes formes d'onde des signaux,
connexion des instruments de mesure/Beschreibung der Signal-Wellenformen, Anschlui3 der Mefiinstrumente

RF signal and T.Error signal after diffraction grating

CH1 RF adjustment.
Signal RF et signal T.Error après ajustement de réseau de
diffraction.
RF-Signal und T.Error-Signal nach Diffraktions-gitter-
Einstellung.

CH2 T.Error
2.0VIdiv

(Photo. 1) RF signal and T.Error signal when there is small diffrac-

(20msecldiv) (Photo. 1)
tion grating position error.
(Foto. 1) The T.Error signal level is small, and the envelope is as
shown in the diagram below.
RF Signal RF et signal T.Error quand il y a une petite
1 .OVldiv erreur de position du réseau de diffraction.
Le niveau de signal T.Error est petit et I'envelope est
telle qu'indiquée dans le diagramme ci-dessous.
RF-Signal und T.Error-Signal bei kleinem' Diffraktions-
gitter-~ositionierungsfehler.
Der T.Error-Signalpegel ist klein, und die HüII-kurve ist

CH2 T.Error
2.0Vldiv
+O(V)

RF signal and T.Error signai in test mode (with focus-

(Photo. 2) ingON).
Trigger point (20msecldiv)
point de déclenchement (Photo. 2, When the sub-beam traces the same bit series as the main
Triggerpunkt (Foto. 2) beam during diffraction grating adjustment, bringing the
RF trigger point to the position shown in the Photo
CHI RF
causes a "projection" to be observies in the T.Error
1 .OVldiv waveform,
Le signal RF et le signal T.Error en mode de test (avec
la mise au point sur ON).
+-O(V)
Quand un faisceau auxiliaire tracela même serie de bits
que le faisceau principal pendant l'ajustement de r6seau
de diffraction, l'apport du point de déclenchement RF
à la position indiqube dans la photo provoque une
CH2 T.Error "projection" qui s'observe dans la forme d'onde d'
2.OVldiv T.Error.
-O(''
RF-Signal und T.Error-Signal irn Testmodus (bei ein-
geschalteter Fokussierung).

-
Wenn der Nebenstrahl die gleiche Bitreihe wie der
Hauptstrahl wahrend der Diffraktionsgitter-Einstellung
Projection (Photo. 3) verfolgt und den RF-Triggerpunkt auf die im Foto
(2wecldiv) Projection (photo. 3) gezeigte Position bringt, wird eine "Hervorstehung"
Hervorstehung
(Foto. 3) verursacht, die in der T.Error-Wellenform beobachtet
werden kann. 63
 ADJUSTMENTIREGLAGEIABGLEICH
RF signal and E.Spot signal in test mode (PLAY).
I f the diffraction grating has been adjusted properly,
the influence of triggering is observed on the E.Spot
waveform of approx. 1% after RF signal, in the form
of a projection.
Signal RF et signal E.Spot en mode de test (PLAY).
CH1 RF
1.OV/div Si le réseau de diffraction a été ajusté correctement,
l'influence du déclenchement s'observe sur la forme
d'onde E.Spot d'environ 1 2 p après le signal RF, sous
la forme d'une projection.
RF-Signal und E.Spot-Signal im Testmodus (PLAY).
Wenn das Diffraktionsgitter richtig eingestellt wurde,
CH2 E.Spot
wird der EinfluB des Triggers in der E.Spot-Wellenforrn
0.1 Vldiv etwa 1 2 p nach dem RF-Signal in der Form einer
AC coupling for Hervorstehung beobachtet.
CH2 only
Couplage CA pour canal 2 seulement
. . - nur für Kanal2
AC-Ko~oluno
(2pecldiv) L lori
pro~ect
Projection
(Photo. 4)
Hervorstehung 4,
RF signal and T.Error signal: in test mode (Focusing
ON) (Disc type 4)
Adjust T.Error so that the waveform is syrnrnetrical
above and below OV. (VR3 of X29-1780-00)
Signal RF et signal T.Error; en mode test (mise au point
ON). (Disque de type 4)
Ajuster T.Error pour que la forme d'onde soit symé-
trique en-dessus et au-dessous de OV. (VR3 de
X29-1780-00)
RF-Signal und T.Error-Signal; im Testmodus (Fokussie-
rung eingeschaltet). (Disc-Typ 4)
T.Error so einstellen, daB die Wellenform über und
unter OV syrnmetrisch ist. (VR3 von X29-1780-00)

RF signal in test mode (PLAY).

Perform the tangential and focusing offset adjustments
so that each of the center cross points are focused into
one point on the display. The crossing points above
and below the center shall also be displayed clearly.
Signal RF en mode de test (PLAY).
Effectuer les ajustements d'offset tangentiel et de mise
au point pour que chacun des points de croisement
central soit mis au point sur un point de l'affichage.
Les points de croisement au-dessus et en-dessous du
centre doivent aussi être affichés clairement.
R F-Signal im Testmodus (PLAY).
Die Tangential- und Fokusversatz-Einstellungen so
durchführen, da8 jeder der mittleren Kreuzungs-
punkte in einem Punkt auf dem Display fokussiert wird.
Auch die Kreuzungspunkte über und unter der Mitte
(Photo. 6)
müssen klar angezeigt werden.
(Photo. 6)
(Foto. 6)
 Eye pattern center
Centre de la forme oculaire
- Augenmuster-Mitte
RF signal and PLCK signal in test mode (PLAY).
When the synch system is normal, the cross points at
the center of the eye pattern shall coincide with the
PLCK fall points.
Le signal RF et le signal PLCK en mode de test (PLAY).
Quand le système sync est normal, les points de croise-
ment au centre de la forme oculaire doivent coïncider
avec les points de chute PLCK.
2.0VIdiv RF-Signal und PLCK-Signal im Testmodus (PLAY).
Wenn das Sync-Sys'tem normal ist, müssen die Kreu-
zungspunkte in der Mitte des Augenmusters mit den
PLCK-Fallpunkten zusammenfallen.

(Foto. 7)

(9)

Oscilloscope

1 pin 5 ptn

Pickup u
Capteur Optical power meter
Abnehmer Compteur de puissance optique
Optikleistungsmesser
(f) FOCUS GAIN (g) TRACKING GAIN
f=9OOHz f=900Hz
4OrnV rms 40rnV rrns

Millivoltmeter
Millivoltmbtre

l
VOLTAGE CHECK TABLE
PC BOARD (Component Side New)
f r ,

MECHA. ASSY Xs2-1210- 00 I

------,----,---A
68
73
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2
Parts with the exploded numbers larger than 700 are not supplied.
83
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L e s articles non mentionnes dans l e Paris No. ne sont pas fournis.
Telle ohne Parts No.werden nicht gellefert.

Ref. No. Address New Parts No. Description Desti- Re-

Parts nation marks
+ma* ~ m g ii sfi6a+ is a % / n; i ~ e na*
DP-1100SG

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Parts PARTS LIST
Parts wlthout Parts No. are not supplled.
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E: Scandinavia &Europe K: USA P: Canada

U: PX(FarEast Hawaii) T: England M: Other Areas
-
UE :AAFES(Europe) X: Australia indicates safety critical cornponents. 93
[Format] [General]
Type: ............................................ Compact disc player Power consumption: .............. 23W
Read system: ............................ Non-contact optical Dimensions: ............................... W: 440mm (1 7-5/1 6")
pickup
Laser: ........................................... GaAIAs. wave- H: 12 4 m m (4-7/8")
length=780nm, 3-beam
tracking
Rotational speed: .................... About 5 0 0 to 2 0 0 rpm
Error correction: ....................... Cross lnterleave Read-Sol- Wei9ht: ....................................... 1 1 .8kg ( 2 6 Ib)
omon code
Audio channels: ....................... 2
[Wireless remote control unit]

[Audio] Model: ......................................... RC-Pl 1 00SG

Type: ............................................
lnfrared pulse
Frequency response: ..............
4Hz 20kHz - Power supply: ........................... DC 3V (two AA size
Signal-to-noise ratio: ..............
more than 108dB batteries)
Total harmonic distortion: ... 0.001 % at 1 kHz Weight: ....................................... 1 15g (with batteries)
Channel separation: ............... more than 106dB at 1 kHz
W o w f lutter: ............................. Below measurable limit
Output voltage [Supplied accessories]
Analog outputs
LlNE OUT (FIXED): ............. Connection cord: ..................... 1 stereo cord
LlNE OUT (VARIABLE): .... Wireless remote control
Digital output (RC-Pl 100SG): ......................... 1
Coax cable terminal: .........
0.5V p-p. 75 ohms Batteries (AA): .......................... 2
Optical output: .....................
- 15dBm - 25dBm -
Headphone jack: ..................
60mW (8 ohms)

Note:
We follow a policy of continuous development.
For this reason specifications may be changed without notice.
Note:
Component and circuitry are subject to modificationto insure best opera-
tion under differing local conditions. This manual is based on the Europe
(E) standard, and provides information on regional cirucuit modification
through use of alternate schematic diagrams, and informationon regional
component variations through use of parts list.

KENWOOD CORPORATION
Shionogi Shibuya Building, 17-5. 2-chome Shibuya. Shibuya-ku, Tokyo 150. Japan

KENWOOD U.S.A. CORPORATION

2201 East Dorninguez Street, Long Beach, CA 90810;
550 Clark Drive. Mount Olive. KI 07828. U.S.A.
KENWOOD ELECTRONICS CANADA INC.
P.O. Box 1075 959 Gana Court. Mississauga, Ontario. Canada L4T 4C2
KENWOOD ELECTRONICS BENELUX N.V.
Mechelsesteenweg 418 8-1930 Zaventern. Belgiurn
KENWOOD ELECTRONICS DEUTSCHLAND GMBH
Rembrucker-Str. 15. M)56 Heusenstamrn. West Gerrnany
TRIO-KENWOOD FRANCE S.A.
Hi-Fi -VIDE0-CAR Hi-Fi
13. Boulevard Ney. 75018 Paris. France
TRIO-KENWOOD U.K. LTD.
17 Bristol Road. The Metropolitan Centre. Greenford. Middx. UB6 8UP England
KENWOOD ELECTRONICS AUSTRALIA PTY. LTD.
4E Woodcock Place, Lane Cove. N.S.W. 2066.Australia
KENWOOD 8 LEE ELECTRONICS, LTD.
Wang Kee Building. 4th Ftoor. 34-37. C o n ~ u g h Road.
t Central. Hong Kong