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DATA SHEET
SAA7376
Digital servo processor and
Compact Disc decoder (CD7)
Product specifications 1998 Feb 26
Supersedes data of 1995 Nov 24
File under Integrated Circuits, IC01
Philips Semiconductors Product specifications
1998 Feb 26 2
Philips Semiconductors Product specifications
1 FEATURES
• Single-speed mode
• Full error correction strategy, t = 2 and e = 4
• Full CD graphics interface
• All standard decoder functions implemented digitally on
chip 2 GENERAL DESCRIPTION
• FIFO overflow concealment for rotational shock The SAA7376 is a single chip combining the functions of a
resistance CD decoder IC and digital servo IC. The decoder part is
• Digital audio interface (EBU), audio only based on the SAA7345 (CD6) with an improved error
• 2 and 4 times oversampling integrated digital filter, correction strategy. The servo part is based on the
including fs mode TDA1301T (DSIC2) with improvements incorporated,
extra features have also been added.
• Audio data peak level detection
• Kill interface for DAC deactivation during digital silence Supply of this Compact Disc IC does not convey an implied
license under any patent right to use this IC in any
• All TDA1301 (DSIC2) digital servo functions, plus extra
Compact Disc application.
high-level functions
• Low focus noise
• Improved playability on ABEX TCD-721R, TCD-725 and
TCD-714 discs
• Automatic closed loop gain control available for focus
and radial loops
• Pulsed sledge support
• Microcontroller loading LOW
• High-level servo control option
• High-level mechanism monitor
• Communication may be via TDA1301/SAA7345
compatible bus or I2C-bus
• On-chip clock multiplier allows the use of 8.4672 MHz
crystal.
4 ORDERING INFORMATION
TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
SAA7376 QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm); SOT393-1
body 14 × 14 × 2.7 mm
1998 Feb 26 3
Philips Semiconductors Product specifications
5 BLOCK DIAGRAM
6 3 4 5 7 10 1 12 16 2 19 32 39 49 56 30 47 59
8
R1
PRE- CONTROL
9 ADC 26
PROCESSING FUNCTION
R2 RA
OUTPUT 27
FO
STAGES
28
Vref SL
11
VRH
GENERATOR
CONTROL
PART 64
52
SCL LDON
51
SDA MICROCONTROLLER
53 INTERFACE
RAB
54
SILD SAA7376
15
HFIN 33
DIGITAL
MOTO1
17 PLL MOTOR
HFREF 34
CONTROL
FRONT END MOTO2
14
ISLICE
Iref 18
EFM
20 DEMODULATOR
TEST1 ERROR
23 CORRECTOR
TEST2 TEST
29 61
TEST3 FLAGS CFLG
SRAM
13
SELPLL
21 60
CRIN C2FAIL
22 AUDIO
CROUT
TIMING PROCESSOR
24 RAM
CL16
ADDRESSER
25
CL11
50 EBU 31
CL4 DOBM
INTERFACE
35
SBSY
36
SFSY
SUBCODE
38 PROCESSOR
SUB PEAK
37 DETECT
RCK
48
SCLK
DECODER 46
58 WCLK
MICRO- SERIAL DATA
STATUS 45
CONTROLLER INTERFACE
DATA
INTERFACE VERSATILE PINS
INTERFACE 44
KILL TEST4
57
RESET 62 63 42 41 40 43
MGD043
V1 V2 V3 V4 V5 KILL
1998 Feb 26 4
Philips Semiconductors Product specifications
6 PINNING
1998 Feb 26 5
Philips Semiconductors Product specifications
1998 Feb 26 6
Philips Semiconductors Product specifications
DDD3(C)
handbook, full pagewidth 58 STATUS
60 C2FAIL
57 RESET
SSD4
SSD3
64 LDON
61 CFLG
54 SILD
53 RAB
51 SDA
52 SCL
50 CL4
55 n.c.
63 V2
62 V1
59 V
56 V
49 V
V 1 48 SCLK
SSA1
VDDA1 2 47 V
DDD2(P)
D1 3 46 WCLK
D2 4 45 DATA
D3 5 44 TEST4
VRL 6 43 KILL
D4 7 42 V3
R1 8 41 V4
SAA7376
R2 9 40 V5
IrefT 10 39 V
SSD2
VRH 11 38 SUB
VSSA2 12 37 RCK
SELPLL 13 36 SFSY
ISLICE 14 35 SBSY
HFIN 15 34 MOTO2
VSSA3 16 33 MOTO1
HFREF 17
Iref 18
VDDA2 19
TEST1 20
CRIN 21
CROUT 22
TEST2 23
CL16 24
CL11 25
RA 26
FO 27
SL 28
TEST3 29
VDDD1(P) 30
DOBM 31
VSSD1 32
MGD042
1998 Feb 26 7
Philips Semiconductors Product specifications
A simplified data flow through the decoder part is The crystal oscillator is a conventional 2 pin design
illustrated in Fig.6. operating between 8 and 35 MHz. This oscillator is
capable of operating with ceramic resonators and also with
7.1.2 CRYSTAL FREQUENCY SELECTION both fundamental and third overtone crystals. External
components should be used to suppress the fundamental
The SAA7376, which has an internal phase-locked loop output of the third overtone crystals as shown in Figs 3
clock multiplier, can be used with 33.8688, 16.9344 or and 4. Typical oscillation frequencies required are 8.4672,
8.4672 MHz crystal frequencies by setting register B and 16.9344 or 33.8688 MHz depending on the internal clock
SELPLL as shown in Table 1. The internal clock multiplier, settings used and whether or not the clock multiplier is
controlled by SELPLL, should only be used if a enabled.
8.4672 MHz crystal, ceramic resonator or external clock is
present. It should be noted that the CL11 output is a
5.6448 MHz clock if a 16.9344 MHz external clock is used.
SAA7376
Table 1 Crystal frequency selection
OSCILLATOR
CRYSTAL FREQUENCY
REGISTER B SELPLL
(MHz)
CROUT CRIN
00xx 0 33.8688 8.4672 MHz
00xx 1 8.4672
330 Ω
01xx 0 16.9344
100 kΩ
1998 Feb 26 8
Philips Semiconductors Product specifications
7.3 Data slicer and clock regenerator The master counter is only reset if:
The SAA7376 has an integrated slice level comparator • A sync coincidence detected; sync pattern occurs
which can be clocked by the crystal frequency clock, or 588 ±1 EFM clocks after the previous sync pattern
8 times the crystal frequency clock (if SELPLL is set HIGH • A new sync pattern is detected within ±6 EFM clocks of
while using an 8.4672 MHz crystal, and register 4 is set its expected position.
to 0xxx). The slice level is controlled by an internal current
The sync coincidence signal is also used to generate the
source applied to an external capacitor under the control
PLL lock signal, which is active HIGH after 1 sync
of the Digital Phase-Locked Loop (DPLL).
coincidence found, and reset LOW if, during 61
Regeneration of the bit clock is achieved with an internal consecutive frames, no sync coincidence is found. The
fully digital PLL. No external components are required and PLL lock signal can be accessed via the SDA or STATUS
the bit clock is not output. The PLL has two registers pins selected by register 2 and 7.
(8 and 9) for selecting bandwidth and equalization.
Also incorporated in the demodulator is a Run Length 2
For certain applications an off-track input is necessary. (RL2) correction circuit. Every symbol detected as RL2 will
This is internally connected from the servo part (its polarity be pushed back to RL3. To do this, the phase error of both
can be changed by the foc_parm1 parameter), but may be edges of the RL2 symbol are compared and the correction
input via the V1 pin if selected by register C. If this flag is is executed at the side with the highest error probability.
HIGH, the SAA7376 will assume that its servo part is
following on the wrong track and will flag all incoming HF 7.4.2 EFM DEMODULATION
data as incorrect.
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
7.4 Demodulator
7.4.1 FRAME SYNC PROTECTION
A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data.
crystal
clock
2.2 kΩ HFIN
HF
input
2.2 nF 47 pF D Q
HFREF
22 kΩ DPLL
1/2VDD
Iref
22 nF 100 µA
VSSA VSS
ISLICE
100 nF VDD
MGA368 - 1
VSSA 100 µA
1998 Feb 26 9
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1998 Feb 26
Philips Semiconductors
handbook, full pagewidth
decoder (CD7)
Digital servo processor and Compact Disc
1
V4
0
SBSY
CD GRAPHICS
SFSY
0 : reg D = xx01 INTERFACE
SUB
V4 SUBCODE MICROCONTROLLER
SDA
INTERFACE reg F INTERFACE
SUBCODE
PROCESSOR EBU
DOBM
INTERFACE
reg A
1 : reg 3 = xx10
(1fs mode)
0 : reg 3 ≠ xx10 1 : no pre-emphasis detected
FIFO OR reg D = 01xx (de-emphasis signal at V5)
0 : pre-emphasis detected
AND reg D ≠ 01xx
1 PHASE 1
1 SCLK
ERROR FADE/MUTE/ DIGITAL 0 COMPENSATION 0 I2S-BUS WCLK
CORRECTOR INTERPOLATE FILTER 0 INTERFACE DATA
reg 3
reg 3 MGD039
KILL DE-EMPHASIS
KILL V3 FILTER
Product specifications
reg C
SAA7376
Fig.6 Simplified data flow of decoder functions.
Philips Semiconductors Product specifications
handbook, full pagewidth SF0 SF1 SF2 SF3 SF97 SF0 SF1
SBSY
SFSY
RCK
SFSY
RCK
SFSY
RCK
P Q R S T U V W
SUB MBG410
1998 Feb 26 11
Philips Semiconductors Product specifications
F8 F1 F2 F3 F4 F5 F6 F7 F8 F1
MGD037
1998 Feb 26 12
Philips Semiconductors Product specifications
1998 Feb 26 13
Philips Semiconductors Product specifications
7.7.3 CONCEALMENT Fade: activates a 128 stage counter which allows the
signal to be scaled up/down by 0.07 dB steps
A 1-sample linear interpolator becomes active if a single
sample is flagged as erroneous but cannot be corrected. 128 = full scale.
The erroneous sample is replaced by a level midway 120 = −0.5 dB (i.e. full scale if oversampling filter
between the preceding and following samples. Left and used).
right channels have independent interpolators. If more 32 = −12 dB.
than one consecutive non-correctable sample is found, the
last good sample is held. A 1-sample linear interpolation is 0 = mute.
then performed before the next good sample (see Fig.10).
7.7.5 PEAK DETECTOR
7.7.4 MUTE, FULL SCALE, ATTENUATION AND FADE The peak detector measures the highest audio level
A digital level controller is present on the SAA7376 which (absolute value) on positive peaks for left and right
performs the functions of soft mute, full scale, attenuation channels. The 8 most significant bits are output in the
and fade; these are selected via register 0: Q-channel data in place of the CRC bits. Bits 81 to 88
contain the left peak value (bit 88 = MSB) and
Mute: signal reduced to 0 in a maximum of 128 steps; bits 89 to 96 contain the right peak value (bit 96 = MSB).
3 ms. The values are reset after reading Q-channel data via
Attenuate: signal scaled by −12 dB. SDA.
Full scale: ramp signal back to 0 dB level. From mute
takes 3 ms.
1998 Feb 26 14
Philips Semiconductors Product specifications
Note
1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated
then the first 18 bits contain data.
1998 Feb 26 15
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1998 Feb 26
Philips Semiconductors
decoder (CD7)
Digital servo processor and Compact Disc
SCLK
DATA 1 0 15 14 1 0 15 14
LEFT CHANNEL DATA (WCLK NORMAL POLARITY)
WCLK
MGD036
SCLK
DATA 0 17 0 17
LEFT CHANNEL DATA
WCLK
Product specifications
MGD035
SAA7376
Fig.12 EIAJ data format (18-bit word length shown).
Philips Semiconductors Product specifications
Table 5 Format
FUNCTION BITS DESCRIPTION
Sync 0 to 3 −
Auxiliary 4 to 7 not used; normally zero
Error flags 4 CFLG error and interpolation flags when selected by register A
Audio sample 8 to 27 first 4 bits not used (always zero). 2’s compliment. LSB = bit 12, MSB = bit 27
Validity flag 28 valid = logic 0
User data 29 used for subcode data (Q-to-W)
Channel status 30 control bits and category code
Parity bit 31 even parity for bits 4 to 30
1998 Feb 26 17
Philips Semiconductors Product specifications
7.10 KILL circuit 2 pin kill: KILL active LOW indicates silence detected on
left channel. V3 active LOW indicates silence detected
The KILL circuit detects digital silence by testing for an
on right channel.
all-zero or all-ones data word in the left or right channel
before the digital filter. The output is switched active LOW
7.11 The VIA interface
when silence has been detected for at least 250 ms, or if
mute is active. Two modes are available which can be The SAA7376 has five pins that can be reconfigured for
selected by register C: different applications (see Table 8).
1 pin kill: KILL active LOW indicates silence detected on
both left and right channels.
1998 Feb 26 18
Philips Semiconductors Product specifications
22 kΩ 22 kΩ
MOTO1 + + MOTO2
M
– –
10 nF 10 nF
VSS VSS
VDD
22 kΩ
22 kΩ
MOTO1 +
M VSS
–
22 kΩ 10 nF
22 kΩ
VSS VSS
22 kΩ
VDD
MGA363 - 1
MOTO1
MOTO2
10 Ω 100 nF
MOTO1 MOTO2
VSS MGA365 - 2
1998 Feb 26 19
Philips Semiconductors Product specifications
MOTO1
MOTO2
V4
V5
Accelerate Brake
V4 V5
10 Ω 100 nF
MOTO1 MOTO2
VSS MGA364 - 2
1998 Feb 26 20
Philips Semiconductors Product specifications
7.12.1.4 CDV/CAV output mode This voltage can be programmed as a percentage of the
maximum possible voltage, via register 6, to limit current
In the CDV motor mode, the FIFO position will be put in
drain during start and stop. The following power limits are
pulse-width modulated form on the MOTO1 pin (carrier
possible;
frequency = 300 Hz). The PLL frequency signal will be put
in pulse-density modulated form (carrier 100% (no power limit), 75%, 50%, or 37% of maximum.
frequency = 4.23 MHz) on the MOTO2 pin. The integrated
motor servo is disabled in this mode. 7.12.3 LOOP CHARACTERISTICS
The PWM signal on MOTO1 corresponds to a total The gain and crossover frequencies of the motor control
memory space of 20 frames, therefore the nominal FIFO loop can be programmed via registers 4 and 5.
position (half full) will result in a PWM output of 60%. The following parameter values are possible;
Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32
7.12.2 SPINDLE MOTOR OPERATING MODES Crossover frequency f4: 0.5 Hz, 0.7 Hz, 1.4 Hz, 2.8 Hz
The operation modes of the motor servo is controlled by Crossover frequency f3: 0.85 Hz, 1.71 Hz, 3.42 Hz.
register 1 (see Table 9).
In the SAA7376 decoder there is an anti-wind-up mode for 7.12.4 FIFO OVERFLOW
the motor servo, selected via register 1. When the If FIFO overflow occurs during Play mode (e.g. as a result
anti-wind-up mode is activated the motor servo integrator of motor rotational shock), the FIFO will be automatically
will hold if the motor output saturates. reset to 50% and the audio interpolator tries to conceal as
much as possible to minimise the effect of data loss.
7.12.2.1 Power limit
In start mode 1, start mode 2, stop mode 1 and stop
mode 2, a fixed positive or negative voltage is applied to
the motor.
1998 Feb 26 21
Philips Semiconductors Product specifications
MGA362 - 2
G
f4 f3 BW f
7.13 Servo part current generated by the external resistor on IrefT. In the
application VRL is connected to VSSA1. The maximum input
7.13.1 DIODE SIGNAL PROCESSING
currents for a range of resistors is given Table 10.
The photo detector in conventional two-stage three-beam
compact disc systems normally contains six discrete Table 10 Maximum current input
diodes. Four of these diodes (three for single Foucault
DIODE INPUT CURRENT RANGE
systems) carry the central aperture signal (CA) while the RIrefT (kΩ)
other two diodes (satellite diodes) carry the radial tracking D1 TO D4 (µA) R1 AND R2 (µA)
information. The CA signal is processed into an HF signal
220 10.909 5.455
(for the decoder function) and LF signal (information for the
focus servo loop) before it is supplied to the SAA7376. 240 10.000 5.000
270 8.889 4.444
The analog signals from the central and satellite diodes
are converted into a digital representation using 300 8.000 4.000
analog-to-digital converters (ADCs). The ADCs are 330 7.273 3.636
designed to convert unipolar currents into a digital code. 360 6.667 3.333
The dynamic range of the input currents is adjustable
390 6.154 3.077
within a given range, which is dependent on the value of
the external resistor connected to pin IrefT. The maximum 430 5.581 2.791
current for the central diodes and satellite diodes is given 470 5.106 2.553
in the following formulae; 510 4.706 2.353
2.4 × 10 6 560 4.286 2.143
I in ( max, central ) = ------------------------ µA 620 3.871 1.935
R IrefT
1998 Feb 26 22
Philips Semiconductors Product specifications
D1
D1 D2 D1
D2
D3
D3
D2 D4 D3
D4
MBG422
1998 Feb 26 23
Philips Semiconductors Product specifications
7.13.3 FOCUS SERVO SYSTEM action of the PID can be switched at the same time as the
gain switching is performed.
7.13.3.1 Focus start-up
Five initially loaded coefficients influence the start-up 7.13.3.6 Focus automatic gain control loop
behaviour of the focus controller. The automatically
The loop gain of the focus control loop can be corrected
generated triangle voltage can be influenced by
automatically to eliminate tolerances in the focus loop.
3 parameters; for height (ramp_height) and DC offset
This gain control injects a signal into the loop which is used
(ramp_offset) of the triangle and its steepness
to correct the loop gain. Since this decreases the optimum
(ramp_incr).
performance, the gain control should only be activated for
For protection against false focus point detections two a short time (for example, when starting a new disc).
parameters are available which are an absolute level on
the CA-signal (CA_start) and a level on the FEn signal 7.13.4 RADIAL SERVO SYSTEM
(FE_start). When this CA level is reached the FOK signal
7.13.4.1 Level initialization
becomes true.
During start-up an automatic adjustment procedure is
If the FOK signal is true and the level on the FEn signal is
activated to set the values of the radial error gain (re_gain),
reached, the focus PID is enabled to switch on when the
offset (re_offset) and satellite sum gain (sum_gain) for TPI
next zero crossing is detected in the FEn signal.
level generation. The initialization procedure runs in a
radial open loop situation and is ≤ 300 ms. This start-up
7.13.3.2 Focus position control loop
time period may coincide with the last part of the motor
The focus control loop contains a digital PID controller start-up time period.
which has 5 parameters which are available to the user. Automatic gain adjustment: as a result of this
These coefficients influence the integrating (foc_int), initialization the amplitude of the RE signal is adjusted to
proportional (foc_lead_length, part of foc_parm3) and within ±10% around the nominal RE amplitude.
differentiating (foc_pole_lead, part of foc_parm1) action of
Offset adjustment: the additional offset in RE due to the
the PID and a digital low-pass filter (foc_pole_noise, part
limited accuracy of the start-up procedure is less than
of foc_parm2) following the PID. The fifth coefficient
± 50 nm.
foc_gain influences the loop gain.
TPI level generation: the accuracy of the initialization
7.13.3.3 Drop-out detection procedure is such that the duty factor range of TPI
becomes 0.4 < duty factor < 0.6 (definition of duty
This detector can be influenced by one parameter factor = TPI HIGH/TPI period).
(CA_drop). The FOK signal will become false and the
integrator of the PID will hold if the CA signal drops below
7.13.4.2 Sledge control
this programmable absolute CA level. When the FOK
signal becomes false it is assumed, initially, to be caused The microcontroller can move the sledge in both directions
by a black dot. via the steer sledge command.
7.13.3.4 Focus loss detection and fast restart 7.13.4.3 Tracking control
Whenever FOK is false for longer than approximately The actuator is controlled using a PID loop filter with user
3 ms, it is assumed that the focus point is lost. A fast defined coefficients and gain. For stable operation
restart procedure is initiated which is capable of restarting between the tracks, the S-curve is extended over ± 0.75 of
the focus loop within 200 to 300 ms depending on the the track. On request from the microcontroller, S-curve
programmed coefficients of the microcontroller. extension over ± 2.25 tracks is used, automatically
changing to access control when exceeding those
7.13.3.5 Focus loop gain switching 2.25 tracks.
The gain of the focus control loop (foc_gain) can be Both modes of S-curve extension make use of a
multiplied by a factor of 2 or divided by a factor of 2 during track-count mechanism. In this mode, track counting
normal operation. The integrator value of the PID is results in an ‘automatic return-to-zero track’, to avoid
corrected accordingly. The differentiating (foc_pole_lead) major music rhythm disturbances in the audio output for
improved shock resistance.
1998 Feb 26 24
Philips Semiconductors Product specifications
The sledge is continuously controlled, or provided with 7.13.4.5 Radial automatic gain control loop
step pulses to reduce power consumption using the
The loop gain of the radial control loop can be corrected
filtered value of the radial PID output. Alternatively, the
automatically to eliminate tolerances in the radial loop.
microcontroller can read the average voltage on the radial
This gain control injects a signal into the loop which is used
actuator and provide the sledge with step pulses to reduce
to correct the loop gain. Since this decreases the optimum
power consumption. Filter coefficients of the continuous
performance, the gain control should only be activated for
sledge control can be preset by the user.
a short time (for example, when starting a new disc).
7.13.4.4 Access This gain control differs from the level initialization.
The level initialization should be performed first.
The access procedure is divided into two different modes
The disadvantage of using the level initialization without
(see Table 11), depending on the requested jump size.
the gain control is that only tolerances from the front-end
are reduced.
Table 11 Access modes
ACCESS ACCESS 7.13.5 OFF-TRACK COUNTING
JUMP SIZE(1)
TYPE SPEED The track position signal (TPI) is a flag which is used to
Actuator jump 1 - brake_distance decreasing indicate whether the radial spot is positioned on the track,
velocity with a margin of ±1⁄4 of the track-pitch. In combination with
Sledge jump brake_distance - 32768 maximum the radial polarity flag (RP) the relative spot position over
power to the tracks can be determined. These signals are, however,
sledge(1) afflicted with some uncertainties caused by;
• Disc defects such as scratches and fingerprints
Note
• The HF information on the disc, which is considered as
1. Microcontroller presettable. noise by the detector signals.
In order to determine the spot position with sufficient
The access procedure makes use of a track counting
accuracy, extra conditions are necessary to generate a
mechanism, a velocity signal based on a fixed number of
track loss signal (TL) and an off-track counter value. These
tracks passed within a fixed time interval, a velocity set
extra conditions influence the maximum speed and this
point calculated from the number of tracks to go and a user
implies that, internally, one of the following three counting
programmable parameter indicating the maximum sledge
states is selected;
performance.
1. Protected state: used in normal play situations. A good
If the number of tracks remaining is greater than the protection against false detection caused by disc
brake_distance then the sledge jump mode should be defects is important in this state.
activated, or, the actuator jump should be performed.
2. Slow counting state: used in low velocity track jump
The requested jump size together with the required sledge
situations. In this state a fast response is important
breaking distance at maximum access speed defines the
rather than the protection against disc defects (if the
brake_distance value.
phase relationship between TL and RP of 1⁄2π radians
During the actuator jump mode, velocity control with a PI is affected too much, the direction cannot then be
controller is used for the actuator. The sledge is then determined accurately).
continuously controlled using the filtered value of the radial 3. Fast counting state: used in high velocity track jump
PID output. All filter parameters (for actuator and sledge) situations. Highest obtainable velocity is the most
are user programmable. important feature in this state.
In the sledge jump mode maximum power (user
programmable) is applied to the sledge in the correct
direction while the actuator becomes idle (the contents of
the actuator integrator leaks to zero just after the sledge
jump mode is initiated).
1998 Feb 26 25
Philips Semiconductors Product specifications
sat2 MBG421
A defect detection circuit is incorporated into the been crossed during time defined by jumpwatchtime
SAA7376. If a defect is detected, the radial and focus error parameter.
signals may be zeroed, resulting in better playability. The 6. Autosequencer state change.
defect detector can be switched off, applied only to focus
control or applied to both focus and radial controls under 7. Autosequencer error.
software control (part of foc_parm1). 8. Subcode interface blocked: the internal decoder
interface is being used.
The defect detector (see Fig.20) has programmable set
points selectable by the parameter defect_parm. It should be noted that if the STATUS pin output is selected
via register 2 and either the microcontroller writes a
7.13.7 OFF-TRACK DETECTION different value to register 2 or the decoder interface is
enabled then the STATUS output will change.
During active radial tracking, off-track detection has been
realised by continuously monitoring the off-track counter 7.13.8.2 Decoder interface
value. The off-track flag becomes valid whenever the
off-track counter value is not equal to zero. Depending on The decoder interface allows registers 0 to F to be
the type of extended S-curve, the off-track counter is reset programmed and subcode Q-channel data to be read via
after 0.75 extend or at the original track in the 2.25 track servo commands. The interface is enabled/disabled by the
extend mode. preset latch command (and the xtra_preset parameter).
7.13.8.1 Interrupt mechanism and STATUS pin Three watchdogs are present:
The STATUS pin is an output which is active LOW, its 1. Focus: detects focus drop out of longer than 3 ms, sets
output is selected by register 7 to be either the status bit focus lost interrupt, switches off radial and sledge
(active LOW) selected by register 2 (only available in servos, disables drive to disc motor.
4-wire bus mode) or the interrupt signal generated by the 2. Radial play: started when radial servo is on-track
servo part. mode and a first subcode frame is found. Detects
when maximum time between two subcode frames
8 signals from the interrupt status register are selectable
exceeds time set by playwatchtime parameter; then
from the servo part via the interrupt_mask parameter. The
sets radial error interrupt, switches radial and sledge
interrupt is reset by sending the read high-level status
servos off, puts disc motor in jump mode.
command. The 8 signals are as follows:
3. Radial jump: active when radial servo in long jump or
1. Focus lost: drop out of longer than 3 ms.
short jump modes. Detects when the off-track counter
2. Subcode ready. value decreases by less than 4 tracks between two
3. Subcode absolute seconds changed. readings (time interval set by jumpwatchtime
parameter); then sets radial jump error, switches radial
4. Subcode discontinuity detected: new subcode time
and sledge servos off to cancel jump.
before previous subcode time, or more than 10 frames
later than the previous subcode time. The focus watchdog is always active, the radial watchdogs
5. Radial error: during radial on-track, no new subcode are selectable via the radcontrol parameter.
frame occurs within time defined by playwatchtime
parameter. During radial jump, less than 4 tracks have
1998 Feb 26 26
Philips Semiconductors Product specifications
7.13.8.4 Automatic sequencers and timer interrupts During reset (i.e. RESET pin is held LOW) the RA, FO and
SL pins are high impedance.
Two automatic sequencers are implemented (and must be
initialized after power-on):
7.13.10 LASER INTERFACE
1. Autostart sequencer: controls the start-up of focus,
radial and motor. The LDON pin (open-drain output) is used to switch the
laser off and on. When the laser is on the output is high
2. Autostop sequencer: brakes the disc and shuts down
impedance. The action of the LDON pin is controlled by the
servos. xtra_preset parameter; the pin is automatically driven if the
When the automatic sequencers are not used it is possible focus control loop is active.
to generate timer interrupts, defined by the
time_parameter coefficient. 7.13.11 RADIAL SHOCK DETECTOR
The shock detector (see Fig.21) can be switched on during
7.13.8.5 High-level status normal track following, and detects within an adjustable
The read high-level status command can be used to obtain frequency whether disturbances in the radial spot position
the interrupt, decoder, autosequencer status registers and relative to the track exceed an adjustable level (controlled
the motor start time. Use of the read high-level status by shock_level). Every time the radial tracking error (RE)
command clears the interrupt status register, and exceeds this level the radial control bandwidth is switched
re-enables the subcode read via a servo command. to twice its original bandwidth and the loop gain is
increased by a factor of 4.
7.13.9 DRIVER INTERFACE The shock detection level is adjustable in 16 steps from
The control signals (pins RA, FO and SL) for the 0 to 100% of the traverse radial amplitude which is sent to
mechanism actuators are pulse density modulated. The an amplitude detection unit via an adjustable band-pass
modulating frequency can be set to either 1.0584 MHz filter (controlled by sledge_parm1); lower corner frequency
(DSD mode) or 2.1168 MHz; controlled via the xtra_preset can be set at either 0 or 20 Hz, and upper corner
parameter. An analog representation of the output signals frequency at 750 or 1850 Hz. The shock detector is
can be achieved by connecting a first-order low-pass filter switched off automatically during jump mode.
to the outputs.
1998 Feb 26 27
Philips Semiconductors Product specifications
7.14.1.1 Writing data to registers 0 to F It should be noted that SILD must be held HIGH; after
subcode read starts, the microcontroller may take as long
The sixteen 4-bit programmable configuration registers, as it wants to terminate the read operation; when enough
0 to F (see Table 12), can be written to via the subcode has been read (1 to 96 bits), terminate reading by
microcontroller interface using the protocol shown in pulling RAB LOW.
Fig.22.
Alternatively, the Q-channel subcode can be read using a
It should be noted that SILD must be held HIGH; A3 to A0
servo command as follows:
identifies the register number and D3 to D0 is the data; the
data is latched into the register on the LOW-to-HIGH • Use the read high-level status command to monitor the
transition of RAB. subcode ready signal.
• Send the read subcode command, and read the
7.14.1.2 Writing repeated data to registers 0 to F required number of bytes (up to 12).
The same data can be repeated several times (e.g. for a • Send the read high-level status command; to re-enable
fade function) by applying extra RAB pulses as shown in the decoder interface.
Fig.23. It should be noted that SCL must stay HIGH
between RAB pulses. 7.14.1.5 Behaviour of the SUBQREADY-I signal
When the CRC of the Q-channel word is good, and no
7.14.1.3 Reading decoder status information on SDA subcode is being read, the SUBQREADY-I status signal
There are several internal status signals, selected via will react as shown in Fig.26.
register 2, which can be made available on the SDA line; When the CRC is good and the subcode is being read, the
SUBQREADY-I: LOW if new subcode word is ready in timing in Fig.27 applies.
Q-channel register.
1998 Feb 26 28
Philips Semiconductors Product specifications
If t1 (SUBQREADY-I status LOW to end of subcode read 7.14.2 MICROCONTROLLER INTERFACE (I2C-BUS MODE)
is below 2.6 ms, then t2 = 13.1 ms (i.e. the microcontroller
can read all subcode frames if it completes the read Bytes are transferred over the interface in groups (i.e.
operation within 2.6 ms after the subcode is ready). If this servo commands) of which there are two types: write data
criterion is not met, it is only possible to guarantee that t3 commands and read data commands.
will be below 26.2 ms (approximately). The sequence for a write data command (that requires
If subcode frames with failed CRCs are present, the t2 and 3 data bytes) is as follows;
t3 times will be increased by 13.1 ms for each defective • Send START condition
subcode frame. • Send address 30H (write)
• Write command byte
7.14.1.6 Write servo commands
• Write data byte 1
A write data command is used to transfer data (a number
• Write data byte 2.
of bytes) from the microcontroller, using the protocol
shown in Fig.28. The first of these bytes is the command • Write data byte 3
byte and the following are data bytes; the number • Send STOP condition.
(between 1 and 7) depends on the command byte.
It should be noted that more than one command can be
It should be noted that RAB must be held LOW; the sent in one write sequence.
command or data is interpreted by the SAA7376 after the
HIGH-to-LOW transition of SILD; there must be a The sequence for a read data command (that reads 2 data
minimum time of 70 µs between SILD pulses. bytes) is as follows;
• Send START condition
7.14.1.7 Writing repeated data in servo commands • Send address 30H (write)
The same data byte can be repeated by applying extra • Write command byte
SILD pulses as shown in Fig.29. SCL must stay HIGH • Send STOP condition.
between the SILD pulses.
• Send START condition
7.14.1.8 Read servo commands • Send address 31H (read)
A read data command is used to transfer data (status • Read data byte 1
information) to the microcontroller, using the protocol • Read data byte 2
shown in Fig.30. The first byte written determines the type • Send STOP condition.
of command. After this byte a variable number of bytes can
be read. It should be noted that RAB must be held LOW; It should be noted that the timing constraints specified for
after the end of the command byte (LOW-to-HIGH the read and write servo commands must still be adhered
transition on SILD) there must be a delay of 70 µs before to.
reading data is started (i.e the next HIGH-to-LOW
transition on SILD); there must be a minimum time of 70 µs
between SILD pulses.
1998 Feb 26 29
Philips Semiconductors Product specifications
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller) A3 A2 A1 A0 D3 D2 D1 D0
SDA (SAA7376)
high-impedance
MGD034
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller) A3 A2 A1 A0 D3 D2 D1 D0
SDA (SAA7376)
high-impedance
MGD033
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller)
high-impedance
MGD032
1998 Feb 26 30
Philips Semiconductors Product specifications
RAB
(microcontroller)
SCL
(microcontroller)
CRC
SDA (SAA7376) OK Q1 Q2 Q3 Qn–2 Qn–1 Qn
STATUS MGD031
RAB
(microcontroller)
SCL
(microcontroller)
high
SDA (SAA7376) CRC OK CRC OK
impedance
MGD030
10.8 ms 15.4 ms
2.3
ms
READ start allowed
1998 Feb 26 31
Philips Semiconductors Product specifications
t2
t1 t3
RAB
(microcontroller)
SCL
(microcontroller)
SDA (SAA7376 ) Q1 Q2 Q3 Qn
MGD029
SCL
(microcontroller)
SDA D7 D6 D5 D4 D3 D2 D1 D0
(microcontroller)
command or data byte
SDA (SAA7376)
high-impedance
SILD
(microcontroller)
SDA
COMMAND DATA1 DATA2 DATA3
(microcontroller)
MGD028
1998 Feb 26 32
Philips Semiconductors Product specifications
SDA
COMMAND DATA1
(microcontroller)
MBG413
microcontroller write (full command)
SILD
handbook, full pagewidth
(microcontroller)
SCL
(microcontroller)
SDA (SAA7376) D7 D6 D5 D4 D3 D2 D1 D0
data byte
SILD
(microcontroller)
SDA
(microcontroller) COMMAND
MGD027
microcontroller read (full command)
1998 Feb 26 33
Philips Semiconductors Product specifications
1998 Feb 26 34
Philips Semiconductors Product specifications
1998 Feb 26 35
Philips Semiconductors Product specifications
1998 Feb 26 36
Philips Semiconductors Product specifications
Note
1. The initial column shows the power-on reset state.
1998 Feb 26 37
Philips Semiconductors Product specifications
Notes
1. These commands only available when internal decoder interface is enabled.
2. <peak_l> and <peak_r> bytes are clocked out LSB first.
3. Decoder status flag information in <dec_stat> is only valid when the internal decoder interface is enabled.
1998 Feb 26 38
Philips Semiconductors Product specifications
1998 Feb 26 39
Philips Semiconductors Product specifications
RAM POR
PARAMETER AFFECTS DETERMINES
ADDRESS VALUE
radcontrol 59H watchdog − enable/disable automatic radial off feature
chip_init − set-up − VRH level setting
enable/disable decoder interface
xtra_preset 4AH set-up 38H laser on/off
RA, FO and SL PDM modulating frequency
microcontroller communication to decoder part
cd6cmd 4DH decoder interface − decoder part commands
interrupt_mask 53H STATUS pin − enabled interrupts
seq_control 42H autosequencer − autosequencer control
focus_start_time 5EH autosequencer − focus start time
motor_start_time1 5FH autosequencer − motor start 1 time
motor_start_time2 60H autosequencer − motor start 2 time
radial_init_time 61H autosequencer − radial initialization time
brake_time 62H autosequencer − brake time
RadCmdByte 63H autosequencer − radial command byte
osc_inc 68H focus/radial AGC − AGC control
frequency of injected signal
phase_shift 67H focus/radial AGC − phase shift of injected signal
level1 69H focus/radial AGC − amplitude of signal injected
level2 6AH focus/radial AGC − amplitude of signal injected
agc_gain 6CH focus/radial AGC − focus/radial gain
1998 Feb 26 40
Philips Semiconductors Product specifications
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDD supply voltage note 1 −0.5 +6.5 V
VI(max) maximum Input voltage (any input) −0.5 VDD + 0.5 V
VO output voltage (any output) −0.5 +6.5 V
VDDdiff difference between VDDA and VDDD − ± 0.25 V
IO output current (continuous) − ± 20 mA
IIK DC input diode current (continuous) − ± 20 mA
Tamb operating ambient temperature −10 +70 °C
Tstg storage temperature −55 +125 °C
Ves electrostatic handling note 2 −2000 +2000 V
note 3 −200 +200 V
Notes
1. All VDD and VSS connections must be made externally to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
9 OPERATING CHARACTERISTICS
VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified.
1998 Feb 26 41
Philips Semiconductors Product specifications
1998 Feb 26 42
Philips Semiconductors Product specifications
1998 Feb 26 43
Philips Semiconductors Product specifications
1998 Feb 26 44
Philips Semiconductors Product specifications
1998 Feb 26 45
Philips Semiconductors Product specifications
1998 Feb 26 46
Philips Semiconductors Product specifications
SBSY
tSFSYH
SFSY
(4-wire mode)
tW(SFSY) tcy(frame)
SFSY
(3-wire mode)
tSFSYL
SFSY
0.8 V
td(SFSY−RCK)
tr tf
VDD – 0.8 V
RCK
0.8 V
td(SFSY−SUB) th(RCK−SUB)
td(RCK−SUB)
VDD – 0.8 V
SUB
0.8 V
MBG414
1998 Feb 26 47
Philips Semiconductors Product specifications
V – 0.8 V
DD
SCLK
0.8 V
t su
th
V DD – 0.8 V
WCLK
DATA
0.8 V
MGD026
1998 Feb 26 48
Philips Semiconductors Product specifications
Notes
1. Negative set-up time means that the data may change after clock transition.
1998 Feb 26 49
Philips Semiconductors Product specifications
tr tf
V DD – 0.8 V
RAB
tr tf
t CH 0.8 V
V DD – 0.8 V
t dRD
SCL
0.8 V t dRZ
t CL
t PD
V DD – 0.8 V
SDA (SAA7376)
high-impedance
0.8 V
MGD025
Fig.33 4-wire bus microcontroller timing; read mode (Q-channel subcode and decoder status information).
tr t CH tf
handbook, full pagewidth
t suCR V DD – 0.8 V
RAB
0.8 V
t t CL
tf CH tr
VDD – 0.8 V
SCL
0.8 V
t CL t t dWZ
hD
t suD
V – 0.8 V
DD
SDA
(microcontroller) high-impedance
0.8 V MBG405
1998 Feb 26 50
Philips Semiconductors Product specifications
SILD
0.8 V
thCLR
tsCLR
VDD – 0.8 V
SCL
0.8 V
tdLD tPD tdLZ
VDD – 0.8 V
SDA
(SAA7376)
0.8 V
MGD024
VDD – 0.8 V
SCL
0.8 V
thCL
tsD tL
tdWZ
thD
VDD – 0.8 V
SDA
(microcontroller)
0.8 V
MBG416
1998 Feb 26 51
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1998 Feb 26
13 APPLICATION INFORMATION
Philips Semiconductors
decoder (CD7)
Digital servo processor and Compact Disc
+V
+V microcontroller +V
interface
2.2 Ω VDDD
4.7 4.7
kΩ kΩ
100
33 µF 100
nF
nF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
+V
LDON
V2
V1
CFLG
C2FAIL
VDDD3C
STATUS
RESET
VSSD4
n.c.
SILD
RAB
SCL
SDA
CL4
VSSD3
7 2.2
LDON
Ω
1 48 2.2 Ω VDDD
33 100 VSSA1
VDDA SCLK
µF nF
2 VDDA1 VDDD2(P) 47 100 nF
6 3 46
D2 D1 WCLK to DAC
3 220 pF 4 45
D3 D2 DATA
1 100 kΩ 220 pF 5 44
D4 D3 TEST4
220 pF 6 43
D1 VRL KILL
4 220 pF 7 42
D4 V3
100 kΩ 220 pF 8 41
D5 5 R1 V4
2 220 pF 9 SAA7376 40
D6 R2 V5
10 39
TDA1300 IrefT VSSD2
52
(3) 270 11 38
VRH SUB
kΩ 12 37 MOTOR
VSSA2 RCK to CD INTERFACE
13 36 graphics
SELPLL SFSY
100 22 14 35
nF kΩ ISLICE SBSY
15 34
HFIN MOTO2
VDDD1(P)
VDDA 16 33
9 VSSA3 MOTO1
CROUT
RFE
HFREF
VDDA2
VSSD1
TEST1
TEST2
TEST3
DOBM
CRIN
2.2 nF 2.2 kΩ
CL16
CL11
Iref
RA
FO
SL
47 100
pF nF
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(1) 22 nF VDD
to power to DOBM
amplifiers transformer
(2)
2.2 Ω
Product specifications
handbook, full pagewidth
SAA7376
connected between pin 18 and ground. MGD023
14 PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm SOT393-1
y
X
48 33
49 32 ZE
e
A2
E HE A
A1 (A 3)
wM θ
Lp
bp
pin 1 index L
64 17 detail X
1 16
w M v M A
e bp ZD
D B
HD v M B
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
96-05-21
SOT393-1 MS-022
97-08-04
1998 Feb 26 53
Philips Semiconductors Product specifications
CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Feb 26 54
Philips Semiconductors Product specifications
16 DEFINITIONS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Feb 26 55
Philips Semiconductors – a worldwide company
Argentina: see South America Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +31 40 27 82785, Fax. +31 40 27 88399
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Tel. +64 9 849 4160, Fax. +64 9 849 7811
Fax. +43 160 101 1210 Norway: Box 1, Manglerud 0612, OSLO,
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, Tel. +47 22 74 8000, Fax. +47 22 74 8341
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Philippines: Philips Semiconductors Philippines Inc.,
Belgium: see The Netherlands 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Brazil: see South America
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, Tel. +48 22 612 2831, Fax. +48 22 612 2327
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102 Portugal: see Spain
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Romania: see Italy
Tel. +1 800 234 7381 Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
China/Hong Kong: 501 Hong Kong Industrial Technology Centre, Tel. +7 095 755 6918, Fax. +7 095 755 6919
72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +852 2319 7888, Fax. +852 2319 7700 Tel. +65 350 2538, Fax. +65 251 6500
Colombia: see South America Slovakia: see Austria
Czech Republic: see Austria Slovenia: see Italy
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
Tel. +45 32 88 2636, Fax. +45 31 57 0044 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +27 11 470 5911, Fax. +27 11 470 5494
Tel. +358 9 615800, Fax. +358 9 61580920 South America: Al. Vicente Pinzon, 173, 6th floor,
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, 04547-130 SÃO PAULO, SP, Brazil,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Spain: Balmes 22, 08007 BARCELONA,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Tel. +34 3 301 6312, Fax. +34 3 301 4107
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Tel. +46 8 632 2000, Fax. +46 8 632 2745
Hungary: see Austria Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 488 3263
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
Tel. +91 22 493 8541, Fax. +91 22 493 0966 TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Indonesia: see Singapore Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +66 2 745 4090, Fax. +66 2 398 0793
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, Tel. +90 212 279 2770, Fax. +90 212 282 6707
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +1 800 234 7381
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Uruguay: see South America
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880 Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +9-5 800 234 7381 Tel. +381 11 625 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Printed in The Netherlands 545102/00/02/pp56 Date of release: 1998 Feb 26 Document order number: 9397 750 03318