Proceedings of the 18th International Symposium on Power Semiconductor Devices & IC's
June 4-8, 2006 Naples, Italy
High Voltage (up to 20V) Devices Implementation
in 0.13 un BiCMOS Process Technology for
System-On-Chip (SOC) Design
Robert Pan, Bob Todd, Pinghai Hao, Robert Higgins, Derek Robinson, Vlad Drobny, Weidong Tian, Jianglin Wang,
Jozef Mitros, Mike Huber, Sateesh Pillai and Sameer Pendharkar
Texas Instruments Inc., 12500 TI Boulevard, MS 971, Dallas, TX 75243, USA
Phone: (972)995-9338; Fax: (972)995-9010; Email: rpan@ti.com
Abstract
This paper describes the integration of the 20V
complementary drain-extended MOS (DECMOS) and
fully isolated drain-extended NMOS (DENMOS)
transistors into a high-volume 0. 13um CMOS
technology with two additional masks. The 20V devices
were optimized for Rsp-BVdss performance without
compromising the advanced 1.5V CMOS performance
in the 0.35um pitch copper, low-K dielectric process
flow. This cost-effective process is very competitive for
the power management (PM) chip design of portable
devices.
Introduction
Today's mobile phone market has become one of
the fastest growing and large scale semiconductor
markets [1]. The competition is extremely high due to
the constant demands of more functionality while
maintaining long battery lifetime, shorter time to
market schedule, and lower cost [2] [3].
The evolution of the cellular phone over the past 10
years has increased the performance, feature, and
functionality demands in the same or smaller die area.
The power management (PM) die in a typical cellular
phone is responsible for the power up control as well as
providing various voltages to other dies in the phone
and for converting the audio to digital signals and vice
versa. This necessitates the integration of high density
logic circuits along with high voltage and power analog
circuits. Present day demands require the PM die to
have more than l00Kgates of logic for audio digital
processing and 20V devices for high voltage
applications like the white LED and battery charger. So
highly integrated circuits become a very attractive
solution [4].
To take advantage of the high gate density of deep
submicron CMOS technologies for next generation
mobile phone power management circuit designs, 20V
devices have been added into a 0.13um CMOS digital
1-4244-971 5-0/06/$20.00 ©)2006 IEEE
process without changing the baseline CMOS
performance. With the compatible CMOS properties,
the existing digital library can be reused. This allowed
the designs to achieve the stringent requirement of
functions, power management, and cost in the shortest
time to market schedule. The dual-gate oxide, single
Poly BiCMOS technology provides 1.5V, 1.8V and
3.3V CMOS, 5V, 9V, 15V and 20V Drain-extended
MOS, Poly Resistors, Bipolar Transistors, high voltage
diodes, EEPROM, OTP EPROM, and high
performance capacitors. Table 1 lists some of the
critical parameters of the primary components
supported in this technology.
Process flow and Device Discussion
The process flow started with the same flow as the
0.13um digital CMOS flow. The high voltage devices
were integrated into the digital CMOS flow by adding
two mask levels and implants to form the N-drift and P-
drift regions. The N-drift and P-drift levels were done
after the N-region and P-region levels to avoid any
process deviation from the CMOS process conditions.
A mask level (N-buried) is needed to support the
isolated 20V DENMOS, 20V DEPMOS and vertical
NPN bipolar transistor. To avoid the screening oxide
loss during multiple implants and photo resist clean-up
processes, ultra-low oxide loss processes were used.
After above implants the process steps follow the
same process flow as the digital CMOS flow without
adding extra thermal cycle. The Silicide Block
processes were used to prevent silicidation of the drain-
extended region of the DEMOS transistors and the body
part of the non-silicided POLY resistors. A low
temperature TEOS was used as the silicide block film
without adding extra thermal budget to the flow. Due to
the very shallow source and drain junctions the silicide
block etch process has to be optimized to avoid silicon
loss which will cause source and drain junction leakage
problems. The back end processes are the same as the
base 0.13um technology with low-k dielectric and
copper processes.
 Figure 1 illustrates the cross-sectional views of the Table 1: Electrical parameters for 1.5V CMOS, high
20V DENMOS and DEPMOS. The N-buried implant is voltage (5 to 20V) Drain-extended MOS, Vertical NPN,
used for DEPMOS and isolated devices. The Poly Resistor, and Plate Capacitor
Rsp/BVdss figure-of-merit are 0.19mQ-cm2/26V for
both the isolated and the non-isolated 20V DENMOS CMOS Vtl Ion Ioff
and 0.6mQ-cm2/32V for the 20V DEPMOS. Figure 3 (volt) (uA/um) log(A/um)
and 5 show the good agreement between the measured 1.5V 0.59 550 -11.2
and simulated BVdss plots. An epitaxial growth process NMOS
was not used due to the extra thermal cycle and cost. 1.5V 0.52 200 -11.2
The N-drift and P-region profiles have to be engineered PMOS
to meet key parameter requirements and wafer level
reliability requirements (Figure 6) for both isolated and DEMOS Vtl BVdss Rsp
non-isolated 20V DENMOS. (volt) (volt) (mQ*cm2)
20V 0.85 26 0.19
The N-buried profile was optimized for both DENMOS
isolated 20V DENMOS and 20V DEPMOS. The P-drift 20V 0.85 32 0.60
and N-region were engineered for DEPMOS for best DEPMOS
device performance. Figures 2 and 4 show the I-V 20V Iso. 0.85 26 0.19
curve of 20V DENMOS and DEPMOS. With the DENMOS
implementation of 20V devices, other devices such as 15V 0.85 21 0.13
5V isolated DENMOS, 15V DECMOS, 9V Symmetric DENMOS
DENMOS and DEPMOS, Vertical NPN, Poly Resistors, 15V 0.85 22 0.42
EEPROM, and OTP EPROM are realized as well. DEPMOS
Combined with a high performance plate capacitor (one 9V Sym 0.70 21 0.28
extra mask level, SEM picture in Figure 7), this DENMOS
technology provides one of the best component sets and 9V Sym 0.70 22 0.98
cost-effective flows for SOC design. DEPMOS
5.5V Iso. 0.43 9 0.05
Conclusion DENMOS

High voltage (5 to 20V) devices were successfully Bipolar Hfe Va BVceo

implemented in a 0.13um BiCMOS flow with only two (volt) (volt)
extra mask levels and without introducing additional (volt) (ot
thermal cycling. Besides the high voltage devices other
analog components are supported in this technology for
NVPNcal 50 20 4.5

the best design integration and market flexibility.

Resistor Res.
Acknowledgment (Q/L)
Poly HSR 480
The authors would like to thank Shelby Dunn for
his bench testing support and the MSTD DCL team in Capacitor Density BV
device characterization. (fF/uM2) (volt)
Plate 1.4 25V
References Capacitor
[1] T. Efland et al., IEEE ISPSD'03, pp. 2-9
[2] M. Annese et al., IEEE ISPSD'05, pp. 363-366
[3] T. Letavic, et al., IEEE ISPSD'05, pp. 367-370
[4] 5. Pendharkar et al., IEEE ISPSD'04, pp. 419-422
 |Fig. 1 -A
BG

BG
|' | " ~ ~ ~ ~ 2.OE-03
S

S
|
PR
gio

||Gate

N-Region
[P-Drift
D

X
BG

BG

e U
40E03

1.0E-03
0.oE+00

3.3V, step -0.3V.

0
t

-5
--

-10
Vd (V)
Figure 4: 20V DEPMOS I-V curves, Vgs from 0 to -
-15 -20

Fig. 1-B N-Buried

20V DEPMOS BV Measured vs Simulated
Figure 1: Cross-sectional views of 20V DENMOS (Fig. 9
1-A), 20V DEPMOS (Fig. 1-B). -10 o Measured
-1 1 Simulated
.2 -12
5.OE-03 -o_13_ 2

-15
0 -10 -20 -30 -40
2.OE03 -
Vd (V)
1 .OE03 Figure 5: 20V DEPMOS BVdss plots measured vs.
simulated results.
0.OE+00
0 5 10 15 20
Vd (V)

Figure 2: 20V Isolated DENMOS I-V curves, Vgs from 100.00%

0 to 3.3V, step 0.3V. *d Idlin
* d gm
* Idsat (forward)

20V DENMOS BV Measured vs Simulated

10.00%

-100 Measured - , , ,-

-121-

x -13
, 1.00%
-14 ; X 10 100 1000 10000 100000
-15 Time (Sec)
0 5 10 15 20
1020 25
25 30
30
VdVd(V)
(V) Figure 6: Vds=20V)
(Vgs= 1.5V, 20V DENMOS for Idlin,bias
worst-case
degradation Idsat,stress
and
Figure 3: 20V DENMOS BVdss plots measured vs. Gm.
simulated results.
 -~~~~~~~~~~~I

Figure 7: SEM cross-sectional view of a Plate Capacitor

which is on top of the shallow trench isolation (STI)
structure for better substrate noise isolation.