CHAPTER 1

INTRODUCTION
1.1 GENERAL
Large inverters have traditionally satisfied the ever-increasing demand
of high power industrial applications, which currently extends from the tens to
hundreds of megawatts. Some examples of this fact are the medium voltage
range (2.3 to 13.8 KV) AC motor drives. Nowadays, it is problematic to
connect only one power semiconductor switch directly to the grid due to the
high voltage range. In order to solve this difficulty, a new type of power
converter has been introduced as a solution in high power applications.
Multilevel Converters use high speed switching components, avoiding the
problem of linking them directly to the grid by connecting single devices
among multiple DC levels. Multilevel Converters are found in many
applications; industrial motor drives, utility interfaces for renewable energy
systems (Photovoltaic, wind energy and fuel cells), flexible AC transmission
systems (FACTS), high voltage direct current transmission (HVDC), and
traction drives systems.
The advantages of this type of converter over the conventional two level
converter are:
 They can operate through a lower switching frequency.
 They draw input current with very low harmonic distortion.
 They produce a smaller common mode voltage, reducing the
stress in the motor bearings.
 They generate a staircase waveform as an output with much lower
harmonic distortion and dv/dt stresses.

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 These are some of the disadvantages when the number of levels in the
converter is increased:
 Unbalanced voltages are introduced.
 A greater amount of switches are required.
 A More complex controller is required due to the amount of
capacitors, which need to be balanced.
Several Multilevel topologies have been developed in the last few years. They
are more complex to modulate than the two level traditional converters
because of the number of switching alternatives that are available. In the last
three decades, three main converter topologies have emerged from the many
proposed:
 Diode Clamped (Neutral Clamped).
 Flying Capacitor (Capacitor Clamped).
 Cascade Voltage Source, Modular Multilevel Converter
(M2C).
Furthermore, several modulation techniques have been developed for
these converters. The modulation techniques include: Sinusoidal Pulse Width
Modulation (SPWM), selective harmonic elimination (SHE-PWM) and Space
Vector Modulation (SVM). The latest and most promising such topology for
high power applications is the Modular Multilevel Converter (M2C). Various
control and modulation methods have been suggested for this topology. The
aim of this master thesis project is to deeply investigate and evaluate one of
them, based on a carrier phase-shifted Pulse Width Modulation (PWM)
technique. Four different control topologies using Phase Shift PWM
techniques on Modular Multilevel Converters are studied and explored in this
work. These topologies could have three loops of control: Averaging Control

2
based on the currents inside the converter, Individual Balancing Control based
on the output current and capacitors voltages, and Arm Balancing Control
based on the voltage difference between the arms of the converter. Moreover
these topologies are easy to implement and do not demand high processing
levels. This project proposes a switching frequency that meets the two required
criteria: low enough to maintain cost feasibility, and high enough to reach a
harmonic performance target. Additionally, this work proposes an analytic
expression for the output voltage spectrum of the converter, which enables
prediction of harmonic performance.
1.2 MULTILEVEL CONVERTER TOPOLOGIES
In the present chapter of the work there is briefly description of the most
important topologies developed. In this regard, there will be mentioned their
advantages and disadvantages while discussing the different configurations
and their operation principles.
1.2.1 Diode Clamped Multilevel Converter
The first invention in multilevel converters was the so-called neutral
point clamped inverter. It was initially proposed as a three level inverter. It has
been shown that the principle of diode clamping can extended to any level. A
diode clamped leg circuit is shown in Fig.1.1.
The main advantages and disadvantages of this topology are:
Advantages:
 High efficiency for the fundamental switching frequency.
 The capacitors can be pre-charged together at the desired
voltage level.
 The capacitance requirement of the inverter is minimized
due to all phases sharing a common DC link.

3
Disadvantages:
 Packaging for inverters with a high number of levels could
be a problem due to the quadratic relation between the
number of diodes and the numbers of levels.
 Intermediate DC levels tend to be uneven without the
appropriate control making the real power transmission a
problem.
 Uneven rating in the diodes needed for the converter.

Fig.1.1 One phase 5-level structure of a Diode Clamped Inverter

Some of the applications using Multilevel Diode Clamped converters are:
 An interface between High voltage DC transmission line and AC
transmission line.
 High power medium voltage variable speed drives.
 Static VAR compensation.

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1.2.2 Flying Capacitor Multilevel Converter
As an alternative for the diode clamped inverter is the capacitor clamped
inverter proposed by Meynard and Foch, which shared many of the
advantages. The structure of the capacitor clamped inverter is similar to that of
the diode clamped converter. The main difference is that the diodes used for
the clamping are replaced by capacitors. A Flying capacitor Converter leg
circuit is shown in Figure1.2. For this topology the most common application
is static VAR generation.

Fig.1.2 One phase 5-level structure of a Flying Capacitor Inverter

The main advantages and disadvantages of this topology are:
Advantages:
 Control of the real and reactive power transmission.
 The large amounts of capacitors allow the inverter to
handle voltages drops and spikes, and short outages.

5
  Redundancies in the switching states are available in order
to balance the voltages in the capacitors.
Disadvantages:
 Efficiency is reduced for real power transmission.
 The large amount of capacitors is more expensive and
bulky than the diodes in the neutral point clamped inverter.
Also packaging is an issue in high number of level
converters.
 Initialization of the system and pre charging the capacitor
voltages is a complex procedure.
1.2.3 Cascade Voltage Source
The cascaded multilevel inverter is based on the series connection of
single leg or double leg (H bridges) inverters with separate DC sources or
capacitors. For each of these two types of configurations several states exist
regarding to the switches states. Figure 1.3, the single leg unit, has 2 states for
each of the two possible current(s) directions while the double unit has 4
states.

Fig.1.3 Single Leg Unit. Fig.1.4 Double Leg Unit

The main advantages and disadvantages of this topology are:

6
Advantages:
 The modularized structure allows easy packaging and storage.
 The quantity of possible voltage levels is more than double the
number of capacitors in the double leg unit (H Bridge).
 Lesser number of switching devices

Disadvantages:
 Separated DC sources or capacitor are required for each module.
 A More complex controller is required due to the amount of
capacitors, which need to be balanced.
1.3 OBJECTIVE
 To generate the Fifteen Level AC Output from the DC sources like
Batteries, Solar Panels.
 Reduce the number of switches in this proposed system.
 Reduce the Total Harmonics distortions (THD) in the output.
1.4 ORGANIZATION OF THE THESIS
This project is organized in Six Chapters.
 In Chapter 1, a brief introduction to the multilevel inverters, THD
associated with the inverter output voltage waveform is described.
 In Chapter 2, an introduction about the concepts of multi carrier
PWM modulation technique is presented.
 In Chapter 3, existing system 11 level inverter is presented.
 In Chapter 4, the proposed system operation is explained.
 In Chapter 5, discusses mat lab simulation results of the proposed
system.

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 In Chapter 6, summarizes the work described in the project,
general conclusions and the further development.

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 CHAPTER-2
LITERATURE REVIEW
1. Peng, M. Calais et all presented, “Multilevel converters for single-phase grid
connected photovoltaic systems— an overview,” in Proc. IEEE Int. Symp.
Ind. Electron, 1998, vol. 1, pp. 224–229
Multilevel voltage source inverters offer several advantages compared to their
conventional counterparts. By synthesising the AC output terminal voltage from
several levels of voltages, staircase waveforms can be produced, which approach
the sinusoidal waveform with low harmonic distortion, thus reducing filter
requirements. The need of several sources on the DC side of the converter makes
multilevel technology attractive for photovoltaic applications. This paper provides
an overview a different multilevel topologies and investigates their suitability for
single-phase grid connected photovoltaic systems. Several Transformerless
photovoltaic systems incorporating multilevel converters are compared regarding
issues such as component count and stress, system power rating and the influence
of the photovoltaic array earth capacitance.
2. Nasrudin A. Rahim et all presented, Single-Phase Seven-Level Grid-
Connected Inverter for Photovoltaic System
This paper proposes a single-phase seven-level inverter for grid-connected
photovoltaic systems, with a novel pulse width-modulated (PWM) control
scheme. Three reference signals that are identical to each other with an offset that
is equivalent to the amplitude of the triangular carrier signal were used to

9
 generate the PWM signals. The inverter is capable of producing seven levels of
output-voltage levels (Vdc, 2Vdc/3, Vdc/3, 0, -Vdc, -2Vdc/3, -Vdc/3) from the dc
supply voltage. A digital proportional-integral current-control algorithm was
implemented in a TMS320F2812 DSP to keep the current injected into the grid
sinusoidal. But the bidirectional switch induces switching losses. Also control
circuit is complex.
3. S. B. Kjaer et all presented, “A review of single-phase grid connected
inverters for photovoltaic modules,” IEEE Trans. Ind. Appl., vol. 41, no. 5,
pp. 1292–1306, Sep./Oct. 2005.
This review focuses on inverter technologies for connecting photovoltaic (PV)
modules to a single-phase grid. The inverters are categorized into four
classifications: 1) the number of power processing stages in cascade; 2) the type
of power decoupling between the PV module(s) and the single-phase grid; 3)
whether they utilizes a transformer (either line or high frequency) or not; and 4)
the type of grid-connected power stage. Various inverter topologies are presented,
compared, and evaluated against demands, lifetime, component ratings, and cost.
Finally, some of the topologies are pointed out as the best candidates for either
single PV module or multiple PV module applications. But in this topology
partial shading effect is high so that power losses are more.
4. P. K. Hinga, et all presented, “A new PWM inverter for photovoltaic power
generation system,” in Conf. Rec. IEEE Power Electron. Spec. Conf., 1994,
pp. 391–395.
In this paper, the authors propose a novel multi-step PWM inverter for a solar
power generation system. The circuit configuration is constructed by adding a bi-
directional switch to the conventional bridge type inverter circuit using the
isolated DC power supply for which the solar cell is very suitable. The new type
of PWM inverter presented has many features such as good output waveform,
small size of filter, low switching losses, and low acoustic noise. In this paper the

10
 authors describe the circuit configuration, control method and the characteristics
of the system, and they also investigate the relation between the inverter and the
solar cell characteristics. But voltage stress is high.

5. Y. Cheng, et all presented, “A comparison of diode-clamped and cascaded

multilevel converters for a STATCOM with energy storage,” IEEE Trans.
Ind. Electron., vol. 53, no. 5, pp. 3112– 3121, Oct. 2006.
The progression of distributed generation within a bulk power system will lead to
the need for greater control of transmission-line power flows. Static synchronous
compensators (STATCOMs) provide a power-electronics-based means of
embedded control of transmission-line voltage and power flows. The integration
of energy storage with a STATCOM can extend traditional STATCOM
capabilities to four-quadrant power flow control and transient stability
improvement. This paper discusses energy storage systems (ESSs) integrated with
conventional and multilevel bidirectional power converters for a hybrid
STATCOM/ESS. Conventional, diode-clamped, and cascaded multilevel
converter-based STATCOM/ESSs are developed, and their performances for a
variety of power system applications are compared using battery energy storage.
But needs additional input DC sources, cost will increase.
6. M. Saeedifard et all presented, “A space vector modulation strategy for a
back-to-back five-level HVDC converter system,” IEEE Trans. Ind.
Electron., vol. 56, no. 2, pp. 452–466, Feb. 2009.
The DC-capacitor voltage drift is the main technical drawback of a multilevel
diode-clamped converter (DCC) system. This paper proposes a space vector
modulation (SVM)-based switching strategy that takes advantage of the
redundant switching states of the SVM to counteract the voltage drift
phenomenon of a five-level DCC-based back-to-back high-voltage direct-current
(HVDC) converter system. The proposed strategy is based on online

11
 minimization of a quadratic cost function, associated with the voltage deviations
of the dc capacitors. The salient feature of the proposed strategy is that it enables
voltage balancing of the DC capacitors with no requirements for offline
calculations, additional controls, or auxiliary power circuitry. Performance of the
proposed SVM-based balancing strategy for a back-to-back HVDC converter
system, but voltage oscillation is high.

CHAPTER-III
EXISTING SYSTEM
3.1 THE EXISTING SYSTEM ELEVEN LEVEL INVERTER
This project presents a new high frequency modulation method for
multilevel converters. The proposed method provides a broad linear operating
range and can be digitally implemented with minimal computational effort.
This modulation method creates a phase voltage composed of a rectangular
component superimposed on the top of a quasi-square shaped reference
function. The reference functions are defined such that the utilization of the dc
link voltage is maximized in any modulation index, while the dv/dt of the
switches is always the minimum possible value. In order to implement the
proposed method, an update time that is much shorter than the fundamental
period is defined in the algorithm for updating the rectangular components of
the reference voltage. The high frequency rectangular component can then be
imposed on the reference function to generate the final switching function by
switching between two voltage levels during the time between two update
instances. Several experimental results are provided to evaluate the
performance of the proposed method and to compare its operation to
conventional methods.

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3.2 THE EXISTING SYSTEM CIRCUIT DIAGRAM

Fig 3.1 Eleven level inverter block diagram

3.3 EXISTING SYSTEM OPERATION
The purpose of this paper is to propose a new switching technique for
multilevel converters that maximizes the utilization of the dc link voltage

13
while limiting the phase voltage transitions to one voltage level, thus
minimizing the dv/dt of switches. The proposed modulation method features a
broad linear operating range relative to a defined modulation index.
Additionally, complex mathematical transformations and offline computations
are not used in this method. Moreover, this method can be applied to the
single-phase inverters as well. The proposed method is suited for digital
implementation and requires far less online computational effort than the SVM
method and less offline calculations and storage space comparing to the SHE
method. Furthermore, using the proposed method, each phase of the three
phase inverter can be controlled independently for the fault-tolerant purposes.
The inverter voltages generated using this method have THD levels
comparable to that of conventional methods such as SVM and SPWM. The
proposed modulation method can be implemented using a low cost digital
controller with minimal computational effort even for the multilevel converters
with large number of voltage levels. In addition, by using the proposed method
the maximum number of switching commutations is less than other high
frequency modulation methods. The proposed modulation method generates a
phase voltage comprised of a high frequency rectangular component riding on
top of a lower frequency quasi-square shaped reference function. A normalized
sample phase voltage generated by the proposed method for an 11-level
inverter is illustrated in Fig. 3.1. The fundamental amplitude of the generated
phase voltage depends on both the shape of the reference function and the duty
cycle of the high frequency rectangular component. These two parameters are
set corresponding to a modulation index defined between zero and one, in a
way that the proposed method provides a broad linear operation range for the
converter. In the proposed method, for an n-level inverter the entire

14
modulation range ([0, 1]) is divided into segments of the same length and a
specific reference function is defined. for each segment. The reference
functions are defined such that the utilization of the dc link voltage is
maximized in any modulation index, the dv/dt of the switches is always the
minimum possible value (one voltage level transition), and the even-order
harmonics of the phase voltages are eliminated naturally. To eliminate the
even order harmonics, the reference functions need to have half-wave
symmetry. Maximizing the fundamental component of the inverter voltage and
minimizing the dv/dt of the switches pose a tradeoff between how fast the
phase voltage can climb to the peak value and how long the peak value can be
kept constant. If the phase voltage climbs very fast to the peak value, the
duration of the peak value is increased, thus increasing the utilization of the dc
link voltage. However, in this condition the dv/dt of the switches are also
increased, which is undesirable. In order to optimize the dc link utilization vs.
the dv/dt of the switches, the defined reference functions feature staircase
shaped rising or falling edges with the steps of two voltage levels. On the other
hand, the duration of each plateau of the rising or falling staircase is defined to
be equal to a single update time of the modulation algorithm, thus maximizing
the speed of climb or descent of the phase voltage to its peak value. This will
maximize the duration of the peak value of the phase voltage and,
correspondingly, the utilization of the dc link voltage. Sample reference
functions for an 11-level inverter are pictured in Fig.3. These modulation
references can be used for multilevel inverters with different number of
voltage levels. For instance, all the five modulation references are used in an
11-level inverter to generate a wide linear modulation range, although only

15
first four and first three of these modulation references are used in the 9-level
and 7-level inverters, respectively.

3.4 EXISTING SIMULATION RESULT

Fig 3.2 Existing simulation output voltage

Eleven levels achieved in the output voltage and output current is clearly
shown in the figure.

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 Fig 3.3 Existing simulation output voltage
3.5 DRAWBACKS
 High THD.
 Complex control circuit.
 More number of switches required.

17
 CHAPTER-4
H-BRIDGE INVERTER:
Here the MOSFET based full bridge inverter circuit is cascaded for this
Fifteen level inverter. Three switches are also connected with this H bridge
inverter circuit. The snubber circuit (RC) is connected across all the switches
for protecting the switching devices from dv/dt and di/dt ratings. Three diodes
are connected parallel to the three switches. It completes the circuit when the
corresponding switch is in off position.

LOAD:
In this project the maximum output power level of the inverter is 10w.
The maximum output voltage level of the inverter is 42 volts. For this power

18
rating we can use lamp or small size motors. This project implemented in a
prototype. The voltage levels of the three sources are different. So this method
of configuration is called as asymmetrical multilevel inverter. The inverter
level is decided by both the modulation index and the applied DC voltage level
of the inverter. By adjusting the different voltage level we can able to increase
the number of levels of the inverter. A FPGA controller is used for generating
the PWM signals the inverter circuit. The switching devices used in this
inverter are MOSFET (IRF840). The power handling capacity of the inverter is
low because the hardware is developed in a prototype.

4.3 PROPOSED SYSTEM CIRCUIT DIAGRAM

Fig 4.2 31 level Inverter circuit diagram

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4.4 PROPOSED SYSTEM CIRCUIT OPERATION
The proposed single-phase Fifteen-level inverter was developed from
the seven-level inverter. It comprises a Single phase conventional H-bridge
inverter, three switches, and three voltage sources. This H-bridge topology is
significantly advantageous over other topologies, i.e., less power switch,
power diodes, for inverters of the same number of levels. Proper switching of
the inverter can produce fifteen output-voltage
4.5 FIFTEEN LEVEL INVERTER PWM GENERATION
In this project multi carrier pulse width modulation technique is used to
generate the Fifteen level output voltage. Seven equal amplitude carrier
triangular signals with offset is compared with the sinusoidal reference signal.
These PWM signals are given to the switches S1, S2, S3. Then the two
sinusoidal signals having 180 degree displacement signals are compared with
the carrier triangular signal, these PWM pulses are having dead band, it will
avoid the shoot through problem between two devices. These PWM pulses are
given to the single phase inverter circuit switches H1, H2, H3, and H4. Here
the switching device is MOSFET; as compared to IGBT the cost is low. The
processor used here is DSPIC. It’s under the category of embedded system.
DSPIC many of the pins are multiplexed pins. So we can use it as either input
or output pins. The operating speed of the DSPIC30F2010 controller operating
speed is much greater than Digital signal processors. These controllers are
used to generate the PWM pulses to the Fifteen level inverter.

CHAPTER 5

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 HARDWARE IMPLEMENTATION
5.1 POWER SUPPLY
There are many types of power supply. Most are designed to convert
Voltage AC Mains electricity to a suitable low voltage supply for electronic
Circuits and other Devices. A power supply can by broken down into a series
of blocks, each of which performs a particular function.

Fig. 5.1: Block diagram of regulated power supply

 Transformer - steps down high voltage AC mains to low voltage AC.
 Rectifier - converts AC to DC, but the DC output is varying.
 Smoothing - smoothes the DC from varying greatly to a small ripple.
 Regulator - eliminates ripple by setting DC output to a fixed voltage.
Here the AC supply main is given to the step down transformer. The
transformer having the different voltages. The output from the transformer is
given to the rectifier circuit. In this rectifier circuit the AC voltage is converted
to DC voltages. The rectified DC voltage is given to the regulator circuit. The
output of the regulator is depends upon the regulator IC chosen in the circuit.
5.2 BRIDGE RECTIFIER
A bridge rectifier can be made using four individual diodes, but it is also
available in special packages containing the four diodes required. It is called a
full-wave rectifier.

21
 Smoothing is performed by a large value electrolytic capacitor
connected across the DC Supply to act as a reservoir, supplying current to the
output when the varying DC Voltage from the rectifier is falling.

Fig:
5.2:

Bridge rectifier Fig: 5.3: FW varying DC

Smoothing
The diagram shows the unsmoothed DC (Dotted line) and the
smoothed DC (solid line). The capacitor charges quickly near the Peak of the
varying DC, and then discharges as it supplies current to the output.

Fig:5.4: Capacitor charging and discharging

Note that smoothing significantly increases the average DC voltage to
almost the peak Value (1.4-× RMS value). For example, 6V RMS AC is

22
rectified to full wave DC of about 4.6V RMS (1.4V is lost in the bridge
rectifier), with smoothing this increases to almost The peak value giving
1.4 × 4.6 = 6.4V smooth DC. Smoothing is not perfect due to the capacitor
voltage falling a little as it discharges, Giving a small ripple voltage. For many
circuits a ripple which is 10% of the supply Voltage is satisfactory and the
equation below gives the required value for the Smoothing capacitor. A larger
capacitor will give less ripple. The capacitor value must Be doubled when
smoothing half-wave DC.

 Smoothing capacitor for 10% ripple, 5 × Io   

C= Vs × f

C = smoothing capacitance in farads (F)

Io = output current from the supply in amps (A)
Vs = supply voltage in volts (V), this is the peak value of the
unsmoothed DC
f    = frequency of the AC supply in hertz (Hz)
5.3 REGULATOR
Voltage regulators ICs are available with fixed (typically 5, 12 and 15V)
or variable Output voltages. They are also rated by the maximum current they
can pass. Negative Voltage regulators are available, mainly for use in dual
supplies. Most regulators include some automatic protection from excessive
current ('overload protection') and Overheating ('thermal protection').

23
 Fig: 5.5: Regulator Fig: 5.6: Regulator IC
Many of the fixed voltage regulator ICs has 3 leads and look like power
transistors, Such as the 7805 +5V 1A regulator shown on the right. They
include a hole for attaching a heat sink if necessary.

Fig: 5.7: Rectifier circuit diagram and wave form

The regulated DC output is very smooth with no ripple. It is suitable for
all electronic circuits. In generally there are two types of regulators are used.
Namely positive and negative type regulators. For positive type regulators
78** series of regulators are used. For negative type regulators 79** series of
regulators are used. Depends upon the voltage and type of the voltage the
regulator IC is selected.
5.4 OPTO ISOLATOR
The function of the opto-isolator is to isolation between the power
circuit and control circuit. In generally the control side power is less compared
to the power circuit. For separating the high voltage side and the low voltage
side the opto-isolator playing a major role. Normally the output of the opto-
isolator is inverse of the input pulse. So in case of inverter circuits the output
of the opto-isolator is given to the transistors and again the signal will be
inverted and given to the driver ic’s.

24
 Fig: 5.8: Opto isolator diagram
5.5 DRIVER CIRCUIT DIAGRAM

Fig: 5.9: Driver circuit diagram

25
 IR2110 IC is used to drive the MOSFET’S. The output of the opto-
isolator is given to the IR2110 ic. There are two output signals are generated
from the drive ic namely both the output pulses are inverted to each other. The
impedance of the MOSFET is more, so the signals which is given to the gate
should be high gain for that the driver ic is used in MOSFET based circuits. A
MOSFET drive circuit is designed to connect the gate directly to a voltage bus
with no intervening resistance other than the impedance of the drive circuit
switch. Gate driver acts as a high-power buffer stage between the PWM output
of the control device and gates of the primary power switching MOSFET.
5.6 H-BRIDGE CIRCUIT DIAGRAM

Fig: 5.10: Single phase inverter circuit

To synthesize a multilevel waveform, the ac output of each of the
different level H-bridge cells is connected in series. The synthesized voltage
26
waveform is, therefore, the sum of the inverter outputs. The number of output
phase voltage levels in a cascaded- inverter is defined by
M=2s+1
where ‘M’ is no of levels of o/p voltage.
‘s’ is the number of dc sources.
Because zero voltage is common for all inverter outputs, the total level
of output voltage waveform becomes 2s+1. Each inverter bridge is capable of
generating three different levels of voltage outputs. When the positive group
switches are turned on, the voltage across that particular bridge is positive.
When the negative group switches are turned on the voltage across that
particular bridge is negative.
In this project the switching device used is MOSFET IRF 840. The
voltage rating is 500v and the current rating is 8 A. Resistance and Capacitor
(RC) snubber circuit is connected across the all the switching devices. This
snubber circuits give the protection to switching devices from the dv/dt and
di/dt. One diode also connected across the switching devices , this diodes are
circulate the current at the same time reverse bias the reverse currents which is
flows to the switching devices.
5.7 ABOUT DSPIC CONTROLLER
Microchip Technology’s Motor Control & Power Conversion family of
dsPIC Digital Signal Controllers provides an easy-to-use solution for
applications requiring motor control. Microchip Technology introduced 20
16-bit Flash micro controllers that provide the industry’s highest performance.
The dsPIC family of Digital Signal Controllers features a fully-
implemented digital signal processor (DSP) engine, 30 MIPS non-pipelined
performance, C compiler friendly design, and a familiar Microcontroller

27
architecture and design environment. The 20 new dsPIC30F2010 devices form
three product families targeting motor control and power conversion, sensor,
and general-purpose applications.
The dsPIC core is a 16-bit (data) non-pipelined modified Harvard
machine that combines the control advantages of a high-performance 16-bit
Microcontroller with the high computation speed of a fully implemented DSP
to produce a tightly coupled, single-chip single-instruction stream solution for
embedded systems designs. The initial 20-dsPIC30F2010devices feature 12
Kbytes to 144 Kbytes of on-chip secure Flash program memory space and up
to eight Kbytes of data space Operating voltage appeals to many
Microcontroller applications that remain at 5 volts, while many DSPs are
restricted to 3.3-supply V maximum. Devices are planned in 40-pin package.
5.7.1 DSPIC 30F2010PIN CONFIGURATION

Figure 5.11 DSPIC 30F2010pin Configurations

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5.7.2 DSPIC30F2010 Architecture Functional Block Diagram

Figure 5.12: Dspic30f2010 Architecture Functional Block Diagram

5.7.3 MOTOR CONTRAL PWM MODULE IN DSPIC
The dsPIC motor control PWM module is optimized for applications,
such as 3-phase AC induction motors, 3-phase brushless DC motors, and
switched reluctance motors.
The motor control PWM module has either 6 or 8 output pins and 3 or 4
PWM generators, depending upon the device. The output pins may be
configured as complementary output pairs or as independent outputs.

29
Critical PWM operating parameters, such as output polarity, are programmed
in non-volatile memory for safety. The non-volatile options reduce the risk of
placing the PWM outputs in a state that might damage the power devices
connected to Peripheral.

Figure 5.13 DSPIC30F2010 Micro Controller

DSPIC MICRO CONTROLLER FEATURES
High Performance Modified RISC CPU
 Modified Harvard architecture
 C compiler optimized instruction set architecture with flexible
addressing modes
 24-bit wide instructions, 16-bit wide data path
 48 Kbytes on-chip Flash program space (16K Instruction words)
 2 Kbytes of on-chip data RAM
 1 Kbytes of non-volatile data EEPROM
MOTOR CONTROL PWM MODULE FEATURES
 Six PWM output channels
- Complementary or Independent Output modes
- And Center Aligned modes
 Three duty cycle generators
 Dedicated time base
 Programmable output polarity

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  Dead-time control for Complementary mode
 Manual output control
 Trigger for A/D conversions
PERIPHARAL FEATURES
 High current sink/source I/O pins: 25 mA/25 mA
 Timer module with programmable presale
 Five 16-bit timers/counters; optionally pair
 16-bit timers into 32-bit timer modules
 16-bit Capture input functions
 16-bit Compare/PWM output functions
 2 UART modules with FIFO Buffers
 1 CAN modules, 2.0B complain
INPUT CAPTURE MODULE
This section describes the Input Capture module and associated
operational modes. The features provided by this module are useful in
applications requiring frequency (Period) and Pulse measurement.
USART
USART stands for the Universal Synchronous/Asynchronous
Receiver/Transmitter. It may sound mysterious, but actually, this is the most
frequent communication device used today throughout the computer world:
micro controllers, (some) cell phones, barcode readers, PCs…First, let us see
what all those words stand for:
 Universal means that it can be used with a wide scope of devices
 Synchronous/Asynchronous shows whether the devices that
communicate with each other require an external synchronization line

31
 (the clock). This device, present in most PICs, can do it both ways. The
Asynchronous mode (without the common clock) is easier to implement,
although it is generally slower than the synchronous
 Receiver/Transmitter means that this device can receive and transmit
(send) data simultaneously. It is also called the two-way or duplex
communication.
5.8 MOSFET
 This N-Channel enhancement mode silicon gate power field effect
transistor is an advanced power MOSFET designed, tested, and
guaranteed to withstand a specified level of energy in the breakdown
avalanche mode of operation.
 The invention of the power MOSFET was partly driven by the
limitations of bipolar power junction transistors (BJTs), which, until
recently, was the device of choice in power electronics applications.
 All of these power MOSFETs are designed for applications such as
switching regulators, switching converters, motor drivers, relay drivers,
and drivers for high power bipolar switching transistors requiring high
speed and low gate drive power.

Figure 5.14: MOSFET symbol Figure 5.15: Hardware model MOSFET

32
Figure 5.16: Unclamped Energy Figure 5.17 Unclamped Energy
Test Circuit Waveforms

Figure 5.18: Switching Time Test Circuit Figure 5.1:9 Switching

Waveforms
The transfer characteristic of an N-channel MOSFET is shown in figure
below

33
 Figure 5.20:Transfer characteristic of N-channel MOSFET
Features Of MOSFET
1. MOSFET has lower switching losses but its on-resistance and
conduction losses are more.
2. MOSFET is a voltage-controlled device.
3. MOSFET has positive temperature co-efficient for resistance.
This makes parallel operation of MOSFET easy. If a MOSFET
shares increased current initially, it heats up faster its resistance
rises and this increased resistance causes this current to shift to
other devices in parallel
4. In MOSFET secondary break down does not occur, because it has
positive temperature co-efficient.
5. MOSFET’s in higher voltage ratings have more conduction losses

34
 CHAPTER-6
SIMULATION& HARDWARE RESULTS
6.1 PROPOSED SYSTEM SIMULINK
The Fifteen level inverter has designed using MATLAB tool box. The
Multi carrier modulation technique is used to produce the PWM pulses.

Fig 6.1 Proposed system Simulink model

6.2 PROPOSED SYSTEM OUTPUT-PWM GENERATION

Fig 6.2 Proposed system MCM comparison

The figure 6.2 shows the multi carrier modulation pulses, these pulses
are given to the additional switches S1, S2, S3, S4 which has switching
frequency 5 KHz.
6.3 MULTI CARRIER PWM PULSES

Fig 6.3 Proposed system PWM pulse to inverter switches S1.

35
 The figure 6.3 shows the PWM pulses to the additional switches. The
modulation index of the MCM PWM technique is 0.95.
6.4 PWM PULSES TO THE H BRIDGE INVERTER

Fig 6.4 Proposed system PWM pulse to the H bridge inverter

The figure 6.4 shows the PWM pulses to the H bridge inverter switches,
the pulses are having 180 degree displacement.
6.5 FIFTEEN LEVEL INVERTER OUTPUT VOLTAGE

Fig 6.5 Proposed system Fifteen level inverter output voltage

36
The figure 6.5 shows the Fifteen level inverter output voltage waveforms. Its
requires only eight switches and four DC sources. Also it is high quality output
voltage.
6.6 FIFTEEN LEVEL INVERTER OUTPUT CURRENT

Fig 6.6 Proposed system Fifteen level inverter output current

The figure 6.5 shows the Fifteen level inverter output voltage waveform.
6.7 THD RESULT

Fig 6.7 Proposed system Fifteen level inverter THD

The fig 6.7 shows the THD results of the proposed inverter.

Fig 6.8 Proposed system hardware view

The figure 6.8 shows the Fifteen level inverter hardware development
proto type system. The DSPIC30F2010 controller is used to generate the PWM
pulses.

37
 CHAPTER 7
CONCLUSION
7.1 CONCLUSION
Multilevel inverters offer improved output waveforms and lower THD.
This paper has presented a novel PWM switching scheme for the proposed
multilevel inverter. In this project only one reference signal and is compared
with a triangular wave signal to generate the PWM signals. Here there are
three different DC voltage levels are used in this multi-level inverters. So this
method of configuration is known as asymmetrical cascaded inverter. By
controlling the modulation index and different levels of DC voltages the
Fifteen levels of the output voltage’s achieved.
FUTURE SCOPE
 We can give the Fifteen level output voltage to matrix converter from
that can we get variable AC output voltage.
 The Fifteen level inverter is applicable for all industrial AC Loads.
 The output of Fifteen level can be increased to further more.
 Renewable energy source when used in effective manner the overall
system efficiency can be increased.

38
 REFERENCES
1. Peng, M. Calais and V. G. Agelidis, “Multilevel converters for single-phase
grid connected photovoltaic systems— an overview,” in Proc. IEEE Int.
Symp. Ind. Electron, 1998, vol. 1, pp. 224–229.
2. Single-Phase Seven-Level Grid-Connected Inverter for Photovoltaic
System Nasrudin A. Rahim, Senior Member, IEEE, Krismadinata
Chaniago, Student Member, IEEE, and Jeyraj Selvaraj
3. S. B. Kjaer, J. K. Pedersen, and F. Blaabjerg, “A review of single-phase
grid connected inverters for photovoltaic modules,” IEEE Trans. Ind. Appl.,
vol. 41, no. 5, pp. 1292–1306, Sep./Oct. 2005.
4. P. K. Hinga, T. Ohnishi, and T. Suzuki, “A new PWM inverter for pho-
tovoltaic power generation system,” in Conf. Rec. IEEE Power Electron.
Spec. Conf., 1994, pp. 391–395.
5. Y. Cheng, C. Qian, M. L. Crow, S. Pekarek, and S. Atcitty, “A comparison
of diode-clamped and cascaded multilevel converters for a STATCOM with
energy storage,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 3112– 3121,
Oct. 2006.
6. M. Saeedifard, R. Iravani, and J. Pou, “A space vector modulation strategy
for a back-to-back five-level HVDC converter system,” IEEE Trans. Ind.
Electron., vol. 56, no. 2, pp. 452–466, Feb. 2009.
7. S. Alepuz, S. Busquets-Monge, J. Bordonau, J. A. M. Velasco, C. A. Silva,
J.Pontt, and J. Rodríguez, “Control strategies based on sym-metrical
components for grid-connected converters under voltage dips,” IEEE Trans.
Ind. Electron., vol. 56, no. 6, pp. 2162–2173, Jun. 2009.
8. J. Rodríguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of
topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49,

39
 no. 4, pp. 724–738, Aug. 2002.
9. J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, “Multi-level
voltage-source-converter topologies for industrial medium-voltage drives,”
IEEE Trans. vol. 54, no. 6, pp. 2930–2945, Dec. 2007.
10.M. M. Renge and H. M. Suryawanshi, “Five-level diode clamped inverter
to eliminate common mode voltage and reduce dv/dt in medium voltage
rating induction motor drives,” IEEE Trans. Power Electron., vol. 23, no. 4,
pp. 3198–1160, Jul. 2008.
11.E. Ozdemir, S. Ozdemir, and L. M. Tolbert, “Fundamental-frequency-
modulated six-level diode-clamped multilevel inverter for three-phase
stand-alone photovoltaic system,” IEEE Trans. Ind. Electron., vol. 56, no.
11, pp. 4407–4431, Nov. 2009.
12.R. Stala, S. Pirog, M. Baszynski, A. Mondzik, A. Penczek, J. Czekonski,
and S. Gasiorek, “Results of investigation of multicell converters with
balancing circuit—Part I,” IEEE Trans. Ind. Electron., vol. 56, no. 7, pp.
2610–2619, Jul. 2009.
13.P. Lezana, R. Aguilera, and D. E. Quevedo, “Model predictive control of an
asymmetric flying capacitor converter,” IEEE Trans. Ind. Electron., vol. 56,
no. 6, pp. 1839–1846, Jun. 2009.
14.A.Nabae, I. Takahashi, and H. Akagi, “A New Neutral-point Clamped
PWM inverter,” IEEE Trans. Ind. Applicat., vol. IA-17, pp. 518-523,
Sept./Oct. 1981.
15.J. S. Lai, F. Z. Peng, “Multilevel Converters - A New Breed of Power
Converters,” IEEE Transactions on Industry Applications, vol. 32, no. 3,
May 1996, pp. 509-517.

40
 APPENDIX
#include <P30F2010.h>
#include "LCD_2010.h"

_FOSC(CSW_FSCM_OFF & XT_PLL8);

_FWDT(WDT_OFF);

#define s4 _LATE0
#define s3 _LATE1
#define s2 _LATE2
#define s1 _LATE3
#define s5 _LATE4
#define s6 _LATE5
unsigned int Index1=0,Sine_Loc1=0,c=0;
signed int Sine_Value1,Value1;
float a=0;
const signed int
lookup[256]
={0,807,1614,2420,3224,4027,4827,5624,6417,7207,7992,8773,9548,
10317,11080,11837,12586,13328,14061,14786,15502,16208,16905,
17592,18267,18932,19585,20226,20855,21472,22075,22665,23241,
23803,24351,24883,25401,25903,26390,26860,27315,27752,28173,
28577,28963,29332,29683,30016,30330,30627,30904,31163,31403,
31624,31826,32008,32171,32315,32439,32543,32627,32692,32737,
32761,32766,32751,32717,32662,32587,32493,32379,32246,32092,
31920,31728,31516,31286,31036,30768,30481,30175,29851,29510,

41
29150,28772,28377,27965,27536,27090,26627,26149,25654,25144,
24619,24079,23524,22955,22372,21775,21165,20542,19907,19260,

18601,17931,17250,16558,15856,15145,14425,13695,12958,1
2212,
11459,10700,9933,9161,8383,7600,6813,6021,5226,4427,3626,2822,
2017,1211,404,-404,-1211,-2017,-2822,-3626,-4427,-5226,-6021,
-6813,-7600,-8383,-9161,-9933,-10700,-11459,-12212,-12958,-13695,
-14425,-15145,-15856,-16558,-17250,-17931,-18601,-19260,-19907,
-20542,-21165,-21775,-22372,-22955,-23524,-24079,-24619,-25144,
-25654,-26149,-26627,-27090,-27536,-27965,-28377,-28772,-29150,
-29510,-29851,-30175,-30481,-30768,-31036,-31286,-31516,-31728,
-31920,-32092,-32246,-32379,-32493,-32587,-32662,-32717,-32751,
-32766,-32761,-32737,-32692,-32627,-32543,-32439,-32315,-32171,
-32008,-31826,-31624,-31403,-31163,-30904,-30627,-30330,-30016,
-29683,-29332,-28963,-28577,-28173,-27752,-27315,-26860,-26390,
-25903,-25401,-24883,-24351,-23803,-23241,-22665,-22075,-21472,
-20855,-20226,-19585,-18932,-18267,-17592,-16905,-16208,-15502,
-14786,-14061,-13328,-12586,-11837,-11080,-10317,-9548,-8773,
-7992,-7207,-6417,-5624,-4827,-4027,-3224,-2420,-1614,-807, 0};

void __attribute__((__interrupt__)) _T1Interrupt(void)

{

Index1 = Index1 + 327; //////////////

Step_freq = 655 ;;;frequency
Sine_Loc1 = Index1 >> 8;

42
 Sine_Value1 = lookup[Sine_Loc1];
Value1 = (Sine_Value1 * (long)17)/32764;

if(Sine_Value1 > 807)

{
s5=1;
s6=0;
}
else if(Sine_Value1 < -807)
{
s5=0;
s6=1;
}
else
{
s5=0;
s6=0;
}

c = abs(Sine_Value1);
// c = (a);

if(c < 1*2047)

{
s1 = 0;

43
 s2 = 0;
s3 = 0;
s4 = 0;
}
else if(c < 2*2047)
{
s1 = 1;
s2 = 0;
s3 = 0;
s4 = 0;
}
else if(c < 3*2047)
{
s1 = 0;
s2 = 1;
s3 = 0;
s4 = 0;
}
else if(c < 4*2047)
{
s1 = 1;
s2 = 1;
s3 = 0;
s4 = 0;
}
else if(c < 5*2047)

44
{
s1 = 0;
s2 = 0;
s3 = 1;
s4 = 0;
}
else if(c < 6*2047)
{
s1 = 1;
s2 = 0;
s3 = 1;
s4 = 0;
}
else if(c < 7*2047)
{
s1 = 0;
s2 = 1;
s3 = 1;
s4 = 0;
}
else if(c < 8*2047)
{
s1 = 1;
s2 = 1;
s3 = 1;
s4 = 0;

45
}
else if(c < 9*2047)
{
s1 = 0;
s2 = 0;
s3 = 0;
s4 = 1;
}
else if(c < 10*2047)
{
s1 = 1;
s2 = 0;
s3 = 0;
s4 = 1;
}
else if(c < 11*2047)
{
s1 = 0;
s2 = 1;
s3 = 0;
s4 = 1;
}
else if(c < 12*2047)
{
s1 = 1;
s2 = 1;

46
 s3 = 0;
s4 = 1;
}
else if(c < 27225)
{
s1 = 0;
s2 = 0;
s3 = 1;
s4 = 1;
}
else if(c < 29681)
{
s1 = 1;
s2 = 0;
s3 = 1;
s4 = 1;
}
else if(c < 32137)
{
s1 = 0;
s2 = 1;
s3 = 1;
s4 = 1;
}
else if(c > 32137)
{

47
 s1 = 1;
s2 = 1;
s3 = 1;
s4 = 1;
}

IFS0bits.T1IF = 0;
}

int main()
{
TRISE = 0x000;
PORTE = 0x000;

PR1 = 2000;
IEC0bits.T1IE = 1;
T1CON = 0x8000;

cmd_write();
data_write(" C: ",0x80,16);
while(1)
{
LCDDisp_INT(Index1,0x89,6);
LCDDisp_INT(c,0xc9,6);
LCDDisp_INT(a,0xc0,6);

48
 }
}

49