15CS203 - COMPUTER SYSTEM ARCHITECTURE

Third Semester/Second Year

OBJECTIVE TYPE QUESTION
Prepared by: Partha Sarathi Chakraborty, Assistant Professor, CSE

Objective Type Questions UNIT – 1 1 mark each

1. In case of zero address instruction method the 6. The register used to store the flags is called
operands are stored in (a) Flag register (b) Status register
(a) Registers (b) Accumulator (c) Tag register (d) Code register
(c) Stack (d) Cache
7. The smallest entity of memory is known as
2. The instructions like MOVE or ADD are called as
(a) Opcode (b) Operator (a) Cell (b) Block (c) Word (d) Byte
(c) Command (d) Variable
8. Identify two phases of executing an instruction are
3. The effective address of the operand is generated by
adding a constant value to the contents of a register
(a) Decode and Storage
was
(b) Fetch and Decode
(a) Immediate mode (b) Index mode
(c) Fetch and Execute
(c) Indirect mode (d) Relative mode
(d) Decode and Execute
4. The arrangement in which some memory address
values are used to refer to peripheral device buffer 9. Refering to the operational units and their intercon-
registers known as nections that realize the architectural specifications
(a) Memory Mapped I/O is known as
(b) Program Controlled I/O (a) Computer Architecture
(c) Device Interface (b) Computer Organization
(d) Cache Arrangement (c) Computer Hardware
(d) Computer System
5. A collection of lines that connects several devices is
called 10. holds the address of the location to
(a) Data Bus (b) Internal Wires be accessed.
(c) Bus (d) Connection Wires (a) MDR (b) MBR (c) MAR (d) PC

Objective Type Questions UNIT – 2 1 mark each

11. The method used to reduce the maximum number (c) Cascade of k n-bit Adder
of summands by half is (d) Carry-Lookahead Adder
(a) Bit-Recoding (b) Carry-Lookahead Logic
16. When period is placed to the right of first signifi-
(c) Bit-Pair Recoding (d) Carry-Save Addition
cant digit, the number is said to be
12. In IEEE 64 bit representation, the exponent (a) Scale factor (b) Denormal
of a floating point number is said to occupy (c) Normalized (d) Unnormalized
bits.
17. The way of removing the guard bits and no changes
(a) 8 (b) 9 (c) 10 (d) 11
in retained bits is called as
13. In standard IEEE floating point number represen- (a) Rounding (b) Von Neumann Rounding
tation, exponent is represent as a (c) Chopping (d) Sticky bit
(a) 2’s complement representation
18. Identify the bit-recoding set (+1, −1) is equivalent
(b) 1’s complement representation
to bit-pair recoding
(c) Biased representation
(a) (0, +1) (b) (−1, 0)
(d) Sign-Magnitude representation
(c) (0, −1) (d) (+1, 0)
14. The multiplier 122 (01111010) can be represent in
19. What will be the delay at 16 bit carry-lookahead
bit recoding booth algorithm as
adder built by four 4-bit carry-lookahead adder, if
(a) M ×(26 + 25 + 24 + 23 + 21 )
each gate level stage delay = 0.001µs.
(b) M ×(27 − 23 − 21 )
(a) 17, 18 (b) 7, 8 (c) 9, 10 (d) 7, 10
(c) M ×(27 − 23 + 22 − 21 )
(d) M ×(−23 + 22 − 21 ) 20. In signed-magnitude binary division, if the dividend
is (11100)2 and divisor is (10011)2 then the result
15. Which approach can be taken to reduce delay in
is
adders?
(a) (00100)2 (b) (10100)2
(a) Carry Save Adder
(c) (11001)2 (d) (01100)2
(b) n-bit Ripple-Carry Adder

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 Objective Type Questions UNIT – 3 1 mark each

21. A word whose individual bits represent a control 27. Pipeline increases the CPU performance through
signal is increase its
(a) Command word (b) Signal word (a) Efficiency (b) Latency
(c) Control word (d) Counter word (c) Throughput (d) Both (a) and (c)
22. The microroutines for all instructions are stored in 28. Highly encoded schemes that use compact codes to
a special memory called specify only a small number of control functions in
(a) µ-routine store (b) Control word each microinstruction are referred as a
(c) Instruction word (d) Control store (a) Horizontal Organization
23. What do you mean by bubbles in the pipeline? (b) Vertical Organization
(a) Hazard (b) Stalls (c) Compact Organization
(c) Side effect (d) Penalty (d) Field-encoded Organization

24. The condition in which either source or destination 29. The branch prediction decision may change depend-
operands are unavailable during pipeline is known ing on execution history is called
as (a) Dynamic branch prediction
(a) Data hazard (b) Structural hazard (b) Speculative branch prediction
(c) Control hazard (d) Instruction hazard (c) Static branch prediction
25. The register that holds the result of ALU is (d) Delayed branch prediction
(a) Y (b) Z (c) R0 (d) TEMP
30. A technique called can minimize the
26. Identify the correct control sequence for increment penalty incurred as a result of conditional branch
PC instructions.
(a) P Cout , M ARin , Select4, Add, Zin → Zout , P Cin (a) Branch prediction
(b) P Cout , M ARin , Read, Add, Zin → Zout , P Cin (b) Dynamic branch prediction
(c) P Cout , M ARin , Yin , Add, Zin → Zout , P Cin (c) Delayed branching
(d) P Cout , M ARin , Select4, Add, Yin → Yout , P Cin (d) Branch folding

Objective Type Questions UNIT – 4 1 mark each

31. Block of cache are grouped into sets and mapping 36. A cache that can support multiple outstanding
allows block of main memory to reside in any block misses is called
of specific set is (a) Write Buffer (b) Prefetching
(a) Cache mapping (c) Lockup-Free Cache (d) Virtual Memory
(b) Associative mapping
(c) Direct mapping 37. What is page table base register?
(d) Set associative mapping (a) It holds starting address of page frame
(b) It holds address of a page
32. Which of the following terms describe that the in- (c) It holds starting address of page table
formation which will be used in near future is likely (d) It holds address of virtual page number
to be in use already?
(a) Spatial Locality (b) Temporal Locality 38. A special hardware unit that translates virtual ad-
(c) Least Recently Used (d) Hit ratio dresses into physical addresses is
(a) Memory Controller
33. What is LRU algorithm? (b) Memory Management Unit
(a) Pages out that have been used recently (c) Direct Memory Access
(b) Pages out that have not been used recently (d) Translation Lookaside Buffer
(c) Pages out the first page in given data
(d) Pages out that have been least used recently 39. The amount of time that elapses after the head is
positioned over the correct track until the starting
34. Which of the following is true about ROM?
position of the addressed sector passes under the
(a) It is faster to access than RAM.
read/write head called
(b) It is non-volatile memory.
(a) Rotational delay (b) Access time
(c) It stores more information than RAM.
(c) Intersector delay (d) Seek time
(d) It is used for cache memory.
35. In write operation, protocol updated 40. The amount of time required to transfer a word of
simultaneously cache location and the main mem- data to or from the memory is called
ory location. (a) Seek Time (b) Memory Latency
(a) Early restart (b) Write-back (c) Delay Time (d) Response Time
(c) Write-through (d) Copy-back
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 Objective Type Questions UNIT – 5 1 mark each

41. All the bits of a byte are transferred simultaneously 46. When large volumes of data are to be moved, a
within the time-frame allotted for the transmission more efficient technique is required called
is known as (a) Programmed IO (b) Interrupt-driven IO
(a) Sequential Data Transfer Mode (c) IO controller (d) Direct Memory Access
(b) Serial Data Transfer Mode
(c) Parallel Data Transfer Mode 47. refers to the exceptional event which
(d) Synchronous Data Transfer Mode causes the CPU to temporarily suspend the current
program being executed.
42. A bus may be driven by more than one source at (a) Polling (b) Error
different time intervals, the driver/buffer should be (c) Interrupt (d) Acknowledge
a tristate device with
(a) 0, 1, or z 48. An IO channel also referred as is a
(b) 00, 01, or 10 processor equipped with more facilities than those
(c) 0, z, z̄ are available in a typical DMA controller.
(d) 0, 1, or z̄ (a) Interrupt controller
(b) IO Control Unit
43. A single chip LSI device is used to interface serial (c) Peripheral Processor Unit
IO to a parallel bus structure called (d) IO Processing Unit
(a) SMART (b) UART
(c) INTR (d) Intel 82C55A 49. When the processor detects an interrupt, it
branches to an interrupt-service routine whose job
44. flag if any one of the two stop bits is 0. it is to poll each I/O module to determine which
(a) Framing Error (b) Parity Error module caused the interrupt. The poll could be in
(c) Overrun Error (d) Interrupt Error the form of a separate command line. It is known
as
45. A low cost, processor-independent bus that housed (a) Hardware Poll (b) Software Poll
on the motherboard of a computer and used to con- (c) IO Poll (d) Vector Interrupt Poll
nect I/O interfaces for a wide variety of devices. A
device connected to it, appears to the processor as 50. It has been adopted as IEEE Standard 1394 and it
if it is connected directly to the processor bus. The uses differential point-to-point serial links.
bus known as (a) USB (b) FireWire
(a) PCI (b) SAS (c) SCSI (d) SATA (c) SATA (d) PCI Express

ANSWER OF OBJECTIVE TYPE QUESTION

1. (c) 11. (c) 21. (d) 31. (d) 41. (c)

2. (a) 12. (d) 22. (d) 32. (b) 42. (a)
3. (b) 13. (c) 23. (b) 33. (d) 43. (b)
4. (c) 14. (c) 24. (a) 34. (b) 44. (a)
5. (c) 15. (c) 25. (b) 35. (c) 45. (a)
6. (b) 16. (c) 26. (a) 36. (c) 46. (d)
7. (a) 17. (c) 27. (d) 37. (c) 47. (c)
8. (c) 18. (a) 28. (b) 38. (b) 48. (c)
9. (b) 19. (d) 29. (a) 39. (a) 49. (b)
10. (c) 20. (b) 30. (c) 40. (b) 50. (b)

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