Looking Ahead

for Resistive
Memory Technology
A broad perspective on ReRAM technology
for future storage and computing.

By Hai (Helen) Li,

Yiran Chen,
Chenchen Liu,
John Paul Strachan,
and Noraica Davila

©iStockphoto.com/sarawuth702

R
esistive random-access memory (ReRAM) is
regarded as one of the most promising alternative non-
volatile memory technologies for its advantages in
very-high-storage density, simple structure, low power
consumption, and long endurance, as well as good
compatibility with traditional complimentary metal–oxide–
Digital Object Identifier 10.1109/MCE.2016.2614523
Date of publication: 14 December 2016
semiconductor (CMOS) technology. In addition to the data stor-
age, ReRAM can also be used for logic operation and
computation, demonstrating a great potential in developing a
non–von Neumann computing system. Extensive studies on
ReRAM technology, including material, device process, cell
and array structure, circuit, and architecture, have been conduct-
ed in recent years. In this article, we provide a broad perspec-
tive on ReRAM technology for future storage and computing.
The models, challenges, and applications are also summarized.

94 IEEE Consumer Electronics Magazine ^ january 2017 2162-2248/17©2017IEEE

NONVOLATILE MEMORY: A BROAD PERSPECTIVE
Nonvolatile memory represents a large variety of memory
technologies that can retain the stored information even when
they are not powered. Flash memory, first invented by Fujio
Masuoka [2], is recognized as the most prominent nonvolatile
memory technology. Since 1988, when it was commercial-
ized by Intel [3], flash memory has been widely adopted in
various applications, from massive data storage like solid-
state drives and memory cards, to consumer electronics such
as digital cameras, mobile phones, and digital audio players.
As devices continue shrinking, however, the development of
flash memory becomes very challenging due to the intrinsic
physical limits and the aggravated device reliability [4].
Alternative memory device technologies have been widely
investigated and developed. Among them, ReRAM, which
stores information by device resistance states [5], shows the
greatest potential in massive data storage. Various metal
oxide materials demonstrate the resistive switching property.
Notably, in 2008, HP Labs [6] described the ReRAM devices
with analog resistive states as memristors, approving the exis-
tence of the fourth basic circuit element predicted by Profes-
sor Leon Chua in 1971 [7]. Usually, the ReRAM devices are
organized in a crosspoint array structure that offers ultradense
data storage. In 2015, a three-dimensional (3-D) XPoint
memory technology demonstrating good stackability and fast
switching was released by Intel Corp. and Micron Technolo-
gy Inc. Crossbar Inc. also released their 3-D ReRAM prod-
Resistive random access memory
is regarded as one of the most
­promising alternative nonvolatile
memory technologies.
ucts, which are advanced in all important aspects compared
to the present nand circuit (nand) flash memory, as sum-
marized in Figure 1 [1].
Besides storage class memory, ReRAM technology can
also be used to develop brain-like computing systems,
enabling a new computing solution with extremely high effi-
ciency. For example, matrix computation can be realized
through ReRAM crosspoint array [8]. Both pure analog and
mixed analog–digital neuromorphic systems have been reported
[9]–[11]. Neuromorphic cores using ReRAM devices for in
situ learning have been successfully demonstrated [12], [13].
THE RESISTIVE MEMORY TECHNOLOGY
ReRAM DEVICE AND OPERATION
In general, ReRAM denotes any RAM that uses resistance
states for information storage. Commonly, two resistance levels,
that is, the high-resistance state (HRS) and the low-resistance

Manufacturability
Scalability BEOL Standard CMOS Fab
Sub 10 nm Easy 3-D Stacking
eFlash Perf and Rel Degrades < 25 nm Existing Tools and Process

Density
Low Cost Process
1F2 with MLC and 3-D Terabytes
2 Additional Backend Masking Steps
NAND 4.8F2 32 GBs
3~4% Incremental Cost Over Standard CMOS

Energy Byte Alterability

Forming-Free No Block Erase Needed
0.064 nJ–Write Energy eFlash >3 ms Per Block Erase
20 × NAND

Read Performance
Temperature
<30 ns Initial Latency for Code Memory
10-Year Retention at 125 °C
2 µs Initial Latency for Data Storage
Flash < 1 Year Below 55 °C
NAND ~75 µs Random Access

Security Write Performance

Filamentary Architecture 140 Mb/s Random Write
OTP/MTP/Fuse Capable NAND 7 Mb/s
Endurance
10 K–1 Billion Cycles
NAND < 1,000 Cycles

FIGURE 1. A summary of NAND flash memory versus crosspoint ReRAM [1].

january 2017 ^ IEEE Consumer Electronics Magazine 95


ReRAM, which stores information
by device resistance states, shows
the ­greatest potential in massive
data storage.
state (LRS), are realized in a device, representing logic 0 and
1, respectively. By carefully controlling the programming
voltage pulsewidth and/or amplitude, more than two resis-
tance states can be obtained, offering even higher data stor-
age density.
The resistive switching property has been observed and
studied in various metal oxide materials, such as
Ti O x, A g O x, H f O x, and TaO x. Based on different switching
mechanisms, these materials can be categorized to five class-
es (Figure 2) [5]. Let’s take the electrochemical metalization
effect described by the filament concept as an example: in a
metal–insulator–metal structural ReRAM, filaments inside an
insulator can be taken as the tiny paths that connect the two
Electrostatic/
Electronic Effects
Electrochemical
Resistive Switching
metal electrodes. By controlling the biasing condition on the
electrodes, the device can form (rupture) the filaments and
therefore obtain the LRS (HRS) [5].
Programming and erasing are two basic ReRAM operations.
The former describes the state transition from HRS to LRS, and
the latter is a reverse procedure. Depending on the switching
operation requirement, ReRAM devices can also be classified
into unipolar and bipolar types [14]. The unipolar operation
executes the programming/erasing by using short/long pulses
or by using high/low voltage with the same voltage polarity,
while the operation of a bipolar switching ReRAM design is
conducted by short pulses with opposite voltage polarities.
ReRAM CROSSPOINT ARRAY
The structure of a crosspoint array was originally used in tele-
communication switching systems. The nanometer ReRAM
design exploits a similar structure in which two layers of
metal wires are connected by memory devices at cross points.
As illustrated in Figure 3, the rows and columns of the
crosspoint structure are called word lines and bit lines, respec-
tively. These metal wires connect to periphery circuitry (e.g.,
sensing circuits) to conduct the write and read operations.
Such a simple structure can achieve the minimal unit storage
area of 4F 2, where F represents technology feature size.
However, accessing such a passive resistive network inevi-
tably induces leakage current flows through unselected paths,
or sneak paths [16], that can be seen in Figure 3. The extra
current on sneak paths can be regarded as noise that degrades
the effective programing voltage in write operation or con-

Bipolar
Metallization Effects
taminates the real information of the target cell during a read.
Valency Change The performance of a crosspoint array thereby depends on
Memory Effects the amount of sneak path leakage current, which is deter-
mined by the number of memory devices as well as the resis-
Thermochemical
Memory Effects tance value of these cells. A popular solution at device level
Unipolar is integrating each ReRAM device with a selective device
Phase Change such as a transistor or a bipolar nonlinear selector, construct-
Memory Effects
ing 1T1R or 1S1R cell structure, respectively.
Improvements in reading procedure and peripheral circuit
FIGURE 2. A general category of resistive switching memory. designs have also been widely explored. For example, multi-
stage reading was introduced by HP Labs [17], which is a
self-referencing technique. The unfolded architecture [18]
inserts a separate column for each ReRAM device to cancel
BL out the impact of sneak paths. Intel proposed to utilize an
WL Selected operational amplifier for data detecting [19]. The scheme
(Vdd)
can suppress the sneak path leakage efficiently, but the large
Unselected
(0) area of operational amplifier severely constrains the design
Unselected
(0) scalability. The issue can be addressed by the weighted sens-
Unselected ing scheme that assigns different weights to different cells
(0)
and reads them simultaneously with one shared operational
amplifier [20].

ReRAM FABRICATION PROCESS

Sensing Circuits Resistance Cell
The fabrication process of ReRAM technology is compatible
Selected Path Leakage Path
with traditional CMOS technology. For example, Figure 4
describes the back-end-of-line (BEOL) fabrication process for
FIGURE 3. The ReRAM crosspoint array structure [15]. ReRAM (memristor) and n-type metal–oxide–semiconductor

96 IEEE Consumer Electronics Magazine ^ january 2017

 (a) (b) (c)

Electrodes/Vias Insulator Layer

Bottom Electrode Top Electrode
Switching Material

(d) (e) (f)

FIGURE 4. The BEOL fabrication process for ReRAM (memristor) and NMOS transistors integrated arrays. (a) An NMOS substrate from
the FEOL process with exposed vias, (b) a metal deposition and patterning of bottom electrodes, (c) an active layer deposition, (d) an
insulator layer deposition and memristor bit definition (nm or μm), and (e) a metal deposition for top electrode and patterning. (f) A
cross-section diagram of the integrated array.

(NMOS) transistors integrated arrays reported by HP Labs. It 3-D ReRAM STRUCTURES

starts with an NMOS substrate from the frond-end-of-line
(FEOL) process with exposed vias, followed by the metal
deposition and patterning of bottom electrodes, the active
layer deposition, the insulator layer deposition and memristor
bit definition (nm or μm), and metal deposition for top elec-
trode and patterning. Figure 4(f) is the cross-section diagram
of the integrated 1T1R ReRAM crosspoint array. The scan-
ning electron microscope (SEM) image of the ReRAM
crosspoint array with a bit size of 2 μm in diameter is shown
in Figure 5. Note that HP Labs designed this ReRAM array
for matrix-vector computation. Therefore, the 1T1R structure
with the active device (NMOS transistor) is adopted to elimi-
nate the sneak path leakage current and properly control the
ReRAM resistance levels.
By leveraging the 3-D vertical stacking technology, the inte-
gration of a ReRAM array can further improve so that 3-D
ReRAM designs have higher storage density and lower fabri-
cation cost.
ReRAM DESIGN WITHOUT SELECTING DEVICE
The crosspoint array without switching devices has advantag-
es, such as the simple process and high array density. Three-
dimensional stacking by constructing multiple memory layers
vertically also benefits from such a design with thin device
thickness. To overcome the sneak path leakage issue, it
requires the ReRAM material to exhibit a high resistance at
LRS (e.g., several KX) and a big resistance difference
between HRS and LRS [16].

Bottom Electrodes
Metal Oxide Pillar Electrode
D
Access Electrodes

Vertical Plane Tox

Plane Electrode
Top Electrodes

Transistor Gate

(WL)

F
ReRAM Cell
Hi H
m

z
GND BL Access SL
100 mm
Terminal Transistor
y x
FIGURE 5. An SEM image of memristor-NMOS fabricated arrays
with a bit size of 2 μm in diameter. FIGURE 6. A schematic view of a 3-D-VRAM array [21].

january 2017 ^ IEEE Consumer Electronics Magazine 97


In general, ReRAM denotes any
RAM that uses resistance states
for information storage.
WL
BL
(a) (b)
FIGURE 7. The stacking structure of unipolar ReRAM crossbar
array [26].
The 3-D design can be achieved by building up multiple
memory layers with insulator in between. In such a design,
every memory layer is independent of other layers. There-
fore, the memory access is exactly the same as the operation
Embedded
Dense Array
Wearable/Mobile Imaging/
Computing Video
512 Mb–2 Gb
Customer Specific Dev.
(28 nm and Below)
Small Latency Array
Smartcard/ Internet of Things
NFC 256 Kb–8 Mb
Ready
(110 nm/55 nm/40 nm)
FIGURE 8. The target applications of ReRAM [28].
98 IEEE Consumer Electronics Magazine ^ january 2017
on a single-layer array. For example, a four-layer bipolar 3-D
stacking structure with a ReRAM cell only was proposed by
Unity Corp.
ReRAM DESIGN WITH ACTIVE SELECTING DEVICE
The 3-D ReRAM designs with an active switching device
such as a metal–oxide–semiconductor field-effect transistor
or a bipolar junction transistor are also widely developed.
Taking the 1T1R structure, for example, the gate of a transis-
tor is isolated from other terminals and can act as a throttle to
turn on or off the current across the ReRAM device. Properly
RRAM Cell
controlling active devices can significantly reduce the leak-
age current and minimize the impacts of the sneak path.
Therefore, a large memory array can be built by using tran-
Diode
sistors as switching devices.
Figure 6 illustrates the 3-D vertical ReRAM (3-D-VRAM)
that enables an ultrahigh-density architecture as a flash
replacement [21]. As can be seen from the figure, the mono-
lithic 3-D multilayer structure improves effective bit density
dramatically. More importantly, the cost overheads associated
with additional layers are eliminated by the removal of some
of the intermediate fabrication process, saving significant
fabrication cost compared to a 3-D horizontal ReRAM
(3-D-HRAM) counterpart [22], [23]. This makes the
3-D-VRAM architecture a much more cost-efficient solution.
Stand-Alone
Social Web SSD/Storage/Cold Archive
in Consumer and Data Centers
4 Gb–Terabit
Under Development
(28 nm)
Industrial Automotive Consumer Storage
Class
16–128 Mb Memory
Under Definition
 3-D XPoint Technology: An Innovative, High-Density Design

Cross-Point Structure Stackable

Perpendicular wires connect These thin layers of memory can be
submicroscopic columns. stacked to further boost density.
An individual memory cell can be
addressed by selecting its top
and bottom wire.

Selector
Nonvolatile Whereas DRAM requires a transistor
3-D XPoint Technology is at each memory cell—making it big
nonvolatile—which means your data and expensive—the amount of
doesn’t go away when your power goes voltage sent to each 3-D XPoint
away—making it a great choice Technology selector enables its
for storage. memory cell to be written to or read
without requiring a transistor.

High Endurance
Unlike other storage memory technologies,
3-D XPoint Technology is not significantly 1 Memory Cell
impacted by the number of write cycles it can Each memory cell can
endure, making it more durable. store a single bit of data.

Transforming the Memory Hierarchy ~8x to 10x Greater Density than DRAM
For the first time, there is a fast, inexpensive and 3-D XPoint Technology’s simple, stackable, transistor-less
nonvolatile memory technology that can serve as design packs more memory into less space, which is
system memory and storage. critical to reducing cost.

1 Gb 1 Gb 1 Gb
1 Gb 1 Gb 1 Gb 1 Gb
1 Gb 1 Gb 1 Gb

3-D XPoint Technology Processor DRAM 3-D XPoint Technology

FIGURE 9. A 3-D XPoint structure and performance [30].

ReRAM DESIGN WITH PASSIVE SELECTING DEVICE

Besides active devices, the passive devices, such as diodes
and nonohmic devices, can also be used as switching devices
in ReRAM design. Those two-terminal passive devices can
be integrated with ReRAM material during the fabrication
process to construct a crosspoint structure.
For example, a diode can be used as the switching device
for unipolar ReRAM [24]. A diode turns on only when the
driving voltage exceeds its threshold voltage in the forward
direction. Otherwise, only a small leakage current can go
through a diode. The vertical diode and heterojunction diode
are promising candidates for a ReRAM switching device
because they can maintain 4F 2 of a single cell area. A stacking
structure of unipolar ReRAM crossbar array was developed FIGURE 10. A 3-D XPoint wafer [31].
by Samsung in [25]. Figure 7 shows the stacking structure of
a unipolar ReRAM crossbar array [26]. Each single cell is
composed of one diode and one ReRAM device (1D1R). THE APPLICATIONS OF RESISTIVE MEMORY
Crossbar Inc. reported the integration of 3-D-stackable 1S1R
passive crossbar ReRAM arrays utilizing a field-assisted ReRAM FOR DATA STORAGE
superlinear threshold (FAST) selector [27]. The FAST selec- As the most promising technology to develop more scalable,
tor utilizes a superlinear threshold layer that provides bidirec- high-capacity, high-performance, and reliable storage solu-
tional volatile switching with large resistance ratio, high tions, resistive memory can be widely used in such areas as
turn-on current, and steep turn-on slope. consumer electronics, enterprise storage, automotive and

january 2017 ^ IEEE Consumer Electronics Magazine 99

 VIN
Ni 1
g11 g12 g1n
g11 g12 g1n
g21 g22 g2n Ni 2
[x1 x2 ... xm ] g21 g22 g2n

gm1 gm2 gmn Nim

gm1 gm2 gmn
y1 y2 yn
IOUT
I1 = ∑ i = 1 gi1Vi
M
y1 = ∑ xi . gi1
No1 No2 Non

(a) (b)

FIGURE 11. A ReRAM crosspoint array for matrix-vector computing implementation. (a) The mathematical matrix-
vector computation and (b) the physical mapping to a crosspoint ReRAM array.

v0 g
WL
x0 w0 v1
w1 v2
x1 Σwi xi
w2
x2 v3
w3
x3 BL
Σgi vi

(a) (b)

CMOS Neurons Memristive Synapse

FIGURE 12. (a) and (b) The implementation of sums-of-product computation in a neural network on a ReRAM
crosspoint array [34].

medical, the Internet of Things, mobile computing, and wear-
ables, as indicated in Figure 8.
Crossbar Inc. has developed stand-alone 3-D ReRAM
products targeting data storage solutions by integrating
thousands of ReRAM cells in a crosspoint [29]. As the
milestone research directed by Intel Corp. and Micron Tech-
nology, the 3-D XPoint technology with initial 128-Gb stor-
age per die using the resistive switching technology was
released in 2015 [30]. The 3-D structure and wafer view can
be seen in Figures 9 and 10, respectively. It is claimed that
up to 1,000 times lower latency and exponentially greater
endurance than nand flash memory can be obtained by
the 3-D XPoint technology, and high-speed and high-capac-
ity data storage can be delivered. It is worthwhile to men-
tion the Machine project, a long-term HP Labs research
project that is memory-driven computing leveraging
ReRAM cells for storage. Notably, HP and SanDisk are
joining together to bring ReRAM (called memristor by
them) technology to the storage memory market. The appli-
cations of ReRAM in storage memory can be classified into
the following areas [32].
USE AS ON-CHIP CACHES
As the fabrication technology node shrinks down to 28 nm or
below, the high standby power and die size become critical
issues. Compared to conventional static random-access mem-
ory (SRAM) technology, ReRAM with nonvolatile data stor-
age and simple array structure can eliminate the standby
power and significantly reduce the die size. Particularly, the
easy 3-D integration of ReRAM on top of a CMOS processor
will further reduce the final die area and accelerate the com-
munication between logic units and caches. The utilization of
nonvolatile ReRAM caches will also enable an instant on/off
feature and make data restore and system recovery easier and

100 IEEE Consumer Electronics Magazine ^ january 2017

faster. Moreover, the cost structure of ReRAM is much lower
than that of SRAM. The higher latency of ReRAM caches
could affect system performance, which can be overcome by
larger cache size and fewer off-chip requests.
SERVE AS MEMORY REPLACEMENT
The chief value of ReRAM as a memory extension is its
lower cost compared to dynamic random-access memory
(DRAM) and other characteristics. Supplying more memory
increases data locality and therefore minimizes the impact of
interserver messaging over low-speed networks. At the
application level, this facilitates faster information retrieval
and more efficient data processing. The following are some
potential applications of resistive memory.
▼▼ Big data analytics: Data is currently being generated at
unprecedented rates and from a growing variety of sources.
The requirement for accurate and real-time analysis, how-
ever, makes the data process and management very chal-
lenging. With large-capacity ReRAM at lower costs, a
server can be equipped with much more memory than
DRAM-only solutions, enabling high operation parallelism
and high utilization of the computation resources.
▼▼ In-memory database: In-memory databases leverage sys-
tem memory to access and process data very rapidly. The
memory availability is critical to the real-world performance
and effectiveness of these databases. Proper u­ tilization of
ReRAM will fill the gap.
▼▼ Relational databases: When deploying a modern relational
database management system, designers must balance con-
flicting requirements. A general goal is to minimize solu-
tion cost while maintaining consistent quality of service.
To cope with these demanding workloads, currently data-
bases implement in-memory caches called buffer pools.
The introduction of ReRAM can increase the capacity of
memory, buffer, and caches of each server, offering a more
scalable solution.
MASSIVE STORAGE DEVICE
A ReRAM-based storage device can be deployed in a distrib-
uted fashion throughout the server and provide a storage
solution at the lowest latencies possible. It would be a good
option when extreme performance on the storage is needed,
such as with database and visualization applications.
▼▼ 
Database applications have evolved to make efficient use
of faster networking, computing, and memory. Storage has
not kept pace, with current solutions being a bottleneck on
database performance. ReRAM provides a high-perform-
ing, scalable, and predictable solution for databases.
▼▼ 
Visualization applications require performance. Whether
accelerating databases or virtual desktop infrastructure
instances, providing predictable response times and high
throughput is essential. ReRAM-based storage helps with
predictable low response times across virtual machines, effi-
cient scaling by consolidating servers with more virtual
machines per physical host, the lowest latency, and the high-
est bandwidth in storage.
N×M
Image Inputs
W
(ReRAM Periphery Digital
Crosspoint Circuits Outputs
Array)
Output
Weight Matrix
Image
FIGURE 13. The basic computation in neural network implemen-
tation with a ReRAM crosspoint array.
ReRAM FOR LOGIC OPERATION
ReRAM technology has been used as new logic operation
media, for example, for field-programmable gate arrays
(FPGAs). Many new FPGA architectures that use ReRAM to
replace conventional SRAM have been proposed, demonstrat-
ing significant improvements on the density of integration,
accessing performance, and energy consumption, and so forth.
For example, Chen et al. presented an FPGA architecture that
can completely substitute ReRAM for SRAM in all the major
components, including the logic blocks, switch blocks, and
connection blocks [33]. In particular, the lookup table design
in logic blocks can be engineered in 3-D stacking to maximize
the benefit from the high density of ReRAM. It naturally sup-
ports bit-addressable access and can be used as DRAM, which
usually has limited utilization in the conventional SRAM-
based FPGAs due to high design complexity and large area.
ReRAM FOR COMPUTING
People attempt to develop very-large-scale integration hard-
ware to mimic neurobiological architecture and therefore
obtain advanced computing systems with high efficiency.
This approach is called neuromorphic computing. The advan-
tages of ReRAM in high density, fast operation, low power
consumption, and analog to biological synapse make it
extremely attractive in neuromorphic system implementa-
tion. It is worthwhile to mention that ReRAM crosspoint
can be naturally used to implement the matrix-vector
computation (or sum-of-product), as depicted in Figure 11
[8]. Neural networks in which sum-of-product ­computations
are a fundamental mathe­­matical component can be imple­
mented efficiently, as can be seen in Figure 12 [34].
Properly controlling active devices
can significantly reduce the leakage
current and minimize the impacts
of the sneak path.
For example, when implementing an artificial neural net-
work for image recognition, digital images are encoded in float-
ing-point format and are then mapped to analog or digital
voltage signals. Figure 13 demonstrates the basic computation
january 2017 ^ IEEE Consumer Electronics Magazine 101

ReRAM technology is expected
to have great potential for
data ­storage and information
processing.
in neural network implementation based on ReRAM crosspoint
array. The synaptic weights in the neural network are represent-
ed by the conductance of ReRAM cells. In this way, the
crosspoint array conducts both network configuration (storage)
and computation. The output of the array will be sensed out by
periphery circuitry and transferred to the recognition result.
The mechanism was first proposed by Hu et al., and a pattern
recognition example was implemented in analog computation
format [8]. Later on, spiking neuromorphic systems by lever-
aging a ReRAM crosspoint array was reported [9]. A neuro-
morphic core 64k cell with phase change memory as a
synaptic device was reported by IBM in 2015 [13]. This is
the new neuromorphic chip released by IBM after the True-
North system reported in 2011, in which SRAMs were adopt-
ed for a synaptic device [35]. Very recently, scientists from
HP Labs reported a dot-product engine based on the 1T1R
crosspoint array [10].
CONCLUSIONS AND FUTURE DIRECTIONS
The ReRAM has been widely investigated in recent years,
with continuous scaling down of nanotechnology. A 3-D
ReRAM crosspoint array with or without switching cells is
widely developed and fabricated. Furthermore, new logic
and computing architectures are enabled by the similar
behavior of ReRAM devices and biological synapses and the
nature mapping of ReRAM crosspoint array and matrix-
vector computation.
For future electronic devices, ReRAM technology is
expected to have great potential for data storage and informa-
tion processing. For example, it can be leveraged across all the
layers along memory hierarchy—used as on-chip caches; serv-
ing as memory replacement for big data analytics, in-memory
databases, and relational databases; adopted in massive storage
devices, and so on. The ReRAM technology also inspires
brain-like computing systems, which could result in a revolu-
tionary change in the making of future electronic devices.
ABOUT THE AUTHORS
Hai (Helen) Li (hal66@pitt.edu) is an associate professor with
the Department of Electrical and Computer Engineering, Uni-
versity of Pittsburgh, Pennsylvania. Previously, she was with
Qualcomm Inc., Intel Corp., Seagate Technology, and Poly-
technic Institute of New York University. Her research interests
include memory design and architecture, neuromorphic archi-
tecture for brain-inspired computing systems, and architecture/
circuit/device cross-layer optimization for low power and high
performance. She has had more than 160 technical articles
published in refereed journals and conferences and 76 U.S.
102 IEEE Consumer Electronics Magazine ^ january 2017
patents granted. She is a Senior Member of the IEEE and a
senior member of the Association of Computing Machinery.
Yiran Chen (yiran.chen@pitt.edu) earned B.S and
M.S. degrees (both with honors) in electronic engineering
from Tsinghua University in Beijing in 1998 and 2001,
respectively, and a Ph.D. degree in electrical and computer
engineering from Purdue University in West Lafayette, Indi-
ana, in 2005. After five years in industry, he joined the Uni-
versity of Pittsburgh, Pennsylvania, in 2010 as assistant
professor and was promoted to associate professor in 2014.
He is now a bicentennial alumni faculty fellow and codirec-
tor of the Evolutionary Intelligence Lab in the Electrical
and Computer Engineering Department, focusing on the
research of nonvolatile memory and storage systems, neuro-
morphic computing, and mobile applications. He has pub-
lished more than 280 journal and conference articles and
holds 90 U.S. patents.
Chenchen Liu (chl192@pitt.edu) is a Ph.D. student in
the Department of Electrical and Computer Engineering,
University of Pittsburgh, Pennsylvania. She earned an M.S.
degree in electronics and communication engineering from
Peking University, China, in 2010. Her research interests
include nonvolatile memory design, neuromorphic archi-
tecture for brain-inspired computing systems, and appli-
cation-specific integrated circuit and system-on-a-chip
hardware design.
John Paul Strachan (john-paul.strachan@hpe.com)
earned his B.S. degree in physics and electrical engineering
from the Massachusetts Institute of Technology in Cambridge
and a Ph.D. degree in applied physics from Stanford Univer-
sity, California, in 2001 and 2007, respectively. He is a
researcher and manager at Hewlett Packard Labs in Palo
Alto, California. He has published more than 45 peer-
reviewed articles and holds over 25 patents. His interests
include studying novel electronic and ionic effects and taking
advantage of them for advanced computing and memory
applications. He also enjoys finding new ways to probe mate-
rial and electronic properties at the nanoscale.
Noraica Davila (noraica.davila@hpe.com) earned her
B.S. degree in electrical engineering in 2011 from the Uni-
versity of Puerto Rico–Mayagez, where she also completed a
certification in materials science; she earned a Ph.D. degree
in electrical engineering in 2015 from Michigan State Uni-
versity in East Lansing, studying infrared electro-thermo-
optical devices based on vanadium dioxide. She is a
postdoctoral researcher at Hewlett Packard Labs and has
more than 20 peer-reviewed journal and conference publica-
tions and holds four patents. Her research interests include
new materials and processes, memristor and semiconductor
devices, c­ omputation hardware, microsystems and optical
systems for materials, and device characterization.
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