Design of loop filter in phase-locked loops
However, in almost all practical applications, another capacitor needs to
S. Mirabbasi and K. Martin
An exact method for designing loop filters in third-order PLLs is
presented. The method is simple and results in a PLL with superior loop
dynamics and improved output jitter while maintaining the same loop
bandwidth compared to that of a PLL designed using the conventional
approach. The method is readily applicable to higher order PLLs.
Introduction: In phase-locked loops (PLLs), the loop filter sets the
PLL’s closed-loop bandwidth as well as its dynamic response [1]. Most
practical loop filters are second order (resulting in a third-order PLL),
for which previously there was no clear-cut design procedure [2, 3]. In
this Letter, we introduce an exact method for designing third-order
PLLs, as opposed to the conventional heuristic method which is based
on approximating the third-order loop with a second-order system.
Fig. 1 Charge-pump PLL
To illustrate the proposed design procedure for second-order loop fil-
ters, the ubiquitous charge-pump PLL, shown in Fig. 1, is considered in
this Letter. In this PLL, the simplest practical loop filter is a first-order
RC filter (i.e. C2 = 0 in Fig. 1). This loop filter leads to a second-order
loop transfer function, for which there is a well established analysis and
design theory [1, 2]. However, the resistor in the loop filter introduces
ripple in the control voltage of the voltage-controlled oscillator (VCO),
even when the loop is locked [3 – 5]. This undesirable ripple may cause
modulation of the VCO output frequency and therefore jitter in its out-
put. To suppress the ripple, a second capacitor (C2 in Fig. 1) is usually
added in parallel with the loop filter [3, 4] (or in parallel with the resis-
tor in the loop filter [5]) which leads to a second-order loop filter (a
third-order PLL).
In this Letter, we propose an exact procedure for designing a third-
order PLL using lowpass Bessel functions. This approach is simple and
results in a PLL with superior loop dynamics and improved output jitter
while maintaining the same loop bandwidth as compared to PLLs
designed using traditional methods.
Fig. 2 Block diagram of linearised PLL
Conventional design procedure: A generic linear model [3, 4] represent-
ing the phase of a charge-pump PLL in the locked state is depicted in
Fig. 2. In this model, Kp = Ip/(2π) is the combined phase-frequency
detector/charge-pump gain, Ko is the VCO gain factor, and Z(s) is the
impedance of the loop filter. For a first-order loop filter consisting of R
and C1 we have Z(s) = K1(1 + s/ωz)/s, where K1 = 1/C1 and ωz = 1/(RC1).
The closed loop phase transfer function would be
This transfer function may be rewritten as Hθ(s) = (2ζωns + ωn2)/(s2 +
2ζωns + ωn2), in which ωn is the natural frequency of the loop and ζ is
the damping factor [1]. The design of second-order loops has been
extensively documented [2]. By proper choice of R and C1, the appropri-
ate ωn and ζ can be designed for, in order to achieve a desired perform-
ELECTRONICS LETTERS 14th October 1999 Vol. 35
ance criteria such as transient settling time and loop bandwidth.
be included (C2 in Fig. 1) to filter out the ripple in the VCO control volt-
age. With this capacitor, the loop filter impedance becomes Z(s) = K2(1
+ s/ωz)/(s(1 + s/ωp)), where K2 = 1/(C1 + C2), ωz = 1/(RC1) and ωp = (C1
+ C2)/(RC1C2). As a result, the closed loop system would be of third
order with the following transfer function:
The common practice when designing this type of PLL [3, 5] is to ini-
tially neglect C2, and design for a second-order system to meet the
desired specifications. Next, a small C2 (perhaps 20 times smaller than
C1) is added which ideally has little effect on the loop dynamics.
Fig. 3 tsωn against ζ for second-order PLL
2% settling
For the second-order system, a plot of tsωn (the normalised 2ettling
time) against ζ is shown in Fig. 3 [Note 1]. Two popular choices for ζ
are 1 and 0.7 [1, 4, 5], where the former results in less overshoot in the
transient response while the latter results in narrower bandwidth. Based
on the choice of ζ and ts, we can find ωn using the plot of Fig. 3. Having
ζ and ωn, the noise bandwidth of the PLL is given by BL = ωn(ζ + 0.25/
ζ)/2 [Hz] where BL = ∫0∞|H(j2πf)|2df [1]. Assuming that C2 = C1/20, the
design equations for the third-order PLL loop filter are C1 = KpKo/ωn2
and R = 2ζ/(C1ωn).
Proposed method: Bessel filters are popular in data communication sys-
tems where a smooth transient response is important: to the best of the
authors’ knowledge they have not been employed previously in the
design of PLLs. In this Letter, we propose a design procedure based on a
third-order transfer function with the same poles as a third-order low-
pass Bessel filter, namely Hθ(s) = (15ω02s + 15ω03)/(s3 + 6ω0s2 + 15ω02s
+ 15ω03). Note that a zero in this prototype function is added to match
the inherent zero of the closed-loop PLL transfer function. For this sys-
tem, the relation between ts and ω0 is given by ω0 . 2.5/ts and the noise
bandwidth is BL . 1.05ω0. The values of the loop filter components are
given by C1 = Kp Ko /(3ω02), C2 = C1/5, and R = 1/(C1ω0). A PLL
designed using this approach has a smoother transient response com-
pared to a PLL designed based on the conventional approach and having
a similar noise bandwidth. In fact, with the same noise bandwidth, the
PLL designed by this method would settle 25% faster than the system
designed based on the conventional approach with ζ = 1. The traditional
method with ζ = 0.7 leads to a system with the same settling time and
noise bandwidth, but worse transient response compared to that of the
proposed method. Also, PLLs designed based on the proposed method
exhibit less ripple in the VCO control voltage and therefore less jitter in
the output. This can be justified by the linearity of the phase response of
a Bessel filter in its passband.
A drawback of the proposed design method is a slightly higher over-
shoot in the transient response of the PLL. This is not a major issue if
the VCO control voltage stays within the operation region of the VCO.
Finally, it should be noted that the proposed design procedure is read-
ily applicable to PLLs with higher order loop filters.
Simulation results: To evaluate the proposed approach, the behaviour of
a previously-locked 250MHz charge-pump PLL was simulated with the
input frequency being stepped from 250 to 255MHz. The simulation
Note 1 In this Figure, the abrupt change in the normalised settling time that occurs for ζ . 0.62
is due to the undershoot of the tail response becoming larger than 2%.
No. 21
program used was a custom C program [5], the accuracy of which has
been confirmed by HSPICE simulations.
settling time was assumed to be 0.4µs (100 times of the period of free-
running VCO frequency) except for case (iv) where the goal was to
achieve the same noise bandwidth as that of case (i). The values of the
loop filter elements in each case along with the PLL closed loop 3 dB
bandwidth (f3dB), noise bandwidth (BL), and settling time (ts), are pre-
sented in Table 1. Note that the simulated settling time for case (ii) was
slightly more than 0.4µs. Also it should be noted that the total capaci-
tance used in the loop filter was roughly the same in cases with the same
noise bandwidth. From the curves in Fig. 4, it is evident that proposed
approach leads to a PLL with a much-smoother transient response with-
out sacrificing the bandwidth. In fact, with the same BL as case (ii), our
method results in a PLL with a settling time of 0.31µs. This result is typ-
ical, i.e. we can design the PLL to have the same noise bandwidth as a
PLL employing the conventional approach with ζ = 1, and at the same
time achieve 25% faster transient response. Also, note that the ripple in
the VCO control voltage is much smaller than that of a PLL designed
using the traditional approach.

Conclusion: A simple exact procedure for designing the loop filter of

third order PLLs has been proposed. PLLs designed by this approach
show a faster and smoother transient response than those designed using
the conventional method without sacrificing the loop bandwidth or the
Fig. 4 VCO control voltage for different cases in response to 5MHz fre-
quency step at 0.1 µs noise bandwidth. The method is readily applicable to higher order PLLs.
Second column is close-up view of last 0.2µs of corresponding response
© IEE 1999 24 August 1999
Electronics Letters Online No: 19991278
Table 1: Values for loop filter components along with ts, f3dB and BL DOI: 10.1049/el:19991278
for four simulation cases
S. Mirabbasi and K. Martin (Department of Electrical and Computer
C1 C2 R ts f3dB BL Engineering, University of Toronto, Toronto, Ontario, M5S 3G4, Canada)
pF pF kW µs MHz MHz E-mail: shahriar@eecg.toronto.edu
Case (i) 17.36 0.87 6.72 0.40 4.10 6.45
Case (ii) 14.24 0.71 10.60 0.43 5.93 8.36 References
Case (iii) 21.16 4.23 7.50 0.40 4.18 6.58 1 GARDNER, F.M.: ‘Phaselock techniques’ (John Wiley & Sons, New York,
Case (iv) 13.12 2.62 9.56 0.31 5.33 8.36 1979)
2 STENSBY, J.L.:
‘Phase-locked loops, theory and applications’ (CRC Press,
New York, 1997)
The control voltage of the VCO for four different scenarios is illus- 3 GARDNER, F.M.: ‘Charge-pump phase-lock loops’, IEEE Trans. Commun.,
trated in Fig. 4. These four cases were: PLL designed by traditional 1980, 3, (11), pp. 1849–1858
4 RAZAVI, B.: ‘Monolithic phase-locked loops and clock recovery circuits-
method with (i) ζ = 0.7, (ii) ζ = 1, (iii) proposed technique and (iv) pro- theory and design’ (IEEE Press, New York, 1996)
posed method having the same BL as in case (ii). It was assumed that Ko 5 JOHNS, D.A., and MARTIN, K.: ‘Analog integrated circuit design’ (John
= 25MHz/V, with a charge-pump current of 100µA. Also, the desired Wiley & Sons, New York, 1997)

ELECTRONICS LETTERS 14th October 1999 Vol. 35 No. 21