The Transistor Revolution

First transistor
Bell Labs, 1948

Lecture 5: IC Fabrication 1
The First Integrated Circuits

Bipolar logic
1960’s

ECL 3-input Gate

Motorola 1966

Lecture 5: IC Fabrication 2
Intel 4004 Micro-Processor

1971
1000 transistors
1 MHz operation

Lecture 5: IC Fabrication 3
 LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION

Lecture 5: IC Fabrication
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Moore’s Law

1959
1960
1961
1962

Electronics, April 19, 1965.

1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
4
Silicon IC processing
F Similar to photographic printing
Expose the silicon wafer through a mask
Process the silicon wafer
Repeat sequentially to pattern all the layers

F Layout: A set of masks that tell a fabricator what to

pattern
For each layer in your circuit
Layers are metal, drain/source implants, gate, etc.
You draw the layers
Subject to vendor-supplied spacing rules

Lecture 5: IC Fabrication 5
The wafer
F Czochralski process
Melt silicon at 1425 °C
Add impurities (dopants)
Spin and pull crystal
F Slice into wafers
0.25mm to 1.0mm thick
F Polish one side

Lecture 5: IC Fabrication 6
Lecture 5: IC Fabrication 7
 Crystal and wafer

Wand A polished wafer

(a finished 250lb crystal)

Lecture 5: IC Fabrication 8
The mask
F Illuminate reticle on wafer
Typically 4× reduction

F Typical image is 25×25mm

4X reticle
Limited by focus

F Step-and repeat across wafer

Limited by mechanical Wafer
alignment

Lecture 5: IC Fabrication 9
Lithography
F Patterning is done by exposing photoresist with light

F Requires many steps per “layer”

F Example: Implant layer

Lecture 5: IC Fabrication Reference: FULLMAN KINETICS 10

Grow Oxide Layer

Lecture 5: IC Fabrication Reference: FULLMAN KINETICS 11

Add Photoresist

Lecture 5: IC Fabrication Reference: FULLMAN KINETICS 12

Mask

Lecture 5: IC Fabrication Reference: FULLMAN KINETICS 13

 Animation

Lecture 5: IC Fabrication Reference: FULLMAN KINETICS 14

Lecture 5: IC Fabrication Reference: FULLMAN KINETICS 15
Lecture 5: IC Fabrication Reference: FULLMAN KINETICS 16
Lecture 5: IC Fabrication Reference: FULLMAN KINETICS 17
Lecture 5: IC Fabrication Reference: FULLMAN KINETICS 18
Lecture 5: IC Fabrication 19
9/03 IEEE spectrum
Patterning

F How we pattern and

expose the resist
To make the patterns
we want on the silicon

IEEE Spectrum, 7/99, p. 41

Lecture 5: IC Fabrication 20
Lecture 5: IC Fabrication 9/03 IEEE spectrum 21
Detailed process sequence

1. Grow epi layer

Ultra-pure single-crystal
silicon

2. Implant n-well

Lecture 5: IC Fabrication 22
Detailed process sequence (con’t)

3. Define active area

4. Grow field oxide

For isolation

Lecture 5: IC Fabrication 23
Detailed process sequence (con’t)

5. Grow gate oxide

6. Pattern polysilicon

Lecture 5: IC Fabrication 24
Detailed process sequence (con’t)

7. Form pFETs

8. Form nFETs

Lecture 5: IC Fabrication 25
Detailed process sequence (con’t)

9. Deposit LTO by CVD

LTO is low-temperature
oxide
CVD is chemical vapor
deposition

10. Deposit Metal1

Usually aluminum

Lecture 5: IC Fabrication 26
Detailed process sequence (con’t)

11. Via definition

Deposit LTO
Make via cuts

12. Deposit Metal2

Usually aluminum

13. Overglass (not shown)

Coat entire chip with Si3N4
Make pad openings in Si3N4

Lecture 5: IC Fabrication 27
An inverter

Lecture 5: IC Fabrication 28
A Pentium cutaway

Figure courtesy
Yan Borodovsky,
Intel

Lecture 5: IC Fabrication 29
National 0.18µm process cutaway

Lecture 5: IC Fabrication 30
Advanced Metallization - Copper

Copper versus Aluminum

~ 40% lower resistivity
Lecture 5: IC Fabrication ~ 10× less electromigration 31
Interconnect Impact on Chip

Lecture 5: IC Fabrication 32
Nature of Interconnect

Local Interconnect Pentium Pro (R)

Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II

Global Interconnect
(Log Scale)
No of nets

SGlobal = SDie
SLocal = STechnology

Source: Intel
10 100 1,000 10,000 100,000
Length (u)
Lecture 5: IC Fabrication 33
Lecture 5: IC Fabrication 34
Permittivity

Lecture 5: IC Fabrication 35
Lecture 5: IC Fabrication 36
Lecture 5: IC Fabrication 37
Lecture 5: IC Fabrication 38
Lecture 5: IC Fabrication 39
Projections

Simulated distribution of dopant

atoms in a 0.05 m nFET
red: acceptor atom
blue: donor atom

All figures from IEEE Spectrum, 7/99

Lecture 5: IC Fabrication 40
An AMD 50nm transistor

Lecture 5: IC Fabrication 41
 Frequency
10000
Doubles every
1000
2 years
Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years

© Rabaey:
Lecture 5:Digital Integrated Circuits2nd
IC Fabrication 42
Courtesy, Intel
 Power Dissipation
100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Lead Microprocessors power continues to increase

© Rabaey:
Lecture 5:Digital Integrated Circuits2nd
IC Fabrication 43
Courtesy, Intel
 Power density
10000
Rocket
Power Density (W/cm2)

Nozzle
1000
Nuclear
Reactor
100

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

Power density too high to keep junctions at low temp

© Rabaey:
Lecture 5:Digital Integrated Circuits2nd
IC Fabrication 44
Courtesy, Intel
 Productivity Trends
Logic Transistor per Chip (M)
10,000
10,000,000 100,000
100,000,000
1,000 Logic Tr./Chip 10,000
1,000,000 10,000,000

(K) Trans./Staff - Mo.

Tr./Staff Month.
100 1,000
Complexity

100,000 1,000,000

Productivity
10 58%/Yr. compounded 100
10,000 Complexity growth rate 100,000

1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
xx Productivity growth rate
x
0.01
10 0.1
100
0.001
1 0.01
10
1995
1981
1983
1985
1987
1989
1991
1993

1997
1999
2001
2003
2005
2007
2009
Source: Sematech

Complexity outpaces design productivity

© Rabaey:
Lecture 5:Digital Integrated Circuits2nd
IC Fabrication 45
Courtesy, ITRS Roadmap
Cost of Integrated Circuits
F NRE (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor

F Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area

Lecture 5: IC Fabrication 46
 NRE Cost is Increasing

© Rabaey:
Lecture 5:Digital Integrated Circuits2nd
IC Fabrication 47
 Die Cost

Single die

Wafer

Going up to 12” (30cm)

© Rabaey:
Lecture 5:Digital Integrated Circuits2nd
IC Fabrication From http://www.amd.com 48