VLSI Circuit Design

Course Teacher
Shantanu
 VLSI CIRCUIT DESIGN

- ARRAY
- PLA
- SRAM & DRAM
- Multiplier
- CPLD and FPGA Architectures
- Fault Simulation & Testing
 PLA (programmable Logic Array)
• 2 major types of data array subsystems-
– Logic Array ( in SOP form)
– Memory Array
• ROM ( Read Only Memory)
• RAM ( Read Write Memory)
– SRAM
– DRAM
 Multiplier
 3-bit (3x3) Unsigned Multiplier

Example:
 3-bit
Unsigned
Multiplier
 Static RAM (SRAM)
 6 Transistor (6T) SRAM cell
SRAM – Write/Read Operation
 For WRITE
Operation-
 Data =1
 Datab =0
 Select =1

 For READ Operation-

 Data =1
 Datab =1 (forcefully)
 Select =1
 SRAM – Row Selection (2x2)

 - Simple inverted input used to select

between 2 rows
 SRAM – Row Selection (4x4)
A B R0 R1 R2 R3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

- A decoder designed to satisfy row

selection for a 4x4 SRAM matrix
- Any one output is high at one time,
selecting a particular row of SRAM
cells
- A 3 input decoder required for more
than 4 rows (5-8)
 SRAM – Column Decoder
 Column Selection/Decoder circuit for SRAM
cells –

- Line Select: enables or disables the decoder from the

entire circuit
- Write: Activates all the column decoders for write operation
- Data: Data input to be stored in SRAM
 4x4 SRAM Matrix
 Design a 4x4 SRAM matrix
 - No. of SRAM cells = 16
 - 2 input Row decoder circuit
 - No. of Column decoder circuits = 4
 Dynamic RAM (DRAM)
 1T DRAM
 - Stores contents as charge on
capacitor
 - Basic cell smaller than SRAM
 - Has to be recharged/refreshed
 periodically as read operation
disturbs
 contents
Read Operation Write Operation
- Data precharged to Vdd/2 - Data = 0 or 1
- Word=1 - Word=1
- Capacitor shares charge with Data - Voltage forced on capacitor,
charged
- Voltage change V
 Definitions

 Field Programmable Device (FPD):

— a general term that refers to any type of integrated circuit

used for implementing digital hardware, where the chip can be
configured by the end user to realize different designs.
Programming of such a device often involves placing the chip
into a special programming unit, but some chips can also be
configured “in-system”. Another name for FPDs is
programmable logic devices (PLDs).

Source: S. Brown and J. Rose, FPGA and CPLD Architectures: A Tutorial,

IEEE Design and Test of Computer, 1996

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 Classifications
 PLA — a Programmable Logic Array (PLA) is a relatively
small FPD that contains two levels of logic, an AND-
plane and an OR-plane, where both levels are
programmable
 PAL — a Programmable Array Logic (PAL) is a relatively
small FPD that has a programmable AND-plane
followed by a fixed OR-plane
 SPLD — refers to any type of Simple PLD, usually either a
PLA or PAL
 CPLD — a more Complex PLD that consists of an
arrangement of multiple SPLD-like blocks on a
single chip.
 FPGA — a Field-Programmable Gate Array is an FPD
featuring a general structure that allows very high
logic capacity.
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 PLA
Programmable AND Plane Programmable OR Plane

Programmable Node

Un-programmed

Connect

Disconnect
X Y O1 O2 O3 O4

X XY
Y XY
XY XY
X X Y Y
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 PLA

Programmable AND Plane Programmable OR Plane

YZ

XZ

XYZ

XY

X Y Z XY+YZ ? ?

XZ+XYZ

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 PAL

Programmable AND Plane Fix OR Plane

X Y O1 O2 O3 O4

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 PAL with Logic Expanders
Programmable AND Plane
Fix OR Plane

Logic expanders
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 PLA v.s. PAL

 PLAs are more flexible than PALs since both AND & OR planes are
programmable in PLAs.

 Because both AND & OR planes are programmable, PLAs are expensive
to fabricate and have large propagation delay.

 By using fix OR gates, PALs are cheaper and faster than PLAs.

 Logic expanders increase the flexibilities of PALs, but result in significant

propagation delay.

 PALs usually contain D flip-flops connected to the outputs of OR gates

to implement sequential circuits.

 PLAs and PALs are usually referred to as SPLD.

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 CPLD

 A CPLD comprises multiple PAL-like blocks on a single

chip with programmable interconnect to connect the blocks.

 CPLD Architecture
I/O block

I/O block
PAL-like PAL-like
block block

Programmable interconnect
I/O block

I/O block
PAL-like PAL-like
block block

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 Altera MAX CPLD

I/O Cell
LAB (Logic Array Block)

LAB LAB
LA
(local

•••
LAB LAB
array)
LAB LAB

Altera MAX chip Macroccell

Chip-wide
interconnect
Each LAB contains 16 macrocells

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 Macrocell of Altera MAX CPLD
System clock System enable

Local Array
Clock, clear, preset, enable
3
Programmable
inversion
M OUT
D Q

5
Product term
select

Parallel expander
To next macrocell

114

Macrocell

MAX 9000 has 33 inputs, can you explain why LA has 114 inputs?
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 FPGA
 FPGA consists of an array of programmable basic logic
cells surrounded by programmable interconnect.

 FPGA Structure

Programmable
Logic cell interconnect

I/O Cell

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 FPGA v.s. CPLD
 Capacitance
SPLDs CPLDs FPGAs
Equivalent gates 0 ~ 200 200 ~ 12,000 1000 ~ 1,000,000

 Applications

CPLDs
1. Implement random glue logics or
Replace circuits previously
implemented by multiple SPLDs
2. Circuits that can exploit wide
AND/OR gates, and do not need
a very large number of flip-flops
are good candidates for
implementation in CPLDs.
FPGAs
1. FPGAs can be used in various
applications: prototyping, FPGA-
based computers, on-site hardware
re-configuration, DSP, logic
emulation, network components,
etc.

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 Fault Simulation & Testing

A circuit that has bee designed properly may still

fail to operate in the field. The failure might be
caused by any of the following.

1. Wafer defects
2. Contaminated atmosphere in clean room
3. Impure processing gases water and chemicals
4. Photomask misalignment

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 Circuit Defects & Faults

When a circuit fails to operate correctly, the

logic realized by the circuit is different from
the logic that was specified for the design.
There are a variety of modes by which a
digital circuit may exhibit failure.
• Stuck fault: One common failure mode
occurs when a signal line is shorted to either
the power rail or the ground rail. These failure
modes are called “stuck” faults, and their
location is called a fault site. A CMOS circuit
has a stuck-on fault if the gate of a transistor
is always ON.

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 Fig: Stuck on fault in a 2-input NOR gate

If X1=0, X2=0 then Y=1, but the pull-down transistor with the
stuck-on gate tends to pull Y to 0. The stuck=on fault causes a
current that always tends to discharge the output node of the
device, making the pull-up action slower. The high current
through the pull down transistor will lead to a thermal
degradation and early failure of the circuit.

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 Bridging fault:
1)Faults due to short circuits in the interconnect between transistors in a
logic cell are called bridging fault. Bridging faults are detected by measuring
the quiescent current IDDQ through the circuit.

Fig: A 2-input NOR gate with bridging fault

When X1=0, X2=1; the bridging fault in the pull-up logic cause
a high current to flow between the rails causing thermal
damage and early mortality of the device. IDDQ testing would
detect the presence of this fault.
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