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https://doi.org/10.1007/s11042-019-08517-w

Low power and high-speed FPGA implementation

for 4D memristor chaotic system for image encryption

Esam A. A. Hagras 1 & Mohamed Saber

1

Received: 21 March 2019 / Revised: 22 October 2019 / Accepted: 26 November 2019

# Springer Science+Business Media, LLC, part of Springer Nature 2019

Abstract
In this paper, we proposed a novel low power and high-speed FPGA implementation of
the 4D memristor chaotic system with cubic nonlinearity based on Xilinx System
Generator (XSG) model. Firstly, a pseudo-random number generator based on the
proposed XSG FPGA implementation of the proposed 4D memristor chaotic system
which implemented into Xilinx Spartan-6 X6SLX45 board with 32 fixed-point format.
The aim of the FPGA implementation is increasing the frequency of the memristor
chaotic random number generators. The FPGA implementation of the memristor chaotic
system results show that the new design approach achieves a maximum frequency of
393 MHz and dissipates 117 m watt. The standard fifteen randomization tests are used to
measure the quality of the proposed pseudo-random number generator based on the 4D
memristor chaotic system and it gives an excellent randomization analysis. Also, the gray
image encryption scheme based on the 4D memristor chaotic system has been introduced.
The proposed cryptosystem has a large keyspace, very low correlation values, high
entropy which is much closer to the ideal entropy value, a high number of pixels change
rate and high unified average changing intensity values. The results and security analysis
of the proposed encryption scheme demonstrate that the investigated encryption approach
can protect high speed and high security against various attack.

Keywords Memristor . FPGA . Image encryption . Chaotic system . Randomization tests

* Esam A. A. Hagras
essam.hagras@deltauniv.edu.eg

Mohamed Saber
mohamed.saber@deltauniv.edu.eg

1
Communications and Computer Department, Faculty of Engineering, Delta University for Science
and Technology, Gamasa, Mansoura, Egypt
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1 Introduction

With the rapid development of computer and network technology, the problem of security in image
information transmission and storage draws more attention and image encryption becomes a critical
research topic [18]. Chaos theory in a complex system has been cited increasing in several different
scientific areas, especially in engineering science such as secure communication and cryptography
[3]. Chaotic systems are affected by initial conditions, control parameters and irregular behaviors
[30]. The main advantages of FPGA are its ability to implement complex mathematical systems
with high-speed operation, minimum resource utilization, and parallel processing, which make it the
choice for the researchers to implement their complex designs.
FPGA implementation of chaotic systems provides high operating frequency, minimum
resource utilization, re-programming, and security [45]. As an example, Lorenz’s chaotic
system implemented using FPGA for fourth-order Runge-Kutta (RK4) algorithm [32].
Recently, Memristor is considered to be the fourth fundamental circuit’s element besides
Capacitance, Resistance and Inductors, which has been arousing peoples wide attention with
its unique circuit properties [7, 10]. Nowadays, an in-depth study of connecting the memristor
with chaotic systems has been conducted by many scholars. An idea of adding the memristor
model to Chua’s circuit is presented in [34], while another idea combined the Lorenz chaotic
with memristor is presented in [44]. Recently, more attention has been paid to research on the
memristor chaotic circuits applied to secure communications [28].
Xilinx System Generator (XSG) is a library integrated inside Simulink program allows to
create, design, simulate and generate a Very High-Speed Integrated Circuit Hardware De-
scription Language (VHDL) code for a digital hardware model realized to describe the
operation of digital systems [47]. The main advantage of XSG is the simplicity to generate a
VHDL code for a complex hardware system and provide the required synchronization between
different parts of the model in a graphical user interface (GUI), which consider as a difficult
task in complex digital systems [11, 48]. Another advantage provided by XSG is hardware co-
simulation in which a hardware model implemented into FPGA board can be simulated in the
program environment. Recently, the XGA is used to design and implement many chaotic
systems such as Henon chaotic map, chaotic cellular neural network, chaotic Quadratic map
and Lorenz chaotic system [5, 15, 21, 51].
In this paper, new low power and high-speed FPGA hardware implementation for four
dimensions memristor chaotic system based on XSG model has been introduced. Also, a new
image encryption algorithm based on the FPGA implementation of the 4 D memristor chaotic
system is considered. The main novelties and contribution of this work are summarized as follows:

1- We proposed XSG-FPGA hardware implementation for the 4D memristor element with

cubic chaotic nonlinearity model.
2- Low power of only 117 mW and high speed of 393 MHz XSG FPGA implementation has
been designed.
3- 4D memristor element with cubic nonlinearity model is used as a random number
generator (4D memristor chaotic RNG).
4- Image encryption algorithm based on the 4D memristor chaotic RNG is introduced with
good security.

The organized of this paper is as follows: section 2 discussed the mathematical model and its
Simulink model 4D memristor chaotic element. Next, section 3 describes the FPGA
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implementation of 4D Memristor Chaotic System. XSG-FPGA Memristor implementation

results have been introduced in section 4. In section 5, proposed 4D Memristor Chaotic Image
Encryption (4D MCIE) has been considered. Results and security analysis for the proposed 4D
MCIE algorithm and comparisons are given in section 6. Finally, conclusions are drowned.

2 4D Memristor chaotic system

The memristor chaotic nonlinear model is normalized, and the dynamical equations are given
as follows:

ẋ ¼ αðz−WðwÞxÞ ð1Þ

ẏ ¼ βðy−zÞ ð2Þ

ż ¼ y−x−ζz ð3Þ

ẇ ¼ x ð4Þ

The window W(w) is the memristor nonlinearity model. In this paper, we use the cubic
nonlinearity model which is given by; W(w) = ψ + 3ηw2 where, x0, y0, z0, w0 are the four state
initial condition of memristor, α, β, ζ are the memristor chaotic system secret parameter and
ψ, η are the cubic nonlinearity parameters. The dynamic analysis of the memristor chaotic
model had been studded in details in [14]. The memristive chaotic nonlinearity system is a
system with four state variables. The four state variables xi, yi, zi and wi stats are used to
perform four dimensional times domain sequence which are used to generate the proposed 4D
memristor chaotic RNG.
Simulink is a Graphical User Interface (GUI) program inside Matlab program, contains
different libraries used for modeling, simulating different systems. The main feature of
Simulink is the simplicity to describe analog, digital, and mixed systems besides the ability
to analyze these systems and control every factor in the system. All input and output signals in
Simulink integrated with MATLAB environment [31]. The memristor system model is
developed from the four simultaneous differential equations in Eq. 1 to Eq. 4 using Simulink
blocks in the discrete-time domain as shown in Fig. 1. The system is modeled as a feedback
system with four outputs represent x, y, z and w variables as in Eq. 1 to Eq. 4. The model uses
four adders and subtractors, two multipliers, five gain, and four discrete time integrators blocks
from the math library in Simulink. The model works with a sample time of 0.001 s which can
be changed to any other value. The proposed system is developed from the state equations
using Simulink in the discrete-time domain, as shown in Fig. 1. The system is simulated, and
the simulation results agree with the simulation that has been done using Matlab code. Figure 2
shows the bifurcation diagram of the proposed model using Simulink.
The same simulations based on Matlab code in the continuous-time domain are
repeated in the discrete-time domain using the memristor Simulink model. Figure 2 shows
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Fig. 1 Simulink model for the proposed 4D Memristor chaotic simulation

the bifurcation diagram for each two output variables, Fig. 2a bifurcation diagram between
(x, y), Fig. 2b bifurcation diagram between (y, z), Fig. 2c bifurcation diagram between (z,
x), Fig. 2d bifurcation diagram between (x, z), Fig. 2e bifurcation diagram between (y, x),
and Fig. 2f bifurcation diagram between (z, y).

3 FPGA implementation of 4D Memristor chaotic system

The memristor system is modelled using an XSG; the architecture is implemented into Xilinx
Spartan-6 X6SLX45 board. The memristor architecture is modeled using XSG in 32 fixed-
point format because the system operates with numbers with a fractional part (real numbers).
The speed of operation is the main feature of using the fixed-point format in arithmetic
operations instead of using floating-point format. In different applications where the high
accuracy is not required, the fixed-point format is used [8].
The difficulty of the proposed method is how to convert (implement) the mathematical
equations to a digital circuit has the advantages of low power consumption and works with high

Fig. 2 Bifurcation diagram for the proposed 4D Memristor chaotic system

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frequency using XSG tool. The design of the hardware model is not easy and differs from designer
to another according to the used algorithms and methods to achieve the required target; low
power, and high speed. The proposed hardware model has the three features; firstly, multiplication
which used in arithmetic equations is a very hardware intensive operation, and different designs
aim to provide low-power, smaller area and higher speed multiplier. Every FPGA board provides
multipliers on board to save the area of FPGA, but using these multipliers did not guarantee speed
or low power consumption of the hardware model. In our paper, the used multipliers are designed
using booth multiplier algorithm [27, 42] which performs multiplication by additions and shifting,
and we did not use the multipliers on the board to achieve low power consumption and speed.
Secondally,synchronization, which means the order of performing the mathematical operations
(timing) is not easy, especially in feedback systems as our hardware model. One lead or lag in one
delay unit will make the final result inaccurate.
Finally, We are the first researchers used the XSG tool for implementing the 4D memristor
chaotic system instead of writing a VHDL code. XSG provides full compatibility between the
software and the XILINX FPGA board and also allows optimization between area and speed
of the hardware model. All these features affect the speed and power consumption of the
hardware model. The final judgment on the performance of the hardware model determined by
performing a comparison with other researcher’s works.
The memristor architecture shown Fig. 3; the architecture consists of five adder/
subtractor (Addsub) blocks, two multipliers (Mult) blocks, five gain (Sigma) blocks,
ten delay units (Delay) blocks, and four integrators subsystem. Inside every integrator,
there is one adder, one delay unit and a register to store the initial condition. The critical
point in this feedback architecture, which is different from the design of Simulink is the
timing, so the delay units in this architecture are placed in critical paths to ensure the
synchronization between the different blocks of the architecture [4]. The architecture
provides the four simultaneous differential equation output variables x, y, z and w, as the
output. The architecture of the 4D memristor chaotic system has four integrators, the
model of the integrator consists of an adder and feedback loop to accumulate the input,
with a specific initial condition as shown in Fig. 4.

Fig. 3 Xilinx System Generator model of proposed memristor implementation

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Fig. 4 Integrator hardware model

The Register transfer level (RTL) indicates the hierarchy of the digital system with the
flow of input signals to the output signals. The critical path, which is the longest path in
synchronous systems, can be investigated in RTL, besides showing the hardware blocks
(register, multiplexer….) of the synthesized system [19]. The RTL of the proposed 4D
memristor chaotic system implementation shown in Fig. 5.

4 FPGA Memristor implementation results

4.1 Behavioural simulation

In this type of simulation, the validity of the memristor hardware model tested by performing
the same type of simulation that has been investigated by the Matlab code and Modelsim
discrete-time model. As an advantage of XSG, we export the output of the architecture to the

Fig. 5 The RTL for the proposed Memristor Chaotic System implementation
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Fig. 6 Bifurcation diagram for the proposed hardware Memristor Chaotic System implementation

workspace of the Matlab program to perform the same kind of theoretical simulations. Figure 6
shows a bifurcation diagram generated by memristor hardware in the same order of Simulink
simulation shown in Fig. 2. Figure 6 indicates the 2D plot for the output variables in the same
order of the Simulink simulations in Fig. 2. It is clear after comparison between the hardware
models simulations with theoretical simulations that both are identical with only a small
difference in amplitudes as a result of finite word length in digital circuits agree with the
mathematical simulations. The system generator tool generates a synthesizable VHDL code
opened using Xilinx ISE software, in which the simulations, pin location, synthesizing to
FPGA board are done. The VHDL simulation in Fig. 7 indicates the simultaneous change of
the four variables x, y, z and w in the time domain. It is known that the output of hardware
model is binary fixed-point numbers between 0 and 1, a good feature in this time-domain
browser (Wave scope) is browsing the variables with decimal values as shown in the Fig. 7.

4.2 Device utilization

After the implementation of the model, the device utilization summary which indicates how
much resources (Registers, LUT, LUT flip-flops) of the FPGA device are used to implement
the memristor architecture is shown in Fig. 8.

Fig. 7 VHDL simulations of the proposed Memristor Chaotic System implementation

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4.3 Timing report

The timing summary report shows whether a design met timing. Xilinx recommends
creating constraints for all input, output, and clock. All input use ‘Global offset in’
constraints, all outputs use ‘Global offset out’ constraints, all clocks use ‘Period’ con-
straint for each clock. The timing report in Fig. 9 indicates whether a design achieved the
timing constraints or not. In the report, the minimum period is the maximum delay from
any synchronous element to another, in other words, it is the maximum frequency which
indicates the speed of the model, and it is 393.660 MHz. The minimum input arrival time
before clock which is the minimum ‘global offset in’ constraint is 0.681 ns, while
maximum output required time after the clock is the maximum ‘Global offset out’
constraint is 3.597 ns. The maximum combinational path delay is the maximum delay
for generating output from combinational circuits in the model is 1.22 ns. After analyzing
the timing report and comparing the results with the input constraints, results ensure that
all constraints are achieved.

4.4 Power consumption

The estimation of power consumption is done using XPower analyzer tool. Generally,
there are two main types of power consumption with FPGA devices. A dynamic power
which, represents the fluctuating power as the design runs; it is the amount of power
generated by the switching and routing for the memristor model. The other type of power
is the quiescent (static) power; it is independent of the memristor model and consumes
when there is no switching activity. The power report also reports the FPGA current
requirements from the different power supply sources. The power report in Fig. 10
indicates that the total dissipated power is 117 watt, which means the design has low
power consumption.

Fig. 8 Device utilization report of the FPGA board for the proposed Memristor Chaotic System
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Fig. 9 The timing report of the FPGA board for the proposed Memristor Chaotic System implementation

5 Proposed 4D Memristor chaotic image encryption (4D MCIE)

In this section, we introduced new image encryption based on the chaotic behavior of the 4D
Memristor elements with cubic nonlinearity. Recently, some of the researchers studied the traditional
chaotic system, for example, logistic map, Lorenz and Chua circuit, and so on. The recent study of
the memristor element shown that the chaotic behavior of this element can enhance the resolution of
the chaos computations [29, 46, 49]. The general block diagram of the proposed 4D MCIE and its
secret parameters are shown in Table 1.
The proposed image encryption exhibit the memristor chaotic behavior and used it in the
confusion and the diffusion steps to encrypt an image as follows:

Step 1. Confusion Process

The confusion process is the pixel image scrambling step, and it changes the pixel position
with no change in its values. Arnold, Hilbert curve and Magic cube pixel transform [23, 24,
33] can be used as a confusion scheme of the image scrambling. The first two output states x
and y of the memristor element are used to generate the two secret parameters (a, b) of Arnold
Cat Map (ACM) by sum the last 100 floating-point values of the x and y states and covert the
summation to find the two decimal values a, b dynamic parameter for Arnold cat map as [50]:




X mþ1 1 a Xm
¼ mod 256 ð5Þ
Y nþ1 b ab þ 1 Y n

This equation is the Arnold cat map which used as scramble map for the image pixel position
where, Xm and Ym are the old pixel position, Xm + 1 and Ym + 1 are the new pixel position for the
scrambled image. The values a, b are the dynamic parameter for Arnold cat map which are two
decimal values can be calculated as:

Fig. 10 Power consumption for the proposed Memristor Chaotic System implementation
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Table 1 parameter values of the fractional-order memristor chaotic model [14]

Parameters Values

x0, y0, z0, w0 (0.001, 0.0, 0.001, 0.001, 0.0)

α, β, ζ α = 5.3, β = 0.75, ζ = 0.1
ψ, η ψ =5.3 and η =0.8
a, b Arnold Cat Map control parameters

100
a ¼ ∑ x*1016 mod 64 ð6Þ
1

100
b ¼ ∑ y*1016 mod 128 ð7Þ
1

Equation (6) is the summation of the last 100 floating-point values x of multiplied by the factor 1016
and the final summation is modulo 64, it mains that the minimum and maximum values for the
parameter a are from 1 to 64, respectively. Also, Eq. (7) can be calculated as Eq. (6) except the range
of the parameter b will be from 1 to 128 of the last 100 floating-point values y, respectively. The last
100 floating-point values of x and the last 100 floating-point values of y are given from the 4D
memristor chaotic system shown in Fig. 3. The encryption schemes required a diffusion process to
enhance security.

Step 2. Diffusion Process

The diffusion process is responsible for changing all pixel values of the scrambled image, so, the
memristor diffusion can be applied based on the last two output states z and w of the 4D memristor
chaotic system shown in Fig. 3 as follows:

1- Select the last M × N floating point values of the z and w states and add z and w as:

 
qi ¼ zi þ wi mod 1 ð8Þ

The final outputs qi are floating point sequence with a length of i = M × N based on z and w
states given from Fig. 3 each with lengths of M × N

2- Convert the M × N q-values into a decimal values in the range of [1, 256] as:

 
Qi ¼ qi *1016 mod 256 ð9Þ

The outputs qi are floating point sequence are multiplied by a factor 1016 and the final
multiplications are modulo 256 in order to convert the qi floating point to decimal values
Qi in the range of [1, 256].
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3- The diffusion process is based on the exclusive-OR (XOR) operation by XOR each pixel
in the scrambled image with the decimal values Qi in the range of [1, 256] bit by bit given
from Eq. (9).

The decryption is the inverse process of the encryption steps with the same secret keys where
the inverse Arnold cat map can be determined as follows [50]:




Xm a*b þ 1 −a X mþ1
¼ mod 256 ð10Þ
Ym −b 1 Y mþ1

The inverse Arnold cat map given in Eq. (10) is the inverse of Eq. (5) which is used to de-
scramble the scrambled image calculated by Eq. (10). Finally, the de-scramble image
given from Eq. (10) is XORed with the decimal values Qi in the range of [1, 256] given
from Eq. (9).
In this paper, the proposed hardware encryption is based on the following steps:

1- The MATLAB function (imread ()) is used to read the input image of pixel size 256 X 256
into matrix data of order 256 X 256 showing the pixel values in vector format. The data is
converted to hexadecimal vector to be suitable for file transfer into the FPGA board.
2- Xilinx spartan-6 has an XCF04S serial configuration Flash PROM to store FPGA
configuration data and potentially additional non-volatile data.
3- Using USB cable, the hexadecimal data file transfers to the onboard flash PROM and
make the FPGA load the input from the onboard flash PROM.
4- Using USB cable, the programing bit file (generated from VHDL file) will be transferred
to the FPGA chip.
5- The output of the hardware model assigned to VGA port which exists in the FPGA board.

6 Results and security analysis

The security performance of the proposed 4D Memristor Chaotic Image Encryption for a different
type of images has been studded and analyzed against statistical attacks, cryptanalytic attacks, and
brute-force attacks. Different images are used in this paper with a size of 256 × 256 pixels. Figure 11
shows the results of the proposed 4D Memristor Chaotic Image Encryption for different images.

6.1 Differential attack analysis

The Number of Pixels Change Rate (NPCR) and the Unified Average Changing Intensity
(UACI) are the famous two methods for the security strength against the differential attack.
The ideal theoretical values of NPCR and UACI are 99.61% and 33.46% [9, 20, 26].
Mathematically, the NPCR and UACI between two cipher image C1 and C2 with the same
secret key are defined as Eqs. (11) to (13) [43]:
N M
∑ ∑ Dði; jÞ
i¼1 j¼1
NPCR ¼ *100% ð11Þ
M *N
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Fig. 11 Histogram analysis of original and encrypted image for the proposed 4D Memristor Chaotic Image
Encryption

Where D (i, j) is a binary matrix of the same size as the cipher image and is defined as:

1 if C 1 ði; jÞ≠C 2 ði; jÞ
Dði; jÞ ¼ ð12Þ
0 if C 1 ði; jÞ ¼ C 2 ði; jÞ

The Eq. (11) is the summation of the two-dimension binary matrix D(i,j) divided by the image
size of length the M × N and the final results multiplied by 100%.
N M
∑ ∑ jC 1 ði; jÞ−C 2 ði; jÞj
1 i¼1 j¼1
UACI ¼ *100 ð13Þ
M *N M N
Also, the Eq. (12) is the summation of the amplitude difference of the two-dimension
binary matrix D(i, j) divided by the image size of length the M × N and the final results
multiplied by 100. The results of the algorithm are compared to the algorithms reported in
some references, as mentioned in Table 2. Table 2 shows the NPCR and UACI results by
varying the value of a single-pixel at a different position. It is noted that form the NPCR
and UACI results that simulated results are nearest the theoretical NPCR and UACI
values, so, it can be said that the proposed encryption algorithm is secure against the
differential attacks.

6.2 Statistical analysis

The proposed 4D Memristor, Chaotic Image Encryption scheme, is tested against three
different statistical attacks: image histogram, correlation and entropy attacks. The best cryp-
tosystem must have excellent statistical analysis results.
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6.2.1 Histogram analysis

An image histogram illustrates the distribution of the pixel intensity values within an
image. It can be seen that the pixel distribution of the encrypted image in Fig. 11 is fully
encrypted and fully uniform pixel distribution, which can extremely reduce the correlation
between the pixel values. So the information of the image can be protected to resist the
statistical attack [43].

6.2.2 Correlation analysis

For grey images, the pixel correlation along one direction is usually tested as follows. Given a
number N, randomly select a set of N pixels. Denote the set of the selected pixels as x and
denote the set of pixels adjacent to the pixels in set x along the intended direction as y. Each
pixel in x and its adjacent pixel in y forms a pixel pair. Then, construct a length-N vector x
using the grey values of the pixels in x, and similarly construct a vector y based on set y.
Finally, the correlation along the intended direction is calculated as given in Eq. (14) where
D(x), D(y) and cov(x, y) are defined in Eq. (15) to Eq. (14):

r¼ pffiffiffiffiffiffiffiffiffiffi
Covðx;yÞ ð14Þ
DðxÞ:DðyÞ

1 N  2
DðxÞ¼ ∑ x−x ð15Þ
N i¼1

1 N  2
DðyÞ¼ ∑ y−y ð16Þ
N i¼1

1 N  
Covðx; yÞ ¼ ∑ x−x y−y ð17Þ
N i¼1
where x and y are the grayscale values of two adjacent pixels in the image, and N is the
total number of pixels selected from the image, and where Cov(x, y) is the covariance of
x and y. D(x), D(y) is the standard deviation of x and y, where x is the average value of x
and y is the average value of y. Figure 12 shows that the correlation analysis of the two
horizontally adjacent pixels in the encrypted image. Also, Table 3 shows that the
correlation coefficients of the encrypted image are nearly to 0, which indicates that the
proposed 4D MCIE have good confusion and diffusion properties. The simulation results
of the correlation analysis are reported in Table 3. It is noted that all the correlation

Table 2 NPCR and UACI results of the proposed 4D Memristor Chaotic Image Encryption

Image Lena pepper Cameraman Baboon

NPCR 99.654 99.663 99.562 99.476

UACI 33.435 33.365 33.411 33.367
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Fig.12 a Correlation analysis of two horizontally adjacent pixels in plain image. b Correlation analysis of two
horizontally adjacent pixels in ciphered image

analysis for the diagonal, horizontal and vertical results are very closed to zero, which
means that the proposed 4D MCIE scheme is robust against the statistical attacks.

6.2.3 Entropy analysis

The randomness of the received image can be calculated by using information entropy, it
represents uncertainty in the cipher image if the entropy of the encrypted image is high, the
image has high randomness, and high confidentiality and the entropy of a system is defined as [9]:
2N −1
H ðmÞ ¼ − ∑ pðmi Þlog 2 pðmi Þ ð18Þ
i¼0

Where m is the source of information, N total number of bits represents the

symbol mi, pðmi Þ probability of symbol mi, the ideal value of the cipher image information
entropy close to 8. The information entropy of the cipher-image produced by our algo-
rithm is 7.99, which is near to 8. That means the minimal probability for attacker to decode
cipher image. In Table 4, the information entropy of the proposed 4D MCIE scheme are
computed and it is much closed to 8.

Table 3 Correlation analysis results of two horizontally adjacent pixels in ciphered image

Image Lena pepper Cameraman Baboon

Correlation 0.0016 0.0018 0.0045 0.0063

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Table 4 information entropy by the proposed 4D MCIE scheme

Lena pepper Cameraman Baboon

7.9978 7.9345 7.9698 7.949

6.3 Key spacing analysis

The key attacks are used to break the security of the cryptosystems by the cryptanalyst to
analyzed the secret key so, the cryptosystems must have high key strength. Also, the key
spacing and key sensitivity analysis are used for the secret key analysis. The brute force attack
is measured by the key spacing analysis and the minimum keyspace to resist the brute-force
attacks is 2100 [9]. According to the IEEE floating-point standard [17], the computational
precision of 32-bit double-precision number is about 10−15, Because any initial condition has
1015 Possible value within (0, 1). The proposed 4D MCIE scheme contains eleven key
parameters, which are the initial values x0, y0, z0, w0, α, β, ζ, ψ, η and a, b. only the last
two parameters are 8-bit key, so, the total keyspace of the proposed algorithm is equal to 1015 ×
9 × 28 × 2 which is much greater than 2100. Finally, the keyspace analysis of the proposed 4D

MCIE scheme indicates that it is large enough to resist the brute force attack.

6.4 Randomization analysis

It is necessary to test the randomization of the proposed 4D Memristor Chaotic RNG

obtained in this paper. The 2010 version US statistical test suite published by the NIST
[35] and is used to check random image encryption; The test statistic is used to calculate p
_ value, that is, the possibility that a random generator produces a less random sequence
than the given test sequence. If p _ value equals 1, it means that the sequence being tested
is completely random, while p _ value 0 indicates a non-random character. A level of
importance (α) is created to determine the acceptance of random hypotheses for a given
sequence. Typically, α is selected in the range [0.001, 0.01]. In this paper, the tested code
images are converted to binary sequences and the value of α is set to 0.01. We use the

Table 5 NIST SP 800–22 pseudo-random sequence test results

Statistic Tests for ciphered image p − value Results

1 Frequency (monobit) 0.8713 Pass

2 Block Frequency (M = 128) 0.6839 Pass
3 Runs 0.4649 Pass
4 longest run of ones (M = 128, N = 49, K = 5) 0.6645 Pass
5 Binary matrix rank test 0.6616 Pass
6 Discrete Fourier transform 0.9475 Pass
7 Non-overlapping template (m = 9, B = 101,000,111) 0.6823 Pass
8 Overlapping template matching 0.7245 Pass
9 Maurer’s “universal statistical” 0.6814 Pass
10 Linear complexity (L = 6, Q = 640, K = 86,741) 0.8254 Pass
11 Serial test (M = 10) 0.9162 Pass
12 Approximate entropy 0.8193 Pass
13 Cumulative sums (Forward) 0.7351 Pass
14 Random excursions (x = 1) 0.6954 Pass
15 Random excursions variant (x = 1) 0.3836 Pass
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Table 6 Comparison of the proposed encryption scheme with some chaotic cryptosystems

References NPCR UACI Correlation entropy

Ref. 2019 [12] 99.5994 33.418 0.0209 7.9931

Ref. 2019 [38] 99.600 33.390 0.0857 7.9992
Ref. 2019 [16] 99.629 33.365 0.0032 7.9956
Proposed 99.654 33.435 0.0016 7.9978

standard tests parameters with the NIST SP 800–22 standard software package [35]. The
results are shown in Table 5. Note that the bit sequence passed the 15 tests and verified the
pseudo random assumption. It is shown that the proposed RNG passed all NIST SP 800–
22 testes.

6.5 Comparison and discussion

A comparison of the proposed encryption system and some of the existing chaotic
cryptosystems based on different mathematical structures presented in [12, 16, 38]
conducted in this section. For a fair comparison, all security analysis applied to the
Lena image of size 256 × 256. The chaotic cryptosystems comparison are presented in
Table 6.
It is shown from Table 6 that the security results of the proposed encryption scheme are
comparable with different chaotic cryptosystems. It is evident from this table that the
proposed cryptosystem is robust against different attacks. A comparison between different
hardware models for chaotic systems in recent years and the proposed hardware imple-
mentation model present in Table 7. As shown in Table 7, the proposed hardware model
provides lower power consumption and the higher operating frequency compared to
different models.

Table 7 Hardware Implementation Comparison between proposed encryption and similar chaotic systems

Reference Analysis Area Resources Max. Frequency Power

Method (MHz) (mW)
Slice LUTs Multipliers
Registers

Ref. 2009 [37] RK4 1138 1969 40 22 –

Ref. 2013 [6] RK4 1695 3251 78 38 321
Ref.2014 [25] RK4 42,021 39,309 – 373 –
Ref.2015 [39] RK4 1477 2727 24 58 –
Ref. 2015 [1] RK4 10,630 17,160 11 86 –
Ref.2016 [2] RK4 86,328 87,207 – 266 –
Ref.2016 [41] RK4 45,805 47,273 – 390 –
Ref. 2017 [36] RK4 94,323 89,129 – 325 –
Ref.2017 [13] RK4 476 928 – 31 –
Ref.2018 [22] Euler 165 311 22 59 –
Ref. 2018 [52] AES 5566 – – 214 –
Ref. 2019 [40] RK4 160 247 0 64 –
Proposed RK4 948 294 0 393 117
system
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7 Conclusions

In this paper, a new low power and high-speed FPGA implementation based on Xilinx System
Generator (XSG) model for the 4D memristor chaotic system with cubic nonlinearity has been
designed. The FPGA implementation of the memristor chaotic system results show that the new
design approach achieves a maximum frequency of 393 MHz and dissipates 117 m watt. The 4D
memristor chaotic system with cubic nonlinearity model is used as a random number generator.
Also, the SP 800–22 standard fifteen randomizations tested is used to proofs the pseudo-random
sequence of the4D memristor chaotic system. Also, the grey image encryption scheme based on the
4D memristor chaotic system with the cubic nonlinearity has been introduced. The confusion and
the diffusion processes are used to get higher strength of the cryptosystem. The statistical tests are
used to measure the quality of the proposed grey image encryption scheme. The proposed
cryptosystem has a large keyspace, very low correlation values, high entropy which is much closer
to the ideal entropy value, a high number of pixels change rate and high unified average changing
intensity values. The results and security analysis of the proposed 4D memristor chaotic encryption
scheme demonstrate that it has high security against various attack. High order nonlinearity for the
4D memristor chaotic can be design and implemented with image encryption and watermarking in
possible direction for our future work.

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institutional affiliations.

Esam Hagras received the B.S degree in Electrical Engineering from faculty of engineering Alexandria
University, Egypt in 1994, M.S degree in 2001, PhD in 2007 Alexandria university, Egypt. Recently works in
Delta University for science and technology, Faculty of Engineering, Communication and Computers Dept. in
Gamsa, Mansoura, Egypt. His research interested in the field of Information and Multimedia Security, Chaotic
cryptography, FPGA hardware Implementation of security systems.
 Multimedia Tools and Applications

Mohamed Saber received the B.S degree in Communication and Electronics Engineering from faculty of
engineering Mansoura University, Egypt in 2001, M.S degree in 2006, PhD in 2012 Kyushu university, Japan.
Recently works in Delta University for science and technology, Faculty of Engineering, Communication and
Computers Dept. in Gamsa, Mansoura, Egypt. His research interested in the Signal processing, Biomedical,
Digital Communication, FPGA hardware Implementation.