module shiftregsiter(

input clk,
input si,
output so,
input reset
);

reg [7:0] tmp;

always @(posedge clk)

begin
if (~reset)
begin
tmp = tmp << 1;
tmp[0] = si;
end
else tmp = tmp;
end

assign so = tmp[7];

always @(posedge reset) tmp = 8'b00000000;

endmodule

module shifttest;

// Inputs
reg clk;
reg si;
reg reset;

// Outputs
wire so;

// Instantiate the Unit Under Test (UUT)

shiftregsiter uut (
.clk(clk),
.si(si),
.so(so),
.reset(reset)
);

initial begin
forever begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end

initial begin
reset <= 0;
#6
 reset <= 1;
#6
reset <= 0;
end

initial begin
forever begin
si= 0;
#7
si = 1;
#8
si = 0;
#8
si = 1;
#8
si = 1;
end
end
endmodule

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module registerleftright(sl, sr, din, clk, reset,Q);
input sl, sr, din, clk, reset;
reg [7:0] Q;
output [7:0] Q;

always @ (posedge clk) begin

if (~reset) begin

if (sl) begin
Q <= {Q[6:0],din};
end

else if (sr) begin

Q <= {din, Q[7:1]};
end
else Q <= Q;
end

end

always @ (posedge reset) begin

Q<= 8'b00000000;
end

endmodule

module test1;
reg clk, reset, din, sl, sr;
wire [7:0] q;

registerleftright registertest(sl, sr, din, clk,reset, q);

initial begin
forever begin
 clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end

initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end

initial begin
sl = 1;
sr = 0;
#50
sl = 0;
#12
sr = 1;
end

initial begin
forever begin
din = 0;
#7
din = 1;
#8
din = 0;
end
end

endmodule
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module registerload(
input clk,
input parallelload,
input [7:0] input1,
input sin,
output sout
);

reg [7:0] tmp;

always @(posedge clk)

begin
if (parallelload)
tmp <= input1;
else
begin
tmp = {tmp[6:0], sin};
 end
end
assign sout = tmp[7];
endmodule

module testparallel;

// Inputs
reg clk;
reg parallelload;
reg [7:0] input1;
reg sin;

// Outputs
wire sout;

// Instantiate the Unit Under Test (UUT)

registerload uut (
.clk(clk),
.parallelload(parallelload),
.input1(input1),
.sin(sin),
.sout(sout)
);

initial begin
forever begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end

initial begin
parallelload = 0;
#10
input1=8'b11111111;
#10
parallelload = 1;
#10
parallelload = 0;
end

initial begin
forever begin
sin = 0;
#7
sin = 1;
#8
sin = 0;
end
end
endmodule

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++