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10, OCTOBER 2005 1167

Two-Dimensional Position Detection System With

MEMS Accelerometers, Readout Circuitry, and
Microprocessor for Padless Mouse Applications
Seungbae Lee, Student Member, IEEE, Gi-Joon Nam, Member, IEEE, Junseok Chae, Member, IEEE,
Hanseup Kim, Student Member, IEEE, and Alan J. Drake, Student Member, IEEE

Abstract—A hybrid two-dimensional position sensing system is and 4) a 16-b RISC microprocessor. Fig. 1 presents the block
designed with microelectromechanical systems (MEMS) for pad- diagram of overall hybrid mouse system. Two MEMS ac-
less mouse applications. The -axis acceleration of the user’s celerometer devices are employed to measure - and -axis
hand movements is measured by two MEMS accelerometer de-
vices. These acceleration values are pulsewidth modulated and con- acceleration of the movements from the user’s hand. These
verted into ( , ) coordinates on the screen by integral operations acceleration values are pulsewidth modulated (PWM) by the
on a microprocessor. The overall system consists of four major CMOS analog readout circuitry and will be converted into ( ,
components: 1) MEMS accelerometers; 2) CMOS analog readout ) coordinates on the screen by performing integral operations
circuitry; 3) an acceleration magnitude extraction module; and on a 16-b RISC microprocessor. In this design, we present
4) a 16-b RISC microprocessor. Mechanical and analog simulation
shows that the designed mouse system can detect acceleration as a hybrid configuration system where each component is not
small as 5.3 mg (g = 9 8 m/s2 ) with 100-kHz sampling frequency based on the same substrate and has to be interfaced with
for low power consumption. others by means of external connection such as wire bonding.
Index Terms—Acceleration measurement, analog inte- The MEMS device is designed in silicon-on-glass (SoG) tech-
grated circuits, microelectromechanical devices, microprocessor nology developed at the University of Michigan. The analog
applications. readout circuit is designed in a dual-poly, single-metal process,
and the digital microprocessor is designed in a 1.5- m AMI
I. INTRODUCTION process through MOSIS using SCMOS design rules. We will,
however, discuss further the possibility of implementing all of

M OST commercial mouse systems are built employing a

ball or optical technique to provide cursor positions. For
example, a ball mouse system detects physical rolling move-
these components as a monolithic system. Another interesting
aspect of this design is that it can be handily extended into a
three-dimensional (3-D) position detection system by adding an
ments of the ball, which can be significantly affected by a non- additional MEMS accelerometer to measure -axis directional
flat or obstructed surface. An optical mouse system avoids these movement.
environmental factors by detecting the reflection of light, in- The remainder of this paper is organized as follows.
stead of physical contacts, on reflective supplementary pads. Section II presents the overall system architecture and explains
Both types of mouse, however, require a special surface, thus each module in detail. Section III describes the verification
limiting the working space and freedom of user’s movements. and testing methodology of the system. Section IV presents
Obviously, a more desirable mouse system will be the one that statistical data of the final design, and Section V describes
is not restricted by any circumstantial factors. the future work relevant to monolithic implementation of all
In this paper, we describe a novel mouse system design the components. Finally, concluding remarks are given in
which detects two-dimensional (2-D) positions without any Section VI.
contacts on additional components such as pads. The system
consists of four major components: 1) microelectromechanical
systems (MEMS) accelerometers; 2) CMOS analog readout
circuitry; 3) an acceleration magnitude extraction module; II. SYSTEM OVERVIEW

A. System Requirements and Constraints

Manuscript received June 25, 2002; revised September 2, 2003.
S. Lee and H. Kim are with the Department of Electrical Engineering and Two system requirements stand out for consideration: speed
Computer Science, University of Michigan, Ann Arbor, MI 48109 USA (e-mail:;; and accuracy. The motion of human hands can be categorized
J. Chai was with the Department of Electrical Engineering and Computer into two kinds: voluntary and involuntary movements [1], [2].
Science, University of Michigan, Ann Arbor, MI 48109 USA. He is now with The focus of our position detection system is to sense only vol-
the Electrical Engineering Department, Arizona State University, Tempe, AZ
85287 USA (e-mail: untary motions, calculate acceleration of those motions, and
G.-J. Nam and A. J. Drake were with the Department of Electrical Engi- convert it into position information. As can be seen in Table I,
neering and Computer Science, University of Michigan, Ann Arbor MI 48109 the highest frequency of hand movement is about 25 Hz, which
USA. They are now with IBM Austin Research, Austin, TX 78758 USA (e-mail:; is slow compared to the speed of modern microprocessors. The
Digital Object Identifier 10.1109/TVLSI.2005.859473 mouse system must be able to generate ( , ) coordinate values
1063-8210/$20.00 © 2005 IEEE

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Fig. 1. Block diagram for the hybrid mouse system.

TABLE I low temperature drift [10]. The device dimensions were opti-
SPEED OF HAND MOTIONS mized for smaller size and larger sensitivity. After optimization,
its functionality was verified using ANSYS. For the analog
readout circuit design, switched-capacitor circuits were chosen
to simplify the interface between analog and digital parts. All
of the analog circuit designs were simulated with HSPICE and
laid out using Mentor Graphics software.
A top-down approach was used to partition the design into
its various analog, digital, and MEMS components. At each
level, each component is decomposed into several submodules
in recursive fashion. After all of the necessary modules were
identified, each module was carefully designed, fully tested for
faster than this rate. Thus, the sampling rate of position infor- functionality, followed by layout versus schematic (LVS) and
mation was chosen to be 100 Hz (every 10 ms), and, accord- parasitic extraction for layout and timing verification. Then,
ingly, the target clock frequency for the microprocessor was those modules are stitched together to form a super-module
set to 100 kHz, thus providing enough operations (1000 clock at a higher level (bottom-up design). Only after all three ver-
pulses) to calculate the coordinates per sampling. In terms ification procedures were satisfied were modules instantiated
of movement accuracy, it is reported that the acceleration noise and used at a higher level of the design hierarchy. The majority
of about 15 mg (g m/s ) is generated when normal of modules—the datapath of the microprocessor, analog cir-
people hold their hands as motionless as possible [7]. This value cuitry, and MEMS device—are full custom designs while the
sets the minimum resolution required for an acceleration detec- microprocessor controller was designed and synthesized using
tion system. Auspiciously, the MEMS accelerometer adopted Verilog HDL.
for the current design provides its finest resolution due to its
micrometer-level dimension and measurement. In a MEMS ac- C. Operational Overview
celerometer, the sensitivity is defined as the capacitance varia-
tion per gravity change, and this variation is easily converted to Fig. 1 shows an overall operational block diagram of the
voltage through analog readout circuits. Thus, the combination mouse system. When a user moves the mouse in an arbitrary
of MEMS accelerometer’s sensitivity, the gain of analog readout direction, the acceleration is decomposed into - and -axis
circuit, and its equivalent input noise determines the overall components which are measured by a corresponding “MEMS
minimum detectable acceleration of the system. Taking this into accelerometer.” The measured acceleration value is represented
account, the analog readout circuit and MEMS accelerometer by a differential capacitance between two capacitors in the
are designed to detect acceleration as small as 5 mg so that our MEMS device. This capacitance value is fed into the system
system can catch any smallest movement a human being can in two different ways: 1) back to the MEMS device to reset it
generate. Consequently, our system specification shows that it so that we can measure the next acceleration without any bias
is sufficiently fast and precise to reflect a variety of movements and 2) into CMOS analog readout circuitry which modulates
from a user. As far as power concerned, low-power consump- the capacitance value into digital pulsewidth output voltage.
tion is expected due to low operational frequency. The polarity of the pulse, whether it is positive or negative,
determines the direction of the acceleration and the width of
the pulse is propositional to the magnitude of the input accel-
B. Design Methodology
eration. An “acceleration magnitude extractor” changes the
A capacitive sensing configuration using the MEMS ac- generated pulsewidth into the units of system clock frequency,
celerometer was chosen because it gives high sensitivity with which will be used by a microprocessor to calculate the exact

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Fig. 3. Fabrication process sequence. (a) Making recess on a glass. (b) Bond
Fig. 2. SoG MEMS accelerometer. glass substrate to a silicon wafer. (c) Thin the silicon wafer down to desired
thickness. (d) Deposit metal contact. (e) DRIE to release the structure.
position coordinates on the screen. In the next section, each
subcomponent is explained in details.

D. MEMS Accelerometer
Typically, there are three different types of MEMS ac-
celerometers: piezoresistive [8], tunneling [9], and capacitive
[10], [11]. The capacitive accelerometer was chosen for this
system because it provides high sensitivity, good dc response,
low drift, low temperature sensitivity, low-power dissipation,
and a simple structure [12]. For implementation, SoG tech-
nology is used to take advantage of its robustness and simplicity Fig. 4. Top view of a fabricated MEMS accelerometer.
of design.
Fig. 2 shows the structure of an SoG lateral accelerometer
and weighs 0.25 mg. The sense capacity and sensitivity are
[10]. A MEMS accelerometer consists of two major compo-
approximately 16.4 pF and 0.78 pF/g, and the noise floor is
nents: a proofmass and sensing electrodes. A thick silicon proof-
10 g/Hz. For the 2-D mouse system, two lateral accelerom-
mass is connected to a frame, which is anchored to a glass sub-
eters are required for sensing - and -axis accelerations. A
strate with suspension beams and comb fingers are formed using
schematic top view of the MEMS accelerometer in Fig. 2 is
deep reactive ion etching (DRIE). Since the proofmass is sus-
shown in Fig. 5(a).
pended over recess on a glass substrate with serpentine suspen-
The fabrication process has five steps requiring only three
sion beams, it is free to move with a response to external accel-
masks. Fig. 3 shows the cross section of the wafer for each fab-
eration. On the other hand, electrodes are attached to the glass
rication step. In the first step, a recess is formed on the glass
substrate [Fig. 3(a)]. Then, the glass wafer with recess is an-
When external forces are applied to the accelerometer—for
odically bonded to silicon water [Fig. 3(b)]. Next, the silicon
example, by the user’s hand movement—the proofmass moves
wafer is thinned to desired thickness with chemical mechan-
against the forced direction due to an inertia force while the
ical polishing (CMP) [Fig. 3(c)]. Metal contacts are evaporated
electrodes are stationary. The movement causes capacitance
[Fig. 3(d)], and, finally, a deep DRIE etch is performed to release
variations between the comb fingers which form parallel-plate
the structure [Fig. 3(e)]. Fig. 4 shows a scanning electron mi-
capacitors, denoted as . One side of the comb fingers gener-
croscope (SEM) picture of a MEMS accelerometer taken after
ates a positive variation , and the other side produces
fabrication. MEMS accelerometers can be readily integrated to
a negative one . The total capacitance change is the
other circuits using post-CMOS processing [13]–[15].
difference between these two values .
Therefore, the external acceleration is converted to the differ- E. CMOS Analog Readout Circuits
ential capacitance variation which can be expressed as
The detected acceleration, which is represented as a differ-
pF/g (1) ential capacitive variation from the MEMS accelerometer as il-
lustrated in Fig. 5(a), is modulated to pulsewidth by the analog
where is the mass of a proofmass, is the rest capaci- readout circuitry as shown in Fig. 5. In general, the lateral ac-
tance, is the sensing gap distance, and is the spring con- celerometer presented in Section II-D can be operated either
stant of suspension beams [11]. From (1), it can be expected in open-loop mode or closed-loop mode. In closed-loop op-
that a heavy accelerometer with a large number of comb fin- erational mode, the overall performance such as linearity, dy-
gers and compliant structure—i.e., small spring constant—pro- namic range, and bandwidth are improved [11]. In our design,
vides good sensitivity, although it is difficult to fabricate such an electromechanical oversampled modulator is used because it
accelerometers. The dimension of the fabricated single-crystal provides direct digital output and force feedback control of the
silicon proofmass is 2.1 mm 2.4 mm 100 m ( ) proofmass simultaneously over a wide dynamic range.

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Fig. 5. Sigma–delta electromechanical modulator with clock phases. (a) Illustration of capacitive accelerometer model for electronic interface. (b) Sigma–delta
electromechanical modulator circuit schematics. (c) Clock phases.

Another various class of electromechanical modulators, the , sense capacitors and are charged through
switched-capacitor sigma–delta electromechanical modulator and . The charge difference between and is in-
[Fig. 5(b)], is employed because it is insensitive to the input tegrated on the feedback capacitor , while the comparator
parasitic capacitance. An efficient gain- and offset-compen- quantizes the charge. In this phase, the offset voltage stored in
sated integrator is obtained by using an offset-storage . is subtracted and thus the output voltage op-amp is com-
This technique is called the correlated double sampling (CDS) pensated. The amplitude of op-amp output voltage corresponds
technique [16] and can reduce noise and offset in op-amp. to the magnitude of applied acceleration. For example, if the
The circuit uses a single-ended charge integrator to read out the MEMS device gets positive acceleration, then the proofmass is
capacitance variation, and the static comparator forms the loop closer to the left anchor of the MEMS accelerometer and
quantizer. Finally, a digital flip-flop samples the output from is bigger than . Since is connected to the negative
the comparator and synchronizes its bitstream with the system reference voltage , the negative net charge is sampled to an
clock. Since the proofmass can be modeled as a second-order integrator, generating positive op-amp output voltage. The ca-
system, the closed-loop system becomes unstable, so a simple pacitance sensitivity defined as the op-amp output voltage due
lead compensator is inserted in the feedback path for to input capacitance charge is calculated by
There are four clock phases in the switched-capacitor inter- (2)
face circuit [Fig. 5(c)]. During the first phase , the sense ca-
pacitors formed between electrodes and proofmass are reset and From (2), the capacitance sensitivity is approximately
the op-amp offset voltage is stored on . In the second phase 0.33 V/pF. The quantized output is also latched at the end of

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Fig. 6. HSPICE simulation for analog readout circuit.

Fig. 8. Brownian noise.

Fig. 7. Layout for sigma–delta analog readout circuitry (die size:
4.5 mm 2 2.6 mm).

this phase. In the third phase , the output of the flip-flop

is fed back to the MEMS accelerometer to place the proof-
mass in the null position by electrostatic forces. If the proofmass
gets positive (negative) accelerations, the output of comparator
will be positive (negative) because of its voltage inversion. This
supply voltage is reapplied to the proofmass to make it return
to the null position by electrostatic forces. The last phase
is used for the control and sensing of the proofmass. The output
of the flip-flop forms pulse bitstreams for the next module.
Fig. 6 shows the HSPICE simulation result of the modulation
of acceleration magnitudes into the corresponding digital pulse
bitstreams (PWM signal). As the acceleration changes, capaci-
tance differences between proofmass and electrodes are sensed
and the corresponding charge is integrated with a 90 phase lag.
The integrated charges are reflected to the voltage at the output
and passed through the comparator generating a PWM signal.
The layout for analog readout circuit shown in Fig. 7 is com-
posed of all the components necessary such as switches, ampli-
Fig. 9. Electronic noises. (a) Amplifier thermal noise. (b) KT =C noise due to
fier, comparator, D-flip-flop, and clock generator. thermal noise sampling switches.

F. Noise Analysis of Closed-Loop System

signal-to-noise ratio (SNR) improvement. Based on the sensi-
There are several noise sources that affect the resolution tivity of accelerometer and capacitance, the equivalent input
(i.e., the minimum detectable input acceleration) of the overall noise of acceleration can be calculated. Each noise source now
system. In an oversampled electromechanical sigma–delta will be described.
system, higher sampling rates reduce the quantization noise. 1) Brownian Noise: The primary mechanical noise source
Each doubling of the sample frequency results in a 3-dB for the device is due to the Brownian motion (Fig. 8) of gas

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Fig. 10. Mass residual motion noise.

molecules between comb fingers. The total noise equivalent ac- This acceleration can be randomized due to the varying input,
celeration (TNEA) [m/(s )] [12] is and hence it can be considered to be noise distributed uniformly
from dc to the proofmass residual motion frequency . This
(3) noise is equivalent to 500 g/ and becomes dominant due
to its low sampling frequency.
where is the Boltzmann constant, is the temperature 5) Dead-Zone Noise: Assuming that the input of the ac-
in Kelvin, is damping coefficient, and is resonance fre- celerometer is zero, the feedback voltage generates
quency. From (3), it is seen that the MEMS accelerometer has with frequency because of electrostatic force. There-
smaller Brownian noise with larger and heavier proofmass. fore, the input signal must be large enough to break this
Plugging device data into this equation results in Brownian dead-zone pattern. The minimum rms input acceleration for
motion noise around 10 g/ . this is g and should be
2) Amplifier Noise: The readout circuitry utilizes correlated counted as noise.
doubling sampling to reduce the input CMOS amplifier flicker 6) Total Noise and Minimum Detectable Acceleration:
noise. However, the amplifier thermal noise [Fig. 9(a)] is am- Since all of the noise sources considered here are uncorrelated,
plified by the ratio of total input capacitors, including parasitics the total noise is obtained simply by summing all of the noise
in the integrating capacitor. The noise at the output of the am- sources, resulting in 530 g/ . Therefore, the minimum
plifier can be expressed by integrating the total noise power and detectable acceleration is the same as the one calculated by
dividing it by the effective noise bandwidth, which is half of integrating this input acceleration density over the bandwidth of
the sampling frequency. Therefore, the amplifier output noise interest, which is 100 Hz. The resultant minimum detectable
voltage due to thermal noise in the op-amp is expressed as acceleration is about 5.3 mg, which is below the smallest
acceleration a human hand can generate/perceive. From the
(4) noise-source consideration, we see that the mass residual
noise dominates with order of magnitude. However, this mass
where is the total input capacitance including parasitics, residual motion noise can be significantly reduced by increasing
is the capacitance of the op-amp output node, and is the sampling frequency at the cost of power consumption and
the sampling frequency. From this equation, the equivalent complexity.
input acceleration noise due to amplifier thermal noise is about
0.7 g/ Hz. G. Acceleration Magnitude Extractor
3) KT/C Noise: A major noise source in switched capac- The modulated pulse bitstream from the CMOS analog
itor circuits is noise [Fig. 9(b)], which is generated by readout circuit is converted into binary data for further pro-
the CMOS switch thermal noise. The rms voltage noise from cessing. Two types of data should be extracted from pulse
thermal switch noise can be calculated by the integration of the bitstreams: polarity and magnitude. The polarity indicates
bandwidth of switch’s RC filter. The voltage noise power den- the direction of acceleration and can be handily extracted by
sity due to this switch thermal noise is expressed as observing the sign of pulse bitstreams. For example, Fig. 11
illustrates the movements of the mouse and corresponding
- (5) acceleration values on both the and axes. It also shows the
possible PWM bit streams. If the value of the pulse is 5 V (dig-
This voltage noise is converted to the equivalent input ital value “1”), the acceleration is toward the positive direction,
acceleration noise as 0.3 g/ Hz. and vice versa. The width of pulse bitstreams is proportional
4) Mass Residual Motion Noise: The proofmass is being to the magnitude of acceleration. The extraction of correct
rebalanced by a pulse train, and thus it has a residual mo- magnitude of acceleration can be achieved via two binary flags
tion with small ac amplitude (Fig. 10). The amplitude of (flip-flops) and a binary counter, as shown in Fig. 12. The
this motion can be shown [17] to be approximately equal to “C” flag is set to the polarity of current input pulse bitstream
m with g and synchronized by the system clock while the “P” flag value is the
100 kHz. This residual motion corresponds to an equiv- one shifted from the “C” flag flip-flop from the previous clock
alent rms of 78 mg acceleration in this MEMS accelerometer. cycle. The comparator compares the two flag values and, when-

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Fig. 11. Movements of a mouse and corresponding accelerations in X and Y axes.

generated values is proportional to the degree of the acceler-

ation of movements, and the polarity of the input bitstreams
determines the direction of user’s movements. In other words,
the positive value of the counter corresponds to the positive
acceleration, and vice versa. The “acceleration register” always
keeps some static values specifying the previous acceleration
magnitude, and the control microprocessor accesses only this
register to calculate the current position cursor. Whenever the
acceleration register loads a new value from the counter, the
“N” flag flip-flop is set to “1,” indicating that the new value has
been loaded. The control microprocessor keeps polling “N” flag
flip-flops to decide whether it should fetch a new acceleration
value or not. The layout for acceleration magnitude extractor is
assembled together with core microprocessor and is shown in
Fig. 16.

H. Core Control Microprocessor

The core control microprocessor is designed to filter the
acceleration output from the analog readout circuits within the
bandwidth of interest and to remove the quantization noise
folded at higher frequency. This can be done with a simple finite
impulse response (FIR) low-pass filter with 100-Hz cutoff
frequency. Also, the microprocessor calculates the position
coordinates based upon the magnitude values of the acceler-
ation from the acceleration extract module. The processor is
based on RISC concepts and is implemented as a modified
two-stage (fetch/decode and execute) pipeline (see Fig. 13).
(b) Instruction fetch takes place during the half cycle before the
Fig. 12. Acceleration magnitude extractor. (a) Overall structure. (b) Operation instruction is decoded to allow a full half-cycle for instruction
illustration. memory access and a full cycle for decoding the instruction.
The microprocessor uses a 16-b word and address space and all
ever two flag values differ—e.g., the polarity of input stream instructions are single-word. In addition to the basic arithmetic
changes—it loads the current value of binary counter into the and logic operations, two application-specific instructions are
buffer register called “acceleration register” and, at the same implemented, which will be described below.
time, it resets the counter. While “C” and “P” flag flip-flops The main part of the application program consists of two pro-
have the same value, the counter keeps increasing or decreasing cedures: polling and integration. For the polling procedure, a
based on the value of the “C” flag. Thus, the magnitude of special instruction is defined called load counter value (LCNT).

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Fig. 13. Core microprocessor architecture.

Fig. 14. Timing strategy.

When LCNT is executed, the core control microprocessor ex- The other special instruction is called SROUT, which moves
amines the value of the “N” flag flip-flip from the previous ac- calculated coordinate values to the 16-b system interface bus.
celeration extract module. If the value of the flip-flop is “1,” the To minimize the interface with outside circuitry, instruction
value of the acceleration register is transferred into one of reg- memory (ROM) and data memory (RAM) have been integrated
isters in the data-path module. At the same time, the “N” flag into the core microprocessor module. Both ROM and RAM
flip-flop is reset to “0” by the microprocessor to indicate the contain 256 words, which is large enough to contain the entire
completion of the transferring operation. application program.
The transferred acceleration magnitude value should be inte-
grated twice so that it is transformed into position coordinates
as shown in the following equation: I. Timing Scheme and Critical Paths

The general timing strategy of the core microprocessor is

(6) shown in Fig. 14. The clocking is predominantly positive edge-
triggered, except for the program counter. The program counter
where and represent velocity, acceleration, and position is a negative edge-triggered component to allow enough instruc-
coordinates, respectively. Instead of implementing the integra- tion memory access time between and . At time , an in-
tion operation, it is performed via two normal addition instruc- struction is loaded into the instruction register, and, between
tions: and . Since the system has abundant and , the newly fetched instruction is decoded. In our design,
instruction cycles for each coordinate calculation, as pointed out every control signal is latched (as shown at time ) to provide
in Section II-A, the lack of special-purpose hardware is justified. stabilized control signals for safe execution of the instruction

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Fig. 15. Timing delay for the critical path.

Fig. 16. Microprocessor layout (5.6 mm 2 5.8 mm).

during the next clock cycle from to . In other words, the en-
tire clock period is dedicated to execute one instruction. Finally,
at time , the result of the execution is written back to either the Fig. 17. Process flow of monolithic implementation. (a) SOI wafer.
register file or the data memory. The rationale behind this timing (b) Analog/digital CMOS process. (c) Deep trench etching. (d) Release.
strategy is to distribute major timing loads to different clock cy-
cles evenly, resulting in the reduced clock period.
Our microprocessor design does not have separate memory
Quicksim Pro was used for transistor-level and Verilog simu-
address register (MAR) or memory data register (MDR),
lation. Parasitics were extracted from the layout, and Mentor’s
because both instruction memory (ROM) and data memory
Accusim was used for the detailed delay and loading effects.
(RAM) are integrated together with the processor. Thus,
Timing information from the parts generated in Epoch [23] was
memory access instructions (Load/Store) are virtually the
extracted automatically during the import process to Mentor’s
same with a register transfer instructions (Mov/Movi), which
Design Architect. Once the functional models were properly
simplifies the system architecture.
back annotated, timing verification was performed in Quicksim
Through extensive simulation, the paths from the register file
Pro. In order to physically verify the design, full-mask LVS
to ALU were determined to be critical primarily because the reg-
was performed by importing the custom datapath into Epoch
ister file is the largest component and the ALU has a ripple-carry
and generating a net-list for the entire core that includes the
adder (see Fig. 15). The ALU delay time is 53.7 ns, which is
custom and Epoch-synthesized parts.
measured from the rising clock edge to the point when the cal-
To facilitate testing, the program counter and instruction reg-
culated data are valid on the system data bus. This critical path
ister were made scannable. The application-specific instruction
permits a maximum clock frequency of approximately 18 MHz,
SROUT moves the specified register value to 16-b output pins
which is above the target frequency of 100 kHz. Recalling that
(SOUT[15:0]), allowing us to observe any arbitrary register
the application target frequency dictates the maximum critical
values of the register file during the testing mode. These two
delay, the ripple-carry adder showed adequate performance in
design-for-testability features allow us to verify the contents
this regard, and a faster ALU was not necessary.
of instruction/data memory efficiently. By applying instruction
addresses at the program counter and observing the values of
instruction register via scan-chain testing mode, the correctness
Verification and simulation were performed using the of the instruction memory (ROM) were verified. Data memory
Mentor Graphics Tools and Epoch Design Compiler. Mentor’s (RAM) was verified by moving contents of a specific memory

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Fig. 18. MEMS accelerometer for monolithic implementation.

location into one of the register in the register file and transfer- design and fabrication, where all of the modules are fabricated in
ring them to the system interface bus via SROUT instruction. a single wafer, are considered as a monolithic implementation.
In other words, all of the necessary modules such as MEMS
accelerometers, the analog readout circuit, and the micropro-
cessor are to be integrated on the same wafer without any inter-
MEMS accelerometer was designed to have character- faces between them. The only major interface with outside cir-
istics such as sensitivity with 0.78 pF/g, dimensions as cuits—other than VDD, GND, clock, and reset signals—is the
2.1 mm 2.4 mm 100 m ( ), and a sensing parallel data bus which transfers positional coordinates calcu-
capacitance of 16.4 pF. The analog circuit has an estimated lated from the microprocessor. Since they are fabricated on the
power of 3 mW, capacitance sensitivity of 0.3 V/pF, and die size same wafer, thus eliminating complex steps for the interface, it
of 4.5 mm 2.6 mm. Mechanical and analog simulation shows greatly reduces the overall costs as well as complex steps for the
that the designed padless mouse system can detect acceleration interface.
as small as 5.3 mg, which is a sufficiently high resolution for With all of these advantages over the hybrid system, how-
mouse applications. ever, the monolithic system has several problems such as noise
The microprocessor, as shown in Fig. 16, contains 53 634 between analog and digital circuits, interconnections between
transistors, and the die size is 5.6 mm 5.8 mm. As described in MEMS devices and analog circuits, and so on. One of the main
Section II-I, the critical path was from the register file to ALU, factors for a noise problem in monolithic system stems from
and the corresponding maximum clock frequency was approx- the fact that the analog and digital circuits are sharing the same
imately 18 MHz. Although maximum achievable clock speed substrate. Although substrate has high resistance, it is not a com-
is 18.1 MHz, its operational frequency is same as the sampling plete isolator, and thus voltage variations in digital parts are ca-
frequency of the analog switched-capacitor sigma-delta readout pacitively coupled to analog circuits and thus may cause mal-
circuits. The power consumption is estimated to be 10 W at functions of a system.
100-kHz operational frequency. The noise problem due to the substrate coupling can be solved
by using silicon-on-insulator (SOI) [18]–[22], which isolates
one module from others by etching substrate boundaries of each
module and making it isolated both physically and electrically.
The hybrid 2-D position detection system has been proposed Also, MEMS accelerometers and analog circuitry can be con-
to combine MEMS accelerometers and digital circuits by means nected to each other by making deep trenches. It is reported
of switched-capacitor circuits using wire bonding. Due to the that the silicon substrate underneath interconnection materials
wire being bonded, however, these different modules in a system (such as metals) can be removed in the process of deep trench
must interface with each other at board level. This not only limits etching because of a sidewall etching effect [14]. The detailed
the size of a system, but also contributes capacitive or resistive fabrication process flow for monolithic implementation com-
parasitics that may degrade the system performance [24]. For bining MEMS devices and analog and digital circuits are basi-
example, stray capacitance and inductance due to wire bonding cally post-CMOS fabrication, as illustrated in Fig. 17. The usual
and bond pads can be up to 1 pF/pad and 1 nH/mm, respec- CMOS processes are done using SOI start wafers, as shown in
tively. To circumvent these drawbacks, a system-on-chip (SoC) Fig. 17(a) and (b). After CMOS processes, deep trenches are

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made for the formation of proofmass of MEMS accelerome- [13] Z. Xiao et al., “Laterally capacity sensed accelerometer fabricated with
ters as well as isolation between analog and digital circuitry the anodic bonding and the high aspect ratio etching,” in Proc. 10th Int.
Conf. Solid-State Sensors and Actuators, 1999, pp. 1518–1521.
[Fig. 17(c)]. Fig. 17(d) presents the release step by removing [14] H. Xie et al., “Post-CMOS processing for high-aspect-ratio integrated
SiO with buffered hydrofluoric acid to suspend the proofmass. silicon microstructures,” in Proc. IEEE Solid-State Sensor and Actuator
During the release, the SiO between analog/digital circuitry are Workshop, 2000, pp. 77–80.
also etched away. Finally, Fig. 18 shows the mask-level MEMS [15] J. Chae, H. Kulah, and K. Najafi, “A hybrid silicon-on-glass (SOG) lat-
eral micro-accelerometer with CMOS readout circuitry,” in Proc. 15th
structure. The close-up view shows an interconnection line, con- IEEE Int. Conf. Micro Electro Mechanical Systems, 2002, pp. 623–626.
tacts, suspension beams, and etch holes which help releasing [16] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects
proofmass during BHF etch process. of op-amp imperfections: Autozeroing, correlated double sampling, and
chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, Nov.
[17] B. Boser and R. T. Howe, “Surface micromachined accelerometers,”
VI. CONCLUSION IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 366–375, Mar. 1996.
[18] Y.-C. Tseng, “AC floating body effects and the resultant analog circuit
issues in submicron floating body and body-grounded SOI MOSFETs,”
In this paper, we presented a novel 2-D position detection IEEE Electron Devices, vol. 46, no. 8, pp. 1685–1692, Aug. 1999.
system for padless mouse applications. The final system consists [19] S. Krishnan and J. G. Fossum, “Grasping SOI floating-body effects,”
of four major components: 1) MEMS accelerometer; 2) analog IEEE Circuits Devices Mag., vol. 14, no. 1, pp. 32–37, Jan. 1998.
[20] G. G. Shahidi et al., “Partially-depleted SOI technology for digital
readout circuit; 3) acceleration magnitude extraction module; logic,” in Proc. ISSCC, 1999, pp. 426–427.
and 4) 16-b RISC microprocessor. Each module was carefully [21] C.-T. Chuang, P.-F. Lu, and C. J. Anderson, “SOI for digital CMOS
designed, laid out, and verified through extensive simulation. VLSI: Design considerations and advances,” Proc. IEEE, vol. 86, no.
4, pp. 689–720, Apr. 1998.
The calculated and simulated minimum detectable acceleration [22] K. K. Das and R. B. Brown, “Evaluation of circuit approaches in par-
is 5.3 mg with a 100-kHz low sampling frequency for low power tially-depleted SOI-CMOS,” in Proc. SOI Conf., 2000, pp. 98–99.
consumption. [23] Epoch: Online Manuals, Cascade Design Automation Corporation,
1994. Epoch, Online.
The hybrid multichip nature of the proposed system will limit [24] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A
the system size and contribute capacitive and resistive parasitics System Perspective, 2nd ed. Reading, MA: Addison-Wesley, 1993.
that may degrade the system performance. To circumvent these
drawbacks, an SoC design and fabrication, where all of the mod-
ules are fabricated on a single wafer, is considered as future
work in this area. Also, the system can be handily extended into
a 3-D position detection system by adding an additional MEMS Seungbae Lee (S’01) received the B.S and M.S.
accelerometer to measure -axis directional movement. degrees from Seoul National University, Seoul,
Korea, in 1990 and 1992, respectively. He is cur-
rently working toward the Ph.D. degree in electrical
engineering and computer science at the University
of Michigan, Ann Arbor.
REFERENCES From 1992 to 1997, he was a Senior Research En-
gineer with LG Electronics Institute of Technology,
[1] R. C. Harwell and R. L. Ferguson, “Physiologic tremor and micro- Seoul, where he was involved with the research and
surgery,” Microsurg., vol. 4, pp. 187–192, 1983. development of speech recognition and synthesis. His
[2] C. N. Riviere and P. K. Khosla, “Accuracy in positioning of handheld current research interests focus on microelectrome-
instruments,” in Proc. 18th Annu. Conf. IEEE Engineering in Medicine chanical systems for RF wireless communications and include micromechan-
and Biology Society, 1996, pp. 212–213. ical resonator reference oscillator and integrated circuit design.
[3] C. N. Riviere, R. S. Rader, and P. K. Khosla, “Characteristics of hand Mr. Lee was the recipient of the First Prize and Best Paper Awards in the
motion of eye surgeons,” in Proc. 19th Annu. Conf. IEEE Engineering Student Design Contest at the 38th Design Automation Conference and the Best
in Medicine and Biology Society, 1997, pp. 1690–1693. Paper Award at the 2004 IEEE Frequency Control Symposium.
[4] K. A. Mann, F. W. Werner, and A. K. Palmer, “Frequency spectrum anal-
ysis of wrist motion for activities of daily living,” J. Orthop. Res., vol.
7, pp. 304–306, 1989.
[5] J. M. Hollerbach, “An oscillatory theory of handwriting,” Biol. Cybern.,
vol. 39, pp. 139–156, 1981.
[6] R. N. Stiles and J. E. Randall, “Mechanical factors in human tremor
frequency,” J. Appl. Physiol., vol. 23, no. 3, pp. 324–330, 1967. Gi-Joon Nam (S’99–M’01) received the B.S. degree
[7] J. E. Randall and R. N. Stiles, “Power spectral analysis of finger accel- in computer engineering from Seoul National Univer-
eration tremor,” J. Appl. Physiol., vol. 19, pp. 357–360, 1964. sity, Seoul, Korea, and the M.S. and Ph.D. degrees in
computer science and engineering from the Univer-
[8] L. M. Roylance and J. A. Angell, “A batch-fabricated silicon accelerom-
sity of Michigan, Ann Arbor.
eter,” IEEE Trans. Electron Devices, vol. ED-26, no. 12, pp. 1911–1917,
Since 2001, he has been with IBM Austin
Dec. 1979.
Research, Austin, TX, and is currently working
[9] C. Yeh and K. Najafi, “A low-voltage bulk-silicon tunneling based mi- on physical design space, particularly placement
croaccelerometer,” IEDM Tech. Dig., pp. 593–596, Dec. 1995. and timing closure flow. His general interests are
[10] J. S. Chae, H. Kulah, and K. Najafi, “An in-plane high-sensitivity, low- computer-aided design algorithms, combinatorial
noise micro-g silicon accelerometer with CMOS readout circuitry,” J. optimizations, VLSI system designs, and computer
Microelectromechanical Syst., vol. 13, no. 4, pp. 628–635, Aug. 2004. architecture.
[11] N. Yazdi and K. Najafi, “An all-silicon single-wafer fabrication tech- Dr. Nam is a member of the Association for Computing Machinery. He is
nology for precision micro accelerometers,” in Proc. 9th Int. Conf. Solid- currently serving on the Technical Program Committee for the ACM/IEEE
State Sensors and Actuators, 1997, pp. 1181–1184. International Symposium on Physical Design (ISPD) and IEEE International
[12] N. Yazdi, F. Ayazi, and K. Najafi, “Micromachined inertial sensors,” System-on-Chip Conference (SOCC). He is currently serving on the Technical
Proc. IEEE, vol. 86, no. 8, pp. 1640–1659, Aug. 1998. Program Committee for the International Conference on Computer Design.

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Junseok Chae (M’03) received the B.S. degree in Hanseup Kim (S’00) received the B.S. degree from
metallurgical engineering from Korea University, Seoul National University, Seoul, Korea, in 1997 and
Seoul, Korea, in 1998 and the M.S. and Ph.D. de- the M.S. degree from the University of Michigan,
grees in electrical engineering and computer science Ann Arbor, in 2003, both in electrical engineering.
from the University of Michigan, Ann Arbor, in He is currently working toward the Ph.D. degree
2000 and 2003, respectively. in electrical engineering in microelectromechanical
From 2003, to 2005, he was a Postdoctoral systems (MEMS) at the University of Michigan.
Research Fellow with Wireless Integrated MicroSys- He interned at LG Corporate Institute of Tech-
tems (WIMS), University of Michigan. He joined nology, Korea, in early 1999, where he participated
the faculty of Arizona State University, Tempe, in in developing a microoptical switch. Since entering
August 2005, where he is currently an Assistant the graduate program in 1999, he has been devel-
Professor of electrical engineering. His areas of interests are MEMS sensors, oping a micro vacuum pump for use in a miniaturized gas chromatograph as
mixed-signal interface electronics, MEMS packaging, and ultrafast pulse well as several polymer-based microfabrication technologies such as wafer
(femtosecond) lasers for micro-/nano-structures. He holds several U.S. patents. bonding and membrane transfer techniques. Recently, he has also been involved
Dr. Chae, along with his colleagues, was the recipient of the First Place Prize with the development of bidirectional micro loud-speaker and chip-cooling
and the Best Paper Award at the Design Automation Conference Student De- chip using acoustic thrust generation. His research interests include the design
sign Contest in 2001 with the paper titled “Two-dimensional position detection and microfabrication of micro actuators and MEMS systems as well as their
system with MEMS accelerometer for mouse application.” He gave an invited integrations with circuits. Up to date, he has authored and coauthored 15 papers
talk at Microsoft Inc. regarding “MEMS technology for consumer electronic in refereed journals and conferences and has served as a technical reviewer for
applications.” the Journal of Microelectromechanical Systems.
Mr. Kim was the recipient of the Best Paper and First Place Awards at the
38th Student Design Contest of Design Automation Conference (DAC 2001)
with four other coauthors.

Alan J. Drake (S’99) received the B.S. degree

in electrical engineering from the University of
Arizona, Tucson, in 1997 and the M.S. degree
in electrical engineering from the University of
Michigan, Ann Arbor, in 2000, where he is currently
working toward the Ph.D. degree.
Currently, he is with IBM Austin Research, Austin,
TX. His research interests include low-power VLSI,
resonant clock generation and distribution, and SOI

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