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CZC Confidential

D
CZC Digital technologies Co.,LTD

Board name: Mother Board Schematic 1. System Block Diagram & Schematic page description;
2. Power Block Diagram & Discription;
Project name: CPL S01 (R48)
3. Annotations & information;
Version: VerC
4. Schematic modify Item and history;
Start Date:JAN 6,2010 5. Power on & off Sequence;
C 6. ACPI Mode Switch Timings;
VerA Release Data:
7. Power On Sequence Map;
8. CLOCK Distribution;

Hardware drawing by: Hardware check by: EMI Check by:

Power drawing by: Power check by:

A Manager Sign by: A


CZC Technology zw
Title
<Title>

Size Project Name Rev


A4 R48 C

Date: Thursday, April 22, 2010 Sheet 1 of 56


5 4 3 2 1
S45 System Block Ver:A
PWR_BTN Board

MB
RJ45 Board
D DDR3 1GB/512M
D
QKey & LID Board
LVDS SO-DIMM 0
DDRIII
VGA +V1.5,+V0.75S
Madison/Park PCIE X16 Arrandale
HDMI
SO-DIMM 1
DDRIII To RJ45
+V1.5,+V0.75S

TFT MUX FDI DMI X4

PWR Switch
LVDS PCIE X1 LAN Controller R5538/TPS2231/OZ2709
VGA
MUX AR8131M
VGA

PCIE X1
MUX USB2.0 Express Card
HDMI HDMI
PCIE X1

PCIE X1 mini PCIE Card


3G
C PCH
USB2.0 C
HM55/HM57
SIM SLOT
SATA
ODD
mini PCIE
SATA USB2.0 Card
HDD
2.5" R
USB AUDIO Board
SPI AZALIA LINK Azalia Codec
AN12948A
ALC662
SATA
L
HP Out
BIOS Mic In
LPC BUS

USB2.0
USB
Port
B SPI KB Ctrl & EC B
WPC8763L SD/MS/MS Pro CARD
USB2.0 Cardreader
UB6238N USB
EC Code Port
+
USB2.0 eSATA
USB Port
KB Matrix

USB2.0 Camera

USB2.0 BT
LED
TP

A A
CZC Technology zw
Title

<Title>
Size Project Name Rev

A4 R48 C
Date:
Thursday, April 22, 2010 Sheet
2 of
56
5 4 3 2 1

AC Mode Battery Mode


POWER RAIL
S0 S1 S3 S4 S5 S0 S1 S3 S4 S5
+V3.3AUX ON ON ON ON ON ON ON ON OFF OFF
+V5AUX ON ON ON ON ON ON ON ON OFF OFF
+V1.5 ON ON ON OFF OFF ON ON ON OFF OFF
D D
+V0.75S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V5S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V3.3S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V1.5S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V1.8S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V1.5S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V1.1S ON ON OFF OFF OFF ON ON OFF OFF OFF
+Vcore ON ON OFF OFF OFF ON ON OFF OFF OFF
GFXCORE ON ON OFF OFF OFF ON ON OFF OFF OFF

14.31818MHz 25MHz
XTAL XTAL
C C

133MHz
BCLK
133MHz 100MHz
BCLK DMI
CPU
120MHz
DP
100MHz
DMI
PCH
100MHz
Buffered PEG A
CK505 100MHz Mode GPU
SATA

100MHz
96MHz PCIE NEW CARD
DOT Mini PCIE SLOT X2
B B

14.31818MHz 33MHz
REF PCI
KBC
100MHz
PCIE

LAN
48MHz

25MHz
XTAL
A No stuff A

CZC Technology zw
Title
<Title>

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 3 of 56


5 4 3 2 1

Board stack up description


Voltage Rails +Vcore:0.75V-1.1V I2C SMB Address PCB Layers

+VDC Primary DC system power supply(9V-12V)


Device Address Hex(W/R) Bus Master Top(Signal1)
D D
+VCC_core Core/VTT voltage for processor Clock Generator 1101 001x D2H/D3H Ground

SO-DIMM0 1010 000x 0xA0 SMB_CLK/DATA PCH Signal2


+V1.8S 1.8V For PCH CPU
SO-DIMM1 1010 010x 0xA4 Signal3 Trace Impedence:50ohm +/-15%
+V1.1S 1.05V /1.1V For PCH CPU GPU
OZ8805LN 0001 011x 16H/17H EC_I2C_CLK2/DATA2 Power
+V0.75S 0.75V DDRIII Termination voltage
EC
+V1.5S 1.5V for system power Thermal Diode G781 1001 100x 98H/99H EC_I2C_CLK/DATA Signal4

Ground
+V1.5 1.5V power rail for DDRIII
Bottom(Signal5)

+V3.3AUX 3.3V always on power rail


+V3.3S 3.3V main power rail
+V5AUX 5V always on power rail
PCB Layer Difference signal Impedence list
+V5S 5V main power rail
C C
USB signal difference impedence 85ohm
LVDS signal difference impedence 85ohm
DDRIII signal difference impedence 85ohm
Power States DDRIII CLK signal difference impedence 68ohm

signal PM_SLP_S3#
state PM_SLP_S4# +V*AUX +V* +V*S CLOCKS
Full ON HIGH ON ON ON ON
S1M(Power On Suspend) HIGH ON ON ON LOW Wake up Events
S3(Suspend to RAM) HIGH LOW ON ON OFF OFF
S4(Suspend to DISK) LOW LOW ON OFF OFF OFF Wake Events State Supported(AC)
S5/Soft Off OFF OFF
With AC IN LOW LOW ON OFF

G3
With Battery LOW LOW OFF OFF OFF OFF
LID switch from EC S3 support
B Power Button from EC S3,S4,S5 support B
Keyboard from EC No
USB device No

[Option]:ns -- Component marked "ns" is not stuff


[Use State]:new --Component Marked "new" is new Materiel.

PCB Footprints
3 5 4

SOT23 SOT23_5

1 2 1 2 3
A A

CZC Technology zw
Title
<Title>

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 4 of 56


5 4 3 2 1

+V3.3AUX 13,14,15,16,17,19,21,22,24,25,27,28,29,30,31,32,34,35
+V1.5S 7,16,21,22,28,35,36
+V1.5 7,8,10,11,33,35
+V1.1S_VTT 7,12,16,17,35,36
+V3.3S 9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48
U1A
+V1.5S_CPU 7
PEG_ICOMPI B26 PEG_IRCOMP_R R1 49.9,1%
PEG_ICOMPO A26 PEG_RXN[15:0] 41
A24 B27 PEG_RXN0
14 DMI_TXN0 DMI_RX#[0] PEG_RCOMPO
C23 A25 EXP_RBIAS R2 750 PEG_RXN1
14 DMI_TXN1 DMI_RX#[1] PEG_RBIAS
B22 PEG_RXN2
14 DMI_TXN2 DMI_RX#[2]
A21 K35 PEG_RXN15 PEG_RXN3
14 DMI_TXN3 DMI_RX#[3] PEG_RX#[0]
J34 PEG_RXN14 PEG_RXN4
PEG_RX#[1] PEG_RXN13 PEG_RXN5
14 DMI_TXP0 B24 DMI_RX[0] PEG_RX#[2] J33
D23 G35 PEG_RXN12 PEG_RXN6
14 DMI_TXP1 DMI_RX[1] PEG_RX#[3]

DMI
B23 G32 PEG_RXN11 PEG_RXN7
14 DMI_TXP2 DMI_RX[2] PEG_RX#[4]
A22 F34 PEG_RXN10 PEG_RXN8
14 DMI_TXP3 DMI_RX[3] PEG_RX#[5]
F31 PEG_RXN9 PEG_RXN9
PEG_RX#[6] PEG_RXN8 PEG_RXN10
D D24 DMI_TX#[0] PEG_RX#[7] D35 D
14 DMI_RXN0 PEG_RXN7 PEG_RXN11
G24 DMI_TX#[1] PEG_RX#[8] E33
14 DMI_RXN1 PEG_RXN6 PEG_RXN12
F23 DMI_TX#[2] PEG_RX#[9] C33
14 DMI_RXN2 PEG_RXN5 PEG_RXN13
H23 DMI_TX#[3] PEG_RX#[10] D32
14 DMI_RXN3 PEG_RXN4 PEG_RXN14
PEG_RX#[11] B32
D25 C31 PEG_RXN3 PEG_RXN15
14 DMI_RXP0 DMI_TX[0] PEG_RX#[12] PEG_RXN2
F24 DMI_TX[1] PEG_RX#[13] B28 PEG_RXP[15:0] 41
14 DMI_RXP1 PEG_RXN1 PEG_RXP0
E23 DMI_TX[2] PEG_RX#[14] B30
14 DMI_RXP2 PEG_RXN0 PEG_RXP1
G23 DMI_TX[3] PEG_RX#[15] A31
14 DMI_RXP3 PEG_RXP2
J35 PEG_RXP15 PEG_RXP3
PEG_RX[0] PEG_RXP14 PEG_RXP4
PEG_RX[1] H34
H33 PEG_RXP13 PEG_RXP5
14 FDI_TXN[7:0] FDI_TXN0 PEG_RX[2] PEG_RXP12 PEG_RXP6
E22 FDI_TX#[0] PEG_RX[3] F35
FDI_TXN1 D21 G33 PEG_RXP11 PEG_RXP7
FDI_TXN2 FDI_TX#[1] PEG_RX[4] PEG_RXP10 PEG_RXP8
D19 FDI_TX#[2] PEG_RX[5] E34
FDI_TXN3 D18 F32 PEG_RXP9 PEG_RXP9
FDI_TXN4 FDI_TX#[3] PEG_RX[6] PEG_RXP8 PEG_RXP10
G21 FDI_TX#[4] PEG_RX[7] D34
FDI_TXN5 E19 F33 PEG_RXP7 PEG_RXP11
FDI_TXN6 FDI_TX#[5] PEG_RX[8] PEG_RXP6 PEG_RXP12
F21 FDI_TX#[6] PEG_RX[9] B33

PCI EXPRESS -- GRAPHICS


FDI_TXN7

Intel(R) FDI
G18 D31 PEG_RXP5 PEG_RXP13
FDI_TX#[7] PEG_RX[10] PEG_RXP4 PEG_RXP14
PEG_RX[11] A32
C30 PEG_RXP3 PEG_RXP15
14 FDI_TXP[7:0] FDI_TXP0 PEG_RX[12] PEG_RXP2
D22 FDI_TX[0] PEG_RX[13] A28
FDI_TXP1 C21 B29 PEG_RXP1
FDI_TXP2 FDI_TX[1] PEG_RX[14] PEG_RXP0
D20 FDI_TX[2] PEG_RX[15] A30 lane reversal
FDI_TXP3 C18 FDI_TX[3] PEG_TXN[15:0] 41
FDI_TXP4 G22 L33 C1 0.1uF/16V,X7R DGPU PEG_TXN15 PEG_TXN0
FDI_TXP5 FDI_TX[4] PEG_TX#[0] C2 0.1uF/16V,X7R DGPU PEG_TXN14 PEG_TXN1
E20 FDI_TX[5] PEG_TX#[1] M35
FDI_TXP6 F20 M33 C3 0.1uF/16V,X7R DGPU PEG_TXN13 PEG_TXN2
FDI_TXP7 FDI_TX[6] PEG_TX#[2] C4 0.1uF/16V,X7R DGPU PEG_TXN12 PEG_TXN3
G19 FDI_TX[7] PEG_TX#[3] M30
L31 C5 0.1uF/16V,X7R DGPU PEG_TXN11 PEG_TXN4
PEG_TX#[4] C6 0.1uF/16V,X7R DGPU PEG_TXN10 PEG_TXN5
14 FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32
E17 M29 C7 0.1uF/16V,X7R DGPU PEG_TXN9 PEG_TXN6
14 FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]
J31 C8 0.1uF/16V,X7R DGPU PEG_TXN8 PEG_TXN7
PEG_TX#[7] C9 0.1uF/16V,X7R DGPU PEG_TXN7 PEG_TXN8
14 FDI_INT C17 FDI_INT PEG_TX#[8] K29
H30 C10 0.1uF/16V,X7R DGPU PEG_TXN6 PEG_TXN9
PEG_TX#[9] C11 0.1uF/16V,X7R DGPU PEG_TXN5 PEG_TXN10
14 FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29
D17 F29 C12 0.1uF/16V,X7R DGPU PEG_TXN4 PEG_TXN11
14 FDI_LSYNC1 FDI_LSYNC[1] PEG_TX#[11]
E28 C13 0.1uF/16V,X7R DGPU PEG_TXN3 PEG_TXN12
PEG_TX#[12] C14 0.1uF/16V,X7R DGPU PEG_TXN2 PEG_TXN13
PEG_TX#[13] D29
D27 C15 0.1uF/16V,X7R DGPU PEG_TXN1 PEG_TXN14
PEG_TX#[14] C16 0.1uF/16V,X7R DGPU PEG_TXN0 PEG_TXN15
PEG_TX#[15] C26
PEG_TXP[15:0] 41
L34 C17 0.1uF/16V,X7R DGPU PEG_TXP15 PEG_TXP0
PEG_TX[0] C18 0.1uF/16V,X7R DGPU PEG_TXP14 PEG_TXP1
PEG_TX[1] M34
M32 C19 0.1uF/16V,X7R DGPU PEG_TXP13 PEG_TXP2
PEG_TX[2] C20 0.1uF/16V,X7R DGPU PEG_TXP12 PEG_TXP3
PEG_TX[3] L30
M31 C21 0.1uF/16V,X7R DGPU PEG_TXP11 PEG_TXP4
PEG_TX[4] C22 0.1uF/16V,X7R DGPU PEG_TXP10 PEG_TXP5
PEG_TX[5] K31
M28 C23 0.1uF/16V,X7R DGPU PEG_TXP9 PEG_TXP6
PEG_TX[6] C24 0.1uF/16V,X7R DGPU PEG_TXP8 PEG_TXP7
PEG_TX[7] H31
K28 C25 0.1uF/16V,X7R DGPU PEG_TXP7 PEG_TXP8
C PEG_TX[8]
G30 C26 0.1uF/16V,X7R DGPU PEG_TXP6 PEG_TXP9 C
PEG_TX[9] C27 0.1uF/16V,X7R DGPU PEG_TXP5 PEG_TXP10
PEG_TX[10] G29
F28 C28 0.1uF/16V,X7R DGPU PEG_TXP4 PEG_TXP11
PEG_TX[11] C29 0.1uF/16V,X7R DGPU PEG_TXP3 PEG_TXP12
PEG_TX[12] E27
D28 C30 0.1uF/16V,X7R DGPU PEG_TXP2 PEG_TXP13
PEG_TX[13] C31 0.1uF/16V,X7R DGPU PEG_TXP1 PEG_TXP14
PEG_TX[14] C27
C25 C32 0.1uF/16V,X7R DGPU PEG_TXP0 PEG_TXP15
PEG_TX[15]

IC,ARD_CFD_rPGA,R1P5

Layout Note: All


resistors need to be
close to Processor +V1.5
(ARD/CFD) to avoid stubs
U1B
H_COMP3 AT23 COMP3
BCLK A16
CLK_MCP_BCLK 12,16
MISC

H_COMP2 AT24 B16 R877


COMP2 BCLK# CLK_MCP_BCLK_L 12,16 1K
H_COMP1 G16 AR30 CK_BCK1 TP53
COMP1 BCLK_ITP
CLOCKS

AT30 CK_BCK1_L TP54


H_COMP0 BCLK_ITP#
AT26 COMP0
PEG_CLK E16
CLK_MCH_PEG 12,14 R872 0 ns
PEG_CLK# D16 CLK_MCH_PEG_L 12,14
TP1 TP_SKTOCC_L AH24 SKTOCC#
DPLL_REF_SSCLK A18
CLK_DP_P 14
DPLL_REF_SSCLK# A17
H_CATERR_L CLK_DP_N 14 CPU_DRAMRST_L R873 0 R0402_0 R875 0
AK14 CATERR# 2 3 DDR3_DRAMRST_L 10,11
+V1.1S_VTT
THERMAL

R0402_0
BSS138
F6 CPU_DRAMRST_L Q6
R6 0 PECI_PCH SM_DRAMRST#
16 H_PECI AT15 PECI

1
R0402_0 AL1 SM_RCOMP_0
SM_RCOMP[0] SM_RCOMP_1 R7 R8
SM_RCOMP[1] AM1
AN1 SM_RCOMP_2 10K,1% 10K,1% R874 R876 0
R319 0 H_PROCHOT_L SM_RCOMP[2] 100K 8,27 DRAMRST_CNTRL R0402_0 DRAMRST_CNTRL_PCH 16
38 H_PROCHOT# AN26 PROCHOT#
R0402_0 AN15 PM_EXTTS_L0 R1054 0 ns
PM_EXT_TS#[0] PM_EXTTS#0_EC 9,27
AP15 PM_EXTTS_L1
PM_EXT_TS#[1] PM_EXTTS_L1 9
DDR3
MISC

H_THRMTRIP_L AK15 NO_STUFF C1043


16 H_THRMTRIP_L THERMTRIP#
B 470pF/50V,X7R B
R9
AT28 TP64 12.4K,1%
PRDY# XDP_PREQ_L ns
PREQ# AP27

AN28 XDP_TCLK
BUF_PLT_RST_L R489 0 ns H_CPURST_L TCK XDP_TMS
AP26 RESET_OBS# TMS AP28 CAD Note:
+V1.1S_VTT
PWR MANAGEMENT

AT27 XDP_TRST_L TCLK: Provide a scope test point at the


TRST# Processor socket breakout via to verify
+V3.3AUX
JTAG & BPM

AL15 AT29 XDP_TDI_R signal integrity of the first


14 H_PM_SYNC PM_SYNC TDI
AR27 XDP_TDO_R R161 51.1,1% platforms.
TDO XDP_TDI_M +V3.3S
TDI_M AR29
AN14 AP29 XDP_TDO_M R22 0
16 H_CPUPWRGD VCCPWRGOOD_1 TDO_M R0402_0
AN25 R21 1K
R10 0 VCCPWRGOOD_R DBR# C314
16 H_CPUPWRGD AN27 VCCPWRGOOD_0
R0402_0 R927 0.1uF/16V,X7R
AJ22 10K
BPM#[0]

5
R318 0 VDDPWRGOOD_R AK13 AK22
14 PM_DRAM_PWRGD SM_DRAMPWROK BPM#[1]
R0402_0 AK24 1 VCC
BPM#[2] DRAMPWRGD_CPU
BPM#[3] AJ24 4
H_VTTPWRGD AM15 AJ25 33,36 V1_1S1_5S_PWROK 2
VTTPWRGOOD BPM#[4] GND SOT23_5
BPM#[5] AH22
AK23 SN74AHC1G08DBV
BPM#[6]

3
TP13 AM26 AH23 +V1.1S_VTT U34
TAPPWRGOOD BPM#[7]

R12 PLT_RSTL_R AL14 NO_STUFF


15,41 BUF_PLT_RST_L RSTIN#
1.5K,1% XDP_TMS R11 51.1,1% ns
XDP_TRST_L
IC,ARD_CFD_rPGA,R1P5 XDP_TDI_R R13 51.1,1% ns
R18
750 XDP_PREQ_L R15 51.1,1% ns R17
51.1,1%
ns
XDP_TCLK R19 51.1,1% ns

+V3.3S

+V1.5S_CPU
Processor Compensation Signals
C235 Processor Pullups DDR3 Compensation Signals
0.1uF/16V,X7R DRAMPWRGD_CPU
H_COMP3 H_COMP1
A A
5

+V1.1S_VTT H_COMP2 H_COMP0 SM_RCOMP_2


33,36 V1_1S1_5S_PWROK R490 1K 1 VCC R16
4 R14 1.5K,1% H_VTTPWRGD NO_STUFF SM_RCOMP_1
2 R23 R24 R25
GND SOT23_5 1.5K,1% 1.1K,1% R26 R27 SM_RCOMP_0
C312 SN74AHC1G08DBV R20 20,1% 20,1% 49.9,1% 49.9,1%
3

0.1uF/16V,X7R U33 750 ns R28 R29 R30


49.9,1% 68 R32

VDDPWRGOOD_R
ns
CZC Technology
68

24.9,1%
100,1% R31 R33
H_CATERR_L

130,1%
H_PROCHOT_L
Layout Note:
Place these
zw
Title
R34 resistors near
750 H_CPURST_L Processor
Panel &VGA connect
Size Project Name Rev

A3 R48 C
Date:
Thursday, April 22, 2010 Sheet
5 of
56
5 4 3 2 1
5 4 3 2 1

U1D

U1C

11 M_B_DQ[63:0]

SB_CK[0] W8 M_CLK_DDR2 11
SB_CK#[0] W9 M_CLK_DDR2_L 11
D SA_CK[0] AA6 M_CLK_DDR0 10
M_B_DQ0 B5 SB_DQ[0] SB_CKE[0] M3 M_CKE2 11 D
AA7 M_B_DQ1 A5
10 M_A_DQ[63:0] SA_CK#[0] M_CLK_DDR0_L 10 SB_DQ[1]
P7 M_CKE0 M_B_DQ2 C3
SA_CKE[0] M_CKE0 10 SB_DQ[2]
M_A_DQ0 A10 M_B_DQ3 B3 V7
SA_DQ[0] SB_DQ[3] SB_CK[1] M_CLK_DDR3 11
M_A_DQ1 C10 M_B_DQ4 E4 V6
SA_DQ[1] SB_DQ[4] SB_CK#[1] M_CLK_DDR3_L 11
M_A_DQ2 C7 M_B_DQ5 A6 M2
SA_DQ[2] SB_DQ[5] SB_CKE[1] M_CKE3 11
M_A_DQ3 A7 Y6 M_B_DQ6 A4
SA_DQ[3] SA_CK[1] M_CLK_DDR1 10 SB_DQ[6]
M_A_DQ4 B10 Y5 M_B_DQ7 C4
SA_DQ[4] SA_CK#[1] M_CLK_DDR1_L 10 SB_DQ[7]
M_A_DQ5 D10 P6 M_CKE1 M_B_DQ8 D1
SA_DQ[5] SA_CKE[1] M_CKE1 10 SB_DQ[8]
M_A_DQ6 E10 M_B_DQ9 D2
M_A_DQ7 SA_DQ[6] M_B_DQ10 SB_DQ[9]
A8 SA_DQ[7] F2 SB_DQ[10] SB_CS#[0] AB8 M_CS_L2 11
M_A_DQ8 D8 M_B_DQ11 F1 AD6
SA_DQ[8] SB_DQ[11] SB_CS#[1] M_CS_L3 11
M_A_DQ9 F10 AE2 M_B_DQ12 C2
SA_DQ[9] SA_CS#[0] M_CS_L0 10 SB_DQ[12]
M_A_DQ10 E6 AE8 M_B_DQ13 F5
SA_DQ[10] SA_CS#[1] M_CS_L1 10 SB_DQ[13]
M_A_DQ11 F7 M_B_DQ14 F3
M_A_DQ12 SA_DQ[11] M_B_DQ15 SB_DQ[14]
E9 SA_DQ[12] G4 SB_DQ[15] SB_ODT[0] AC7 M_ODT2 11
M_A_DQ13 B7 M_B_DQ16 H6 AD1
SA_DQ[13] SB_DQ[16] SB_ODT[1] M_ODT3 11
M_A_DQ14 E7 AD8 M_B_DQ17 G2
SA_DQ[14] SA_ODT[0] M_ODT0 10 SB_DQ[17]
M_A_DQ15 C6 AF9 M_B_DQ18 J6
SA_DQ[15] SA_ODT[1] M_ODT1 10 SB_DQ[18]
M_A_DQ16 H10 M_B_DQ19 J3
M_A_DQ17 SA_DQ[16] M_B_DQ20 SB_DQ[19]
G8 SA_DQ[17] G1 SB_DQ[20] M_B_DM[7:0] 11
M_A_DQ18 K7 M_B_DQ21 G5 D4 M_B_DM0
M_A_DQ19 SA_DQ[18] M_B_DQ22 SB_DQ[21] SB_DM[0] M_B_DM1
J8 SA_DQ[19] J2 SB_DQ[22] SB_DM[1] E1
M_A_DQ20 G7 M_B_DQ23 J1 H3 M_B_DM2
M_A_DQ21 SA_DQ[20] M_B_DQ24 SB_DQ[23] SB_DM[2] M_B_DM3
G10 SA_DQ[21] M_A_DM[7:0] 10 J5 SB_DQ[24] SB_DM[3] K1
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ25 K2 AH1 M_B_DM4
M_A_DQ23 SA_DQ[22] SA_DM[0] M_A_DM1 M_B_DQ26 SB_DQ[25] SB_DM[4] M_B_DM5
J10 SA_DQ[23] SA_DM[1] D7 L3 SB_DQ[26] SB_DM[5] AL2
M_A_DQ24 L7 H7 M_A_DM2 M_B_DQ27 M1 AR4 M_B_DM6
M_A_DQ25 SA_DQ[24] SA_DM[2] M_A_DM3 M_B_DQ28 SB_DQ[27] SB_DM[6] M_B_DM7
M6 SA_DQ[25] SA_DM[3] M7 K5 SB_DQ[28] SB_DM[7] AT8
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ29 K4
M_A_DQ27 SA_DQ[26] SA_DM[4] M_A_DM5 M_B_DQ30 SB_DQ[29]
L9 SA_DQ[27] SA_DM[5] AM7 M4 SB_DQ[30]
M_A_DQ28 L6 AN10 M_A_DM6 M_B_DQ31 N5
C M_A_DQ29 SA_DQ[28] SA_DM[6] M_A_DM7 M_B_DQ32 SB_DQ[31] C
K8 SA_DQ[29] SA_DM[7] AN13 AF3 SB_DQ[32]
M_A_DQ30 N8 M_B_DQ33 AG1
SA_DQ[30] SB_DQ[33] M_B_DQS_L[7:0] 11
M_A_DQ31 P9 M_B_DQ34 AJ3 D5 M_B_DQS_L0
M_A_DQ32 SA_DQ[31] M_B_DQ35 SB_DQ[34] SB_DQS#[0] M_B_DQS_L1
AH5 SA_DQ[32] AK1 SB_DQ[35] SB_DQS#[1] F4
M_A_DQ33 AF5 M_B_DQ36 AG4 J4 M_B_DQS_L2
SA_DQ[33] M_A_DQS_L[7:0] 10 SB_DQ[36] SB_DQS#[2]
M_A_DQ34 AK6 C9 M_A_DQS_L0 M_B_DQ37 AG3 L4 M_B_DQS_L3
M_A_DQ35 SA_DQ[34] SA_DQS#[0] M_A_DQS_L1 M_B_DQ38 SB_DQ[37] SB_DQS#[3] M_B_DQS_L4
AK7 SA_DQ[35] SA_DQS#[1] F8 AJ4 SB_DQ[38] SB_DQS#[4] AH2
DDR SYSTEM MEMORY A

M_A_DQ36 AF6 J9 M_A_DQS_L2 M_B_DQ39 AH4 AL4 M_B_DQS_L5


SA_DQ[36] SA_DQS#[2] SB_DQ[39] SB_DQS#[5]

DDR SYSTEM MEMORY - B


M_A_DQ37 AG5 N9 M_A_DQS_L3 M_B_DQ40 AK3 AR5 M_B_DQS_L6
M_A_DQ38 SA_DQ[37] SA_DQS#[3] M_A_DQS_L4 M_B_DQ41 SB_DQ[40] SB_DQS#[6] M_B_DQS_L7
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AK4 SB_DQ[41] SB_DQS#[7] AR8
M_A_DQ39 AJ6 AK9 M_A_DQS_L5 M_B_DQ42 AM6
M_A_DQ40 SA_DQ[39] SA_DQS#[5] M_A_DQS_L6 M_B_DQ43 SB_DQ[42]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AN2 SB_DQ[43]
M_A_DQ41 AJ9 AT13 M_A_DQS_L7 M_B_DQ44 AK5
M_A_DQ42 SA_DQ[41] SA_DQS#[7] M_B_DQ45 SB_DQ[44]
AL10 SA_DQ[42] AK2 SB_DQ[45]
M_A_DQ43 AK12 M_B_DQ46 AM4
M_A_DQ44 SA_DQ[43] M_B_DQ47 SB_DQ[46]
AK8 SA_DQ[44] AM3 SB_DQ[47] M_B_DQS[7:0] 11
M_A_DQ45 AL7 M_B_DQ48 AP3 C5 M_B_DQS0
SA_DQ[45] M_A_DQS[7:0] 10 SB_DQ[48] SB_DQS[0]
M_A_DQ46 AK11 C8 M_A_DQS0 M_B_DQ49 AN5 E3 M_B_DQS1
M_A_DQ47 SA_DQ[46] SA_DQS[0] M_A_DQS1 M_B_DQ50 SB_DQ[49] SB_DQS[1] M_B_DQS2
AL8 SA_DQ[47] SA_DQS[1] F9 AT4 SB_DQ[50] SB_DQS[2] H4
M_A_DQ48 AN8 H9 M_A_DQS2 M_B_DQ51 AN6 M5 M_B_DQS3
M_A_DQ49 SA_DQ[48] SA_DQS[2] M_A_DQS3 M_B_DQ52 SB_DQ[51] SB_DQS[3] M_B_DQS4
AM10 SA_DQ[49] SA_DQS[3] M9 AN4 SB_DQ[52] SB_DQS[4] AG2
M_A_DQ50 AR11 AH8 M_A_DQS4 M_B_DQ53 AN3 AL5 M_B_DQS5
M_A_DQ51 SA_DQ[50] SA_DQS[4] M_A_DQS5 M_B_DQ54 SB_DQ[53] SB_DQS[5] M_B_DQS6
AL11 SA_DQ[51] SA_DQS[5] AK10 AT5 SB_DQ[54] SB_DQS[6] AP5
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ55 AT6 AR7 M_B_DQS7
M_A_DQ53 SA_DQ[52] SA_DQS[6] M_A_DQS7 M_B_DQ56 SB_DQ[55] SB_DQS[7]
AN9 SA_DQ[53] SA_DQS[7] AR13 AN7 SB_DQ[56]
M_A_DQ54 AT11 M_B_DQ57 AP6
M_A_DQ55 SA_DQ[54] M_B_DQ58 SB_DQ[57]
AP12 SA_DQ[55] AP8 SB_DQ[58]
M_A_DQ56 AM12 M_B_DQ59 AT9
M_A_DQ57 SA_DQ[56] M_B_DQ60 SB_DQ[59]
AN12 SA_DQ[57] M_A_A[15:0] 10 AT7 SB_DQ[60]
M_A_DQ58 AM13 Y3 M_A_A0 M_B_DQ61 AP9
M_A_DQ59 SA_DQ[58] SA_MA[0] M_A_A1 M_B_DQ62 SB_DQ[61]
AT14 SA_DQ[59] SA_MA[1] W1 AR10 SB_DQ[62] M_B_A[15:0] 11
M_A_DQ60 AT12 AA8 M_A_A2 M_B_DQ63 AT10 U5 M_B_A0
B M_A_DQ61 SA_DQ[60] SA_MA[2] M_A_A3 SB_DQ[63] SB_MA[0] M_B_A1 B
AL13 SA_DQ[61] SA_MA[3] AA3 SB_MA[1] V2
M_A_DQ62 AR14 V1 M_A_A4 T5 M_B_A2
M_A_DQ63 SA_DQ[62] SA_MA[4] M_A_A5 SB_MA[2] M_B_A3
AP14 SA_DQ[63] SA_MA[5] AA9 SB_MA[3] V3
V8 M_A_A6 R1 M_B_A4
SA_MA[6] M_A_A7 SB_MA[4] M_B_A5
SA_MA[7] T1 AB1 SB_BS[0] SB_MA[5] T8
M_A_A8 11 M_B_BS0 M_B_A6
SA_MA[8] Y9 W5 SB_BS[1] SB_MA[6] R2
M_A_A9 11 M_B_BS1 M_B_A7
AC3 SA_BS[0] SA_MA[9] U6 R7 SB_BS[2] SB_MA[7] R6
10 M_A_BS0 M_A_A10 11 M_B_BS2 M_B_A8
AB2 SA_BS[1] SA_MA[10] AD4 SB_MA[8] R4
10 M_A_BS1 M_A_A11 M_B_A9
U7 SA_BS[2] SA_MA[11] T2 SB_MA[9] R5
10 M_A_BS2 M_A_A12 M_B_CAS_L M_B_A10
SA_MA[12] U3 AC5 SB_CAS# SB_MA[10] AB5
M_A_A13 11 M_B_CAS_L M_B_RAS_L M_B_A11
SA_MA[13] AG8 Y7 SB_RAS# SB_MA[11] P3
M_A_A14 11 M_B_RAS_L M_B_WE_L M_B_A12
SA_MA[14] T3 AC6 SB_WE# SB_MA[12] R3
M_A_CAS_L M_A_A15 11 M_B_WE_L M_B_A13
AE1 SA_CAS# SA_MA[15] V9 SB_MA[13] AF7
10 M_A_CAS_L M_A_RAS_L M_B_A14
AB3 SA_RAS# SB_MA[14] P5
10 M_A_RAS_L M_A_WE_L M_B_A15
AE9 SA_WE# SB_MA[15] N1
10 M_A_WE_L

IC,ARD_CFD_rPGA,R1P5

OCD_CPU IC,ARD_CFD_rPGA,R1P5

OCD_CPU

A CZC Technology zw
A

Title

Panel &VGA connect


Size Project Name Rev

A R48 C
Date:
Thursday, April 22, 2010 Sheet
6 of
56
5 4 3 2 1
5 4 3 2 1

U1F

+V1.1S_VTT

+VCORE

AG35 VCC1 VTT0_1 AH14


AG34 VCC2 VTT0_2 AH12
AG33 VCC3 VTT0_3 AH11
AG32 VCC4 VTT0_4 AH10
AG31 VCC5 VTT0_5 J14
AG30 J13 C33 C34 C35 C36 C37 C38 C39 C40
VCC6 VTT0_6 +VCC_GFXCORE U1G GFXVR_DPRSLPVR_R R128 10K
AG29 VCC7 VTT0_7 H14 10uF/10V X5R
10uF/10V X5R
10uF/10V X5R
10uF/10V X5R
10uF/10V X5R
10uF/10V X5R
10uF/10V X5R
10uF/10V X5R
AG28 H12 ns ns
VCC8 VTT0_8
AG27 VCC9 VTT0_9 G14 AT21 VAXG1
AG26 VCC10 VTT0_10 G13 AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE 37
AF35 G12 AT18 AT22 GFXVR_EN R35 470
VCC11 VTT0_11 VAXG3 VSSAXG_SENSE VSS_AXG_SENSE 37

SENSE
LINES
AF34 G11 C41 C43 C42 C44 AT16
VCC12 VTT0_12 VAXG4
AF33 VCC13 VTT0_13 F14 22uF/6.3V,X5R22uF/6.3V,X5R10uF/10V X5R 10uF/10V X5RAR21 VAXG5
D AF32 VCC14 VTT0_14 F13 AR19 VAXG6 D
AF31 VCC15 VTT0_15 F12 AR18 VAXG7
AF30 VCC16 VTT0_16 F11 AR16 VAXG8 GFX_VID[0] AM22 GFXVR_VID_0 37
AF29 E14 AP21 AP22 +V1.1S_VTT
VCC17 VTT0_17 +VCC_GFXCORE VAXG9 GFX_VID[1] GFXVR_VID_1 37
AF28 VCC18 VTT0_18 E12 AP19 VAXG10 GFX_VID[2] AN22 GFXVR_VID_2 37

GRAPHICS VIDs
AF27 VCC19 VTT0_19 D14 AP18 VAXG11 GFX_VID[3] AP23 GFXVR_VID_3 37
AF26 D13 AP16 AM23 R36 1K ns GFXVR_EN
VCC20 VTT0_20 VAXG12 GFX_VID[4] GFXVR_VID_4 37
AD35 D12 AN21 AP24

1.1V RAIL POWER


VCC21 VTT0_21 VAXG13 GFX_VID[5] GFXVR_VID_5 37 +V1.5

GRAPHICS
AD34 VCC22 VTT0_22 D11 AN19 VAXG14 GFX_VID[6] AN24 GFXVR_VID_6 37
AD33 C14 C64 C65 AN18
VCC23 VTT0_23 VAXG15
AD32 VCC24 VTT0_24 C13 10uF/10V X5R 10uF/10V X5R AN16 VAXG16
AD31 C12 AM21 AR25 GFXVR_EN
VCC25 VTT0_25 VAXG17 GFX_VR_EN GFXVR_EN 37
AD30 C11 AM19 AT25 GFXVR_DPRSLPVR_R
VCC26 VTT0_26 VAXG18 GFX_DPRSLPVR GFXVR_IMON TP23 FB92 120ohm/100MHz,2.5A ns
AD29 VCC27 VTT0_27 B14 AM18 VAXG19 GFX_IMON AM24
AD28 B12 AM16 +V1.5S
VCC28 VTT0_28 VAXG20 FB93 120ohm/100MHz,2.5A ns
AD27 VCC29 VTT0_29 A14 AL21 VAXG21
AD26 A13 +V1.1S_VTT AL19
VCC30 VTT0_30 VAXG22 GFX_IMON 37 +V1.5S_CPU
AC35 A12 AL18 FB90 120ohm/100MHz,2.5A
VCC31 VTT0_31 VAXG23
AC34 VCC32 VTT0_32 A11 AL16 VAXG24
AC33 AK21 AJ1 FB91 120ohm/100MHz,2.5A
VCC33 VAXG25 VDDQ1
AC32 VCC34 AK19 VAXG26 VDDQ2 AF1
AC31 VCC35 AK18 VAXG27 VDDQ3 AE7

- 1.5V RAILS
AC30 AF10 AK16 AE4 C45 C46 C47 C48 C49 C50 C51
VCC36 VTT0_33 VAXG28 VDDQ4 1uF/10V,X5R 1uF/10V,X5R 1uF/10V,X5R
AC29 VCC37 VTT0_34 AE10 AJ21 VAXG29 VDDQ5 AC1 22uF/6.3V,X5R 22uF/6.3V,X5R
AC28 AC10 AJ19 AB7 1uF/10V,X5R 1uF/10V,X5R
VCC38 VTT0_35 VAXG30 VDDQ6
CPU CORE SUPPLY

AC27 VCC39 VTT0_36 AB10 AJ18 VAXG31 VDDQ7 AB4


AC26 Y10 C52 C53 AJ16 Y1 +V1.5S_CPU +V1.5
VCC40 VTT0_37 +V1.1S_VTT VAXG32 VDDQ8
AA35 VCC41 VTT0_38 W10 22uF/6.3V,X5R 22uF/6.3V,X5R AH21 VAXG33 VDDQ9 W7
AA34 VCC42 VTT0_39 U10 AH19 VAXG34 VDDQ10 W4
AA33 T10 AH18 U1

POWER
VCC43 VTT0_40 VAXG35 VDDQ11
AA32 VCC44 VTT0_41 J12 AH16 VAXG36 VDDQ12 T7
AA31 J11 T4 C136 0.1uF/16V,X7R
VCC45 VTT0_42 +VTT_43 R38 0 VDDQ13 C137 0.1uF/16V,X7R DIMM0
AA30 VCC46 VTT0_43 J16 VDDQ14 P1
AA29 J15 +VTT_44 R39 0 N7 C138 0.1uF/16V,X7R
VCC47 VTT0_44 +V1.1S_VTT VDDQ15 C139 0.1uF/16V,X7R
AA28 VCC48 VDDQ16 N4 DIMM1
AA27 L1 C143 0.1uF/16V,X7R

DDR3
VCC49 VDDQ17 C144 0.1uF/16V,X7R
AA26 VCC50 J24 VTT1_45 VDDQ18 H1

FDI
Y35 VCC51 J23 VTT1_46
Y34 VCC52 H25 VTT1_47
Y33 +V1.1S C54 C55
VCC53
Y32 VCC54 22uF/6.3V,X5R
22uF/6.3V,X5R
Y31 P10 +V1.1S_VTT
VCC55 VTT0_59
Y30 VCC56 VTT0_60 N10
Y29 R1166 L10
VCC57 1K VTT0_61
Y28 VCC58 VTT0_62 K10
Y27 ns
VCC59
Y26 VCC60
V35 AN33 PSI_L TP14 +V1.1S_VTT
VCC61 PSI#
V34 VCC62
V33 H_VID[0:6] 38 J22

1.1V
VCC63 +V1.1S VTT1_63 +V1.1S_VTT
POWER

V32 AK35 H_VID0 R1167 K26 J20


VCC64 VID[0] H_VID1 1K VTT1_48 VTT1_64
V31 VCC65 VID[1] AK33 J27 VTT1_49 VTT1_65 J18

PEG & DMI


V30 AK34 H_VID2 J26 H21
C V29
VCC66 VID[2]
AL35 H_VID3 C56 C57 C58 J25
VTT1_50 VTT1_66
H20
C
VCC67 VID[3] H_VID4 R1168 VTT1_51 VTT1_67
V28 AL33 22uF/6.3V,X5R
22uF/6.3V,X5R 22uF/6.3V,X5R H27 H19
CPU VIDS

VCC68 VID[4] H_VID5 1K VTT1_52 VTT1_68


V27 VCC69 VID[5] AM33 G28 VTT1_53
V26 AM35 H_VID6 G27
VCC70 VID[6] PM_DPRSLPVR_R VTT1_54
U35 VCC71 PROC_DPRSLPVR AM34 G26 VTT1_55
U34 VCC72 F26 VTT1_56
U33 E26 L26 +V1.8S
VCC73 VTT1_57 VCCPLL1
U32 E25 L27

1.8V
VCC74 H_VTTVID1 TP4 VTT1_58 VCCPLL2
U31 VCC75 VTT_SELECT G15 VCCPLL3 M26
U30 VCC76
U29 VCC77
U28 C59 C60 C61 C62 C63
VCC78
U27 VCC79 1uF/10V,X5R1uF/10V,X5R2.2uF/6.3V,X7R 4.7uF/10V,X5R 22uF/6.3V,X5R
U26 +VCORE
VCC80
R35 VCC81 CORE_IMON 38
R34 VCC82
R33 IC,ARD_CFD_rPGA,R1P5
VCC83 TP5
R32 VCC84 ISENSE AN35
R31 R41
VCC85
R30 VCC86 100
R29 VCC87
R28 VCC88 VCC_SENSE AJ34 VCC_SENSE 38
SENSE LINES

R27 VCC89 VSS_SENSE AJ35 VSS_SENSE 38


R26 VCC90
P35 VCC91
P34 B15 TP_VTT_SENSE TP2
VCC92 VTT_SENSE TP_VSS_SENSE_VTT TP3 R42
P33 VCC93 VSS_SENSE_VTT A15
P32 VCC94 100
P31 VCC95
P30 VCC96
P29 VCC97
P28 VCC98
P27 VCC99
P26 VCC100

IC,ARD_CFD_rPGA,R1P5

+V1.1S 13,14,16,17,34,35,36
+VCC_GFXCORE 37
+V1.8S 15,16,28,34,36
+V1.1S_VTT 5,12,16,17,35,36
+VCORE 28,38
+V1.5 5,8,10,11,33,35
B +V1.5S 16,21,22,28,35,36 B
+V1.5S_CPU 5

+VCORE 22u*12

C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77
22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R

+VCORE
10u*16

A C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 A
10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R

+VCORE

CZC Technology zw
C90 C91 C92 C93 Title
10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R

Panel &VGA connect


Size Project Name Rev

A3 R48 C
Date:
Thursday, April 22, 2010 Sheet
7 of
56
5 4 3 2 1
5 4 3 2 1

U1H U1I

AT20 VSS1 VSS81 AE34


AT17 VSS2 VSS82 AE33
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162
AR26 VSS5 VSS85 AE30 K6 VSS163
AR24 VSS6 VSS86 AE29 K3 VSS164
AR23 VSS7 VSS87 AE28 J32 VSS165
AR20 VSS8 VSS88 AE27 J30 VSS166
AR17 VSS9 VSS89 AE26 J21 VSS167
AR15 VSS10 VSS90 AE6 J19 VSS168
AR12 VSS11 VSS91 AD10 H35 VSS169
AR9 VSS12 VSS92 AC8 H32 VSS170
AR6 VSS13 VSS93 AC4 H28 VSS171
AR3 VSS14 VSS94 AC2 H26 VSS172
AP20 VSS15 VSS95 AB35 H24 VSS173
AP17 VSS16 VSS96 AB34 H22 VSS174
AP13 VSS17 VSS97 AB33 H18 VSS175
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177
D AP4 VSS20 VSS100 AB30 H11 VSS178 D
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182
AN20 VSS25 VSS105 AB6 G31 VSS183
AN17 VSS26 VSS106 AA10 G20 VSS184
AM29 VSS27 VSS107 Y8 G9 VSS185
AM27 VSS28 VSS108 Y4 G6 VSS186
AM25 VSS29 VSS109 Y2 G3 VSS187
AM20 VSS30 VSS110 W35 F30 VSS188
AM17 VSS31 VSS111 W34 F27 VSS189
AM14 VSS32 VSS112 W33 F25 VSS190
AM11 VSS33 VSS113 W32 F22 VSS191
AM8 VSS34 VSS114 W31 F19 VSS192
AM5 VSS35 VSS115 W30 F16 VSS193
AM2 VSS36 VSS116 W29 E35 VSS194
AL34 W28 E32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS
AL20 VSS40 VSS120 W6 E21 VSS198
AL17 VSS41 VSS121 V10 E18 VSS199
AL12 VSS42 VSS122 U8 E13 VSS200
AL9 VSS43 VSS123 U4 E11 VSS201
AL6 VSS44 VSS124 U2 E8 VSS202
AL3 VSS45 VSS125 T35 E5 VSS203
AK29 VSS46 VSS126 T34 E2 VSS204 VSS_NCTF1 AT35
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34
AK17 VSS50 VSS130 T30 D9 VSS208 VSS_NCTF5 B2

NCTF
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1
AJ23 VSS52 VSS132 T28 D3 VSS210 VSS_NCTF7 A35
AJ20 VSS53 VSS133 T27 C34 VSS211
AJ17 VSS54 VSS134 T26 C32 VSS212
AJ14 VSS55 VSS135 T6 C29 VSS213
AJ11 VSS56 VSS136 R10 C28 VSS214
AJ8 VSS57 VSS137 P8 C24 VSS215
AJ5 VSS58 VSS138 P4 C22 VSS216
AJ2 VSS59 VSS139 P2 C20 VSS217
AH35 VSS60 VSS140 N35 C19 VSS218
AH34 VSS61 VSS141 N34 C16 VSS219
AH33 VSS62 VSS142 N33 B31 VSS220
AH32 VSS63 VSS143 N32 B25 VSS221
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 VSS65 VSS145 N30 B18 VSS223
AH29 VSS66 VSS146 N29 B17 VSS224
AH28 VSS67 VSS147 N28 B13 VSS225
AH27 VSS68 VSS148 N27 B11 VSS226
AH26 VSS69 VSS149 N26 B8 VSS227
AH20 VSS70 VSS150 N6 B6 VSS228
AH17 VSS71 VSS151 M10 B4 VSS229
AH13 L35 A29
C AH9
VSS72 VSS152
L32 A27
VSS230 C
VSS73 VSS153 VSS231
AH6 VSS74 VSS154 L29 A23 VSS232
AH3 VSS75 VSS155 L8 A9 VSS233
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2
AF4 VSS78 VSS158 K34
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30

IC,ARD_CFD_rPGA,R1P5 IC,ARD_CFD_rPGA,R1P5

+V1.5 5,7,10,11,33,35

U1E

RSVD32 AJ13
RSVD33 AJ12

AP25 RSVD1
AL25 RSVD2 RSVD34 AH25
AL24 RSVD3 RSVD35 AK26
AL22 RSVD4
AJ33 RSVD5 RSVD36 AL26
AG9 RSVD6 RSVD_NCTF_37 AR2
M27 RSVD7
L28 RSVD8 RSVD38 AJ26
10 M_VREF_DQ_DIMM0C R43 0 ns VREF_CH_A_DIMM J17 AJ27
R44 0 ns VREF_CH_B_DIMM SA_DIMM_VREFDQ RSVD39
11 M_VREF_DQ_DIMM1C H17 SB_DIMM_VREFDQ
G25 RSVD11
G17 RSVD12
3 2 E31 RSVD13 RSVD_NCTF_40 AP1
E30 RSVD14 RSVD_NCTF_41 AT2
2N7002K R1047 R1046 CFG0
Q7 100K 100K AT3
RSVD_NCTF_42
RSVD_NCTF_43 AR1
B B
1

3 2
PCI-Express Configuration Select NO_STUFF
2N7002K AL28 R45
Q8 CFG0 RSVD45
AM30 CFG[0] RSVD46 AL29 CFG0 1:Single PEG 3.01K,1% Layout Note:
AM28 AP30 0:Bifurcation enabled ns Location of all CFG strap resistors needs
CFG[1] RSVD47
1

AP31 AP32 to be close to trace to minimize stub


CFG3 CFG[2] RSVD48
AL32 CFG[3] RSVD49 AL27
CFG4 AL30 AT31
CFG[4] RSVD50
AM31 CFG[5] RSVD51 AT32
5,27 DRAMRST_CNTRL
AN29 CFG[6] RSVD52 AP33
CFG7 AM32 AR33
CFG[7] RSVD53
AK32 CFG[8] RSVD_NCTF_54 AT33
AK31 CFG[9] RSVD_NCTF_55 AT34
AK28 CFG3
RESERVED

CFG[10] RSVD_NCTF_56 AP35


AJ28 CFG[11] RSVD_NCTF_57 AR35
AN30 CFG[12] RSVD58 AR32
Close to DIMM AN32 CFG[13]
AJ32 CFG[14]
CFG3 - PCI-Express Static Lane Reversal
+V1.5 AJ29 E15
CFG[15] RSVD_TP_59 1 :Normal Operation R47
AJ30 CFG[16] RSVD_TP_60 F15
AK30 A2 CFG3 0 :Lane Numbers Reversed 3.01K,1%
CFG[17] KEY 15 -> 0, 14 -> 1, ...
H16 RSVD_TP_86 RSVD62 D15
RSVD63 C15
R1042 AJ15 RSVD64_R R48 0 ns
1K,1% RSVD64 RSVD65_R R49 0 ns
RSVD65 AH15

R71 0 M_VREF_DQ_DIMM0C B19


R0402_0 RSVD15
A19 RSVD16
R1043 R50 0 ns H_RSVD17_R A20 CFG4
1K,1% R51 0 ns H_RSVD18_R RSVD17
B20 RSVD18
RSVD_TP_66 AA5
U9 RSVD19 RSVD_TP_67 AA4
T9 R8 CFG4 - Display Port Presence R52
RSVD20 RSVD_TP_68
RSVD_TP_69 AD3 3.01K,1%
AC9 AD2 1:Disabled; No Physical Display Port ns
+V1.5 RSVD21 RSVD_TP_70 attached to Embedded Display Port
AB9 RSVD22 RSVD_TP_71 AA2 NO_STUFF
RSVD_TP_72 AA1 CFG4
R9 0:Enabled; An external Display Port
RSVD_TP_73 device is connected to the Embedded
RSVD_TP_74 AG7
Display Port
C1 RSVD_NCTF_23 RSVD_TP_75 AE3
R1044 A3
1K,1% CFG7 R46 3.01K,1% RSVD_NCTF_24

RSVD_TP_76 V4
R91 0 M_VREF_DQ_DIMM1C ns V5
R0402_0 RSVD_TP_77
RSVD_TP_78 N2
J29 RSVD26 RSVD_TP_79 AD5
R1045 NO_STUFF J28 AD7
1K,1% RSVD27 RSVD_TP_80
RSVD_TP_81 W3
A34 RSVD_NCTF_28 RSVD_TP_82 W2
A33 RSVD_NCTF_29 RSVD_TP_83 N3
A RSVD_TP_84 AE5 A
C35 RSVD_NCTF_30 RSVD_TP_85 AD9
B35 RSVD_NCTF_31
AP34 TP_RSVD86 R61 0 ns
VSS

IC,ARD_CFD_rPGA,R1P5
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Title

Panel &VGA connect


Size Project Name Rev

A3 R48 C
Date:
Thursday, April 22, 2010 Sheet
8 of
56
5 4 3 2 1
5 4 3 2 1

D +V3.3S
+V3.3S 5,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48 D

+V3.3S

R320 ns vdd
100

1
C141 Under DIMM

0.1uF/16V,X7R

3
ns
U2 THERMDA 1 Q155

1
MMBT3904-F

1
C140

VCC

2
8 2 ns
14,22,27 EC_SMB1_CLK SMBCLK DXP 2200pF/25V,X7R ns

2
7 3 THERMDC
14,22,27 EC_SMB1_DAT SMBDATA DXN

C 10,11 TS#_DIMM0_1
R1048 0 ns PM_THRM_DN# 6
G781
ADM1032AR C
ALERT# LM86CIM
R1049 0 ns G781_PULLHIGH 4 MAX6657MSA vdd

GND
5,27 PM_EXTTS#0_EC THERM# SOIC-8
TO EC output
SOIC8_1P27_3P9 W83L771ASG

5
U28

1
ns
+V3.3S

VCC
8 2 THERMDA
14,22,27 EC_SMB1_CLK SMBCLK DXP
7 3 THERMDC
14,22,27 EC_SMB1_DAT SMBDATA DXN
G781
R1053 R1050 PM_THRM_DN# 6 ADM1032AR
10K 10K ALERT# LM86CIM
ns ns G781_PULLHIGH 4 MAX6657MSA

GND
THERM# SOIC-8

Input To EC TSSOP8_P65_3P0

5
W83L771 TSSOP8
ns
R1051 0 ns TS#_DIMM0_1
27 PM_EXTTS_DIMM

R1052 0 ns
5 PM_EXTTS_L1

B B

A A

CZC Technology zw
Title
<Title>

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 9 of 56


5 4 3 2 1

Channel A High :9.2mm


M_A_DQ[63:0] 6 +V1.5
DIMM1A
6 M_A_A[15:0]
M_A_A0 98 5 M_A_DQ0 DIMM1B
M_A_A1 A0 DQ0 M_A_DQ1
97 A1 DQ1 7 75 VDD VSS 44
M_A_A2 96 15 M_A_DQ2 76 48
M_A_A3 A2 DQ2 M_A_DQ3 VDD VSS
95 A3 DQ3 17 81 VDD VSS 49
M_A_A4 92 4 M_A_DQ4 82 54
M_A_A5 A4 DQ4 M_A_DQ5 VDD VSS
91 A5 DQ5 6 87 VDD VSS 55
M_A_A6 90 16 M_A_DQ6 88 60
M_A_A7 A6 DQ6 M_A_DQ7 VDD VSS
86 A7 DQ7 18 93 VDD VSS 61
M_A_A8 89 21 M_A_DQ8 94 65
M_A_A9 A8 DQ8 M_A_DQ9 VDD VSS
85 A9 DQ9 23 99 VDD VSS 66
D M_A_A10 107 A10/AP DQ10 33 M_A_DQ10 100 VDD VSS 71 D
M_A_A11 84 35 M_A_DQ11 105 72
M_A_A12 A11 DQ11 M_A_DQ12 VDD VSS
83 A12/BC# DQ12 22 106 VDD VSS 127
M_A_A13 119 24 M_A_DQ13 111 128
M_A_A14 A13 DQ13 M_A_DQ14 +V3.3S VDD VSS
80 A14 DQ14 34 112 VDD VSS 133
M_A_A15 78 36 M_A_DQ15 117 134
A15 DQ15 M_A_DQ16 VDD VSS
DQ16 39 118 VDD VSS 138
109 41 M_A_DQ17 123 139
6 M_A_BS0 BA0 DQ17 VDD VSS
108 51 M_A_DQ18 124 144
6 M_A_BS1 BA1 DQ18 VDD VSS
79 53 M_A_DQ19 C94 C95 145
6 M_A_BS2 BA2 DQ19 VSS
M_CS_L0 114 40 M_A_DQ20 0.1uF/16V,X7R
2.2uF/6.3V,X7R 199 150
6 M_CS_L0 S0# DQ20 VDDSPD VSS
M_CS_L1 121 42 M_A_DQ21 151
6 M_CS_L1 S1# DQ21 VSS
101 50 M_A_DQ22 77 155
6 M_CLK_DDR0 CK0 DQ22 NC1 VSS
103 52 M_A_DQ23 122 156
6 M_CLK_DDR0_L CK0# DQ23 NC2 VSS
102 57 M_A_DQ24 125 161
6 M_CLK_DDR1 CK1 DQ24 NCTEST VSS
104 59 M_A_DQ25 162
6 M_CLK_DDR1_L CK1# DQ25 VSS
73 67 M_A_DQ26 198 167
6 M_CKE0 CKE0 DQ26 9,11 TS#_DIMM0_1 EVENT# VSS
74 69 M_A_DQ27 30 168
6 M_CKE1 CKE1 DQ27 5,11 DDR3_DRAMRST_L RESET# VSS
115 56 M_A_DQ28 172
6 M_A_CAS_L CAS# DQ28 VSS
110 58 M_A_DQ29 173
6 M_A_RAS_L RAS# DQ29 VSS
113 68 M_A_DQ30 M_VREF_DQ_DIMM0C 1 178
6 M_A_WE_L WE# DQ30 8 M_VREF_DQ_DIMM0C VREF_DQ VSS
SA0_DIM0 197 70 M_A_DQ31 126 179
SA1_DIM0 SA0 DQ31 M_A_DQ32 VREF_CA VSS
201 SA1 DQ32 129 VSS 184
SODIMM0_1_SMB_CLK_R 202 131 M_A_DQ33 C96 C97 185
11,12,14 SMB_CLK_S2 SCL DQ33 VSS
SODIMM0_1_SMB_DATA_R 200 141 M_A_DQ34 0.1uF/16V,X7R
2.2uF/6.3V,X7R 2 189
11,12,14 SMB_DATA_S2 SDA DQ34 VSS VSS
143 M_A_DQ35 3 190
DQ35 M_A_DQ36 VSS VSS
6 M_ODT0 116 ODT0 DQ36 130 8 VSS VSS 195
6 M_ODT1 120 132 M_A_DQ37 9 196
ODT1 DQ37 M_A_DQ38 VSS VSS
6 M_A_DM[7:0] DQ38 140 13 VSS
M_A_DM0 11 142 M_A_DQ39 14
M_A_DM1 DM0 DQ39 M_A_DQ40 R1157 0 ns M_VREF_DQ_DIMM0 VSS +V0.75S
28 DM1 DQ40 147 11,33 M_VREF 19 VSS
M_A_DM2 46 149 M_A_DQ41 20
C M_A_DM3 DM2 DQ41 M_A_DQ42 VSS C
63 DM3 DQ42 157 25 VSS
M_A_DM4 136 159 M_A_DQ43 C98 C99 26 203
M_A_DM5 DM4 DQ43 M_A_DQ44 VSS VTT
153 DM5 DQ44 146 0.1uF/16V,X7R
2.2uF/6.3V,X7R 31 VSS VTT 204
M_A_DM6 170 148 M_A_DQ45 32
M_A_DM7 DM6 DQ45 M_A_DQ46 VSS
187 DM7 DQ46 158 37 VSS 205 205
160 M_A_DQ47 38 206
6 M_A_DQS[7:0] M_A_DQS0 12 DQ47 M_A_DQ48 VSS 206
DQS0 DQ48 163 43 VSS
M_A_DQS1 29 165 M_A_DQ49
M_A_DQS2 47 DQS1 DQ49 M_A_DQ50 DDRIIISODIMM-204PS_BLACK-RH-1
DQS2 DQ50 175
M_A_DQS3 64 177 M_A_DQ51 VRefCA on both SO-DIMMs can be connected by a single M_VREF_MCH trace
M_A_DQS4 137 DQS3 DQ51 M_A_DQ52
DQS4 DQ52 164
M_A_DQS5 154 166 M_A_DQ53 VRefDQ on both SO-DIMMs can be shared by a second separate M_VREF_MCH trace
M_A_DQS6 171 DQS5 DQ53 M_A_DQ54 Place these caps
DQS6 DQ54 174
M_A_DQS7 188 176 M_A_DQ55 close to VTT1 and
6 M_A_DQS_L[7:0] M_A_DQS_L0 10 DQS7 DQ55 M_A_DQ56 VTT2. Place C21
DQS#0 DQ56 181
M_A_DQS_L1 27 M_A_DQ57 on common path
DQS#1 DQ57 183
M_A_DQS_L2 45 M_A_DQ58 for both DIMM's
DQS#2 DQ58 191
M_A_DQS_L3 62 193 M_A_DQ59
M_A_DQS_L4135 DQS#3 DQ59 M_A_DQ60
DQS#4 DQ60 180
M_A_DQS_L5152 182 M_A_DQ61
M_A_DQS_L6169 DQS#5 DQ61 M_A_DQ62 +V0.75S
DQS#6 DQ62 192
M_A_DQS_L7186 194 M_A_DQ63
DQS#7 DQ63

DDRIIISODIMM-204PS_BLACK-RH-1

C100 C101 C102 C103 Place near Vtt pins


1uF/10V,X5R 1uF/10V,X5R 1uF/10V,X5R 1uF/10V,X5R

B +V1.5 B

Place two capacitors close to the VR


Layout Note: Place and one between the two DIMMs
+ C110 these Caps near
C104 C105 C106 C107 C108 C109 220uF/6.3V,POSCAP SO-DIMM1.
10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R
ns
NO_STUFF
+V1.5
+V3.3S

C111 C112 C113 C114


1uF/10V,X5R 1uF/10V,X5R 1uF/10V,X5R 1uF/10V,X5R
NO_STUFF +V1.5 5,7,8,11,33,35
+V3.3S 5,9,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48
Note: R53
If SA0_DIM0 = 0, SA1_DIM0 = 0 +V0.75S 11,28,33
10K
SO-DIMM0 SPD Address is 0xA0 ns
SO-DIMM0 TS Address is 0x30

A
If SA0_DIM0 = 1, SA1_DIM0 = 0
SO-DIMM0 SPD Address is 0xA2
SO-DIMM0 TS Address is 0x32
SA0_DIM0
SA1_DIM0
CZC Technology zw
A

Title
R54 R55
10K 10K
Panel &VGA connect
Size Project Name Rev

A R48 C
Date:
Thursday, April 22, 2010 Sheet
10 of
56
5 4 3 2 1
5 4 3 2 1

+V1.5 5,7,8,10,33,35
Channel B High :5.2mm +V3.3S 5,9,10,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48
+V0.75S 10,28,33

DIMM2A
M_B_DQ[63:0] 6 +V1.5
6 M_B_A[15:0]
M_B_A0 98 5 M_B_DQ0 DIMM2B
M_B_A1 A0 DQ0 M_B_DQ1
97 A1 DQ1 7 75 VDD VSS 44
M_B_A2 96 15 M_B_DQ2 76 48
A2 DQ2 VDD VSS
D M_B_A3 95 A3 DQ3 17 M_B_DQ3 81 VDD VSS 49 D
M_B_A4 92 4 M_B_DQ4 82 54
M_B_A5 A4 DQ4 M_B_DQ5 VDD VSS
91 A5 DQ5 6 87 VDD VSS 55
M_B_A6 90 16 M_B_DQ6 88 60
M_B_A7 A6 DQ6 M_B_DQ7 VDD VSS
86 A7 DQ7 18 93 VDD VSS 61
M_B_A8 89 21 M_B_DQ8 94 65
M_B_A9 A8 DQ8 M_B_DQ9 VDD VSS
85 A9 DQ9 23 99 VDD VSS 66
M_B_A10 107 33 M_B_DQ10 100 71
M_B_A11 A10/AP DQ10 M_B_DQ11 VDD VSS
84 A11 DQ11 35 105 VDD VSS 72
M_B_A12 83 22 M_B_DQ12 106 127
M_B_A13 A12/BC# DQ12 M_B_DQ13 +V3.3S VDD VSS
119 A13 DQ13 24 111 VDD VSS 128
M_B_A14 80 34 M_B_DQ14 112 133
M_B_A15 A14 DQ14 M_B_DQ15 VDD VSS
78 A15 DQ15 36 117 VDD VSS 134
39 M_B_DQ16 118 138
DQ16 M_B_DQ17 VDD VSS
6 M_B_BS0 109 BA0 DQ17 41 123 VDD VSS 139
108 51 M_B_DQ18 124 144
6 M_B_BS1 BA1 DQ18 VDD VSS
79 53 M_B_DQ19 C115 C116 145
6 M_B_BS2 BA2 DQ19 VSS
114 40 M_B_DQ20 0.1uF/16V,X7R 2.2uF/6.3V,X7R 199 150
6 M_CS_L2 S0# DQ20 VDDSPD VSS
121 42 M_B_DQ21 151
6 M_CS_L3 S1# DQ21 VSS
101 50 M_B_DQ22 77 155
6 M_CLK_DDR2 CK0 DQ22 NC1 VSS
103 52 M_B_DQ23 122 156
6 M_CLK_DDR2_L CK0# DQ23 NC2 VSS
102 57 M_B_DQ24 125 161
6 M_CLK_DDR3 CK1 DQ24 NCTEST VSS
104 59 M_B_DQ25 162
6 M_CLK_DDR3_L CK1# DQ25 VSS
73 67 M_B_DQ26 198 167
6 M_CKE2 CKE0 DQ26 9,10 TS#_DIMM0_1 EVENT# VSS
74 69 M_B_DQ27 30 168
6 M_CKE3 CKE1 DQ27 5,10 DDR3_DRAMRST_L RESET# VSS
115 56 M_B_DQ28 172
6 M_B_CAS_L CAS# DQ28 VSS
110 58 M_B_DQ29 173
6 M_B_RAS_L RAS# DQ29 VSS
113 68 M_B_DQ30 M_VREF_DQ_DIMM1C 1 178
6 M_B_WE_L WE# DQ30 8 M_VREF_DQ_DIMM1C VREF_DQ VSS
SA0_DIM1 197 70 M_B_DQ31 126 179
SA1_DIM1 SA0 DQ31 M_B_DQ32 VREF_CA VSS
201 SA1 DQ32 129 VSS 184
202 131 M_B_DQ33 C117 C118 185
10,12,14 SMB_CLK_S2 SCL DQ33 VSS
10,12,14 SMB_DATA_S2 200 141 M_B_DQ34 0.1uF/16V,X7R 2.2uF/6.3V,X7R 2 189
C SDA DQ34 M_B_DQ35 VSS VSS C
DQ35 143 3 VSS VSS 190
6 M_ODT2 116 130 M_B_DQ36 8 195
ODT0 DQ36 M_B_DQ37 VSS VSS
6 M_ODT3 120 ODT1 DQ37 132 9 VSS VSS 196
140 M_B_DQ38 13
6 M_B_DM[7:0] DQ38 VSS
M_B_DM0 11 142 M_B_DQ39 14
M_B_DM1 DM0 DQ39 M_B_DQ40 R1158 0 ns M_VREF_DQ_DIMM1 VSS
28 DM1 DQ40 147 10,33 M_VREF 19 VSS
M_B_DM2 46 149 M_B_DQ41 20 +V0.75S
M_B_DM3 DM2 DQ41 M_B_DQ42 VSS
63 DM3 DQ42 157 25 VSS
M_B_DM4 136 159 M_B_DQ43 C119 C120 26
M_B_DM5 DM4 DQ43 M_B_DQ44 VSS VTT 203
153 DM5 DQ44 146 0.1uF/16V,X7R 2.2uF/6.3V,X7R 31 VSS VTT 204
M_B_DM6 170 148 M_B_DQ45 32
M_B_DM7 DM6 DQ45 M_B_DQ46 VSS
187 DM7 DQ46 158 37 VSS 205 205
160 M_B_DQ47 38
6 M_B_DQS[7:0] M_B_DQS0 DQ47 M_B_DQ48 VSS 206 206
12 DQS0 DQ48 163 43 VSS
M_B_DQS1 29 165 M_B_DQ49 DDRIIISODIMM-204PS_BLACK-RH
M_B_DQS2 DQS1 DQ49 M_B_DQ50 VRefCA on both SO-DIMMs can be connected by a single M_VREF_MCH trace
47 DQS2 DQ50 175
M_B_DQS3 64 177 M_B_DQ51
M_B_DQS4 DQS3 DQ51 M_B_DQ52 VRefDQ on both SO-DIMMs can be shared by a second separate M_VREF_MCH trace
137 DQS4 DQ52 164
M_B_DQS5 154 166 M_B_DQ53
M_B_DQS6 DQS5 DQ53 M_B_DQ54
171 DQS6 DQ54 174
M_B_DQS7 188 176 M_B_DQ55
6 M_B_DQS_L[7:0] M_B_DQS_L0 DQS7 DQ55 M_B_DQ56
10 DQS#0 DQ56 181
M_B_DQS_L1 27 183 M_B_DQ57
M_B_DQS_L2 DQS#1 DQ57 M_B_DQ58
45 DQS#2 DQ58 191
M_B_DQS_L3 62 193 M_B_DQ59
M_B_DQS_L4 DQS#3 DQ59 M_B_DQ60
135 DQS#4 DQ60 180
M_B_DQS_L5 152 182 M_B_DQ61 +V0.75S
M_B_DQS_L6 DQS#5 DQ61 M_B_DQ62
169 DQS#6 DQ62 192
M_B_DQS_L7 186 194 M_B_DQ63
DQS#7 DQ63

B DDRIIISODIMM-204PS_BLACK-RH B
C122 C123 C124 Place near Vtt pins
C121 1uF/10V,X5R 1uF/10V,X5R 1uF/10V,X5R
Note: 1uF/10V,X5R
SO-DIMM1 SPD Address is 0xA4 SO-DIMM1 is placed farther from
SO-DIMM1 TS Address is 0x34 the Processor than SO-DIMM0

+V1.5

+V3.3S Layout Note: Place


+ C131 these Caps near
C125 C126 C127 C128 C129 C130 220uF/2.5V SO-DIMM1.
10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R 10uF/10V X5R ns
R56
10K

SA1_DIM1
+V1.5
SA0_DIM1

A
R57
10K
C132
1uF/10V,X5R
C133
0.1uF/16V,X7R
C134
0.1uF/16V,X7R
C135
0.1uF/16V,X7R
CZC Technology zw
A

Title

Panel &VGA connect


Size Project Name Rev

A R48 C
Date:
Thursday, April 22, 2010 Sheet
11 of
56
5 4 3 2 1
5 4 3 2 1

+V3.3S
+V3.3S 5,9,10,11,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48
+V1.1S_VTT 5,7,16,17,35,36 +V3.3S

Total Power:495mW
Typical current:IDD=150mA
U44
@3.3V Core and 3.3V IO CPU_STOP# R59 10K
IDTCV186-2C PCI_STOP#_R R108 10K ns
+V3.3S +V3.3S_CLK TSSOP56_P5_6P1
FB83 IO_VOUT
NC 40
2 48 VR_PWRGD_CLKEN
D VDD_PCI CKPWRGD/PWRDWN# +V3.3S D
9 VDD_48

4.7uF/10V,X5R

4.7uF/10V,X5R
16

10UF/6.3V,X5R
300ohm/100MHz,1A VDD
C939 C935 C936 C937 C938 C941 31
0.1uF/16V,X7R
0.1uF/16V,X7R
0.1uF/16V,X7R
0.1uF/16V,X7R
0.1uF/16V,X7R
0.1uF/16V,X7R VDD_SRC SMB_CK 0 R70 SMB_CLK_S2

C933

C940

C934
47 VDD_CPU SCLK 56 SMB_CLK_S2 10,11,14
53 55 SMB_DAT 0 R69 SMB_DATA_S2
VDD_REF SDATA SMB_DATA_S2 10,11,14
R865
+V1.1S_VTT VDDIO_CLK XTAL_IN 15,1%
XTAL_IN 52
51 XTAL_OUT
XTAL_OUT
FB84 300ohm/100MHz,1A 12 VDD_96_IO

3
ns 20 VDD_PLL3_IO CK505_CPU0_L R62 0 CLK_BUF_CPU_BCLK_L IO_VOUT R866 33 Q92
26 45 1

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R
VDD_SRC_IO1 CPU0# CLK_BUF_CPU_BCLK_L 14
C949 C942 C943 C944 C945 37 46 CK505_CPU0 R60 0 CLK_BUF_CPU_BCLK MMBT3904-F
VDD_SRC_IO2 CPU0 CLK_BUF_CPU_BCLK 14
0.1uF/16V,X7R
0.1uF/16V,X7R
0.1uF/16V,X7R
0.1uF/16V,X7R
0.1uF/16V,X7R

C946

C947

C948
Reserved for ICS9LPRS525 41 VDD_CPU_IO

2
R75 0 ns C1034 VDDIO_CLK
CPU1# 42 CLK_MCP_BCLK_L 5,16
43 R74 0 ns
CPU1 CLK_MCP_BCLK 5,16 100pF/50V,NPO

TP66 1 38

10UF/6.3V,X5R
PCI0/CR#A SRC8#/ITP# C927
3 PCI1/CR#B SRC8/ITP 39
PCI2_TME 0.1uF/16V,X7R

C950
4 PCI2/TME
+V3.3S_CLK PCI3/CFGP 5 PCI3 SRC7#/CR#_E 35
PCI4_SRC5_EN 6 36
PCIF5_ITP_EN PCI4/SRC5_EN SRC7/CR#_F
7 PCI_F5/ITP_EN
32 R72 0 ns
SRC6# CLK_MCH_PEG_L 5,14
33 R73 0 ns
SRC6 CLK_MCH_PEG 5,14
R796 R791 R792
10K 10K 10K 29 CPU_STOP#
ns ns ns CK505_FSC R781 10K SRC5#/CPU_STOP# PCI_STOP#_R R98 0 ns PCI_STOP#
SRC5/PCI_STOP# 30 PCI_STOP# 16
R99 10K
PCI3/CFGP PCI2_TME PCIF5_ITP_EN PCI4_SRC5_EN R786 22 54
14 CLK_BUF_REF14 REF0/FSC/TEST_SEL R76 0 ns PCIE_REFCLKN
SRC4# 28 PCIE_REFCLKN 14,41
CK505_FSB R782 1K 49 27 R77 0 ns PCIE_REFCLKP
FSB/TEST_MODE SRC4 PCIE_REFCLKP 14,41
R797 R793 R795 R794 CK505_FSA R787 2.2K 10 25 R127 0 ns
USB_48MHz/FSA SRC3#/CR#_D R112 10K PEG_CLKREQ#_CLK 14,42
C 10K 10K 10K 10K SRC3/CR#_C 24 C
R788 22
24 EXT_25/48
8 22 CK505_SRC2_L R68 0 CLK_BUF_EXP_N
VSS_PCI SRC2#/SATA# CLK_BUF_EXP_N 14
11 21 CK505_SRC2 R67 0 CLK_BUF_EXP_P
VSS_48 SRC2/SATA CLK_BUF_EXP_P 14
15 VSS_IO
19 18 CK505_SRC1_L R66 0 CLK_BUF_CKSSCD_N
VSS_PLL3 SRC1#/DREFSSCLK# CLK_BUF_CKSSCD_N 14
Design Note: 23 17 CK505_SRC1 R65 0 CLK_BUF_CKSSCD_P
VSS_SRC1 SRC1/DREFSSCLK CLK_BUF_CKSSCD_P 14
1.PCI2_TME 34 VSS_SRC2 CK505_SRC0_L R64 0 CLK_BUF_DOT96_N
0=overclocking of CPU and SRC allowed 44 14 CLK_BUF_DOT96_N 14
VSS_CPU SRC0#/DOT96# CK505_SRC0 R63 0 CLK_BUF_DOT96_P
1=overclocking of CPU and SRC NOT allowed 50 13 CLK_BUF_DOT96_P 14
VSS_REF SRC0/DOT96
2..PCIF5_ITP_EN
0=SRC8/SRC8#
1=ITP/ITP#
On powerup,The logic value on this pin determines Function 0 or Function 1

3.PCI4_SRC5_EN
0=PCI_STOP#/CPU_STOP#
1=SRC5/SRC5#
On powerup,The logic value on this pin determines Function 0 or Function 1

+V1.1S_VTT

FSC FSB FSA R778 R776 R780


Host Clock
BSEL2 BSEL1 BSEL0 1K 1K 56
B frequency MHz ns ns B
Y7 XTAL_IN +V3.3S
CK505_FSA 14.318MHz,18pf
1 0 1 100 1 2 XTAL_OUT
CLK_BUF_REF14 C931 100pF/50V,NPO ns
CK505_FSB X2S60X35
0 0 1 133 EXT_25/48 C932 100pF/50V,NPO ns R783
C925 C926 10K
CK505_FSC 27pF/50V,NPO 27pF/50V,NPO
0 1 1 166 R918 VR_PWRGD_CLKEN
10K

3
0 1 0 200 R777 R770 R772 Q91
0 0 1K 2N7002K R774
ns 1 10K
38 CLKEN# ns
0 0 0 266

2
1 0 0 333

1 1 0 400

1 1 1 Reserved

A A

CZC Technology zw
Title

Panel &VGA connect


Size Project Name Rev

A4 R48 C
Date:
Thursday, April 22, 2010 Sheet
12 of
56
5 4 3 2 1
5 4 3 2 1

+V3.3AUX +V3.3_RTC
+V1.1S 7,14,16,17,34,35,36
+V3.3S 5,9,10,11,12,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48
+V3.3AUX 5,14,15,16,17,19,21,22,24,25,27,28,29,30,31,32,34,35
JCMOS - CMOS SETTING
SAVE CMOS -- (1- 2) DEFAULT +V3.3_RTC 17
D1 C147
CLEAR CMOS -- (2-3) +V3.3S
1uF/10V,X5R
2
RTC Circuitry
BAT54C 3 R78 20K,1% RTCRST_C C148 LDRQ0_L R870 10K
18pF/50V,NPO LDRQ1_L R871 10K
1
R79 20K,1% C149 32.768kHz,20ppm,12.5pF

1
1uF/10V,X5R
Y2
BAT_D

C150 R80
D J1 X4S67x15 10M
D
1uF/10V,X5R

4
JOPEN C151
R81 ns 18pF/50V,NPO U3A
1M J4
JOPEN RTC_X1 B13 D33
RTCX1 FWH0 / LAD0 LPC_AD0 21,27
ns RTC_X2 D13 B33
RTCX2 FWH1 / LAD1 LPC_AD1 21,27
R82 Cap values depend on Xtal C32
FWH2 / LAD2 LPC_AD2 21,27
1K FWH3 / LAD3 A32 LPC_AD3 21,27
RTC_RST_L C14 RTCRST#
FWH4 / LFRAME# C34 LPC_FRAME# 21,27
SRTC_RST_L D17
SM_INTRUDER_L SRTCRST# LDRQ0_L
LDRQ0# A34
LDRQ1_L

RTC

LPC
A16 INTRUDER# LDRQ1# / GPIO23 F34
+V3.3_RTC
R83 PCH_INTVRMEN A14 AB9
INTVRMEN SERIRQ INT_SERIRQ 21,27
INTVRMEN - Integrated SUS 332K,1%
3

1.1V VRM Enable ?HIGH C247 10pF/50V,NPO ns


Wafer2P125
R164 33 A30
RTCCN1 25 HDA_BIT_CLK HDA_BCLK
SATA0RXN AK7 SATA_RXN0 23
1 HWS2_1P25R R165 33 D29 AK6
25 HDA_SYNC HDA_SYNC SATA0RXP C152 0.01uF/25V,X7R SATA_RXP0 23
2 SATA0TXN AK11 SATA_TXN0 23
HDA_SPKR P1 AK9 C153 0.01uF/25V,X7R
25 HDA_SPKR SPKR SATA0TXP SATA_TXP0 23
R173 33 C30 Distance between the PCH and
25 HDA_RST_L HDA_RST#
4

SATA1RXN AH6 SATA_RXN1 23 cap on the "P" signal should


SATA1RXP AH5 SATA_RXP1 23
G30 AH9 C156 0.01uF/25V,X7R be identical distance between
25 HDA_SDIN0 HDA_SDIN0 SATA1TXN SATA_TXN1 23 the PCH and cap on the "N"
AH8 C157 0.01uF/25V,X7R
SATA1TXP SATA_TXP1 23
HDA_SDIN1 F30 signal for same pair.
25 HDA_SDIN1 HDA_SDIN1
SATA2RXN AF11
TP7 HDA_SDIN2 E32 AF9
RTC_ADHESIVE1 RTC_CBL1 HDA_SDIN2 SATA2RXP
AF7

IHDA
HDA_SDIN3 SATA2TXN
+ TP8 F32 HDA_SDIN3 SATA2TXP AF6
HM55 No function.
- SATA3RXN AH3
C RTC_Adhesive RTCBAT with Cable R229 33 B29 AH1 C
assembly assembly 25 HDA_SDOUT HDA_SDO SATA3RXP
SATA3TXN AF3
SATA3TXP AF1
HDA_DOCK_EN_L H32 HDA_DOCK_EN# / GPIO33 C158 0.01uF/25V,X7R
AD9

SATA
TP_HDA_DOCK_RST_L SATA4RXN C159 0.01uF/25V,X7R SATA_RXN2 22
TP9 J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8 SATA_RXP2 22
AD6 C160 0.01uF/25V,X7R
SATA4TXN SATA_TXN2 22
AD5 C161 0.01uF/25V,X7R
SATA4TXP SATA_TXP2 22
PCH_JTAG_TCK M3 AD3
+V1.1S JTAG_TCK SATA5RXN
SATA5RXP AD1
PCH_JTAG_TMS K3 AB3
PCH_JTAG_TMS R84 51ns JTAG_TMS SATA5TXN +V1.1S
SATA5TXP AB1
PCH_JTAG_TDI K1
PCH_JTAG_TDI R85 51ns JTAG_TDI
PCH_JTAG_TDO

JTAG
J2 JTAG_TDO SATAICOMPO AF16
PCH_JTAG_TDO R86 51ns +V3.3S
PCH_JTAG_RST_L J4 AF15 SATACOMP R87 37.4,1%
TRST# SATAICOMPI
PCH_JTAG_RST_L R88 10K ns
R869
R89 51 ns SPI_CLK BA2 10K
SPI_CLK
NO_STUFF
SPI_CS_L0 AV3 SPI_CS0#
PCH_JTAG_TCK R90 4.7K iTPM Enable/Disable SPI_CS_L1 +V3.3S
TP58 AY3 SPI_CS1# SATALED# T3 SATA_LED# 29
Enable iTPM : R333 stuff
SPI_SI Disable iTPM : R333 no stuff
SPI_SI AY1 Y9 SATA_DET_L0 R94 10K
+V3.3S SPI_MOSI SATA0GP / GPIO21
SPIMISO SATA_DET_L1_R R92 10K

SPI
AV1 SPI_MISO SATA1GP / GPIO19 V1
R248 8.2K ns SPI_SI

IbexPeak-M_Rev1_5

+V3.3S
B B
+V3.3S

Layout Toplogy for SPI CLK and MOSI R463 R464


R95 1K ns HDA_SPKR ns U31

1
NO_STUFF W25Q32BVSSIG R462
L1 = 1-5" 3.3K 3.3K SOIC8_1P27_3P9 10K C405
R96 10K INT_SERIRQ SPI_CS_L01 0.1uF/16V,X7R
SPIMISO 2 CE# VDD 8

2
L2 or L3 = 0.5-2" HOLD#
No Reboot Strap R86 WP# SO HOLD# 7 SPI_CLK
3 WP# SCK 6
L2 +/- L3 <= 0.1" 4 VSS SPI_SI
SI 5
SPI Device 1 HDA_SPKR No stuff = Default
Stuff = No Reboot
ns
U30 +V3.3S
L2 Flash Descriptor Security Override W25Q32BVSSIG
SOP8_1P27_5P3
L1 HDA_DOCK_EN# BIOS_LOCK: SPI_CS_L01
SPIMISO 2 CE# VDD 8 HOLD#
PCH LOCK=2-3 (default)
SO HOLD# 7
GPIO33 UNLOCK=1-2 WP# 3 SPI_CLK
WP# SCK 6 SPI_SI
4 VSS SI 5
L3 +V3.3S

SPI_CS_L01 8
1 8
MISO Topology Open SPI Device 2 SPIMISO 2
2 7 7 HOLD#
WP# 3 6 SPI_CLK
3 6 SPI_SI
4 4 5 5
4

BIOS_CN2
3 H2X4KZ
BIOS_LOCK 2X4 2mm
HDA_DOCK_EN_L 2 DIP MSS3 ns
SWS7D67x26

A A
1
放在后盖下方。
CZC Technology zw
6

Title
R97
1K
Panel &VGA connect
Size Project Name Rev

A4 R48 C
Date:
Thursday, April 22, 2010 Sheet
13 of
56
5 4 3 2 1
5 4 3 2 1

U3B
+V3.3S 5,9,10,11,12,13,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48
+V3.3AUX 5,13,15,16,17,19,21,22,24,25,27,28,29,30,31,32,34,35
BG30 B9 PCH_GPIO11
21 PCIE_RXN1 PERN1 SMBALERT# / GPIO11 +V5AUX 17,19,22,24,27,28,29,32,33,34,35,36
21 PCIE_RXP1 BJ30 PERP1 +V1.1S 7,13,16,17,34,35,36
C170 0.1uF/16V,X7R PCIE_TXN1_C BF29 H14 SMB_CLK
21 PCIE_TXN1 PETN1 SMBCLK +V5S 15,16,17,18,19,20,21,23,25,26,28,29,35,36,37,38
C171 0.1uF/16V,X7R PCIE_TXP1_C BH29
21 PCIE_TXP1 PETP1 SMB_DATA
SMBDATA C8
21 PCIE_RXN2 AW30 PERN2
21 PCIE_RXP2 BA30 PERP2
C172 0.1uF/16V,X7R 3G PCIE_TXN2_C BC30 J14 PCH_UPEK_INIT_L
21 PCIE_TXN2 C169 0.1uF/16V,X7R 3G PCIE_TXP2_C PETN2 SML0ALERT# / GPIO60
BD30 PETP2
21 PCIE_TXP2 SML0_CLK
SML0CLK C6
22 PCIE_RXN2_EXPRESS AU30 PERN3 SML0_DATA

SMBus
22 PCIE_RXP2_EXPRESS AT30 PERP3 SML0DATA G8
C358 0.1uF/16V,X7R AU32
22 PCIE_TXN2_EXPRESS PETN3
C357 0.1uF/16V,X7R AV32
22 PCIE_TXP2_EXPRESS PETP3
M14 PCH_GPIO74
SML1ALERT# / GPIO74
BA32 PERN4
BB32 E10 SML1_CLK R109 0 R0402_0 +V3.3S
PERP4 SML1CLK / GPIO58 EC_SMB1_CLK 9,22,27
BD32 PETN4
BE32 G12 SML1_DATA R110 0 R0402_0
PETP4 SML1DATA / GPIO75 EC_SMB1_DAT 9,22,27

PCI-E*
D BF33 PERN5 D
BH33 T13 R1055
PERP5 CL_CLK1 1K
BG32

Controller
PETN5
BJ32 PETP5 CL_DATA1 T11
PEG_CLKREQ#_CLK

Link
PCIE_RXN6_R 12,42 PEG_CLKREQ#_CLK
24 PCIE_RXN6_LAN BA34 PERN6 CL_RST1# T9
PCIE_RXP6_R AW34 PEG_CLKREQ_L R111 0
24 PCIE_RXP6_LAN PERP6
C173 0.1uF/16V,X7R PCIE_TXN6_C BC34 R0402_0
24 PCIE_TXN6_LAN C174 0.1uF/16V,X7R PCIE_TXP6_C PETN6
BD34 PETP6
24 PCIE_TXP6_LAN

3
PEG_CLKREQ_L
PEG_A_CLKRQ# / GPIO47 H1 Q171
AT34 PERN7
AU34 2N7002K
PERP7 CK_PEG_N R100 0 DGPU PCIE_REFCLKN SOT23
AU36 PETN7 CLKOUT_PEG_A_N AD43 PCIE_REFCLKN 12,41 1
CK_PEG_P R101 0 DGPU PCIE_REFCLKP DGPU DGPU_PWROK 16
AV36 PETP7 CLKOUT_PEG_A_P AD45 PCIE_REFCLKP 12,41

2
HM55 No function. BG34 AN4 CK_DMI_N R102 0 R0402_0 CLK_MCH_PEG_L
PERN8 CLKOUT_DMI_N CLK_MCH_PEG_L 5,12
BJ34 AN2 CK_DMI_P R103 0 R0402_0 CLK_MCH_PEG

PEG
PERP8 CLKOUT_DMI_P CLK_MCH_PEG 5,12
BG36 PETN8
BJ36 PETP8 CK_DP0_N R104 0 R0402_0 CLK_DP_N
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1 CK_DP0_P R105 0 R0402_0 CLK_DP_P
CLK_DP_N 5
+V3.3AUX CLKOUT_DP_P / CLKOUT_BCLK1_P AT3 CLK_DP_P 5
AK48 CLKOUT_PCIE0N
AK47 CLKOUT_PCIE0P
AW24

From CLK BUFFER


R106 10K PCH_SRC0_CLKREQ_L CLKIN_DMI_N CLK_BUF_EXP_N 12
P9 PCIECLKRQ0# / GPIO73 CLKIN_DMI_P BA24
CLK_BUF_EXP_P 12 PEG_CLKREQ_L R107 10K
DGPU
CLK_PCIE_MINICARD1_L CK_PEG1_N AM43 AP3
21 CLK_PCIE_MINICARD1_L CLKOUT_PCIE1N CLKIN_BCLK_N CLK_BUF_CPU_BCLK_L 12
CLK_PCIE_MINICARD1 CK_PEG1_P AM45 AP1
21 CLK_PCIE_MINICARD1 CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_CPU_BCLK 12
CLK_MINICARD1_OE_L U4
21 CLK_MINICARD1_OE_L PCIECLKRQ1# / GPIO18
F18 CLK_BUF_DOT96_N
CLKIN_DOT_96N CLK_BUF_DOT96_P CLK_BUF_DOT96_N 12
CLKIN_DOT_96P E18 CLK_BUF_DOT96_P 12
CLK_PCIE_MINICARD2_L CK_PEG2_N AM47
21 CLK_PCIE_MINICARD2_L CLKOUT_PCIE2N
CLK_PCIE_MINICARD2 CK_PEG2_P AM48
21 CLK_PCIE_MINICARD2 CLKOUT_PCIE2P CLK_BUF_CKSSCD_N
CLK_MINICARD2_OE_L CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_CKSSCD_P CLK_BUF_CKSSCD_N 12
21 CLK_MINICARD2_OE_L N4 PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P AH12 CLK_BUF_CKSSCD_P 12

TP_CLKOUT_PCIE3N AH42 P41 CLK_BUF_REF14


22 GPP_CLK2_N CLKOUT_PCIE3N REFCLK14IN CLK_BUF_REF14 12
TP_CLKOUT_PCIE3P AH41
22 GPP_CLK2_P CLKOUT_PCIE3P +V1.1S
PCH_SRC3_CLKREQ_L A8 J42 CLK_PCI_FB
22 EXPRESS_CLKREQ# PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB 15
C177
AM51 AH51 25M_PCH01 R113 0 R0402_0 XTAL25_IN
+V3.3AUX CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT
AM53 CLKOUT_PCIE4P XTAL25_OUT AH53 IGP Stuff
18pF/50V,NPO

2
R114 10K PCH_SRC4_CLKREQ_L M9 AF38 XCLK_RCOMP R115 91,1%
PCIECLKRQ4# / GPIO26 XCLK_RCOMP R116 Y10
1M 25MHz,20pF Cap values depend on Xtal
CLK_PCIE_LAN_L R118 0 R0402_0CK_PEGB_N AJ50 T45 TP_CLK_FLEX0 TP10
X2 : D04-1001100-T16
24 CLK_PCIE_LAN_L CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
CLK_PCIE_LAN R119 0 R0402_0CK_PEGB_P AJ52 R351 D04-1001100-T02
C 24 CLK_PCIE_LAN CLKOUT_PCIE5P C178 C

1
0 If no IGP,stuff
H6 P43 TP_CLK_FLEX1 TP11 ns
24 CLK_PCIE_LAN_REQ_L PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
Clock Flex

TP_CLK_FLEX2 18pF/50V,NPO
AK53 CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 T42 TP12
AK51 CLKOUT_PEG_B_P +V3.3AUX
R117 10K PCH_SRC5_CLKREQ_L P13 N50 TP_CLK_FLEX3 TP15
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
PCH_GPIO74 R120 10K
IbexPeak-M_Rev1_5
PCH_GPIO11 R121 10K

PCH_UPEK_INIT_L R122 10K

SMB_CLK R123 2.2K


+V3.3S
+V5S SMB_DATA R124 2.2K
+V5S +V3.3S
SML0_CLK R125 2.2K

SML0_DATA R126 2.2K


R131
R129 4.7K
1

4.7K
1

SMB_DATA 3 2 SMB_DATA_S2 SML1_CLK R130 2.2K ns


2N7002K SMB_DATA_S2 10,11,12
SMB_CLK 3 2 SMB_CLK_S2
2N7002K SMB_CLK_S2 10,11,12 Q5 SML1_DATA R132 2.2K ns
Q4 SMB_DATA_S3
SMB_DATA_S3 10,11,12
SMB_CLK_S3
SMB_CLK_S3 10,11,12

R359 0 R0402_0

R360 0 R0402_0
R353 0 ns
SMB_DATA_A 21,22,24
R352 0 ns
SMB_CLK_A 21,22,24

U3C
BA18 FDI_TXN0
FDI_RXN0 FDI_TXN1 FDI_TXN0 5
5 DMI_RXN0 BC24 DMI0RXN FDI_RXN1 BH17 FDI_TXN1 5
BJ22 BD16 FDI_TXN2
5 DMI_RXN1 DMI1RXN FDI_RXN2 FDI_TXN2 5
AW20 BJ16 FDI_TXN3
5 DMI_RXN2 DMI2RXN FDI_RXN3 FDI_TXN3 5
B 5 DMI_RXN3 BJ20 BA16 FDI_TXN4 B
DMI3RXN FDI_RXN4 FDI_TXN5 FDI_TXN4 5
FDI_RXN5 BE14 FDI_TXN5 5
BD24 BA14 FDI_TXN6
5 DMI_RXP0 DMI0RXP FDI_RXN6 FDI_TXN6 5
BG22 BC12 FDI_TXN7
5 DMI_RXP1 DMI1RXP FDI_RXN7 FDI_TXN7 5
5 DMI_RXP2 BA20 DMI2RXP
BG20 BB18 FDI_TXP0
+V1.1S 5 DMI_RXP3 DMI3RXP FDI_RXP0 FDI_TXP0 5
BF17 FDI_TXP1
FDI_RXP1 FDI_TXP2 FDI_TXP1 5
BE22 DMI0TXN FDI_RXP2 BC16 FDI_TXP2 5
5 DMI_TXN0 FDI_TXP3
BF21 DMI1TXN FDI_RXP3 BG16 FDI_TXP3 5
5 DMI_TXN1 FDI_TXP4
BD20 DMI2TXN FDI_RXP4 AW16
5 DMI_TXN2 FDI_TXP5 FDI_TXP4 5
BE18 DMI3TXN FDI_RXP5 BD14 FDI_TXP5 5
R133 5 DMI_TXN3 FDI_TXP6
FDI_RXP6 BB14 FDI_TXP6 5
BD22 BD12 FDI_TXP7
49.9,1% 5 DMI_TXP0 DMI0TXP FDI_RXP7 FDI_TXP7 5
BH21 DMI1TXP
5 DMI_TXP1
BC20 DMI2TXP
5 DMI_TXP2 FDI_INT
BD18 DMI3TXP FDI_INT BJ14
5 DMI_TXP3 FDI_INT 5
DMI
FDI

BF13 FDI_FSYNC0
FDI_FSYNC0 FDI_FSYNC0 5 +V3.3AUX
BH25 DMI_ZCOMP
BH13 FDI_FSYNC1
DMI_COMP_R FDI_FSYNC1 FDI_FSYNC1 5
BF25 DMI_IRCOMP FDI_LSYNC0 +V3.3S SUS_PWR_ACK R134 10K
FDI_LSYNC0 BJ12
FDI_LSYNC0 5
BG14 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 5 AC_PRESENT R135 10K
PM_CLKRUN_L R136 8.2K
+V3.3S PM_RI_L R137 10K

PM_RSMRST_PCHL R138 100K PM_BATLOW# R139 8.2K


PM_PCH_PWROK R1151 1K PM_SYSRST_L T6 J12
SYS_RESET# WAKE# PCIE_WAKE# 21,22,24
PCIE_WAKE# R140 1K
SYS_PWROK M6 Y1 PM_CLKRUN_L R322 0 R0402_0
SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# 27
R141
10K PM_SLP_LAN_L R142 10K ns
PM_PCH_PWROK
System Power Management

B17 PWROK
MAIN_PWROKR465 0 ns PM_SYSRST_L R143 10K ns
PM_MPWROKR144 0 MPWROK_R K5 P8 SUS_STAT# 19
MEPWROK SUS_STAT# / GPIO61
PWR_BTN# R145 10K
AUXPWROK_R R146 AUXPWROK_R A10 F3 TP_SUS_CLK TP16
0 ns LAN_RST# SUSCLK / GPIO62

D9 E4 PM_SLP_S5_L TP61
5 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 +V3.3S

R147 27,28,32,36 PM_RSMRST# R233 0 PM_RSMRST_PCHL C16 H7 PM_SLP_S4_L R230 0 R0402_0 SLP_S4# 22,27,28,29
RSMRST# SLP_S4#
10K
LAN DISABLE
A R304 0 ns SUS_PWR_ACK M1 P12 PM_SLP_S3_L R232 0 R0402_0 SLP_S3# 22,27,28,36 A
27 SUS_PWR_ACK_EC SUS_PWR_DN_ACK / GPIO30 SLP_S3#

27 PWR_BTN# P5 K8 PM_SLP_M_L R305 0 SLP_S3# C406


PWRBTN# SLP_M# 0.1uF/16V,X7R
5

27,42 AC_PRESENT_EC R231 0 ns AC_PRESENT P7 N2 TP_PM_SLP_DSWL TP18 SYS_PWROK R466 0 R0402_0


ACPRESENT / GPIO31 TP23 VCC 1 MAIN_PWROK 27,36
EC OD output PM_PCH_PWROK R467 0 R0402_0 4
27 PM_BATLOW#
must be high to startup
PM_BATLOW# A6 BATLOW# / GPIO72 PMSYNCH BJ10 H_PM_SYNC
H_PM_SYNC 5
PM_MPWROK GND
2

U32
IMVP_OK 19,27,28,38
CZC Technology
3

PM_RI_L F14 RI# SLP_LAN# / GPIO29 F6 PM_SLP_LAN_L SOT23_5


SN74AHC1G08DBV
zw
Title
IbexPeak-M_Rev1_5 If integrated Intel LAN is not supported on the platform,
GPIO29 must be left as No Connect. In addition,
this GPIO29 can not be used for any other purposes.
Panel &VGA connect
Size Project Name Rev

A3 R48 C
Date:
Thursday, April 22, 2010 Sheet
14 of
56
5 4 3 2 1
5 4 3 2 1

U3D
L_BKLT_EN T48 BJ46
19 L_BKLT_EN LVDS_VDD_EN L_BKLTEN SDVO_TVCLKINN
T47 L_VDD_EN SDVO_TVCLKINP BG46 HW Strap Purpose PCH PIn
19 LVDS_VDD_EN
L_BKLT_CTRL Y48 BJ48
19 L_BKLT_CTRL L_BKLTCTL SDVO_STALLN
SDVO_STALLP BG48 No Reboot SPKR
LVDS_DDC_CLK AB48 RSVD GPIO[34]
19 LVDS_DDC_CLK LVDS_DDC_DATA L_DDC_CLK A16 swap override GNT[3]#/ GPIO[55]
Y45 L_DDC_DATA SDVO_INTN BF45
19 LVDS_DDC_DATA Integrated VRM Enable/Disable INTVRMEN
SDVO_INTP BH45
L_CTRL_CLK Boot BIOS Strap bit [1] BBS[1] GNT[1]#/ GPIO[51]
AB46 L_CTRL_CLK
L_CTRL_DATA Boot BIOS Strap bit[0] BBS[0] GNT[0]#
V48 L_CTRL_DATA ESI Strap (Server only) GNT[2]#/ GPIO[53] PCH_GPIO53
LVDS_IBG Intel Anti-Theft Technology Enable NV_ALE
AP39 LVD_IBG SDVO_CTRLCLK T51 Flash Descriptor Security Override GPIO33/DOCK_EN#
TP19 TP_LVDS_VBG AP41 T53 NO_STUFF
LVD_VBG SDVO_CTRLDATA TPM Functionality Disable SPI_MOSI
DMI Termination Voltage NV_CLE
Place near PCH R148 AT43 ESI Strap (Server only) R149
LVD_VREFH RSVD HDA_SDO
2.37K,1% AT42 LVD_VREFL DDPB_AUXN BG44 RSVD GPIO[8] 1K
BJ44 RSVD GPIO[27] PCH_GPIO53 Low = Enabled ns
DDPB_AUXP
DDPB_HPD AU38 RSVD HDA_SYNC
19 LVDSA_CLK_L LVDSA_CLK_L AV53 RSVD GPIO[15] High = Disabled

LVDS
LVDSA_CLK#
19 LVDSA_CLK AV51 BD42
LVDSA_CLK DDPB_0N
D
DDPB_0P BC42 D
19 LVDSA_DATA0_L BB47 BJ42
LVDSA_DATA#0 DDPB_1N
19 LVDSA_DATA1_L BA52 BG42
LVDSA_DATA#1 DDPB_1P

Digital Display Interface


19 LVDSA_DATA2_L AY48 BB40
LVDSA_DATA#2 DDPB_2N
AV47 LVDSA_DATA#3 DDPB_2P BA40
DDPB_3N AW38
19 LVDSA_DATA0 LVDSA_DATA0 +V1.8S
BB48 LVDSA_DATA0 DDPB_3P BA38
19 LVDSA_DATA1 LVDSA_DATA1 BA50
LVDSA_DATA2 LVDSA_DATA1
19 LVDSA_DATA2 AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49 DMI Termination Voltage NO_STUFF
DDPC_CTRLDATA AB49
R150 PCI_GNT_L3
19 LVDSB_CLK_L AP48 Set to Vcc when LOW 1K
LVDSB_CLK# ns
19 LVDSB_CLK AP47 BE44 NV_CLE
LVDSB_CLK DDPC_AUXN
DDPC_AUXP BD44 Set to Vcc/2 when HIGH NO_STUFF
19 LVDSB_DATA0_L AY53 AV40
LVDSB_DATA#0 DDPC_HPD R151
19 LVDSB_DATA1_L AT49 LVDSB_DATA#1 NV_CLE
19 LVDSB_DATA2_L AU52 BE40 A16 swap override Strap/Top-Block 1K
LVDSB_DATA#2 DDPC_0N ns
AT53 LVDSB_DATA#3 DDPC_0P BD40 Swap Override jumper
DDPC_1N BF41
19 LVDSB_DATA0 LVDSB_DATA0 AY51 BH41 PCI_GNT#3 Low = A16 swap
LVDSB_DATA1 LVDSB_DATA0 DDPC_1P +V1.8S override/Top-Block
19 LVDSB_DATA1 AT48 BD38
LVDSB_DATA2 LVDSB_DATA1 DDPC_2N Swap Override enabled
19 LVDSB_DATA2 AU50 BC38
LVDSB_DATA2 DDPC_2P High = Default
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36 NO_STUFF
Intel Anti-Theft Technology Enable
R152
R310 0 AA52 U50 DPD_CTRLCK 10K
20 CRT_BLUE CRT_BLUE DDPD_CTRLCLK DPD_CTRLCK 18
R311 0 AB53 U52 DPD_CTRLDAT ns
20 CRT_GREEN CRT_GREEN DDPD_CTRLDATA DPD_CTRLDAT 18
R312 0 AD53 NV_ALE High = Enabled Stuff PU
20 CRT_RED CRT_RED Low = Disabled Unstuff PU (Default)
DDPD_AUXN BC46
CRT_DDC_CLK V51 BD46
20 CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA V53 AT38 DPD_HPD_PCH
20 CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD NV_ALE
DDPD_0N BJ40 DPD_LANE0_N 18
R153 0 HSYNC Y53 BG40
20 CRT_HSYNC CRT_HSYNC DDPD_0P DPD_LANE0_P 18
R154 0 VSYNC Y51 BJ38
20 CRT_VSYNC CRT_VSYNC DDPD_1N DPD_LANE1_N 18
DDPD_1P BG38 DPD_LANE1_P 18
BF37

CRT
DDPD_2N DPD_LANE2_N 18
DAC_IREF_R AD48 BH37
DAC_IREF DDPD_2P DPD_LANE2_P 18
AB51 CRT_IRTN DDPD_3N BE36 DPD_LANE3_N 18
R155 BD36
DDPD_3P DPD_LANE3_P 18
1K,1%
IbexPeak-M_Rev1_5
U3E
LO note: Place near PCH H40 AD0 NV_CE#0 AY9
N34 AD1 NV_CE#1 BD1
C44 AD2 NV_CE#2 AP15
A38 AD3 NV_CE#3 BD8
C36 AD4
J34 AD5 NV_DQS0 AV9
C +V5S C
A40 AD6 NV_DQS1 BG8
D45 AD7
E36 AD8 NV_DQ0 / NV_IO0 AP7
H48 AD9 NV_DQ1 / NV_IO1 AP6
E40 AD10 NV_DQ2 / NV_IO2 AT6
C40 AD11 NV_DQ3 / NV_IO3 AT9

1
M48 AD12 NV_DQ4 / NV_IO4 BB1
M45 AD13 NV_DQ5 / NV_IO5 AV6
F53 AD14 NV_DQ6 / NV_IO6 BB3
DPD_HPD_PCH 2 3 R317 0 M40 BA4
UMA DPD_HPD 18 AD15 NV_DQ7 / NV_IO7
M43 AD16 NV_DQ8 / NV_IO8 BE4

NVRAM
J36 AD17 NV_DQ9 / NV_IO9 BB6
R174 K48 BD6
+V3.3S Q154 AD18 NV_DQ10 / NV_IO10
100K F40 AD19 NV_DQ11 / NV_IO11 BB7
2N7002K C42 BC8
R468 2.2K CRT_DDC_CLK UMA UMA AD20 NV_DQ12 / NV_IO12
K46 AD21 NV_DQ13 / NV_IO13 BJ8
M51 AD22 NV_DQ14 / NV_IO14 BJ6
R469 2.2K CRT_DDC_DATA J52 BG6
AD23 NV_DQ15 / NV_IO15
K51 AD24
R292 2.2K LVDS_DDC_CLK L34 BD3 NV_ALE
AD25 NV_ALE NV_CLE
F42 AD26 NV_CLE AY6
R293 2.2K LVDS_DDC_DATA J40 AD27
G46 AD28
R156 10K L_CTRL_CLK F44 AU2 NV_RCOMP
AD29 NV_RCOMP
M47 AD30
R157 10K L_CTRL_DATA H36 AV7
AD31 NV_RB#

PCI
CRT_BLUE R158 150,1%
J50 AY8 R159
C/BE0# NV_WR#0_RE#
G42 C/BE1# NV_WR#1_RE# AY5 32.4,1%
H47 ns
CRT_GREEN R160 150,1% +V3.3S C/BE2#
G34 C/BE3# NV_WE#_CK0 AV11
NV_WE#_CK1 BF5
INT_PIRQA_L G38
INT_PIRQB_L H51 PIRQA#
CRT_RED R162 150,1% INT_PIRQC_L B37 PIRQB# USB_PN0
PIRQC# USBP0N H18 USB_PN0 21
R1040 INT_PIRQD_L A44 J18 USB_PP0
PIRQD# USBP0P USB_PP0 21
10K A18 USB_PN1
UMA PCI_REQ_L0 F51
USBP1N
C18 USB_PP1
USB_PN1 21 to rear IO
REQ0# USBP1P USB_PP1 21
L_BKLT_EN R163 100K PCI_REQ_L1 A46 N20 USB_PN2
REQ1# / GPIO50 USBP2N USB_PN2 22
R234 0 PCI_REQ_L2 B45 P20 USB_PP2
18 DGPU_SELECT# REQ2# / GPIO52 USBP2P USB_PP2 22
ns PCI_REQ_L3 M53 J20 USB_PN3
REQ3# / GPIO54 USBP3N USB_PN3 26
L20 USB_PP3
USBP3P USB_PP3 26
PCI_GNT_L0 F48 F20 USB_PN4
Place the 3 resistors close to PCH R1041 PCI_GNT_L1 K45
GNT0# USBP4N
G20 USB_PP4
USB_PN4 29 to PIN header
GNT1# / GPIO51 USBP4P USB_PP4 29
10K PCH_GPIO53 F36 A20 USB_PN5
DGPU_PWM_SELECT# GNT2# / GPIO53 USBP5N USB_PN5 19
DGPU PCI_GNT_L3 H53 C20 USB_PP5
GNT3# / GPIO55 USBP5P USB_PP5 19
USBP6N M22
TP34 INT_PIRQE_L B41 N22
INT_PIRQF_L PIRQE# / GPIO2 USBP6P
K53 PIRQF# / GPIO3 USBP7N B21 HM55 No function.
INT_PIRQG_L A36 D21
INT_PIRQH_L PIRQG# / GPIO4 USBP7P USB_PN8
A48 PIRQH# / GPIO5 USBP8N H22 USB_PN8 29
J22 USB_PP8
PCIRST_L K6
USBP8P
E22
USB_PP8 29 to rear IO
TP20

USB
B PCIRST# USBP9N USB_PN9 28 B
USBP9P F22 USB_PP9 28
PCI_SERR_L E44 A22
SERR# USBP10N USB_PN10 28
PCI_PERR_L E50 C22
PERR# USBP10P USB_PP10 28
USBP11N G24 USB_PN11 24
USBP11P H24 USB_PP11 24
PCI_IRDY_L A42 L24 USB_PN6
IRDY# USBP12N USB_PN6 22
H44 M24 USB_PP6
PAR USBP12P USB_PP6 22
PCI_DEVSEL_L F46 A24 USB_PN7
DEVSEL# USBP13N USB_PN7 22
PCI_FRAME_L C46 C24 USB_PP7
FRAME# USBP13P USB_PP7 22
PCI_LOCK_L D49 PLOCK# USB_BIAS
USBRBIAS# B25
PCI_STOP_L D41
PCI_TRDY_L STOP# R166 +V3.3AUX
C48 TRDY# USBRBIAS D25
22.6,1%
M7 PME#
N16 USB_OC_L0
PLT_RST_L OC0# / GPIO59 USB_OC_L1
21,22,24 PLT_RST_L D5 PLTRST# OC1# / GPIO40 J16
F16 USB_OC_L2 USB_OC_L6 R167 10K
R168 47 CLKOUT_PCI0 OC2# / GPIO41 USB_OC_L3 USB_OC_L5 R169 10K
27 CLK_LPC_KBC N52 CLKOUT_PCI0 OC3# / GPIO42 L16 USB_OC_L3 22
CLK_PCI_FB R170 22 CLKOUT_PCI1 P53 E14 USB_OC_L4 USB_OC_L7 R301 10K
14 CLK_PCI_FB CLKOUT_PCI1 OC4# / GPIO43 USB_OC_L5 USB_OC_L4 29 USB_OC_L0 R178 10K
P46 CLKOUT_PCI2 OC5# / GPIO9 G16
CLK_PCIF_PORT80 R171 47 CLKOUT_PCI3 P51 F12 USB_OC_L6 USB_OC_L2 R172 10K
21 CLK_PCIF_PORT80 CLKOUT_PCI3 OC6# / GPIO10 USB_OC_L7 USB_OC_L1 R303 10K
P48 CLKOUT_PCI4 OC7# / GPIO14 T15
USB_OC_L3 R249 10K
C179 C180 C181 USB_OC_L4 R309 10K
10pF/50V,NPO 10pF/50V,NPO IbexPeak-M_Rev1_5
NO_STUFF ns 10pF/50V,NPO ns
ns

PCI_GNT_L0
+V3.3S PCI_GNT_L1
+V3.3S

PCI_IRDY_L RN1 1 28.2K


INT_PIRQD_L 3 4 Boot BIOS Strap R175 R176
PCI_REQ_L2 5 6 C182 PCI_GNT_L0 PCI_GNT_L1 Boot BIOS Location 1K 1K
+V5S 14,16,17,18,19,20,21,23,25,26,28,29,35,36,37,38
PCI_REQ_L1 7 8 0.1uF/16V,X7R 0 0 LPC ns ns
+V1.8S 7,16,28,34,36
PCI_SERR_L RN2 1 28.2K 0 1 Reserved NO_STUFF
+V3.3S 5,9,10,11,12,13,14,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48

5
PCI_DEVSEL_L 3 4 R715 0 1 0 PCI
+V3.3AUX 5,13,14,16,17,19,21,22,24,25,27,28,29,30,31,32,34,35 21,27 LPC_RST#
PCI_LOCK_L 5 6 VCC 1 PLT_RST_L 1 1 SPI
+V5AUX 17,19,22,24,27,28,29,32,33,34,35,36
PCI_PERR_L 7 8 4
5,41 BUF_PLT_RST_L
PCI_REQ_L0 RN3 1 28.2K 2
INT_PIRQB_L GND
3 4
INT_PIRQF_L 5 6 U4

3
PCI_REQ_L3 7 8 R177 SOT23_5
100KSN74AHC1G08DBV
INT_PIRQA_L RN4 1 28.2K
A PCI_FRAME_L 3 4 A
PCI_TRDY_L 5 6
INT_PIRQH_L 7 8
INT_PIRQG_L
INT_PIRQC_L
RN5 1
3
28.2K
4
Buffer to reduce loading on PLT_RST#.
INT_PIRQE_L 5 6
PCI_STOP_L 7 8

CZC Technology zw
Title

Panel &VGA connect


Size Project Name Rev

A3 R48 C
Date:
Thursday, April 22, 2010 Sheet
15 of
56
5 4 3 2 1
5 4 3 2 1
U3F

PCH_GPIO0 Y3 AH45 TP_CLKOUT_SRC6N TP21


BMBUSY# / GPIO0 CLKOUT_PCIE6N +V1.1S 7,13,14,17,34,35,36
CLKOUT_PCIE6P AH46 TP_CLKOUT_SRC6P TP22 +V1.8S 7,15,28,34,36
LPC_SMI# C38
27 LPC_SMI# TACH1 / GPIO1 +V3.3AUX +V3.3S 5,9,10,11,12,13,14,15,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48
+V3.3AUX 5,13,14,15,17,19,21,22,24,25,27,28,29,30,31,32,34,35
TP56 DGPU_HPD_INTR_L D37 TACH2 / GPIO6 +V5AUX 17,19,22,24,27,28,29,32,33,34,35,36
CLKOUT_PCIE7N AF48
SCI# J32 AF47 PM_LANPHY_ENABLE
R371 10K ns

MISC
27 SCI# TACH3 / GPIO7 CLKOUT_PCIE7P +V1.5S_1.8S 17
+V1.1S_VTT 5,7,12,17,35,36
HOST_ALERT_L2 F10 GPIO8 HOST_ALERT_L1 R179 1K
+V1.5S 7,21,22,28,35,36
PM_LANPHY_ENABLE K9 U2
LAN_PHY_PWR_CTRL / GPIO12 A20GATE A20M# 27 +V5S 14,15,17,18,19,20,21,23,25,26,28,29,35,36,37,38
HOST_ALERT_L1 T7 HOST_ALERT_L2 R180 10K
GPIO15
+V3.3AUX VDDR3 36,41,42,43,45,48
AA2 CK_BCK0_N R181 0 R0402_0 CLK_MCP_BCLK_L
41 DGPU_HOLD_RST# SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 CLK_MCP_BCLK_L 5,12 SPI_CS_L2 R182 10K
DGPU_PWROK F38 CK_BCK0_P R183 0 R0402_0 CLK_MCP_BCLK
14 DGPU_PWROK TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_MCP_BCLK 5,12 +V1.1S_VTT GPIO57 R184 10K
36,42 MADISON_POWOK R302 0 BIOS_REC Y7 BG10 H_PECI_R R186 0 R0402_0
SCLOCK / GPIO22 PECI H_PECI 5
R185 DGPU

GPIO
10K TP57 TP_GPIO24 H10 T1 H_RCIN_L
ns GPIO24 RCIN# KB_RST# 27 R187
GPIO27 +V3.3S
AB12 GPIO27 PROCPWRGD BE10
H_CPUPWRGD 5 56
D NO_STUFF D

CPU
SPI_CS_L2 V13 BD10 PCH_THRMTRIPL_R 54.9K,1% R189
R188 GPIO28 THRMTRIP# H_THRMTRIP_L 5 H_RCIN_L R190 10K
10K M11 STP_PCI# / GPIO34
ns 12 PCI_STOP#
GPIO35 V6
+V3.3AUX GPIO35 DGPU_PWR_EN# R191 1K
DGPU_PWR_EN# AB7 BA22 TP52
SATA2GP / GPIO36 TP1 DGPU_HPD_INTR_L R192 10K
DGPU_PRSNT# AB13 AW22 TP65
SATA3GP / GPIO37 TP2 DGPU_PRSNT# R194 10K
R193 R195 MFG_MODE V3 BB22
SLOAD / GPIO38 TP3 GPIO35 R196 10K
10K 10K
CRB_SV_DET P3 AY45
SDATAOUT0 / GPIO39 TP4 DGPU_HOLD_RST# R197 10K
PCH_GPIO45 H3 AY46
PCIECLKRQ6# / GPIO45 TP5 PCH_GPIO0 R198 10K
F1 PCIECLKRQ7# / GPIO46 TP6 AV43
5 DRAMRST_CNTRL_PCH MFG_MODE R199 10K
SV_SET_UP AB6 AV45
SDATAOUT1 / GPIO48 TP7 SV_SET_UP R200 10K
GPIO49 AA4 AF13
SATA5GP / GPIO49 / TEMP_ALERT# TP8 LPC_SMI# R201 10K
GPIO57 F8 M18
GPIO57 TP9 SCI# R202 10K
PLL On DIE VR Enable R156 TP10 N18
GPIO49 R203 10K
A4 VSS_NCTF_1 TP11 AJ24
GPIO27 Stuff : Disable PLL On DIE A49 VSS_NCTF_2

NCTF
No Stuff : Enable PLL On DIE PCI_STOP# R58 10K

RSVD
A5 VSS_NCTF_3 TP12 AK41
A50 VSS_NCTF_4
A52 AK42 TP13_PCH
VSS_NCTF_5 TP13
A53 VSS_NCTF_6 NO_STUFF
B2 VSS_NCTF_7 TP14 M32
B4 R205
VSS_NCTF_8
B52 VSS_NCTF_9 TP15 N32 3.01K,1%
B53 ns
VSS_NCTF_10 DGPU_PWROK R204 100K ns
BE1 VSS_NCTF_11 TP16 M30
BE53 VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
BF53 VSS_NCTF_14
BH1 VSS_NCTF_15 TP18 H12
BH2 VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23
BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
BJ49 VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
BJ52 VSS_NCTF_25 NC_4 AB41
BJ53
C D1
VSS_NCTF_26
T39
C
VSS_NCTF_27 NC_5
D2 VSS_NCTF_28
D53 VSS_NCTF_29
E1 P6 INIT3_3V_L TP68
VSS_NCTF_30 INIT3_3V#
E53 VSS_NCTF_31
C10 TP_PCH_SST TP67
TP24
IbexPeak-M_Rev1_5
+V1.1S +V3.3S_LDO

+V1.1S_PCH_VCC
U3G POWER +VCCA_DAC_1_2
FB2
AB24 VCCCORE[1] VCCADAC[1] AE50
AB26 VCCCORE[2]
AB28 VCCCORE[3] VCCADAC[2] AE52 300ohm/100MHz,1A
AD26 C184 C185
C183 VCCCORE[4]
AD28 AF53 0.01uF/25V,X7R 0.1uF/16V,X7R

CRT
VCCCORE[5] VSSA_DAC[1]
0.1uF/16V,X7R AF26 VCCCORE[6]
AF28 AF51

VCC CORE
VCCCORE[7] VSSA_DAC[2]
AF30 VCCCORE[8]
AF31 VCCCORE[9]
AH26 VCCCORE[10] +V3.3S
AH28 VCCCORE[11]
AH30 VCCCORE[12]
AH31 AH38 R206 0
VCCCORE[13] VCCALVDS R0603
AJ30 VCCCORE[14]
AJ31 AH39 R208 0
VDDR3 VCCCORE[15] VSSA_LVDS ns +V1.8S
+V3.3S +V1.1S
NO_STUFF
L1
AP43 VCCTX_LVD_J
VCCTX_LVDS[1]
VCCTX_LVDS[2] AP45 0.1uH/300mA
VCCTX_LVDS[3] AT46 NO_STUFF

LVDS
AK24 AT45 C186 C187 C188 R209
R207 VCCIO[24] VCCTX_LVDS[4] +V3.3S
0.01uF/25V,X7R 0.01uF/25V,X7R 22uF/6.3V,X5R 0
R1005 10K L2
10K +V1.1S_VCCAPLL_EXP_R1 +V1.1S_VCCAPLL_EXP BJ24 ns
R1072 1K DGPU BIOS_REC VCCAPLLEXP
48 DGPU_PWR_EN#_VDDR3 10uH/500mAns VCC3_3[2] AB34

ns NO_STUFF C189 AN20 AB35


VCCIO[25] VCC3_3[3] C190
VDDC_VR_EN 35,36 10uF/10V X5R AN22 VCCIO[26]
R235 ns

HVCMOS
AN23 VCCIO[27] VCC3_3[4] AD35 1uF/10V,X5R
3

10K 7,13,14,17,34,35,36 +V1.1S_VCC_EXP AN24


Q169 ns VCCIO[28]
JCRV - BIOS RECOVERY AN26 VCCIO[29]
2N7002K DISABLE -- (1- X) DEFAULT AN28
DGPU_PWR_EN# R338 0 SOT23 VCCIO[30]
1 ENABLE -- (1-2) BJ26 VCCIO[31]
ns ns BJ28 VCCIO[32]
AT26 VCCIO[33]
2

C191 C192 C193 C194 C195 AT28


R1006 VCCIO[34]
10uF/10V X5R 0.1uF/16V,X7R 0.1uF/16V,X7R 0.1uF/16V,X7R 0.1uF/16V,X7R AU26 VCCIO[35]
100K +V1.5S_1.8S R210
AU28 VCCIO[36]
ns AV26 20K,1%
VCCIO[37] R0402
AV28 VCCIO[38] VCCVRM[2] AT24
AW26 VCCIO[39]
AW28 U5
B VCCIO[40] +V1.1S_VTT +V5S APL5315BI-TRL B
BA26 AT16

DMI
VCCIO[41] VCCDMI[1] SOT23_5 R212
BA28 VCCIO[42]
BB26 AU16 63.4K,1%
+V3.3S
BB28
VCCIO[43] VCCDMI[2]
1 5
61.9k,1% ---63.4k
+V3.3S VCCIO[44] EN SET +V3.3S_LDO
BC26 VCCIO[45]
R211 100K 0.8V
BC28 C196 2 R0402

PCI E*
VCCIO[46] GND
BD26 VCCIO[47] 1uF/10V,X5R
BD28 VCCIO[48] 3 VIN VOUT 4
CRB_SV_DET R213 10K ns +V1.8S
BE26 VCCIO[49] VCCPNAND[1] AM16
BE28 VCCIO[50] VCCPNAND[2] AK16
NO_STUFF BG26 VCCIO[51] VCCPNAND[3] AK20
C197 BG28 AK19 C198
+V1.1S VCCIO[52] VCCPNAND[4] C0402 C199 C200
0.1uF/16V,X7R BH27 VCCIO[53] VCCPNAND[5] AK15
R214 AK13 1uF/10V,X5R 22uF/6.3V,X5R 0.1uF/16V,X7R
L3 VCCPNAND[6]
100K AN30 VCCIO[54] VCCPNAND[7] AM12
AN31 AM13

NAND / SPI
+V1.5S_1.8S VCCIO[55] VCCPNAND[8]
10uH/500mAns VCCPNAND[9] AM15

AN35 VCC3_3[1]
NO_STUFF C201 C202
10uF/10V X5R 1uF/10V,X5R
ns AT22 VCCVRM[1]
+V1.1S +V1.1S_VCCAPLL_FDI +V3.3S
BJ18 VCCFDIPLL VCCME3_3[1] AM8
VCCME3_3[2] AM9
AM23 AP11

FDI
VCCIO[1] VCCME3_3[3]
VCCME3_3[4] AP9

IbexPeak-M_Rev1_5 C203
1uF/10V,X5R

+V1.1S

R215 0 ns
R0805
NO_STUFF
A +V1.5S
A

+V1.5S_1.8S
NO_STUFF
R216 0 ns
R0805
+V1.8S

R217 0
R0805
CZC Technology zw
Title

Panel &VGA connect


Size Project Name Rev

A3 R48 C
Date:
Thursday, April 22, 2010 Sheet
16 of
56
5 4 3 2 1
5 4 3 2 1
+V1.1S L4
ns +V1.1S_VCCA_CLK
10uH/500mA
U3J POWER +V1.1S

NO_STUFF C204 C205 AP51 V24 +V1.1S_VCCUSBCORE


VCCACLK[1] VCCIO[5]
10uF/10V X5R 1uF/10V,X5R VCCIO[6] V26
ns ns C207 U3I
AP53 VCCACLK[2] VCCIO[7] Y24
+V1.1S +V3.3AUX U3H
VCCIO[8] Y26 1uF/10V,X5R AY7 VSS[159] VSS[259] H49
AB16 VSS[0] B11 VSS[160] VSS[260] H5
AF23 VCCLAN[1] VCCSUS3_3[1] V28 B15 VSS[161] VSS[261] J24
VCCSUS3_3[2] U28 AA19 VSS[1] VSS[80] AK30 B19 VSS[162] VSS[262] K11
AF24 VCCLAN[2] VCCSUS3_3[3] U26 AA20 VSS[2] VSS[81] AK31 B23 VSS[163] VSS[263] K43
C206 U24 C208 C209 AA22 AK32 B31 K47
VCCSUS3_3[4] VSS[3] VSS[82] VSS[164] VSS[264]
0.1uF/16V,X7R VCCSUS3_3[5] P28 0.022uF/16V,X7R 0.1uF/16V,X7R AM19 VSS[4] VSS[83] AK34 B35 VSS[165] VSS[265] K7
C248 0.1uF/16V,X7R TP_PCH_DSW Y20 P26 AA24 AK35 B39 L14
+V1.1S DCPSUSBYP VCCSUS3_3[6] VSS[5] VSS[84] VSS[166] VSS[266]
VCCSUS3_3[7] N28 AA26 VSS[6] VSS[85] AK38 B43 VSS[167] VSS[267] L18
VCCSUS3_3[8] N26 AA28 VSS[7] VSS[86] AK43 B47 VSS[168] VSS[268] L2
AD38 VCCME[1] VCCSUS3_3[9] M28 AA30 VSS[8] VSS[87] AK46 B7 VSS[169] VSS[269] L22
VCCSUS3_3[10] M26 AA31 VSS[9] VSS[88] AK49 BG12 VSS[170] VSS[270] L32
AD39 VCCME[2] VCCSUS3_3[11] L28 AA32 VSS[10] VSS[89] AK5 BB12 VSS[171] VSS[271] L36
C210

USB
VCCSUS3_3[12] L26 AB11 VSS[11] VSS[90] AK8 BB16 VSS[172] VSS[272] L40
0.1uF/16V,X7R AD41 VCCME[3] VCCSUS3_3[13] J28 AB15 VSS[12] VSS[91] AL2 BB20 VSS[173] VSS[273] L52
VCCSUS3_3[14] J26 AB23 VSS[13] VSS[92] AL52 BB24 VSS[174] VSS[274] M12
+V3.3AUX
AF43 VCCME[4] VCCSUS3_3[15] H28 AB30 VSS[14] VSS[93] AM11 BB30 VSS[175] VSS[275] M16
VCCSUS3_3[16] H26 AB31 VSS[15] VSS[94] BB44 BB34 VSS[176] VSS[276] M20
D AF41 VCCME[5] VCCSUS3_3[17] G28
+V3.3S
AB32 VSS[16] VSS[95] AD24 BB38 VSS[177] VSS[277] N38 D
VCCSUS3_3[18] G26 AB39 VSS[17] VSS[96] AM20 BB42 VSS[178] VSS[278] M34
AF42 VCCME[6] VCCSUS3_3[19] F28 AB43 VSS[18] VSS[97] AM22 BB49 VSS[179] VSS[279] M38
VCCSUS3_3[20] F26 AB47 VSS[19] VSS[98] AM24 BB5 VSS[180] VSS[280] M42
V39 VCCME[7] VCCSUS3_3[21] E28 AB5 VSS[20] VSS[99] AM26 BC10 VSS[181] VSS[281] M46
+V3.3AUX
VCCSUS3_3[22] E26 AB8 VSS[21] VSS[100] AM28 BC14 VSS[182] VSS[282] M49

Clock and Miscellaneous


V41 VCCME[8] VCCSUS3_3[23] C28 AC2 VSS[22] VSS[101] BA42 BC18 VSS[183] VSS[283] M5
VCCSUS3_3[24] C26 AC52 VSS[23] VSS[102] AM30 BC2 VSS[184] VSS[284] M8

2
V42 VCCME[9] VCCSUS3_3[25] B27 AD11 VSS[24] VSS[103] AM31 BC22 VSS[185] VSS[285] N24
A28 D2 AD12 AM32 BC32 P11
VCCSUS3_3[26] VSS[25] VSS[104] VSS[186] VSS[286]

2
Y39 VCCME[10] VCCSUS3_3[27] A26 BAT54C AD16 VSS[26] VSS[105] AM34 BC36 VSS[187] VSS[287] AD15
C211 D3 AD23 AM35 BC40 P22
+V1.1S +V1.1S VSS[27] VSS[106] VSS[188] VSS[288]
Y41 VCCME[11] VCCSUS3_3[28] U23 0.1uF/16V,X7R BAT54C AD30 VSS[28] VSS[107] AM38 BC44 VSS[189] VSS[289] P30

3
+V5AUX
AD31 VSS[29] VSS[108] AM39 BC52 VSS[190] VSS[290] P32
Y42 VCCME[12] VCCIO[56] V23 AD32 VSS[30] VSS[109] AM42 BH9 VSS[191] VSS[291] P34

3
R218 AD34 AU20 BD48 P42
+V5A_PCH_VCC5REFSUS VSS[31] VSS[110] VSS[192] VSS[292]
V5REF_SUS F24 AU22 VSS[32] VSS[111] AM46 BD49 VSS[193] VSS[293] P45
C212 +VCCRTCEXT +V5S
AD42 VSS[33] VSS[112] AV22 BD5 VSS[194] VSS[294] P47
0.1uF/16V,X7R V9 C213 10 AD46 AM49 BE12 R2
DCPRTC VSS[34] VSS[113] VSS[195] VSS[295]
1uF/10V,X5R AD49 VSS[35] VSS[114] AM7 BE16 VSS[196] VSS[296] R52
+V1.5S_1.8S C214 R219 AD7 VSS[36] VSS[115] AA50 BE20 VSS[197] VSS[297] T12
0.1uF/16V,X7R K49 +V5S_PCH_VCC5REF AE2 BB10 BE24 T41
V5REF VSS[37] VSS[116] VSS[198] VSS[298]
AU24 VCCVRM[3] AE4 VSS[38] VSS[117] AN32 BE30 VSS[199] VSS[299] T46
C215 10

PCI/GPIO/LPC
AF12 VSS[39] VSS[118] AN50 BE34 VSS[200] VSS[300] T49
VCC3_3[8] J38 1uF/10V,X5R Y13 VSS[40] VSS[119] AN52 BE38 VSS[201] VSS[301] T5
BB51 VCCADPLLA[1] AH49 VSS[41] VSS[120] AP12 BE42 VSS[202] VSS[302] T8
+V1.1S_VCCA_A_DPL BB53 L38 AU4 AP42 BE46 U30
VCCADPLLA[2] VCC3_3[9] +V3.3S VSS[42] VSS[121] VSS[203] VSS[303]
AF35 VSS[43] VSS[122] AP46 BE48 VSS[204] VSS[304] U31
+V1.1S
VCC3_3[10] M36 AP13 VSS[44] VSS[123] AP49 BE50 VSS[205] VSS[305] U32
+V1.1S_VCCA_B_DPL BD51 AN34 AP5 BE6 U34
VCCADPLLB[1] VSS[45] VSS[124] VSS[206] VSS[306]
BD53 VCCADPLLB[2] VCC3_3[11] N36 AF45 VSS[46] VSS[125] AP8 BE8 VSS[207] VSS[307] P38
C216 AF46 AR2 BF3 V11
VSS[47] VSS[126] VSS[208] VSS[308]
AH23 VCCIO[21] VCC3_3[12] P36 0.1uF/16V,X7R AF49 VSS[48] VSS[127] AR52 BF49 VSS[209] VSS[309] P16
AJ35 VCCIO[22] AF5 VSS[49] VSS[128] AT11 BF51 VSS[210] VSS[310] V19
C217 +V3.3S
AH35 VCCIO[23] VCC3_3[13] U35 AF8 VSS[50] VSS[129] BA12 BG18 VSS[211] VSS[311] V20
1uF/10V,X5R C218 AG2 AH48 BG24 V22
VSS[51] VSS[130] VSS[212] VSS[312]
0.1uF/16V,X7R AF34 VCCIO[2] AG52 VSS[52] VSS[131] AT32 BG4 VSS[213] VSS[313] V30
VCC3_3[14] AD13 AH11 VSS[53] VSS[132] AT36 BG50 VSS[214] VSS[314] V31
AH34 VCCIO[3] AH15 VSS[54] VSS[133] AT41 BH11 VSS[215] VSS[315] V32
C219 C220 +V1.1S
AH16 VSS[55] VSS[134] AT47 BH15 VSS[216] VSS[316] V34
1uF/10V,X5R AF32 0.1uF/16V,X7R L5 AH24 AT7 BH19 V35
VCCIO[4] +V1.1S_VCCAPLL_L ns +V1.1S_VCCAPLL VSS[56] VSS[135] VSS[217] VSS[317]
VCCSATAPLL[1] AK3 AH32 VSS[57] VSS[136] AV12 BH23 VSS[218] VSS[318] V38
+VCCSST V12 AK1 10uH/500mA AV18 AV16 BH31 V43
DCPSST VCCSATAPLL[2] C222 C223 VSS[58] VSS[137] VSS[219] VSS[319]
AH43 VSS[59] VSS[138] AV20 BH35 VSS[220] VSS[320] V45
C221 1uF/10V,X5R 10uF/10V X5R NO_STUFF AH47 AV24 BH39 V46
ns ns VSS[60] VSS[139] VSS[221] VSS[321]
0.1uF/16V,X7R AH7 VSS[61] VSS[140] AV30 BH43 VSS[222] VSS[322] V47
+V1.1A_INT_VCCSUS Y22 AJ19 AV34 BH47 V49
DCPSUS +V1.1S VSS[62] VSS[141] VSS[223] VSS[323]
VCCIO[9] AH22 AJ2 VSS[63] VSS[142] AV38 BH7 VSS[224] VSS[324] V5
+V1.5S_1.8S
AJ20 VSS[64] VSS[143] AV42 C12 VSS[225] VSS[325] V7
C224 +V1.1S_VCC_SATA AJ22 AV46 C50 V8
+V3.3AUX VSS[65] VSS[144] VSS[226] VSS[326]
0.1uF/16V,X7R P18 VCCSUS3_3[29] VCCVRM[4] AT20 AJ23 VSS[66] VSS[145] AV49 D51 VSS[227] VSS[327] W2
AJ26 VSS[67] VSS[146] AV5 E12 VSS[228] VSS[328] W52
U19 C225 AJ28 AV8 E16 Y11
C VCCSUS3_3[30]
AH19 AJ32
VSS[68] VSS[147]
AW14 E20
VSS[229] VSS[329]
Y12
C
SATA

1uF/10V,X5R
PCI/GPIO/LPC

VCCIO[10] VSS[69] VSS[148] VSS[230] VSS[330]


U20 VCCSUS3_3[31] AJ34 VSS[70] VSS[149] AW18 E24 VSS[231] VSS[331] Y15
VCCIO[11] AD20 AT5 VSS[71] VSS[150] AW2 E30 VSS[232] VSS[332] Y19
U22 VCCSUS3_3[32] AJ4 VSS[72] VSS[151] BF9 E34 VSS[233] VSS[333] Y23
VCCIO[12] AF22 AK12 VSS[73] VSS[152] AW32 E38 VSS[234] VSS[334] Y28
AM41 VSS[74] VSS[153] AW36 E42 VSS[235] VSS[335] Y30
+V3.3S
VCCIO[13] AD19 AN19 VSS[75] VSS[154] AW40 E46 VSS[236] VSS[336] Y31
V15 VCC3_3[5] VCCIO[14] AF20 AK26 VSS[76] VSS[155] AW52 E48 VSS[237] VSS[337] Y32
VCCIO[15] AF19 AK22 VSS[77] VSS[156] AY11 E6 VSS[238] VSS[338] Y38
+V3.3S_VCCPCORE V16 AH20 AK23 AY43 E8 Y43
VCC3_3[6] VCCIO[16] VSS[78] VSS[157] VSS[239] VSS[339]
AK28 VSS[79] VSS[158] AY47 F49 VSS[240] VSS[340] Y46
C226 Y16 AB19 F5 P49
VCC3_3[7] VCCIO[17] VSS[241] VSS[341]
0.1uF/16V,X7R VCCIO[18] AB20 G10 VSS[242] VSS[342] Y5
+V1.1S_VTT IbexPeak-M_Rev1_5
VCCIO[19] AB22 G14 VSS[243] VSS[343] Y6
VCCIO[20] AD22 G18 VSS[244] VSS[344] Y8
AT18 V_CPU_IO[1] G2 VSS[245] VSS[345] P24
VCCME[13] AA34 G22 VSS[246] VSS[346] T43
C229 +V1.1S
CPU

VCCME[14] Y34 G32 VSS[247] VSS[347] AD51


4.7uF/10V,X5R C227 C228 AU18 Y35 G36 AT8
V_CPU_IO[2] VCCME[15] +V3.3AUX VSS[248] VSS[348]
0.1uF/16V,X7R 0.1uF/16V,X7R VCCME[16] AA35 G40 VSS[249] VSS[349] AD47
+V3.3_RTC
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
A12 L30 AF39 AM6
RTC

VCCRTC VCCSUSHDA VSS[252] VSS[352]


H16 AT13
HDA

C231 C232 VSS[253] VSS[353]


H20 VSS[254] VSS[354] AM5
0.1uF/16V,X7R 0.1uF/16V,X7R IbexPeak-M_Rev1_5 C230 H30 AK45
VSS[255] VSS[355]
1uF/10V,X5R H34 VSS[256] VSS[356] AK39
H38 VSS[257] VSS[366] AV14
H42 VSS[258]
+V1.1S
L6
+V1.1S_VCCA_A_DPL
10uH/500mA
IbexPeak-M_Rev1_5

CT1 C234
22uF/6.3V,TAN 1uF/10V,X5R

L7
+V1.1S_VCCA_B_DPL
10uH/500mA
C1279 C233
220uF/6.3V,FPCAP + CT2 C236
+ CESD66 22uF/6.3V,TAN 1uF/10V,X5R
220uF/6.3V,POSCAP
ns ns
B B

+V5S 14,15,16,18,19,20,21,23,25,26,28,29,35,36,37,38
+V1.5S_1.8S 16
+V1.1S_VTT 5,7,12,16,35,36

+V1.1S 7,13,14,16,34,35,36
+V3.3_RTC 13
+V3.3S 5,9,10,11,12,13,14,15,16,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48
+V3.3AUX 5,13,14,15,16,19,21,22,24,25,27,28,29,30,31,32,34,35
+V5AUX 19,22,24,27,28,29,32,33,34,35,36

A A

CZC Technology zw
Title

Panel &VGA connect


Size Project Name Rev

A3 R48 C
Date:
Thursday, April 22, 2010 Sheet
17 of
56
5 4 3 2 1
3 2 1

D4
+V3.3S 5,9,10,11,12,13,14,15,16,17,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48
+V5S 14,15,16,17,19,20,21,23,25,26,28,29,35,36,37,38
VCC5V_HDMI 2 +V5S
F1
R220 0 R0402_0 J2 FB3 3 BAT54C 2 1
R221 0 R0402_0 FS1206
23 20 220ohm/100MHz,2A 1 1.1A
CHK1 L4S2012
90ohm@100MHz,0.5A FB0603
TXOUT_L2_P 4 3 1 R222 0 R0402_0
1 2 ns 2 R223 0 R0402_0
TXOUT_L2_N 3
4 1 2 TXOUT_L1_P
R224 0 R0402_0 5 4 3 ns
R225 0 R0402_0 6 TXOUT_L1_N
TXOUT_L0_P 7 CHK2 90ohm@100MHz,0.5A L4S2012
4 3 8 R226 0 R0402_0
C TXOUT_L0_N 1 2 ns 9 R227 0 R0402_0 C
10 TMDS_CLK_P
CHK3 90ohm@100MHz,0.5A 11 1 2 ns
L4S2012 12 4 3 TMDS_CLK_N
13
14 CHK4 90ohm@100MHz,0.5A
I2C_CLK_5V 15 L4S2012
16 DDC_DATA_5V
17
18
DVI2_HPD 19
C237
22 21 0.1uF/16V,X7R

R240 0
2041003 TYCO ns
HDMID19_H56IN_REV
GND_HDMI GND_HDMI GND_HDMI
GND_HDMI

2041003 TYCO
R236 R238 DVI2_HPD
27 HDMI_HPD_EC
33 20K,1%

R239
100K U40
VCC5V_HDMI
PS8271
QFN48_P5

41 38 I2C_CLK_5V R241
42 DDC1CLK IN1_SCL OUT_SCL
42 37 DDC_DATA_5V 2.2K
42 DDC1DATA IN1_SDA OUT_SDA
44 I2C_CLK_5V
42 TXCAM_DPA3N IN1_D1n
TMDS CLK 45 36 TMDS_CLK_N
42 TXCAP_DPA3P IN1_D1p OUT_D1n
B 35 TMDS_CLK_P B
OUT_D1p
42 HPD1 46 IN1_HPD
33 TXOUT_L0_N VCC5V_HDMI
OUT_D2n TXOUT_L0_P
OUT_D2p 32
42 TX0M_DPA2N 47 IN1_D2n
TMDS TX0 48 30 TXOUT_L1_N
42 TX0P_DPA2P IN1_D2p OUT_D3n
29 TXOUT_L1_P R242
OUT_D3p 2.2K
42 TX1M_DPA1N 1 IN1_D3n
TMDS TX1 2 27 TXOUT_L2_N
42 TX1P_DPA1P IN1_D3p OUT_D4n
26 TXOUT_L2_P DDC_DATA_5V
IN2_PEQ OUT_D4p
3 IN1_PEQ
4 HDMI_SEL# OUT
42 TX2M_DPA0N IN1_D4n
TMDS TX2 5 40 DDC_BUF
42 TX2P_DPA0P IN1_D4p DDCBUF
39 DVI2_HPD L GPU
OUT_HPD
28 TP55 H IGP
CFG_HPD
8
TMDS CLK15 DPD_LANE3_N 9
IN2_D1n
34 PRE_EMI
15 DPD_LANE3_P IN2_D1p PRE_EMI
10 24 R867 499,1%
15 DPD_HPD IN2_HPD REXT
11 23 C1039 2.2uF/6.3V,X7R
TMDS TX015 DPD_LANE2_N 12
IN2_D2n CEXT
15 DPD_LANE2_P IN2_D2p
SW_DDC 22
13
+V3.3S +V3.3S TMDS TX115 DPD_LANE1_N 14
IN2_D3n
21 HDMI_SEL# R868 0
15 DPD_LANE1_P IN2_D3p SW_MAIN DGPU_SELECT# 15
IN1_PEQ 15 IN2_PEQ +V3.3S
PWDN 25
R711R706R707R336R337R710 16
TMDS TX215 DPD_LANE0_N 17
IN2_D4n
6 FB85 300ohm/100MHz,1A
15 DPD_LANE0_P IN2_D4p VDD1
VDD2 31
4.7K 4.7K 4.7K 2.2K 2.2K 4.7K
ns ns ns ns C1042 C1041 C1040
15 DPD_CTRLCK 19 IN2_SCL GND1 18
20 43 0.01uF/25V,X7R 0.1uF/16V,X7R4.7uF/10V,X5R
15 DPD_CTRLDAT IN2_SDA GND2
GND_PAD 49
DDC_BUF 7
A
DPD_CTRLCK NC A
DPD_CTRLDAT
IN1_PEQ
IN2_PEQ
PRE_EMI

R712R708R709 CZC Technology zw


Title
4.7K 4.7K 4.7K HDMI
ns ns ns
Size Project Name Rev
A3 R48 C

Date: Thursday, April 22, 2010 Sheet 18 of 56


3 2 1
5 4 3 2 1

+V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,20,21,22,24,25,27,28,29,34,35,36,37,38,48
+V3.3AUX +V5S +V5S
+V5S 14,15,16,17,18,20,21,23,25,26,28,29,35,36,37,38
+V5AUX
+V5AUX 17,22,24,27,28,29,32,33,34,35,36
+VDC
+VDC 22,28,30,32,33,34,35,37,38,39
+V3.3AUX 5,13,14,15,16,17,21,22,24,25,27,28,29,30,31,32,34,35
R243

1
4.7K
Q14 +V3.3S +V5S
BSS138 LCDVDD
14,27,28,38 IMVP_OK 2 3 VLDT_PWRGD_5V Q15
FB5 0 ns AO3415
FB0805
FB75 0 2 3 FB76 0 500mA
FB0805 FB0805
C238
VLDT_PWRGD_5V R244 1000pF/50V,X7R C239 C240
1M SOT23

1
D 0.1uF/16V,X7R 10UF/6.3V,X5R D

R245 100K

3
1N4148WS D42 DGPU
42,44 FPVCC
Q16 Q17 +V3.3S
BSS138 2N7002K
1N4148WS D43 UMA 3 2 1
15 LVDS_VDD_EN
FB6 LCDVDD LCDCON1

2
R247 Panel CON. 2x20Pin
R339 33 ns R246 0 ns 100K LCD2X20_1P0

42
42 BLON_PWM
120ohm/100MHz,1A
2 1
4 3 B_LCDCLK1+
27 TTL_ADJ R299 33 27 AUO_E-Color_EN R460 0 6 5 B_LCDCLK1-
8 7
FB7 I2C_CLK 10 9 B_LCD0+
I2C_DATA 12 11 B_LCD0-
120ohm/100MHz,1A 14 13

ACES 88242-40xx
R486 33 ns BKLT_PWM LCD0- 16 15 B_LCD1+
15 L_BKLT_CTRL +VDC FB12 0 LCD0+ B_LCD1-
18 17
FB0805 20 19
R250 C241 LEDVDD LCD1- 22 21 B_LCD2+
100K Q18 LCD1+ 24 23 B_LCD2- LEDVDD
1000pF/50V,X7R AO3415 26 25
LCD2- 28 27
2 3FB8 0 500mA LCD2+ 30 29
FB0805 32 31 ECR_EN 27
ns LCDCLK1- 34 33 BKLT_PWM
R251 C242 SOT23 C243 C244 LCDCLK1+ 36 35 BKLT_ON
20K ns 38 37 D+

1
ns 1000pF/50V,X7R USBCAM_VCC 40 39 D-
ns 0.1uF/25V,X7R 10uF/25V,X5R
ns

41
R252 1K
+V3.3S ns
VLDT_PWRGD_5V

R255
20K
R257 ns
R256
C C
1N4148WS D45 DGPU 100K R253 0
42 GPIO7_BLON
1

3
Q19 4.7K FB11 R254 0
BSS138 ns Q20 +V5AUX CHK5 90ohm@100MHz,0.5A
120ohm/100MHz,1A 2N7002K 4 3 D+
15 USB_PP5 ns
1N4148WS D44 UMA 3 2 R714 4.7K LIGHT_ON BKLT_ON 1 1 2 D-
15 L_BKLT_EN 15 USB_PN5 L4S2012
ns USBCAM_VCC
+V3.3AUX FB9 120ohm/100MHz,1A

2
R258 4.7K ns C246 R259 FB0603
100K C245
D5 1N4148WS 1000pF/50V,X7R ns FB10 120ohm/100MHz,1A 10UF/6.3V,X5R HONDA-LVCC40SFYG-40PIN
22,27 LIDSW# FB0603 C0805
14 SUS_STAT# R260 0 ns D6 1N4148WS ns
HONDA
R261 0
27 HW_OFF_BKLT#

LVDS_SEL# OUT

L GPU

H IGP

CHANEL A CHANEL B

B_LCDCLK1+ LVDSB_CLK 15
B_LCDCLK1- LVDSB_CLK_L 15
LCDCLK1+ R262 0 DGPU
TXCLK_L+ 42
B LCDCLK1- R459 0 DGPU B_LCD0+ LVDSB_DATA0 15 B
TXCLK_L- 42
B_LCD0- LVDSB_DATA0_L 15
LCD0+ R491 0 DGPU
TXOUT_L0+ 42
LCD0- R492 0 DGPU B_LCD1+ LVDSB_DATA1 15
TXOUT_L0- 42
B_LCD1- LVDSB_DATA1_L 15
LCD1+ R493 0 DGPU
TXOUT_L1+ 42
LCD1- R494 0 DGPU B_LCD2+ LVDSB_DATA2 15
TXOUT_L1- 42
B_LCD2- LVDSB_DATA2_L 15
LCD2+ R495 0 DGPU
TXOUT_L2+ 42
LCD2- R496 0 DGPU
TXOUT_L2- 42

LCDCLK1+ R497 0 UMA LVDSA_CLK 15


LCDCLK1- R498 0 UMA LVDSA_CLK_L 15

LCD0+ R499 0 UMA LVDSA_DATA0 15


LCD0- R500 0 UMA LVDSA_DATA0_L 15

LCD1+ R501 0 UMA LVDSA_DATA1 15


LCD1- R502 0 UMA LVDSA_DATA1_L 15

LCD2+ R503 0 UMA LVDSA_DATA2 15


LCD2- R504 0 UMA LVDSA_DATA2_L 15

A A

I2C_DATA

R506 0 UMA R507 0 DGPU


15 LVDS_DDC_DATA SDA_LVDS 42

R505 0 UMA R508 0 DGPU


15 LVDS_DDC_CLK SCL_LVDS 42
I2C_CLK CZC Technology zw
Title
Panel &VGA connect

Size Project Name Rev


Custom R48 C

Date: Thursday, April 22, 2010 Sheet 19 of 56


5 4 3 2 1
5 4 3 2 1

VSYNC#

R510 0 UMA R511 0 DGPU


15 CRT_VSYNC VSYNC_DAC1 42,48

R519 0 DGPU
42 R_DAC1
RGB_SEL# OUT R509 0 UMA R512 0 DGPU R518 0 UMA R
15 CRT_HSYNC HSYNC_DAC1 42,48 15 CRT_RED
L GPU HSYNC# R521 0 DGPU
42 G_DAC1
R520 0 UMA G
H IGP 15 CRT_GREEN
D R523 0 DGPU D
42 B_DAC1
R522 0 UMA B
15 CRT_BLUE

DAC_SDAT

R514 0 UMA R515 0 DGPU


15 CRT_DDC_DATA DDC6DATA 42

R513 0 UMA R516 0 DGPU


15 CRT_DDC_CLK DDC6CLK 42
DAC_SCL

+V3.3S

R264
10K
+5VCRT
+5VCRT +V5S D8
+5VCRT R406 0
C CRT_DET# 27 C
2
D9 D10 D11 F2 +5VCRT
BAT54SPT BAT54SPT BAT54SPT 1 2 BAT54C 3 R265 R266
4.7K 4.7K
2 2 2 1.1A 1 FB15 D66 D13
220ohm/100MHz,2A 1N4148WS BAT54SPT
1N4148WS
RED_1 3 GREEN_1 3 BLUE_1 3 D65 +V3.3S
FS1206
2 2
1 1 1 R267 100K VGA1

17
GND_CRT GND_CRT GND_CRT
GND_CRT C260 0.1uF/16V,X7R 3 D12 3
BAT54SPT

1
6 GND GND_CRT 1 GND_CRT 1 GND_CRT
R L8 82nH/100Mhz RED_1 1 R NC
11
7 GND
G L9 82nH/100Mhz GREEN_1 2 G SDA
12 R268 0 SPDAT1_5V 3 2 DAC_SDAT
8 GND R0402_0
B L10 82nH/100Mhz BLUE_1 3 B HSYNC 13
9 NC
Q21
C261 C262 C263 C264 C265 C266 4 NC VSYNC 14
R269 R270 R271 10 GND 2N7002K
150,1% 150,1% 150,1% 10pF/50V,NPO10pF/50V,NPO10pF/50V,NPO 10pF/50V,NPO 10pF/50V,NPO 10pF/50V,NPO 5 GND CLK
15 R272 0
shell R0402_0

1
shell

16
dsub15C-F
VGA2F15H12IN_REV_NB SPCLK1_5V 3 2 DAC_SCL
GND_CRT +5VCRT

+5VCRT D14 D15 Q22


BAT54SPT BAT54SPT GND_CRT 2N7002K

2 2
B C267 B
U11 3 3
1 OE# 5 0.1uF/16V,X7R R273 0
VCC
1 GND_CRT 1 GND_CRT
VSYNC# 2 ns
A GND_CRT
3 4 CRT_VS R274 27 CRT_VS_1 GND_CRT
GND Y +5VCRT
74AHCT1G125
U12
1 OE# VCC 5 C268 0.1uF/16V,X7R GND_CRT
GND_CRT H24
HSYNC# 2 BOSS
A MH24X40X80
3 4 CRT_HS R275 27 CRT_HS_1 ns
GND Y
74AHCT1G125

1
C269 C270
GND_CRT

1
10pF/50V,NPO 10pF/50V,NPO

GND_CRT
GND_CRT

A A

+V5S 14,15,16,17,18,19,21,23,25,26,28,29,35,36,37,38
+V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,21,22,24,25,27,28,29,34,35,36,37,38,48

CZC Technology zw
Title
Panel &VGA connect

Size Project Name Rev


Custom R48 C

Date: Thursday, April 22, 2010 Sheet 20 of 56


5 4 3 2 1
5 4 3 2 1

+V3.3Aux
+VDC
+VDC 19,22,28,30,32,33,34,35,37,38,39
+V3.3S FB20 100ohm/100MHz,3A+V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,22,24,25,27,28,29,34,35,36,37,38,48
FB0603
+V5S ns
+V5S 14,15,16,17,18,19,20,23,25,26,28,29,35,36,37,38
+V3.3AUX FB21 100ohm/100MHz,3A
+V3.3AUX
+V3.3AUX 5,13,14,15,16,17,19,22,24,25,27,28,29,30,31,32,34,35
FB0603
+V3.3S FB16 100ohm/100MHz,3A +V1.5S 3G
+V1.5S 7,16,22,28,35,36
FB0603 ns
+V1.5S
D D
FB17 100ohm/100MHz,3A +V1.5S VCC_pcie
FB0603 R716 0 3G
R276 0 PCIE1 3V3_PCIE R717 0 3G 3GPCIE1
R277 0 PCIE MINI CARD PCIE MINI CARD
MINIPCIEH56_S minipcieh56

52

24

48
28
L4S2012

6
ns 3G

52

24

48
28
L4S2012

6
ns 3 4 36
15 USB_PN1 LED_WPAN# 46

+3.3VAUX

1.5V
3.3VAux0

+3.3VAUX1

+1.5V0
+1.5V1
TP24 USB_D- R290 0 ns WIRELESS_LED#
15 USB_PN0 3 4 36 46 15 USB_PP1 2 1 38 LED_WLAN# 44

+3.3VAUX
+3.3V0
+3.3V1

+1.5V0
+1.5V1
+1.5V2
USB_D- LED_WPAN# R300 0 ns USB_D+ TP63
15 USB_PP0 2 1 38 USB_D+ LED_WLAN# 44 WIRELESS_LED# 29 LED_WWAN# 42
42 TP25 90ohm@100MHz,0.5A
90ohm@100MHz,0.5A LED_WWAN# CHK9 R287 0 3G PLT_RST_L
PERST# 22
CHK6 22 11 1 R288 0 ns PCIE_WAKE#
PERST# PLT_RST_L 15,22,24 14 CLK_PCIE_MINICARD2_L REFCLK- WAKE#
14 CLK_PCIE_MINICARD1_L 11 REFCLK- WAKE# 1 PCIE_WAKE# 14,22,24 14 CLK_PCIE_MINICARD2 13 REFCLK+ CLKREQ# 7 CLK_MINICARD2_OE_L 14
14 CLK_PCIE_MINICARD1 13 REFCLK+ CLKREQ# 7 CLK_MINICARD1_OE_L 14
32 R457 0 ns
SMB_DATA SMB_DATA_A 14,22,24

PCIE mini Card V1.2


32 31 30 R458 0 ns
SMB_DATA SMB_DATA_A 14,22,24 14 PCIE_TXN2 PETN0 SMB_CLK SMB_CLK_A 14,22,24
31 PETN0 SMB_CLK 30 SMB_CLK_A 14,22,24 33 PETP0
14 PCIE_TXN1 14 PCIE_TXP2

PCIE mini Card


33 PETP0 COEX2 5
14 PCIE_TXP1
CHANNEL_CLK 5 COEX1 3
CHANNEL_DATA 3 14 PCIE_RXN2 23 PERN0
23 25 20 HW_RATIO_OFF_3G#R291 0 HW_RATIO_OFF#2 27
14 PCIE_RXN1 PERN0 14 PCIE_RXP2 PERP0 W_DISABLE#
25 20 HW_RATIO_OFF_WLAN# R278 1K
14 PCIE_RXP1 PERP0 RESERVED_DISABLE HW_RATIO_OFF# 27,29
17 RESERVED0/UIM_C8
TP26 17 19
TP27 RESERVED0 RESERVED1/UIM_C4
19 RESERVED1 37 GND15
37 VCC_pcie 39
3V3_PCIE RESERVED_PCIE0 +3.3VAux2 +V3.3S
39 RESERVED_PCIE1 41 +3.3VAux3
41 RESERVED_PCIE2 43 GND16
43 +V3.3S 45

Debug Card
RESERVED_PCIE3 RESERVED0
45 RESERVED_PCIE4 47 RESERVED1
C PCIE1_H1 3GPCIE1_H1 R455 C
47 RESERVED_PCIE5 49 RESERVED2
Cu Boss for MiniPCIE H5.6 49 51 Cu Boss for MiniPCIE 2*3mm
TP28 RESERVED_PCIE6 R454 RESERVED3
51 RESERVED_PCIE7 SIM_VCC 8 10K
TP29 SIM_DAT0 UIM_PWR
8 RESERVED_SIM4 10 UIM_DATA
TP30 10 10K SIM_CLK 12 CLK_MINICARD2_OE_L
TP31 RESERVED_SIM3 SIM_RESET UIM_CLK
12 RESERVED_SIM2 14 UIM_RESET
TP32 14 CLK_MINICARD1_OE_L 16
+V1.5S TP33 RESERVED_SIM1 UIM_VPP 3G
16

GND10
GND11
GND12
GND13

GND14
RESERVED_SIM0

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13

GND14
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

9
15
21
27
29
35
4
18
26
34
40
50
53
54
C275 C276 C277

55
9
15
21
27
29
35
4
18
26
34
40
50
53
54

55

4.7uF/10V,X5R 0.1uF/16V,X7R 0.1uF/16V,X7R

3V3_PCIE
U15
uclamp0504a ns
C272 C273 SIM_CLK 1 6 SIM_VCC R289 10K SIM_DAT0
C271 C274 4.7uF/10V,X5R IN1 IN4 3G
0.1uF/16V,X7R 2 GND1GND2 5
4.7uF/10V,X5R 0.1uF/16V,X7R SIM_DAT0 3 4 SIM_RESET
IN2 IN3

SC89_6 C291 C292


+V3.3S LPCDBG1 C290 0.1uF/16V,X7R 100pF/50V,NPO
B 88511-12XX Aces 88511-12XX 0.1uF/16V,X7R 3G 3G B
FPCE12_P5R 3G

LPC_AD0
1 1 Pitch 0.5mm Easy on FPC
13,27 LPC_AD0 2 2
LPC_AD1 3 3 13 13
13,27 LPC_AD1
LPC_AD2 4 4
13,27 LPC_AD2
LPC_AD3 5 5 HW_RATIO_OFF_WLAN# SIMREADER1
13,27 LPC_AD3
LPC_FRAME# 6 6 SIMreader
13,27 LPC_FRAME#
LPC_RST# 7 7 SIM9H19
3

+V5S 8 8 3G
15 CLK_PCIF_PORT80 9 9
10 1014 14 Q31 SIM_VCC 1
SOT23 SIM_VCC
11 11 1 R476 1K VCC_pcie
SERIRQ 12 12 2N7002K 4
13,27 INT_SERIRQ +V3.3AUX SIM_VPP
C293 C294
2

ns C295 C296 C297


10UF/6.3V,X5R 10UF/6.3V,X5R 0.1uF/16V,X7R0.1uF/16V,X7R0.1uF/16V,X7R SIM_RESET 3
3G 3G 3G 3G 3G SIM_CLK SIM_RST
5 SIM_CLK
HW_RATIO_OFF_3G# R478 SIM_DAT0 6
4.7K SIM_IO
7 SIM_DAT0
8 SIM_MCMD
3

3 9 SIM_CDDETECT
GSLECT1
Q32 DIP LSSM12 +V1.5S 2
SOT23 SIM_GND0
1 R477 1K 3G_SWITCH 2 SWS3D35X95 10 SIM_GND1
2N7002K 11
LPC_DEBUG1 SIM_GND2
0.1uF/16V,X7R

12 SIM_GND3
2

+V3.3S FPC10 1.0mm


C621

1 13 SIM_GND4
FPC10_1p0rt R479 C401 C278 C279
100K 4.7uF/10V,X5R 0.1uF/16V,X7R 0.1uF/16V,X7R
10 27,29 BT_ON 3G 3G 3G
LPC_AD0 10
A
13,27 LPC_AD0 9 9
A
LPC_AD1 8
13,27 LPC_AD1 8
3

LPC_AD2 7
13,27 LPC_AD2 7
LPC_AD3 6 11
13,27 LPC_AD3 6 11
LPC_FRAME# 5 12 Q33
13,27 LPC_FRAME# 5 12
4 SOT23 1 R481 1K
15,27 LPC_RST# 4
3 2N7002K
15 CLK_PCIF_PORT80
2
3
2
CZC Technology
2

1 zw
1 Title
Panel &VGA connect

Size Project Name Rev


MB pin10----DB pin1 Custom R48 C

Date: Thursday, April 22, 2010 Sheet 21 of 56


5 4 3 2 1
5 4 3 2 1
+V3.3AUX

+V3.3S
+V5S 14,15,16,17,18,19,20,21,23,25,26,28,29,35,36,37,38 +VDC 19,28,30,32,33,34,35,37,38,39
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,24,25,27,28,29,34,35,36,37,38,48
+V3.3AUX +V1.5S 7,16,21,28,35,36
+V3.3S +V1.5S BT_CN1
+V3.3AUX 5,13,14,15,16,17,19,21,24,25,27,28,29,30,31,32,34,35
R279 R280 R281 R282 88511-12XX
+V5AUX 17,19,24,27,28,29,32,33,34,35,36
100K 100K 100K 10K FPCE12_P5R
R0402 R0402 R0402 R0402 Iac_P_R
C280 C282 newcard U13 ns 1 1
0.1uF/16V,X7R C281 0.1uF/16V,X7R OZ27C10LN newcard newcard 2 2 PWRSWVCC_MBXP 30,32 +V3.3AUX
13 13 3 3 PWR_LED 27
0.1uF/16V,X7R QFN20_P5 CP_USB#
newcard newcard EXP_3.3V 4 4 SLP_LED 27
12 1.5Vin1 3.3Vout1 3 5 5
newcard 14 5 EXP_CPPE#
1.5Vin2 3.3Vout2 6 6 LIDSW# 19,27
D
EXP_AUX_3.3V EXP_OC# 7 7 QKEY1 27 D
2 3.3Vin1 3.3Vauxout 15 8 8 GPU_LED 27
4 3.3Vin2 9 9 SLIDE_INTR# 27
11 EXP_1.5V NEW_CARD_CLKREQ# 14 1410 10
1.5Vout1 EC_SMB1_DAT 9,14,27
17 13 +V3.3S
3.3Vauxin 1.5Vout2 11 11 EC_SMB1_CLK 9,14,27
EXP_RST# C283 0.1uF/16V,X7R 12 12
14,27,28,36 SLP_S3# 1 STBY# PERST# 8
D16 1N4148WS 20 10 EXP_CPPE# newcard
14,27,28,29 SLP_S4# newcard SHDN# CPPE# 88511

5
EXP_OC# D17 1N4148WS EXPRESS_RST# 6 9 CP_USB# ACES
SYSRST# CPUSB#
16 NC 1 VCC
newcard RCLKEN 18 7 4 EXPRESS_RST#
R284 0 EXP_OC# RCLKEN GND1 PLT_RST_L
15,21,24 PLT_RST_L 19 OC# PAD 21 2
ns GND
U14

3
SOT23_5
SN74AHC1G08DBV

USB_CN1 88502-26xx VUSB1


newcard fpce26_1p0r
26 26
MYLAR1 VUSB2
MYLAR 25 25
24 24
newcard 23 23
J3 22 22
21 21
PCI-EXP
NEWCARD_STD
PVC 20 20
C Q23 19 19 SATA_RXN2 13 C
28 28 18 18 SATA_RXP2 13
newcard NEW_CARD_CLKREQ#
14 PCIE_TXP2_EXPRESS 25 PETp0 CLKREQ# 16 2 32N7002K EXPRESS_CLKREQ# 14
ns
17 17
newcard EXPRESS CARD1 16 16 SATA_TXN2 13
14 PCIE_TXN2_EXPRESS 24 PETn0 15 15 SATA_TXP2 13
6 Shield
RESV1 14 14
14 PCIE_RXP2_EXPRESS 22 PERp0 13 13 USB_PP7 15

1
5 EXP_3.3V RCLKEN newcard 27 27 12 12
RESV2 USB_PN7 15
14 PCIE_RXN2_EXPRESS 21 PERn0 11 11
+3.3VS_2 15 10 10 USB_PP6 15
14 GPP_CLK2_P 19 REFCLK+ 9 9 USB_PN6 15
14 C284 C285
+3.3VS_1 10UF/6.3V,X5R 8 8
14 GPP_CLK2_N 18 REFCLK- 7 7 MB_MIC1_L 25
0.1uF/16V,X7R ns
EXP_CPPE# 6 6 MB_MIC1_R 25
27 EXP_CPPE# 17 CPPE# GND0 26 5 5 MIC1_JD 25
newcard EXP_AUX_3.3V
EXP_RST# 4 4 GND_AUD
13 PERST# 3 3 MB_LINEOUT_L 25
+3.3VAUX 12 2 2 MB_LINEOUT_R 25
11 C286 C287 EXPRESSCARD_SCREW1
EXPRESSCARD_SCREW2
14,21,24 PCIE_WAKE# WAKE# 0.1uF/16V,X7R 10UF/6.3V,X5R screw 2*3mm screw 2*3mm 1 1 HP_JD 25
8 ns
14,21,24 SMB_DATA_A SMB_DATA
23 newcard 88502 ACES
GND1
14,21,24 SMB_CLK_A 7 SMB_CLK
R285 0 EXP_1.5V +V5AUX
R286 ns
0 CP_USB# 4 10
newcard CPUSB# +1.5V_1
+1.5V_2 9
2 newcard
1 USB+ 3
15 USB_PP2 USB_D+
3 4 20 C288
15 USB_PN2 GND2
USB- 2 1 0.1uF/16V,X7R newcard newcard C421
CHK7 USB_D- GND3 C289 0.1uF/16V,X7R
B L4S2012 90ohm@100MHz,0.5A 27 newcard10UF/6.3V,X5R R480 U36 B
G1 ns 470K VUSB1
G2 28 6 IN OUT 1
1

G3 29
D19 30 2 R475 20K
D18 EGA1-0603-V05 G4 USB_OC# ILIM C451
3 FAULT# GND 5
EGA1-0603-V05 ESDPAD_R0603 EN 4 EN 7 0.1uF/16V,X7R
PAD
2

ESDPAD_R0603 C1269
newcard 1CH4110C-SY+1CX42201-SY 1000pF/50V,X7R TPS2553
newcard
Foxconn
+V5AUX

C424
0.1uF/16V,X7R
R483 U37
470K 6 1 VUSB2
IN OUT

ILIM 2 R482 20K


R1138 0 ns USB_OC# 3 5 C422
87213-xxx0x-x +VDC 15 USB_OC_L3 R1139 0 EN 4
FAULT# GND
7 0.1uF/16V,X7R
14,27,28,29 SLP_S4# EN PAD
Aces +V3.3AUX SLP_LED- TPS2553
7

6 Iac_P_R R283 20K PWR_LED- C423


5 0.1uF/16V,X7R
PWRSWVCC_MBXP 30,32
3

A 4 BT_R18 ns A
3

3 PWR_LED- BT_R16 BT_Q5 1K


2 SLP_LED- 1K BT_Q4 2N7002K R0402
1 R0402 2N7002K 1 SLP_LED 27
27 PWR_LED 1 SOT23 ns
SOT23
CZC Technology
2

Wafer6P10 ns
8

PWRBTN_CN BT_R17 BT_R19 zw


hws6_1p0r 1uF/10V,X5R 1uF/10V,X5R Title
R0402 R0402 Roll wheel board
ns
Size Project Name Rev
A3 R48 C

Date: Thursday, April 22, 2010 Sheet 22 of 56


5 4 3 2 1
5 4 3 2 1

+V5S
+V5S 14,15,16,17,18,19,20,21,25,26,28,29,35,36,37,38
+V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48

C16619

D SATA1 D

13 SATA_TXP0 S2 TX
13 SATA_TXN0 S3 TX#
GND0 S1
C298 0.01uF/25V,X7R S5 S4
13 SATA_RXN0 RX# GND1
C299 0.01uF/25V,X7R S6 S7
13 SATA_RXP0 RX GND2
T1 ns V3.3_SATA P1 VCC3_0
P2 VCC3_1 GND3 P4
P3 VCC3_2 GND4 P5
GND5 P6
+V5S V_HDD0 P7 VCC5_0
P8 VCC5_1
P9 P10
FB24 Average 1A,Peak 1.5A P11
VCC5_2 GND6
P12
V_HDD0 RESVE GND7
P13 VCC12_0
100ohm/100MHz,3A P14 VCC12_1 NC0 1
FB0603 C300 C301 C302 C303 P15 2
4.7uF/10V,X5R 4.7uF/10V,X5R0.1uF/16V,X7R 0.1uF/16V,X7R VCC12_2 NC1
C C0603 C0603 C0402 C0402 SATACN C
SATA22R_REV

VerB: ADD HDD2 Option FFC 1x10


SATA2
ns
10 10
SATA_TXP1R721 0 ns 9
SATA_TXN1R722 0 ns 9
8 8 12 12
7 7
6 6
SATA_RXN1 C420 0.01uF/25V,X7R ns 5
SATA_RXP1 C425 0.01uF/25V,X7R ns 4 5
V_HDD1 4
3 3 11 11
2 2
+V5S 1 1
ACES 88502 fpce10_1p0r
FB25 Average 1A,Peak 1.8A
B V_HDD1 B

100ohm/100MHz,3A ODDCN1
FB0603 C304 C305 C306 C307 R723 0 S2
13 SATA_TXP1 TX
4.7uF/10V,X5R 4.7uF/10V,X5R 0.1uF/16V,X7R 0.1uF/16V,X7R R724 0 S3 S1
13 SATA_TXN1 TX# GND0
C0603 C0603 C0402 C0402 S4
C308 0.01uF/25V,X7R GND1
13 SATA_RXN1 S5 RX# GND2 S7
C309 0.01uF/25V,X7R S6
13 SATA_RXP1 RX
T2 ns Device_present P1 P4
V_HDD1 DP MD
P2 VCC5_1 GND4 P5
P3 VCC5_2 GND5 P6

1 NC0 NC1 2

ODD_SATA CONN
LN21133-D407-9F
SATAS13RIN_REV

A A
CZC Technology zw
Title
SATA HDD ODD
Size Project Name Rev
A4 R48 C

Date: Thursday, April 22, 2010 Sheet 23 of 56


5 4 3 2 1
5 4 3 2 1

+V3.3AUX
+V3.3AUX 5,13,14,15,16,17,19,21,22,25,27,28,29,30,31,32,34,35
AR8131/M, 8121 GigaBit Lan +V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,25,27,28,29,34,35,36,37,38,48
AR8132/M, 8114 10M/100M Lan +V5AUX
+V3.3S VCC_3.3V +V5AUX 17,19,22,27,28,29,32,33,34,35,36

Close to U26 For AR8131/M, 8132/M: C675=1uF FB97 220ohm/100MHz,2A VCC_3.3V Interface with motherboard

0.1uF/16V,X7R CLK_PCIE_LAN
0.1uF/16V,X7R CLK_PCIE_LAN#
FB0603
+V3.3AUX
For AR8121/8114: C675=0.1uF ns
C1231 C1232
For AR8131/M, 8132/M: remove R348, C325. C337=0.1uF FB98 220ohm/100MHz,2A Layout: Place near to 8102E
FB0603 10UF/6.3V,X5R0.1uF/16V,X7R
For AR8121/8114: remove L9, C306, R322. C337=1uF. C325 close to Pin1 PCIE_RXP1_LANR
14 PCIE_RXP6_LAN
C1227 0.1uF/16V,X7R
Pin Name: PCIE_RXN1_LANR
C681, C670 14 PCIE_RXN6_LAN

PCIE_TXN1_LAN
PCIE_TXP1_LAN
R1101 0 R0603 ns 1) name_AR8131M&8132M/AR8121&8114 C1233 C1228 0.1uF/16V,X7R

PCIE_RXN1_LANR
PCIE_RXP1_LANR
close to PCIE_TXN1_LAN
D 2) One name denotes the two names are 14 PCIE_TXN6_LAN D

AVDDVCO2
L31 LX/VDD18O 1uF/10V,X5R PCIE_TXP1_LAN
Pin1 Pin2 14 PCIE_TXP6_LAN

AVDDL
4.7uH/260mA the same.

DVDDL
DVDDL
C1229 C1230 C1280 CLK_PCIE_LAN#
14 CLK_PCIE_LAN_L
CLK_PCIE_LAN
14 CLK_PCIE_LAN
10UF/6.3V,X5R 0.1uF/16V,X7R 10UF/6.3V,X5R R1165 5.1K
ns PCIE_WAKE#

41 C1236
40 C1235
14,21,22 PCIE_WAKE#
ns
R1102 0 RSTn
15,21,22 PLT_RST_L
AVDD_CEN R1103 0 R0603 AVDD_CEN/AVDDH

49
48
47
46
45
44
43
42

39
38
37
Pin6 U65 R1104 0 LAN_CLKREQ#
14 CLK_PCIE_LAN_REQ_L
C1234

RX_P

REFCLKP

TX_P
LED_LINK10_100n
GND

LED_ACTn
DVDD_REG/DVDDL1
DVDD_REG/DVDDL2

AVDDL2

AVDDL1
RX_N

REFCLKN

TX_N
0.1uF/16V,X7R SMBCLK R1105 0 ns
SMB_CLK_A 14,21,22
SMBDATA R1133 0 ns
SMB_DATA_A 14,21,22
EXT_25/48
EXT_25/48 12
C683 close to Pin30
For AR8131/8132: Remove C683
VCC_3.3V
R1106 0
R0603 ns

A
t
h
e
r
o
s
C1237 ns R1107
R1108 0 LX/VDD18O 1 36 AVDDL
0.1uF/16V,X7R 10K R0603 VCC_3.3V LX/VDD18O AVDDL3
2 VDD3V NC 35
2

ns ns RSTn 3 34 TESTMODE
1 VCC_3.3V/CTR12 PCIE_WAKE# 4 PERSTn TESTMODE
33 SMBDATA R1111 4.7K ns For AR8121/8114: Remove R335
Pin5 VCC_3.3V/CTR12 WAKEn AR8131M/AR8132M/AR8121/AR8114 SMDATA DVDDL
VCC_3.3V
CLKREQn/PNP_PWR_SEL R1109 0 LAN_CLKREQ#
5 VDD3V/CTR12 DVDDL2 32
AVDDL SOT23 ns C1238 AVDD_CEN/AVDDH 6 31 SMBCLK
VDD17/VDDHO SMCLK
3

MMBT3904-F R1112 4.7K SEL_25M/VREF 7 30 TWSI_SDA C1241 0.1uF/16V,X7R


AVDDL Q170HM772 PNP 0.1uF/16V,X7R AVDDL SEL_25M/VBG1P18 TWSI_DATA;TEST_PAD TWSI_SCL C1267 0.1uF/16V,X7R
8 VDD11_REG/AVDDL TWSI_CLK;3.3V 29 For AR8121/8114: Pin27 power-on strapping (internal pull- up for input)
C1243 1000pF/50V,X7R XTLO 9 28 DVDDL
C1239 ns C1240 ns XTLI XTLO DVDDL1 CLKREQn/PNP_PWR_SEL R1113 4.7K
10 XTLI CLKREQn/PNP_PWR_SEL 27 VCC_3.3V If R341 and R343 are removed, Q1 collector connects 3.3V and remove R327.
R1110 0 AVDDH ns AVDDVCO1 11 26
0.1uF/16V,X7R 10UF/6.3V,X5R R0603 Pin15 RBIAS 12
AVDD_REG/AVDDL LED_LINK1000n
25 AVDDH R1115 4.7K ns
C
RBIAS AVDDH2 If R341 is removed ,and R343 is stuffed, Q1 collector connects 1.8V and remove R328.
C

R1117
For AR8131/M, 8132/M: 2.37K,1% VCC_3.3V
option1: remove R328, R327, R349, R334, C302, C342, C311, Q7. RSTn R1118 4.7K ns
option2: remove R328, R327, R349, R339, C302, C342, C311, Q7.
VCC_3.3V TWSI

AVDDH1
AVDDL5

AVDDL4
C1242

VDDHO
TRXN0

TRXN1

TRXN2

TRXN3
TRXP0

TRXP1

TRXP2

TRXP3
PCIE_WAKE# R1119 4.7K ns VCC_3.3V 0.1uF/16V,X7R
ns
U66 R1114 R1116
For AR8121/8114: remove C320, R339 8131M/8132M/8121/8114 1 8 4.7K 0
A0 VCC

13
14
15
16
17
18
19
20
21
22
23
24
qfn48_p4 2 7 ns
Q7 close to Pin8 3
A1 WP
6 TWSI_SCL
A2 SCL TWSI_SDA
R6,R8,R13 and R14 are 4 5
Close to LAN IC VSS SDA

AVDDH

AVDDH
AVDDL

AVDDL
R1121 49.9,1% pull-up resistors, which might AT24C02N-10SU-2.7
R1122 49.9,1% ns
C1244 0.1uF/16V,X7R R1123 49.9,1% not be necessary due to For AR8131M/8132M: R340=0 ohm. Remove U12, C301, R344.
Clock Resource C1245 0.1uF/16V,X7R
R1124
R1125
49.9,1%
49.9,1% existence on motherboard.
For AR8121/8114 : Remove R336 R1126 49.9,1% For AR8131/8132 eeprom application, reserve TWSI circuit.
C1246 0.1uF/16V,X7R R1127 49.9,1%
For AR8131/M, 8132/M Input 25M: Remove R336, C339 R1128 49.9,1%
C1247 0.1uF/16V,X7R

MDI0+

MDI1+

MDI2+

MDI3+
For AR8131/M, 8132/M Input 48M: Stuff R336. Remove C339

MDI0-

MDI1-

MDI2-

MDI3-
Pin6 AVDD_CEN/AVDDH R1120 0 R0603 ns AVDDH
For AR8132/M and AR8114:
For AR8131/M, AR8132/M: Remove R342
R549,R550,R551,R554,C731 and
25MHz Crystal C732 can be removed.
XTLO
XTLI
Y11
AVDDL AVDDH DVDDL AVDDL
2 1
For AR8131/M, 8132/M: remove FB74
C1248 C1249 C1253 C1254 C1255 C1256 C1257 C1258 C1259 C1260 C1261 C1262 C1263 C1264 BLM15AG100SN1
B
18pF/50V,NPO 25MHz,20pF 18pF/50V,NPO FB99 300ohm/100MHz,1A DVDDL B
X2S50X32 1uF/10V,X5R 0.1uF/16V,X7R 0.1uF/16V,X7R 0.1uF/16V,X7R 0.1uF/16V,X7R 0.1uF/16V,X7R 1uF/10V,X5R 0.1uF/16V,X7R 0.1uF/16V,X7R 0.1uF/16V,X7R 0.1uF/16V,X7R 0.1uF/16V,X7R ns

P
i
n
1
1
ns ns ns
R1129 0 R0603 R1130 0 R0603 AVDDVCO1
ns
External clock C684, C685 C1252
EXT_25/48 10pF/50V,NPO C1250 close to C1251
1000pF/50V,X7R 1uF/10V,X5R
Pin8
For AR8121/8114 : Remove C322

P
i
n
4
2
FB100 300ohm/100MHz,1A AVDDVCO2
For AR8131/M, 8132/M intertnal clock: Remove C322
C1265
For AR8131/M, 8132/M external clock: Remove Y4, C687, C688
0.1uF/16V,X7R
If the external clock is swing from 0 to 0.8V, EXT_25/48
can be connected to XTLI directly. U16
LAN 1500VRMS
MDI0+ 2 1CT:1CT 23 RJ45_MDI0+ U17 If overclocking, R332, FB75 stuffed and R330 removed.
TD1+ MX1+
13 N4 N2 5 87213-xxx0x-x If not overclocking, R330, FB75 stuffed and R332 removed.
V_DAC AVDD_CEN 1 24 12 4
TCT1 MCT1 N3 N1
MDI0- RJ45_MDI0- MDI0- RJ45_MDI0-
ACES For AR8131/M, AR8132/M: FB75 can be 0 ohm
3 TD1- MC1- 22 9 TD- TX- 8
MDI1+ 5 1CT:1CT 20 RJ45_MDI1+
TD2+ MX2+ V_DAC +V5AUX
11 TDC CMT 6
V_DAC 4 21

17
TCT2 MCT2 MDI0+ RJ45_MDI0+
10 TD+ TX+ 7
MDI1- RJ45_MDI1-
1CT:1CT
6 TD2- MX2- 19
MDI2+ 8 1CT:1CT 17 RJ45_MDI2+ MDI1- 15 2 RJ45_MDI1- 15
TD3+ MX3+ RD- RX-
14
V_DAC 7 18 14 3 13
TCT3 MCT3 RDC RXC 15 USB_PN11
15 USB_PP11 12
A MDI2- 9 16 RJ45_MDI2- MDI1+ 16 1 RJ45_MDI1+ 11 A
MDI3+ TD3-
1CT:1CT MX3- RJ45_MDI3+ RD+
1CT:1CT RX+
11 TD4+ MX4+ 14 10
RJ45_MDI3- 9
V_DAC 10 15 RJ45_MDI3+ 8
TCT4 MCT4 C414 H16101ME R298 R297 RJ45_MDI2- 7
MDI3- 12 13 RJ45_MDI3- TFS16_1p27 75 75 RJ45_MDI2+ 6
TD4- MX4- 0.1uF/16V,X7R ns ns ns RJ45_MDI1- 5
RJ45_MDI1+ 4 RJCN1
RJ45_MDI0- 3 Wafer15P1
R296 R295 R294 R228 RJ45_MDI0+ 2 hws15_1p0r
C417 C416 C415 C418
TRAN24_1P27
75 75 75 75 SMH_SPLANE SMH_SPLANE 1 CZC Technology zw
0.1uF/16V,X7R 0.1uF/16V,X7R 0.1uF/16V,X7R 0.1uF/16V,X7R Title
SMH_SPLANE LAN

16
Size Project Name Rev
C R48 C

Date: Thursday, April 22, 2010 Sheet 24 of 56


5 4 3 2 1
5 4 3 2 1

+V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,27,28,29,34,35,36,37,38,48
+V5S
+V5S 14,15,16,17,18,19,20,21,23,26,28,29,35,36,37,38
+V3.3AUX 5,13,14,15,16,17,19,21,22,24,27,28,29,30,31,32,34,35
+V3.3S FB26 VCC5CODEC +V5S
220ohm/100MHz,2A FB27

FB0603 C339 C340 C341 C342 C343 C344 220ohm/100MHz,2A C345


0.1uF/16V,X7R 0.1uF/16V,X7R 10UF/6.3V,X5R 10UF/6.3V,X5R +V3.3S +V3.3AUX
C0402 C0402 C0805 0.1uF/16V,X7R 0.1uF/16V,X7R C0805 FB0603 0.1uF/16V,X7R
C0402 C0402 Cross moat place C0402

FB42 FB35

10
GND_AUD 220ohm/100MHz,2A 220ohm/100MHz,2A

25
38
1
9
FB0603 FB0603

P2
ns 8

VDD1
VDD2

AVDD1
AVDD2
ns MDC_3V3 8
TPC30 TP TP48 A_GPIO0 AMP_OUT_L 8
2 GPIO0 FRONT-OUT-L 35 7 7

P1 ACES 87213-08xx
13 HDA_SDOUT MDCCN1
6 6
TPC30 TP TP47 A_GPIO1 AMP_OUT_R 13 HDA_SYNC
D 3 GPIO1 FRONT-OUT-R 36 13 HDA_SDIN1 5 5 88460-08XX D
4 4 HWS8_P8R
C584 13 HDA_RST_L
ns NC1 37 3 3
29 0.1uF/16V,X7R 2
NC2 13 HDA_BIT_CLK 2
1 1
1
R321 51K R0402 C347 1uF/10V,X5R C0402 PC_Beep 11 27 C348 10UF/6.3V,X5R
27 BTL_BEEP 13 HDA_RST_L REST# VREF GND_AUD
C0805

9
6 28 MIC1_VREFO_L
C350 13 HDA_BIT_CLK BITCLK MIC1-VREFO-L
R323 75K R0402 C349 1uF/10V,X5R C0402 100pF/50V,NPO 10
13 HDA_SPKR C0402 13 HDA_SYNC SYNC MIC2_VREFO
MIC2-VREFO 30
5 SDOUT
13 HDA_SDOUT U20
LINE2-VREFO 31
R324 R325 R326 33 8 ALC662
13 HDA_SDIN0 SDIN
4.7K 4.7K R0402 LQFP48_P5 32 MIC1_VREFO_R
R0402 R0402 R327 10K ns MIC1-VREFO-R
PC_Beep 12 33
PC-BEEP NC5
MIC1_JD R328 20K,1% JACK_DET_A 13 34 JACK_DET_B R329 39.2K,1% HP_JD
R0402 Sense A Sense B R0402
LINEOUT_L C351 10UF/6.3V,X5R 14 43
C0805 LINE2-L CEN-OUT
All of JD resistors should be
placed as close as possible to LINEOUT_R C352 10UF/6.3V,X5R 15 44
C0805 LINE2-R LFE-OUT
the sense pin of codec. INT_MIC C449 1uF/10V,X5R 16 45
C0402 MIC2-L NC3
C450 1uF/10V,X5R 17 46
C0402 MIC2-R NC4
18 47 AMP_SHDW
CD-L SPDIFI/EAPD
20 CD-R SPDIFO 48

MIC1_L C353 1uF/10V,X5R 21


C0402 MIC1-L
SURR-OUT-L 39
MIC1_R C354 1uF/10V,X5R 22
MIC2_VREFO R380 4.7K C0402 MIC1-R R334 20K,1% R0402
JDREF 40 GND_AUD
R0402 23 LINE1-L
SURR-OUT-R 41

CD-GND
24

AGND1
AGND2
LINE1-R

GND1
GND2
C C
INPUT:STEREO MIC-IN
OUTPUT:CENT/LFE

4
7

19

26
42
+ MIC1 MIC1_VREFO_L R340 2.2K
INT_MIC FB22 220ohm/100MHz,2A 1 Microphone R0402
onboard stereo
FB0603 2 BZ_D6027 MIC1_VREFO_R R341 2.2K microphone
C317 R0402

100pF/50V,NPO
GND_AUD MIC1_L R342 1K FB29 220ohm/100MHz,2A
MB_MIC1_L 22
FB0603
+V3.3S MIC1_R R343 1K FB30 220ohm/100MHz,2A
MB_MIC1_R 22
FB0603
MIC1_JD
MIC1_JD 22
R316 R344 R345
10K 22K 22K
D20 1N4148WS R0402
27 EC_AMP_Mute#
SOD323 ns ns

A_GPIO0 D25 1N4148WS ns Mute#


SOD323 GND_AUD

AMP_SHDW D26 1N4148WS ns


SOD323 AMP_OUT_L C455 1uF/10V,X5R R335 AMP_L R356 10K,1% Stereo Microphone Jack
51.1K,1% R350 0 ns
+V5S C1035 680pF/25V,X7R R0402
INPUT:STEREO MIC-IN
FB28 OUTPUT:CENT/LFE
220ohm/100MHz,2A GND_AUD C363 0.1uF/16V,X7R
VDD_AMP C0402
U21 C374 ns
TPA6017A2 FB0603 Mute# C457 1uF/10V,X5R
Tssop20_P65_4P4G C360 C361 C375 C0402
AMP_R 17 18 +INTSPR C802 0.1uF/16V,X7R 0.1uF/16V,X7R 0.1uF/16V,X7R 1uF/10V,X5R GND_AUD
RIN- ROUT+ C0402
4.7uF/10V,X5R C0402 C0402
-INTSPR C0603 U46
7 14

36

35

34

33

32

31

30

29

28

27

26

25
ns RIN+ ROUT- AN12947A
GND_AUD C459 C0603 R263 27K ns 9 4 +INTSPL HQFP48_P5G

HP_STBY

SP_STBY

VCC

NC4

GND1

NC3

VREFSP

SP_INL

PREOUT_L

Pre-charge_L

AGCOUT_L

AGCIN_L
0.47UF/25V,Y5V R0402 LIN+ LOUT+ GND_AUD
B C460 0.47UF/25V,Y5V 10 8 -INTSPL VCC5CDC B
ns C0603 BYPASS LOUT-
AMP_L 5 16 37 24 GND_AUD
LIN- VDD NC5 GND_SPL
12 NC PVDD1 6
15 VDD_AMP 38 23
Mute# PVDD2 VCC_CP SP_OUTL_2
19 SHDWN# GND1 1
11 C373 1uF/10V,X5R 39 22 -INTSPL
GAIN0 AGC_LV1 GND2 C0402 C1 SP_OUTL_1 C1037
2 GAIN0 GND3 13
20 40 21 100pF/50V,NPO
GAIN1 AGC_LV2 GND4 GND_AUD GND_CP SP_OUTL+2 +V5S
3 GAIN1 GND5 21
GND_AUD 41 20 +INTSPL VCC5CDC
ns C2 SP_OUTL+1 FB33
GND_AUD C803 4.7uF/10V,X5R 42 19
VSS_CP VCC_SPL
GND_AUD C362 2.2uF/6.3V,X7R 43 18 220ohm/100MHz,2A
VDD_HP VCC_SPR C364 C365
LINEOUT_L R703 10K +INTSPR C372 FB0603
44 HP_INL SP_OUTR+2 17 1uF/10V,X5R 1uF/10V,X5R
C1283 100pF/50V,NPO C0402 C0402 4.7uF/10V,X5R
R704 20K 45 16 C1038 C0603
HP_L HP_OUTL SP_OUTR+1 100pF/50V,NPO
HP_R 46 15 -INTSPR
GND2 SP_OUTR_2
HP_L R346 20,1% FB31 220ohm/100MHz,2A R702 20K GND_AUD 47 14
MB_LINEOUT_L 22 HP_OUTR SP_OUTR_1
FB0603 C1284 100pF/50V,NPO

Pre-charge_R
HP_R R347 20,1% FB32 220ohm/100MHz,2A LINEOUT_R R701 10K 48 13

AGCOUT_R
PREOUT_R
MB_LINEOUT_R 22 HP_INR GND_SPR
FB0603 GND_AUD

GND_PAD
GND_AUD

AGCIN_R
AGC_Lv1

AGC_Lv2

AGC_Det

HP_JD

SP_INR
HP_JD 22

GND0
NC0

NC1

NC2
R348 R349
22K 22K +V3.3S
1

10

11

12

49
ns ns
GND_AUD

AGC_LV1 C456
AGC_LV2 R396 1uF/10V,X5R
GND_AUD R330 R331 GND_AUD
10K 10K
R0402 R0402
100KC453
C452
A 87213-xxx0x-x 1uF/10V,X5R C1036 680pF/25V,X7R A

Aces 2.2uF/6.3V,X7R
R358 10K,1%
6

GND_AUD
AMP_OUT_R C454 R357 AMP_R
4 +INTSPL AGC_LV1 1uF/10V,X5R 51.1K,1%
3 -INTSPL AGC_LV2
2 +INTSPR
1 -INTSPR
AGC_LV1 AGC_LV2 AGC ON Level Po Rl=4
R332 R333
0 0 9.8dBV 2.0w
Wafer4P125
10K
R0402
10K
R0402
CZC Technology zw
ns ns 0 1 9.0dBV 1.8w
SPEAKER1 Title
hws4_1p0r
1 0 8.1dBV 1.5w HD Audio-ALC883
5

1 1 6.0dBV 1.0w Size Project Name Rev


GND_AUD A2 R48 C
GND_AUD
Date: Thursday, April 22, 2010 Sheet 25 of 56
5 4 3 2 1
5 4 3 2 1

+V5S
+V5S 14,15,16,17,18,19,20,21,23,25,28,29,35,36,37,38
R718 0 R0402_0
R719 0 R0402_0 +V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48
CHK10
90ohm@100MHz,0.5A
2 1 U_DNA
15 USB_PN3
D 3 4 U_DPA D
15 USB_PP3
L4S2012 ns

VCC5_USB

VCC33 VCC_CARD

VCCPHY VCC18

18
23

3
U22
VCC33 VCCPHY VCC18 VCC_CARD

VccA
VddA

Vcc5V
Vcc33O

Vcc18O
CrdVcc
11 LedZ
9 ResetZ
XI 16 10 SDWPD/MSBS C368 C367 C366
XI SdWpd 4.7uF/10V,X5R 1uF/10V,X5R 4.7uF/10V,X5R
C XO 17 C
XO MSINSZ
MsInsZ 15
U_DNA 21
U_DPA D- SDCLK
22 D+ SdClk 32
13 SDCMD/D7 C458
Y9 SdCmd
REXT 20 0.1uF/16V,X7R
Rref SDCDZ
1 2 SdCdZ 8
19 GndA
12MHz,20pF 24 VssA Gpio 31
R354

GND_PAD
7 Gnd1 NC2 6
X2S

MsData4
MsData5
MsData6
SdData0
SdData1
SdData2
SdData3
12.1K,1% 14 Gnd2 NC1 1
R355 270K
ns

+V5S VCC5_USB

33

30
29
27
25
28
26
12
C370 C371 UB6239_QFN32_AP
20pF/50V,NPO 20pF/50V,NPO
C0402 C0402
QFN32_P5 CARD_D6 TP37 FB39
CARD_D5 TP40
CARD_D4 TP41 300ohm/100MHz,1A
CARD_D3
CARD_D2 C408 C369 C407
CARD_D1 4.7uF/10V,X5R 4.7uF/10V,X5R 0.1uF/16V,X7R
CARD_D0 C0603

B B

VCC_CARD CARDREADER VCC_CARD


MXP019-A0-603X
cr19in3_rev
11 SD_VDD MS_VCC 4
C410 C413
9 16 0.1uF/16V,X7R 4.7uF/10V,X5R
SD_VSS1 MS_VSS1 C0402 C0603
21 SD_VSS3 MS_VSS2 2
C411 17 ns
SD_VSS2 MSINSZ
MS_INS 8
0.1uF/16V,X7R SDCDZ 20 15 SDWPD/MSBS
C0402 SDWPD/MSBS SD_CD MS_BS
22 SD_WP
SDCMD/D7 6 5 MS_CLK_R
SD_CMD MS_SCLK
MS_CLK_R 14 12 CARD_D0
SD_CLK MS_SDIO CARD_D1
MS_DATA1 13
CARD_D0 18 10 CARD_D2
CARD_D1 SD_DAT0 MS_DATA2 CARD_D3
19 SD_DAT1 MS_DATA3 7
CARD_D2 1
CARD_D3 SD_DAT2
3 SD_CD/DAT3

CD/WP/GND_SD2 24
CD/WP/GND_SD1 23
A A
MS_CLK_R R472 33 R0402 SDCLK

C412
10pF/50V,NPO
C0402
ns
CZC Technology
Title
Cardreader SD/MMC/MS
Resistors put near IC
Size Project Name Rev
CAP put near Socket A3 R48 C

Date: Thursday, April 22, 2010 Sheet 26 of 56


5 4 3 2 1
5 4 3 2 1

+V3.3S +V5S
+V5S 14,15,16,17,18,19,20,21,23,25,26,28,29,35,36,37,38
+V3.3AUX
+V3.3AUX 5,13,14,15,16,17,19,21,22,24,25,28,29,30,31,32,34,35
+V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,28,29,34,35,36,37,38,48
R361 4.7K ns LPC_AD3 +V5AUX
+V5AUX 17,19,22,24,28,29,32,33,34,35,36
R362 4.7K ns LPC_AD2 +V3.3S
R363 4.7K ns LPC_AD1 +V3.3AUX ECVCC
R364 4.7K ns LPC_AD0 FB34
R365 4.7K ns LPC_FRAME# 220ohm/100MHz,2A
R366 10K INT_SERIRQ R367 0 R0603 AVCC VDD
R368 10K PM_CLKRUN#
C376 C377 C378 C379 C380 C381
R369R370 C382 C383 C384
ECVCC 10UF/6.3V,X5R0.1uF/16V,X7R0.1uF/16V,X7R0.1uF/16V,X7R0.1uF/16V,X7R
C0805 0.1uF/16V,X7R 10UF/6.3V,X5R 0.1uF/16V,X7R 0.1uF/16V,X7R
D 0 0 C0805 D
C385

VDD
R372 4.7K VCC_POR# 0.1uF/16V,X7R
output

115

102
AGND R414 0 ns ECVCC

19
46
76
88

80
PM_EXTTS#0_EC 5,9

4
AVCC R373 0 U24

VCC1
VCC2
VCC3
VCC4
VCC5

AVCC
VDD
Reserved
14 EC_PWROFF# BTL_LED 29
C386 0.01uF/25V,X7R SLP_S3# GPIO34 EC_SMB1_CLK R374 4.7K
GPIO10/HGPIO00/LPCPD# 124 T5 ns
C387 0.01uF/25V,X7R SLP_S4# C388 0.1uF/16V,X7R 104 7 EC_SMB1_DAT R375 4.7K
VREF LRESET# LPC_RST# 15,21
2 BAT_DATA R376 4.7K
LCLK CLK_LPC_KBC 15
PCB_Mark0 97 3 BAT_CLK R377 4.7K
AD0/GPI90 LFRAME# LPC_FRAME# 13,21
PCB_Mark1 98 126 QKEY1 R378 10K
ECVCC AD1/GPI91 LAD0 LPC_AD0 13,21
31 BATTEP_BATIN# 99 AD2/GPI92 LAD1 127 LPC_AD1 13,21
R379 0 ns 100 128
22 EXP_CPPE# AD3/GPI93 LAD2 LPC_AD2 13,21
14,22,28,36 SLP_S3# R382 0 108 1
GPIO05 LAD3 LPC_AD3 13,21 T6 ns
14,22,28,29 SLP_S4# R383 0 96 125 +V5AUX
GPIO04 SERIRQ INT_SERIRQ 13,21
R394 R385 28 FAN_V R384 0 ns 101 8 PM_CLKRUN#
DA0/GPI94 CLKRUN#/GPIO11/HGPIO02 PM_CLKRUN# 14
U23 39 CC_SET 105 122 EC_RCIN-
DA1/GPI95 KBRST# T7 ns
1

W25X40BVSSIG R386 30 AC_IN 106 121 EC_A20GATE- KBSCLK R387 10K ns


10K 10K SOIC8_1P27_3P9 10K C389 GPI96 GA20 ECSCI# KBSDATA R388 10K ns
22 SLIDE_INTR# 107 GPI97 ECSCI# 29
SPI_CS# 1 0.1uF/16V,X7R EC_SMI# MSCLK R389 10K ns
CE# VDD 8 ns T8 GPIO64/SMI# 9
2

FRD# 2 HOLD# MSDATA R390 10K ns


WP# SO HOLD# 7 SPI_CLK 20 CRT_DET# 81 SWD/GPIO66 GPIO63/PWUREQ# 123 MAIN_PWROK 14,36
TPSCLK R391 10K
3 WP# SCK 6 GPIO71 74 V11S_ON 34
4 FWR# R392 1K TPSDAT R395 10K
VSS SI 5 14 PWR_BTN#
R393 1K
64 GPIO01 GPIO72 75
BADDR1
VR_ON 28,38
30 PWRSW#_XP 95 GPIO03 SOUT_CR/GPIO83/BADDR1 111
19,22 LIDSW# LIDSW# 93 28 MAIN_ON MAIN_ON 28,33,34,35,36
ns PM_RSMRST# GPIO06/HGPIO06 GPIO53 ns 0 R452
14,28,32,36 PM_RSMRST# 94 GPIO07/HGPIO07 GPIO36 15 DRAMRST_CNTRL 5,8
U25 21,29 BT_ON R436 1K 119 26 R397 0
GPIO23 GPIO51 V1_5_ON 33
W25X40BVSSIG 22 PWR_LED R398 0 109 24 GPIO47/JEN0#
SOP8_1P27_5P3 GPIO30 GPIO47/JEN0#
29 CHG_LED 120 GPIO31 SIN_CR/GPIO87 113 CHA_OFF 39
SPI_CS# 1 ECVCC
FRD# CE# VDD 8 HOLD#
ns T10
MSCLK
2 SO HOLD# 7 18 HDMI_HPD_EC 84 GPIO77 PSCLK3/GPIO25 12
WP# 3 SPI_CLK SHBM MSDATA
WP# SCK 6 FWR#
83 GPIO76/SHBM PSDAT3/GPIO12 13
4 VSS SI 5 21 HW_RATIO_OFF#2 82 GPIO75
22 AC_OFF AC_OFF 30
BADDR0 GPIO45 ALWAYS_ON
C 112 GPIO84/HGPIO01/BADDR0 GPIO40 16 ALWAYS_ON 32 C
TRIS# 110
SPI_CS# ECVCC GPIO82/HGPIO00/TRIS# 0 R422
1 1 8 8 21,29 HW_RATIO_OFF# 73 GPIO70 GPIO42/TCK 17 BT_LED# 29
FRD# 2 7 HOLD# 19 HW_OFF_BKLT# HW_OFF_BKLT# 6 20 ns 0 R381 IMVP_OK 14,19,28,38
+V3.3S WP# 2 7 SPI_CLK GPIO24/HGPIO01 GPIO43/TMS
3 3 6 6 GPIO44/TDI 21 T12 ns
4 5 FWR# 22 QKEY1 114 23 Panel_ID0
4 5 GPIO16/HGPIO04 GPIO46/TRST# Panel_ID1 0 R453
GPIO50/TDO 25 ECR_EN 19
32KXCLKIN 77 27
Q25 BIOS_CN1 32KXCLKO 32KX1/32KCLKIN GPIO52/RDY# VCC_POR# SUS_PWR_ACK_EC 14
ns T11 79 32KX2 VCC_POR# 85
1

2N7002K H2X4KZ 30
25 EC_AMP_Mute# CLKOUT/GPIO55
ns 2X4 2mm 54 SCANIN0
EC Output Signal! ns KBSIN0 SCANIN1
25 BTL_BEEP 62 B_PWM0/GPIO13 KBSIN1 55
2 3 EC_RCIN- 19 TTL_ADJ R399 0 118 56 SCANIN2
16 KB_RST# R400 0 ns A_PWM1/GPIO21 KBSIN2 SCANIN3
22 PWR_LED 32 A_PWM0 KBSIN3 57 KBCON1
28 FAN_V R407 0 28 FAN_TACH R401 0 ns 63 58 SCANIN4
R402 0 pwm out R403 0 TB1/GPIO14/HGPIO04 KBSIN4 SCANIN5 SCANIN0 C393 100pF/50V,NPO ns
31 TA1/GPIO56 KBSIN5 59 1 1
+V3.3S 14 PM_BATLOW# R451 0 ns 117 60 SCANIN6 2 SCANIN1 C400 100pF/50V,NPO ns
TA2/GPIO20 KBSIN6 SCANIN7 2 SCANIN2 C426 100pF/50V,NPO ns
KBSIN7 61 3 3
29 CAPLOCK# 65 53 SCANOUT0 4 SCANOUT0 C427 100pF/50V,NPO ns
GPIO32 KBSOUT0/JENK# SCANOUT1 4 SCANOUT1 C430 100pF/50V,NPO ns
29 NUMLOCK# 66 GPIO33 KBSOUT1/TCK 52 5 5
R720 Q26 51 SCANOUT2 6 SCANOUT2 C431 100pF/50V,NPO ns
KBSOUT2/TMS 6
1

2N7002K 68 50 SCANOUT3 7 SCANIN3 C428 100pF/50V,NPO ns


31,48 BAT_DATA GPIO62/SDA2 KBSOUT3/TDI 7
ns 67 49 SCANOUT4 8 SCANOUT3 C429 100pF/50V,NPO ns
31,48 BAT_CLK GPIO61/SCL2 KBSOUT4 8
10K EC Output Signal! 69 48 SCANOUT5 9 SCANOUT4 C438 100pF/50V,NPO ns
9,14,22 EC_SMB1_DAT SDA1 KBSOUT5/TDO 9
2 3 EC_A20GATE- 70 47 SCANOUT6 10 SCANOUT5 C439 100pF/50V,NPO ns
16 A20M# 9,14,22 EC_SMB1_CLK SCL1 KBSOUT6/RDY# 10
43 SCANOUT7 11 SCANOUT6 C432 100pF/50V,NPO ns
FRD# KBSOUT7 SCANOUT8 11 SCANOUT7 C433 100pF/50V,NPO ns
86 F_SDI KBSOUT8 42 12 12
R404 0 FWR# 87 41 SCANOUT9 13 SCANOUT8 C437 100pF/50V,NPO ns
F_SDO KBSOUT9 SCANOUT10 13 SCANIN4 C436 100pF/50V,NPO ns
KBSOUT10 40 26 26 14 14
+V3.3S SPI_CS# 90 39 SCANOUT11 25 15 SCANOUT9 C435 100pF/50V,NPO ns
F_CS0# KBSOUT11 SCANOUT12 25 15 SCANIN5 C434 100pF/50V,NPO ns
19 AUO_E-Color_EN 91 GPIO81 KBSOUT12/GPIO64 38 16 16
SPI_CLK R405 33 92 37 SCANOUT13 17 SCANIN6 C447 100pF/50V,NPO ns
F_SCK KBSOUT13/GPIO63 SCANOUT14 17 SCANOUT10 C448 100pF/50V,NPO ns
KBSOUT14/GPIO62 36 18 18
22 SLP_LED R473 0 KBSDATA 11 35 SCANOUT15 19 SCANOUT11 C440 100pF/50V,NPO ns
Q27 R474 0 KBSCLK PSDAT2/GPIO27 KBSOUT15/GPIO61/XOR_OUT 19 SCANIN7 C441 100pF/50V,NPO ns
22 GPU_LED 10 PSCLK2/GPIO26 KBSOUT16/GPIO60 34 T33 ns 20 20
1

2N7002K TPSDAT 71 33 21 SCANOUT12 C446 100pF/50V,NPO ns


29 TPSDAT PSDAT1 KBSOUT17/GPIO57/HGPIO03 T35 ns 21
EC Output Signal! TPSCLK 72 22 SCANOUT13 C445 100pF/50V,NPO ns
29 TPSCLK PSCLK1 22
B 23 SCANOUT14 C444 100pF/50V,NPO ns B
23
AGND

ECSCI# SCANOUT15 C443 100pF/50V,NPO ns

GND1
GND2
GND3
GND4
GND5
GND6
2 3 44 VCORF 24 24
16 SCI#
AC_PRESENT_EC 14,42
R408 0
103

5
18
45
78
89
116
ns C390 EC OD output 88502-24xx
+V3.3S
PM_EXTTS_DIMM 9 fpce24_1p0r
1uF/10V,X5R WPC8763L
LQFP128_P4 input
AGND R409 0
88502 Aces
Q28 R0402
1

2N7002K
ns
EC Output Signal! AGND
2 3 EC_SMI#
16 LPC_SMI#

R410 0

R411 100K R0402 IMVP_OK


R412 100K R0402 MAIN_ON +V3.3AUX R416 PM_RSMRST#
R413 100K R0402 ns V11S_ON 4.7K

3
R415 100K R0402 V1_5_ON
ECVCC 1 Q29
ECVCC
32KXCLKIN 2N2222
SOT23

2
GPIO47/JEN0#
SCANOUT0
R417 20M 32KXCLKO BADDR0 R418 R419 R420 R421 Fuction P.M2 P.M1 P.M0 R423 10K EC_PWROFF#
BADDR1 10K 10K 10K 10K ns
SHBM R0402 R0402 R0402 R0402 VerA 0 0 0
SCANOUT15 ns ns ns ns
R424 TRIS# VerB 0 0 1
Y5 33K Panel_ID0 PCB_Mark0
32.768kHz,20ppm,12.5pF Panel_ID1 PCB_Mark1 VerC 0 1 0
X4S67x15
*
A A
1 4 R425 R426 R427 R428 R429 R430 R431 VerD 0 1 1
R432 R433
C391 2 3 C392 10K 10K C1285 C1286
10K 10K 10K 10K 10K 10K 10K R0402 R0402 R434 R435 100pF/50V,NPO
5.6pF/50V,NPO 5.6pF/50V,NPO ns ns ns ns ns 100pF/50V,NPO 10K 10K
R0402 R0402

strap config

CZC Technology zw
Title
WPC8763L

Size Project Name Rev


Custom R48 C

Date: Thursday, April 22, 2010 Sheet 27 of 56


5 4 3 2 1
5 4 3 2 1

+V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,29,34,35,36,37,38,48
+V5S
+V5S 14,15,16,17,18,19,20,21,23,25,26,29,35,36,37,38
+V5AUX
+V5AUX 17,19,22,24,27,29,32,33,34,35,36
+V3.3AUX 5,13,14,15,16,17,19,21,22,24,25,27,29,30,31,32,34,35

+V3.3AUX
+V5AUX

FB37 100ohm/100MHz,3A
ns

FB36 100ohm/100MHz,3A Reserved


D ns D
C397
0.1uF/16V,X7R

R446 0 R0402_0
R447 0 R0402_0 6
CHK12 90ohm@100MHz,0.5A L4S2012 6
5 5
Wafer4P 1.25 4 3 4
15 USB_PN9 ns 4 8 8

6
Vfan 1 2 3
CPUFAN_CN2
15 USB_PP9 3 7 7
2 2
1 1 1
fan_tech_cn R484 0 ns Pin2 2 HWS4_1P25
FAN_V R485 0 ns Pin3 3 fpce6_1p0r
4 1 1 FFC6 1.0
FingerPrint
ns D27 D28 ns

5
EGA10603V05A1-B EGA10603V05A1-B

2 2
ns ns
87213-xxx0x-x
Aces
+V3.3S +V3.3AUX
+V5AUX

R439 FB41 100ohm/100MHz,3A


10K
+V5S ns
FB40 100ohm/100MHz,3A
C R440 1K C
FAN_TACH 27
FB38 100ohm/100MHz,3A ns C409
ns Vfan 0.1uF/16V,X7R
Q30 Wafer3P 1.25
BCP69T1

8
4 CPUFAN_CN1
C1 R470 0 R0402_0
3 E C 2 1
R487 0 Pin2 2 HWS3_1P25 R471 0 R0402_0 6
CHK13 90ohm@100MHz,0.5A L4S2012
B

R441 fan_tech_cn R488 0 Pin3 3 5


1K 4 3 4 CN_USB
15 USB_PN10
1

D24 1 2 ns 3 Wafer6P1
15 USB_PP10
R442 C394 C395 1N4148WS 2 hws6_1p0r

5
10 SOD323 1
0.1uF/16V,X7R 10UF/6.3V,X5R
R443 R444 C0805
1K 5.11K,1% 1 1

7
C396
0.1uF/16V,X7R D29 D30
EGA10603V05A1-B EGA10603V05A1-B ns
5

U26 2 2
1 ns ns
87213-xxx0x-x
+
4 +V3.3S Aces
3 R445
-
10K,1% FAN_V=3.30V,Vfan=5V
C398 LMV321DBV
FAN_V2.65V,Vfan=4V
2

0.1uF/16V,X7R R524
4.7K FAN_V=1.98V,Vfan=3V VDC1 TestP TPC60 ns
19,22,30,32,33,34,35,37,38,39 +VDC
R448 R449 200K V33AL1 TestP TPC60 ns
FAN_V 27 5,13,14,15,16,17,19,21,22,24,25,27,29,30,31,32,34,35 +V3.3AUX
B 100K C399 V5AL1 TestP TPC60 ns B
17,19,22,24,27,29,32,33,34,35,36 +V5Aux
R450
100K 4.7uF/10V,X5R V75 TestP TPC60 ns
10,11,33 +V0.75S
ns C0603
V5S1 TestP TPC60 ns
14,15,16,17,18,19,20,21,23,25,26,29,35,36,37,38 +V5S
V33S1 TestP TPC60 ns
5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,29,34,35,36,37,38,48 +V3.3S
V18S1 TestP TPC60 ns
7,15,16,34,36 +V1.8S
H26 H22 H23 H25 H21 H17 H19 H16 H18 H20 CPUCORE1 TestP TPC60 ns
7,38 +VCORE
BOSS BOSS BOSS BOSS BOSS BOSS BOSS BOSS BOSS BOSS
MH24X40X65 MH24X40X80 MH24X40X80 MH24X40X80 MH40X70T MH40X70T MH40X70T MH39X60 MH39X60 MH40X70T V15S1 TestP TPC60 ns
7,16,21,22,35,36 +V1.5S
ns ns ns ns ns ns ns ns
14,27,32,36 PM_RSMRST# RSMRST#1 TestP TPC30 ns

36 V1_1S_VTT_PWROK 1V1_PWROK1TestP TPC30 ns


1

DGPU DGPU GFX_PWROK1TestP TPC30 ns


37 GFX_PWROK
1

27,38 VR_ON IMVP_ON1 TestP TPC30 ns

MAIN_ON1 TestP TPC30 ns


27,33,34,35,36 MAIN_ON

14,19,27,38 IMVP_OK IMVP_OK1 TestP TPC30 ns

14,22,27,36 SLP_S3# SLP_S3#1 TestP TPC30 ns


H27 H10 H11 H12 H13 H14 H15
BOSS BOSS BOSS BOSS BOSS BOSS BOSS 14,22,27,29 SLP_S4# SLP_S4#1 TestP TPC30 ns
MH24_32X40X55 MH24X40X80 MH24X40X80 MH24X40X80 MH24X40X80 MH24X40X80 MH24X40X80
ns ns ns ns ns ns ns
BOT
A A
1

FD1 FD2 FD3 FD4 FD5 FD6 FD7 FD8


1

FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS


ns ns ns ns ns ns ns ns
CZC Technology zw
Title
USB Conn&USB camera
Size Project Name Rev
Custom R48 C

Date: Thursday, April 22, 2010 Sheet 28 of 56


5 4 3 2 1
+V5AUX 5 +V5AUX 17,19,22,24,27,28,32,33,34,35,36
4 3 2 1
+V3.3AUX 5,13,14,15,16,17,19,21,22,24,25,27,28,30,31,32,34,35
TPSDAT TPSCLK
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,34,35,36,37,38,48 +V5S
+V5S 14,15,16,17,18,19,20,21,23,25,26,28,35,36,37,38

3
+V5AUX Touch_CN
FFC4 1.0
fpce4_1p0r TP_C2 TP_D1 TP_D2
0.1uF/16V,X7R BAT54SPT BAT54SPT
1 1 TPSCLK C0402 SOT23 SOT23
6 6 2 2
C404 5 5 3 3 TPSDAT ns ns

2
0.1uF/16V,X7R
R461 U35 FB103 4 4
470K 6 IN 1 USB_VCC
120ohm/100MHz,2.5A
TPSCLK 27
D OUT
2 R456 20K
TPSDAT 27
+V5S +V5S
D
USB_OC ILIM C402
3 FAULT# GND 5
R1096 0 4 7 0.1uF/16V,X7R
14,22,27,28 SLP_S4# EN PAD Synaptics : TM-00268-008
TPS2553
TP_R1 330 LEFT_button
C403 QFN6_P65 R0402

3
0.1uF/16V,X7R TP_LSW1 Touch_BTN1

1
3 4 FFC4 1.0
TP_C5 TP_D3 fpce4_1p0r
1 2 D33 100pF/50V,NPO BAT54SPT 1 1
TMG-533-V ESDPAD_R0603 C0402 SOT23 2 2 6 6

2
USB_OC R1097 0 SWS6D50 ns ns 3 3 5 5
USB_OC_L4 15

5
6

2
ns 4 4
R1092 C1222
560K 1000pF/50V,X7R +V5S
R0402 ns
ns TP_R2 330 RIGHT_Button
R0402

3
USB1 TP_RSW1

1
USBC003 3 4
R1093 0 USB4H36IN TP_D4
R1094 0 USB_VCC 1 1 2 D32 TP_C4 BAT54SPT
VCC1 ESDPAD_R0603 100pF/50V,NPO SOT23
HOLE0 5

2
1 2 2 6 TMG-533-V ns C0402 ns
15 USB_PN8 -DATA1 HOLE1

5
6

2
4 3 SWS6D50
100uF/10V,TAN
15 USB_PP8 3 +DATA1 HOLE2 7
HOLE3 8
L4S2012
C C
CT7343_28

4 GND
90ohm@100MHz,0.5A C1224 +V5S
C1225

+
CHK11 0.1uF/16V,X7R
1 1
ns
+V3.3S
D72 D73
EGA10603V05A1-B EGA10603V05A1-B

2 2 C442
USB_GND2 R1095 0.1uF/16V,X7R
0 NUMLOCK# BL-HB334E-TRB NUM+ LED_R7 330
27 NUMLOCK# LED_NUM LED3_0802R
R0603
USB_GND2 ns 27 CAPLOCK# CAPLOCK# LED_CAP CAP+ LED_R8 330
BL-HB334E-TRB LED3_0802R
USB_GND2
HDD_LED# LED_HDD IDE+ LED_R10 330 R0402
13 SATA_LED#
BL-HB334E-TRB LED3_0802R

WIRELESS_LED# LED_WIRELS1 WIRE+ LED_R11 330 R0402


WIRELESS_LED# 21 WIRELESS_LED# BL-HB334E-TRB LED3_0802R

BT_LED# LED_BT BT+ LED_R12 499,1% R0402


27 BT_LED#
3

BT_R21 LED3_0802R BL-HJC34E-TRB


1K BT_Q6
R0402 2N7002K
WIRELESS_LED 1 SOT23 +V3.3AUX
21,27 HW_RATIO_OFF# +V3.3AUX
B B
AMBER
C1287
2

1000pF/50V,X7R

BT_R1
330 BT_R2
R0402 499,1%

BTL_LED+
R0402

CHG+
LED_BTL LED_CHG
BL-HB334E-TRB BL-HJC34E-TRB AMBER
+V3.3S +V3.3AUX LED3_0802R LED3_0802R
BT+ BT_C1 1000pF/50V,X7R
C0402
IDE+ BT_C2 1000pF/50V,X7R
C0402

3
FB18 FB4 BT_R3 CAP+ BT_C3 1000pF/50V,X7R
300ohm/100MHz,1A 300ohm/100MHz,1A 1K BT_Q1 C0402
ns R0402 2N7002K NUM+ BT_C4 1000pF/50V,X7R
BlueTooth Interface 27 BTL_LED BTL_LED 1 SOT23 C0402
7

WIRE+ BT_C5 1000pF/50V,X7R


C0402

3
1 BT_R4 BT_R5 BTL_LED+ BT_C6 1000pF/50V,X7R
2 1uF/10V,X5R BT_Q2 1K C0402
3 hws6_1p0r R0402 2N7002K R0402 CHG+ BT_C7 1000pF/50V,X7R
4 Wafer6P1 ns SOT23 1 C0402
A C310 C311 Blue_LED 5 Bluetooth BT_LED#
CHG_LED 27
A
10UF/6.3V,X5R 0.01uF/25V,X7R 21,27 BT_ON 6

2
Q2
MMBT3904-F BT_R6
1uF/10V,X5R CZC Technology
8

R437 0 R0402_0 ns R0402 zw


R438 0 R0402_0 1 R4 1K Blue_LED ns Title
CHK8 90ohm@100MHz,0.5A L4S2012 ns <Title>
15 USB_PN4 4 3
2

1 2 ns Size Project Name Rev


15 USB_PP4
R5 10K A3 R48 C
ns
Date: Thursday, April 22, 2010 Sheet 29 of 56
5 4 3 2 1

+VDC
+VDC 19,22,28,32,33,34,35,37,38,39
+V3.3AUX
+V3.3AUX 5,13,14,15,16,17,19,21,22,24,25,27,28,29,31,32,34
BATT+
BATT+ 31,39
Iac_P
Iac_P 39

D D

AD:90W 4.74A 30mohm


30V/20V 30V/20V
7.7A/21mohm +VDC 7.7A/21mohm BATT+
8.5nC 8.5nC
30V/20V SCHOTTKY SCHOTTKY
AD+ 9.1A/20mohm VIN+ 30V/1.4A 30V/1.4A
87343-02xx ACES 33nC
Q93 Q94 Q95
SI4435BDY SI4812BDY SI4812BDY
PWRCN1 R878
F3 SOIC8_1P27_3P9
1 4.74A 4.74A 1 8 1 8 8 1
1
2 7 2 7 7 2
7A FB86 3 6 3 6 6 3
120ohm/100MHz,2.5A 0.015,1%
2 2 S 5 S 5 5 S
D R1206 D D
G R879 G G
2pWafer R881 10 R882

4
HW2_2P5 FB87 R880 C1044 51K 10
R883 0 120ohm/100MHz,2.5A 51K 0.01uF/25V,X7R
R0805 C1292 2.2uF/6.3V,X7R
R884 0 C1045 C1046 SOT23 4700pF/50V,X7R C1047 CHR_PB 39
R0805 0.1uF/25V,X7R 0.1uF/25V,X7R Q96
C0603 C0603 DTB114EK
2 3 C0603
CHR_PA 39
C GND_AD C

R885

1
Layout:Use bridge connect GND_AD and GND GND_AD 51K

Iac_M 39

3
Q97
2N7002K
1 SOT23 Iac_P 39
27 AC_OFF

2
From EC
R886
51K

B +V3.3AUX B

+V3.3AUX AD+
2

D46

3
R887 BAT54SPT R888
20K,1% SOT23 Q98 15K
2N7002K
SOT23 1
3

PWRSW#_XP 27 C1048

2
R890 1000pF/50V,X7R
27 AC_IN R889 1K 10K
3

Q99 C1049 C1050


2N7002K 1000pF/50V,X7R 1000pF/50V,X7R R891
3--6.5V 1 SOT23 20K,1% C1293
22,32 PWRSWVCC_MBXP
4700pF/50V,X7R
2

R892
20K
R0402
A A

Boot to XP OS
CZC Technology
Title

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 30 of 56


5 4 3 2 1
5 4 3 2 1
BATT+
BATT+ 30,39

+V3.3AUX
+V3.3AUX 5,13,14,15,16,17,19,21,22,24,25,27,28,29,30,32,34

D D

GND_MBAT GND_MBAT

C1126 C1125
0.1uF/25V,X7R 0.1uF/25V,X7R
GND_MBAT C1294 C1295 C0603 C0603
4700pF/50V,X7R 4700pF/50V,X7R
BATT+
FB94
F4
8
7A FB88
C14468 ALLTOP FS1206
7 VBAT_F P FB89
BATT+

C BATT+ 6 120ohm/100MHz,2.5A
C
BATCON1 5 BAT_DATA_R R893 100,1%
SDAT BAT_DATA 27,48
BATTCN
bat7r_in 4 BAT_CLK_R R894 100,1% BATTEP_BATIN#
SCLK BAT_CLK 27,48
TEMP 3 BAT_IN# R895 100,1% 0.5-2.5V Battery OK
BATTEP_BATIN# 27
BAT_IN#
2 C1051 <0.5V or >2.5V Battery Fail
GND 1000pF/50V,X7R R896
1 10K
GND
R897 ns 0
R0603
9

R898 ns 0 +V3.3AUX
R0603

GND_MBAT

Use bridge connect GND_MBAT and GND

B B
D47 D48
2 +V3.3AUX 2 +V3.3AUX
BAT_CLK 3 BAT_DATA 3

1 C1052 1 C1053
0.1uF/16V,X7R 0.1uF/16V,X7R
C0402 C0402
BAT54SPT BAT54SPT
SOT23 SOT23

A A

CZC Technology
Title

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 31 of 56


5 4 3 2 1
+VDC
+VDC 19,22,28,30,33,34,35,37,38,39
+V3.3AUX
+V3.3AUX 5,13,14,15,16,17,19,21,22,24,25,27,28,29,30,31,34,35
+V5AUX
+V5AUX 17,19,22,24,27,28,29,33,34,35,36

+VDC

D D
C1061 30V/25V
22pF/50V,NPO 7A/30mohm

5
6
7
8
8.7nC C1054 C1055 C1056
10uF/25V,X5R 0.1uF/25V,X7R 1000pF/50V,X7R

D
GND_AL
C1206 C0603
3V_HDR 4 Q156

G
C1062 SI4800BDY
1000pF/50V,X7R

S
3
2
1
GND_AL
L22
3V_LX 3V_LX 3V_OUT
+V3.3AUX
GND_AL 3.3uH/6A
CKS2D66 C1273 CC:7A
17.6mohm 220uF/6.3V,FPCAP
OC:12A

5
6
7
8
+ CESD66 +
R899 C1057

D
C1058 100K 150uF/6.3V/15mohm/Panasonic
1000pF/50V,X7R 3V_LDR 4 Q157 CT7343_19

G
SI4812BDY ns
R900

S
30V/20V

CS_V3N

CS_V3P

AUX_POK

3
2
1
7.7A/21mohm
8.5nC 36.5K,1%
SCHOTTKY
30V/1.4A <50mV R901 CO-LAYOUT
GND_AL 47
+VDC
C1059

25

24

23

22

21

20

19
0.22uF/16V,X5R

CS2P
GNDA0

VSET2

POK2

LX2

HDR2
CS2N
R902 C1060
0 0.01uF/25V,X7R

CS_V3N
CS_V3P
V3A_ON 1 18
2010-1-7 ON/SKIP2 BST2
5V_VIN 2 17
VIN LDR2
C 2.75V
5V_VREF 3 VREF U55 VDDP 16
5V_LDO C
C1063 4 OZ815LN 15
0.01uF/25V,X7R <400KHz TSET QFN24_P5 GNDP
5V_LDO R903 10 5 14
C1064 VDDA LDR1 C1065
0.1uF/16V,X7R R904 V5A_ON 6 13 1uF/10V,X5R
GND_AL 24.9K,1% ON/SKIP1 BST1

VSET1

HDR1
GND_AL C1066

CS1N

POK1
CS1P

LX1
1uF/10V,X5R
+VDC
C1067
0.22uF/16V,X5R
7

10

11

12
R905
82.5K,1% GND_AL C1068 C1071 C1069

1
2.5V 5V_VSET 10uF/25V,X5R 0.1uF/25V,X7R 1000pF/50V,X7R
AUX_POK
D1 D1 C1206 C0603
3V_VSET 1.68V 5V_HDR 8
CS_V5N

CS_V5P

G1
S1
C1070
R906 1000pF/50V,X7R 5V_LX 5 7
169K,1% L23
6 5V_LX 5V_OUT
+V5AUX
D2 4.7UH/5.5A
GND_AL 5V_LDR 3 CKS2D66 CC:5A
C1078 32mohm
GND_AL 1000pF/50V,X7R G2 S2 Q101 C1274 OC:10A
GND_AL FDS6900AS R907 220uF/6.3V,FPCAP

4
100K + CESD66 +
C1072
30V/20V 150uF/6.3V/15mohm/Panasonic
6.9A/34mohm R908 CT7343_19
GND_AL 6.1nC ns
8.2A/28mohm
C1077 5.8nC 20K,1% For USB

B B
22pF/50V,NPO 2.3A
<50mV R911 CO-LAYOUT
47

C1074
0.01uF/25V,X7R

CS_V5N
CS_V5P
D49
BAT54C
2 SOT23
27 ALWAYS_ON
L C*R1*R2
3 R909 1K R910 2.2K V5A_ON =
RL R1+R2
1 R912 4.7K V3A_ON 0.22ms
39 ACAV
D50 1N4148WS
C1073 D51 SOD323
0.01uF/25V,X7R BZT52C3V6S-F/3.6V 0.5ms
D52
SOD323 C1075 C1076
0.1uF/16V,X7R 0.1uF/16V,X7R
22,30 PWRSWVCC_MBXP
+V3.3AUX
1N4148WS
SOD323 +V5AUX

R913
10K
R916
+V3.3AUX R914 PM_RSMRST# 14,27,28,36
34K,1%
0
3

R0603
Q102
2N7002K GND_AL

A A
R915 1 SOT23
20K,1%
2
3

2010-1-7
Q103
2N7002K
AUX_POK 1 SOT23
2

C1079
1uF/10V,X5R
C0402
CZC Technology Quaf
Title
Power +V3.3Aux +V5Aux +10V

Size Project Name Rev


C R48 C

Date: Thursday, April 22, 2010 Sheet 32 of 56


5 4 3 2 +V5AUX 1 +V5AUX 17,19,22,24,27,28,29,32,34,35
+VDC
+VDC 19,22,28,30,32,34,35,37,38,39

+V0.75S 10,11,28

+V1.5 5,7,8,10,11,35

GND_DDR GND_DDR

D D
+VDC
C1092 C1091
1000pF/50V,X7R 22pF/50V,NPO
C0402 C0402
C1082
R917 C1080 C1081 C0402
Vout=2.75*R2/(Rh+Rl) 82.5K,1% 30V/25V 10uF/25V,X5R 0.1uF/25V,X7R 1000pF/50V,X7R
2010-3-16 R0402 V1_5_PWROK 36 7A/30mohm C1206 C0603
8.7nC
1.8V 34K/64.9K

M_CSN
1.5V

M_CSP

5
6
7
8
D
1.5V 53.6K/64.9K V2
4 Q158 TPC60
R919 SI4800BDY ns

G
C1083 105K,1%

1
1000pF/50V,X7R R0402 L24

3
2
1
+VDC C0402 DDR_LX DDR_LX
+V1.5
2.2uH/8A

25

24

23

22

21

20

19
CKS2D66
GND_DDR GND_DDR C1085 +V5AUX 11.5mohm

CSP

LX
VSET
PAD

CSN

PGD

HDR
R920 0.22uF/16V,X5R CC:7A
1K C0402 R921
OC:14A

5
6
7
8
R0402 M_DDR_ON 1 18 D53 100K
ON/SKIP BST 1N4148WS R0402 C1275

D
0.6ms SOD323 R922 220uF/6.3V,FPCAP
GND_DDR C1084 2 17 4 Q159 R0402 + CESD66 + C1086
0.01uF/25V,X7R VIN LDR SI4812BDY 220uF/2.5V,POSCAP

G
C C0402 CT7343_19
C

S
2.75V <400KHz 3 U56 16 30V/20V 51.1K,1% ns
VREF VDDP +V5AUX

3
2
1
OZ812LN 7.7A/21mohm
8.5nC <50mV R923
4 QFN24_P5 15 SCHOTTKY 47
C1087 TSET GNDP C1088 30V/1.4A R0402
0.1uF/16V,X7R R0402 1uF/10V,X5R C1089
C0402 +V5AUX 5 14 C0402 5600pF/50V,X7R
VDDA VSS2 CO-LAYOUT
10
GND_DDR R924 M_VTT_ON 6 13
ON_VTT VSS1

M_CSN
M_CSP
VTTREF

C1090

VDDQ1

VDDQ2
1uF/10V,X5R VTTS

VTT1

VTT2
C0402
7

10

11

12
GND_DDR
10,11 M_VREF +V0.75S

+V1.5 CC:2A
C1094 C1095 C1096 OC:2.5A
C1093 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
1uF/10V,X5R C1097 C1099 C0805 C0805 C0805
C0402 1000pF/50V,X7R 10uF/6.3V,X5R
C0402 C0805
L C*R1*R2
=
GND_DDR GND_DDR C1098
B C0805
RL R1+R2 B
10uF/6.3V,X5R

47
R925
R0402 R926

0
R0603

GND_DDR

0 R0402M_DDR_ON
27 V1_5_ON
R928

ns
27,28,34,35,36 MAIN_ON 0 R0402 M_VTT_ON
R930

A 5,36 V1_1S1_5S_PWROK A
R1159
100K
R0402
CZC Technology
Title

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 33 of 56


5 4 3 2 1
+V5AUX
+V5AUX 17,19,22,24,27,28,29,32,33,35,36
+V1.5S
+V1.5S 7,16,21,22,28,35,36
+VDC
+VDC +VDC 19,22,28,30,32,33,35,37,38,39
al conectar la fuente se escucha +V1.05S
+V1.05S
el zumbido de la frecuencia, lo C1214
10uF/25V,X5R
C1100
10uF/25V,X5R
C1101
0.1uF/25V,X7R
C1102
1000pF/50V,X7R
+V1.8S 7,15,16,28,36
que me hace sospechar de un 30V/20V
C1206 C1206 C0603
+V3.3AUX 5,13,14,15,16,17,19,21,22,24,25,27,28

D filtro. o no se? necesito un soga 30A/10mohm


8.8nC
+V1.1S 7,13,14,16,17,35,36 D
Ausente

5
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,

D
GND_IC
HDR2B 4 Q107
SiR462DP

G
PWRPAK_SO8

S
C1106 L25

3
2
1
C1108 22pF/50V,NPO V1_1_LX V1_1_LX
1000pF/50V,X7R
+V1.1S
Q108 Q109 0.68uH
SiR466DP SiR466DP CKS2D100

CS1_1N

CS1_1P

5
PWRPAK_SO8 PWRPAK_SO8 CC:25A
D68

D
+ + 2010-1-7
C1104 SS3P4 R936 C1103 C1215 OC:30A
0.1uF/16V,X7R 4 4 100K,1%R1098 220uF/2V/15mohm 220uF/2V/15mohm
ns CT7343_19 CT7343_19

G
LDR2B

12

11

10

9
100K,1%

S
5V

CSP

LX
CSN

HDR

3
2
1

3
2
1
D54
1N4148WS
1.1V 13 8 R934
VSET BST 47
R937 VREF11 14 U57 7 30V/20V 2010-1-7 C1105
105K,1% 2.75V VRFE OZ8111LN LDR 40A/5.1mohm
TSET11 15 6 21.5nC
R938 TSET GNDP 3300pF/50V,X7R
8111PR 10 16 5 8111PR +V5AUX
VDDA VDDP

ON/SKIP
C C
GNDA1

17 2010-1-14

PGD
GNDA
Presente
VIN

C1107 R939 C1109

CS1_1N
CS1_1P
1000pF/50V,X7R 73.2K,1% 1uF/10V,X5R C1110
1

4
1uF/10V,X5R

+V3.3S
cuando enciendo
GND_IC GND_IC GND_IC
R1073
aparece el +V3.3S y del
10K otro lado de la pull up
2010-3-16
C1276
R940
100K
pasa
V1_1S_PWROK 35,36 a 7 mV, no tengo

VREF11 TSET11
3300pF/50V,X7R los 3.3 eso esta bien???
R1187 V1_1S_ON
0 +VDC

R1186
100K,1% C1296
ns 0.1uF/16V,X7R Presente
ns al presionar pwr cambia +V3.3AUX

de estado a HI 1A
GND_IC
B VREF11
R941
C1111 B
10uF/6.3V,X5R
C0805
0 +V1.8S
C1112
U58

9
0.1uF/16V,X7R
C0402

PAD
+V5AUX 5 4
VIN VOUT2
GND_IC
6 3 1A CC:1A
VDDA VOUT1
GND_IC C1116 7 2
1uF/10V,X5R POK FB C1113 C1114 C1115
8 1 47pF/50V,NPO R942 C0805 C0805
EN GND ns 32.4K,1% 10uF/6.3V,X5R 10uF/6.3V,X5R

OZ8033GN
SOIC8_1P27_3P9G

36 V1_8S_PWROK
27,28,33,35,36 MAIN_ON R1160 0 R0402_0 R944 V1_8S_ON R945
1K 0.1ms 24.9K,1%
Vout=0.8 * (1+Rh/RL)
27 V11S_ON 0 R0402_0 R947 V1_1S_ON V1_8S_ON R948 0
R946 4.7K 0.5ms R0402_0

A D55 A
1N4148WS
SOD323
C1117 C1118
0.1uF/16V,X7R 0.1uF/16V,X7R
CZC Technology
Title

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 34 of 56


5 4 3 2 1
+V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,36,37,38,4
+V5S
+V5S 14,15,16,17,18,19,20,21,23,25,26,28,29,36,37,38
+V3.3AUX
+V3.3AUX 5,13,14,15,16,17,19,21,22,24,25,27,28,29,30,31,32,34
+V5AUX
+V5AUX 17,19,22,24,27,28,29,32,33,34,36
+VDCS
VDDC
VDDC 36,43
10V
+VDC
+VDC 19,22,28,30,32,33,34,37,38,39

+V1.1S 7,13,14,16,17,34,36

+V1.5 5,7,8,10,11,33

+V5AUX +V3.3AUX +V1.5 +V1.5S 7,16,21,22,28,36

D 1.8V_REG
1.8V_REG 36,42,43,44
D
+V1.1S_VTT 5,7,12,16,17,36
D56 D57
SOD323 SOD323 Q111 MVDDQ
MVDDQ 36,43,45,46,47
Q112
Q113 SI4800BDY SI4800BDY 1.0V_REG
1.0V_REG 36,41,42,43,44

5
6
7
8

5
6
7
8

5
6
7
8
DTB114EK SI4800BDY 30V/25V 1N4148WS 30V/25V 1N4148WS 30V/25V
SOT23 7A/30mohm 7A/30mohm 7A/30mohm

D
Q110 R950 8.7nC 8.7nC 8.7nC
2 3 R951 1K 0.1ms 4 0.2ms 4 0.2ms 4
+VDC

G
10K 20K,1% 20K,1%

S
R949 R952

3
2
1

3
2
1

3
2
1
1

C1119 C1120
R953 C1121
10K C1290 2A 0.01uF/25V,X7R 2A 0.01uF/25V,X7R 2A
+V5S +V3.3S +V1.5S
3

0.01uF/25V,X7R 0.1uF/25V,X7R
Q114
2N7002K
0 1 SOT23
27,28,33,34,36 MAIN_ON
R955 C1122 C1123 C1124
2010-1-7 1uF/10V,X5R
2

1uF/10V,X5R 1uF/10V,X5R

C no esta presente +V1.5 C


+V1.1S +V1.1S

D67
SOD323
Q163 DGPU Q161 Q162
SiR466DP SiR466DP SiR466DP
5

5
DTB114EK PWRPAK_SO8 30V/20V DTB114EK PWRPAK_SO8 30V/20V 1N4148WS PWRPAK_SO8 30V/20V
SOT23 40A/5.1mohm SOT23 40A/5.1mohm DGPU 40A/5.1mohm
D

D
Q160 R1061 21.5nC Q164 R1063 21.5nC 21.5nC
2 3 R1060 1K 0.1ms 4 2 3 R1062 1K 0.1ms 4 0.2ms 4
+VDC +VDC
G

G
DGPU DGPU
34K,1% 10K 20K,1%
S

S
DGPU
DGPU R1059
3
2
1

3
2
1

3
2
1
DGPU
1

1
C1217
R1064 R1065 C1218
10K C1216 C1288 10K C1289 0.01uF/25V,X7R 2A
+V1.1S_VTT VDDC MVDDQ
3

3
0.1uF/25V,X7R DGPU 0.01uF/25V,X7R 0.1uF/25V,X7R
Q165 0.01uF/25V,X7R Q166 DGPU DGPU DGPU
2N7002K 2N7002K
0 1 SOT23 0 1 SOT23
34,36 V1_1S_PWROK 16,36 VDDC_VR_EN
R1066 C1219 R1067 DGPU 2010-1-7 C1220 C1221
2010-1-7 1uF/10V,X5R DGPU 1uF/10V,X5R
2

2
C1291 1uF/10V,X5R
0.1uF/16V,X7R DGPU DGPU
ns
2010-1-8

B B
+V1.5

+V3.3AUX
2A

C1162 1A
10uF/6.3V,X5R
C0805 C1163
DGPU 1.0V_REG 10uF/6.3V,X5R
C0805
U61 1.8V_REG
9

DGPU
CC:1A
PAD

U62

9
+V5AUX 5 4
VIN VOUT2

PAD
6 3 +V5AUX 5 4
VDDA VOUT1 VIN VOUT2
C1167 7 2 6 3 1A CC:1A
1uF/10V,X5R POK FB C1164 C1165 C1166 VDDA VOUT1
DGPU 8 1 47pF/50V,NPO R1008 C0805 C0805 C1171 7 2
EN GND ns 6.98K,1% 10uF/6.3V,X5R 10uF/6.3V,X5R 1uF/10V,X5R POK FB C1168 C1169 C1170
DGPU DGPU DGPU DGPU 8 1 47pF/50V,NPO R1009 C0805 C0805
EN GND
OZ8033GN ns 32.4K,1% 10uF/6.3V,X5R 10uF/6.3V,X5R
SOIC8_1P27_3P9G DGPU DGPU DGPU
OZ8033GN
DGPU SOIC8_1P27_3P9G
36 1_0V_REG_PWROK R1010 DGPU
24.9K,1%
DGPU 36 1_8V_REG_PWROK R1011
Vout=0.8 * (1+Rh/RL)
24.9K,1%
36 VDDC_PWROK R1012 2.2K Vout=0.8 * (1+Rh/RL) DGPU

DGPU 0.22ms 36 VDDC_PWROK R1013 4.7K


0.47ms
2010-1-7 DGPU
C1271
0.1uF/16V,X7R C1272

A DGPU 2010-1-7 0.1uF/16V,X7R


DGPU A

CZC Technology
Title

Size Project Name Rev


A2 R48 C

Date: Thursday, April 22, 2010 Sheet 35 of 56

5 4 3 2 1
5 4 3 2 1
+V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,37,38,48
+V5S
+V5S 14,15,16,17,18,19,20,21,23,25,26,28,29,35,37,38
+V5AUX
+V5AUX 17,19,22,24,27,28,29,32,33,34,35
VDDC
VDDC 35,43
+V1.5S
+V1.5S 7,16,21,22,28,35
+V1.1S 7,13,14,16,17,34,35
1.8V_REG 35,42,43,44
+V1.8S 7,15,16,28,34
1.0V_REG 35,41,42,43,44
+V1.1S_VTT 5,7,12,16,17,35
MVDDQ
MVDDQ 35,43,45,46,47
VDDR3
VDDR3 16,41,42,43,45,48

+V5S +V3.3S +V1.8S +V1.1S

D D
MVDDQ 1.8V_REG 1.0V_REG

R961 R962 R963 R964


47 47 47 47 R997 R998 R999
R0603 R0603 R0603 R0603 47 47 47
R0603 R0603 R0603
DGPU DGPU DGPU

3
+V5AUX Q118 Q119 Q120 Q121
2N7002K 2N7002K 2N7002K 2N7002K +V5AUX Q136 Q137 Q138
1 SOT23 1 SOT23 1 SOT23 1 SOT23 2N7002K 2N7002K 2N7002K
1 SOT23 1 SOT23 1 SOT23

2
DGPU DGPU DGPU

2
R966
100K R1004
100K
DGPU

DISCHARGE
GFX_DISCHARGE
3

3
Q123
2N7002K Q144
0 R0402_0 1 SOT23 +V1.1S_VTT +V1.5S 2N7002K
27,28,33,34,35 MAIN_ON
R968 0 1 SOT23
16,35 VDDC_VR_EN
R1007 DGPU
2

DGPU

2
R969 R970
47 47
R0603 R0603

C C
3

3
Q124 Q125
2N7002K 2N7002K
1 SOT23 1 SOT23
2

D79
1N4148WS
34,35 V1_1S_PWROK V1_1S1_5S_PWROK 5,33

5,33 V1_5S_PWROK

+V5AUX
+V5AUX

+V3.3S

R0402 VDDR3
R929 R0402
34K,1% R1069
R1170 34K,1%
10K DGPU R1173
10K +V3.3S
V1_1S_VTT_PWROK 28 DGPU
VDDC_PWROK 35
R932
3

R1070

3
1 Q105 R973
+V1.1S_VTT
3

MMBT3904-F 1 Q167 10K


VDDC

3
3.83K,1% SOT23 Q106 MMBT3904-F
B B
2

R0402 2N7002K 3.83K,1% SOT23 Q168

2
1 SOT23 R0402 DGPU 2N7002K 2010-1-7 R974 0 R0402_0
33 V1_5_PWROK MAIN_PWROK 14,27
R933 DGPU 1 SOT23
10K R1071 DGPU
2

R0402 10K R976 0 R0402_0


34 V1_8S_PWROK MAIN_PWROK -- VR_ON 99--300ms Delay

2
R0402
DGPU
14,22,27,28 SLP_S3# D58 1N4148WS

D59 1N4148WS
14,27,28,32 PM_RSMRST#

28 V1_1S_VTT_PWROK D80 1N4148WS

5,33 V1_1S1_5S_PWROK D78 1N4148WS

D81
+V5AUX 1N4148WS
+V5AUX
DGPU

+V3.3S
R0402
R1161 R0402
34K,1% R1171 VDDR3
R1162 34K,1%
10K DGPU 2010-1-7

V1_5S_PWROK 5,33
MVDDQ_PWROK R1172
10K
3

DGPU
3

R1163 8.2K 1 Q172


+V1.5S
3

MMBT3904-F R1174 8.2K 1 Q177


MVDDQ
3

SOT23 Q173 MMBT3904-F MVDDQ_PWROK R1175 0 R0402_0 MADISON_POWOK 16,42


2

2N7002K DGPU SOT23 Q178


2

1 SOT23 DGPU 2N7002K


R1164 1 SOT23

A 10K R1176 DGPU 35 1_0V_REG_PWROK R1177 0 R0402_0


A
2

R0402 10K
2

R0402
DGPU
35 1_8V_REG_PWROK R1178 0 R0402_0

CZC Technology
Title

Size Project Name Rev


A2 R48 C

Date: Thursday, April 22, 2010 Sheet 36 of 56

5 4 3 2 1
5 4 3 2 1
+V3.3S
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,38,48
+V5S
+V5S 14,15,16,17,18,19,20,21,23,25,26,28,29,35,36,38
+VDC
+VDC 19,22,28,30,32,33,34,35,38,39
UMA Soft star
GND_GFX
+VCC_GFXCORE 7
22pF/50V,NPO
C1127

GND_GFX CSP_GFX 1A
+V3.3S +VDC

D CSN_GFX 1000pF/50V,X7R
D
GND_GFX
C1130 C1128 C1129 C1131 C1132 C1133 C1134
1000pF/50V,X7R 0.01uF/25V,X7R UMA R977 10uF/25V,X5R 0.1uF/25V,X7R 1000pF/50V,X7R 10uF/25V,X5R
UMA RG UMA 2.2K C1206 C0603 C1206
Set Loadline R978 UMA UMA UMA UMA UMA
-7mV/A UMA1K,1%
UMA 1K,1%
TO GPU
7 VCC_AXG_SENSE
GFX_PWROK 28

GFX_SLEW

GFX_COMP
30V/20V

5
C1135 R979 30A/10mohm
330pF/50V,X7R 3.83K 8.8nC

D
ns UMA
C1136 GFX_HDR 4 Q128

GFX_RSP
GND_GFX
SiR462DP

G
24

23

22

21

20

19

18

17
PWRPAK_SO8

S
2200pF/25V,X7R C1138 UMA UMA L26

RSP

CSP

COMP

LX
CSN

SLEW

PG6

HDR

3
2
1
C1137 UMA GFX_LX GFX_LX VGFX 18A
330pF/50V,X7R 25 16 GFX_BST +VCC_GFXCORE
RSP_LL BST 0.56uH/25A

5
ns Q129 Q115 CKS2D100
1uF/10V,X5R SiR466DP SiR466DP 1.8mΩ

D
7 VSS_AXG_SENSE 26 RSN GNDP 15 CC:18A
PWRPAK_SO8 PWRPAK_SO8
GFX_IMON_R 27 14 GFX_LDR 4 ns 4 UMA + ESR=15mohm + ESR=15mohm OC:26A
IMON U59 LDR C1139 C1140

G
R980 GFX_VDD OZ8291 UMA R982 220uF/2V/15mohm
220uF/2V/15mohm

S
+V5S 28 VDDA VDDP 13 +V5S
10 120℃ QFN32_P5 R981 47 CT7343_19 CT7343_19

3
2
1

3
2
1
UMA 29 12 30V/20V 100K UMA
VR_TTb UMA VR_ON 40A/5.1mohm UMA UMA UMA
HW Pull Up R1099
C C1141
1uF/10V,X5R
30 CLK_ENb VID6 11 C1142
1uF/10V,X5R
21.5nC ns
100K,1% C
UMA GFX_VREF 31 10 UMA
VREF VID5
GND_GFX GFX_VBT 32 9 C1143
VBT VID4

DSLP
TSET

GFX_EN
VID0

VID1

VID2

VID3
OVP

33 PAD VIN 3300pF/50V,X7R

CSN_GFX
CSP_GFX
GFX_VREF 1

8
1.5V C1144 UMA
0.01uF/25V,X7R R1075
UMA
0
GFXVR_EN 7
C1145 R1153 R983 UMA
1uF/10V,X5R 51.1K,1% 24.9K,1% GFXVR_VID_6 7
UMA UMA UMA GND_GFX

OVP 1.7V 1.2V


GFXVR_VID_5 7
GND_GFX 300KHz
GFXVR_VID_4 7
R984
R1154 100K,1%
GFXVR_VID_3 7
100K,1% UMA C1277
0.1uF/16V,X7R GFX_IN R987
2.2K
GFXVR_VID_2 7
UMA

B GFXVR_VID_1 7
R986 B
GND_GFX GND_GFX
C1146 R985
10K 0
GFXVR_VID_0 7
0.01uF/25V,X7R UMA R0603
UMA UMA

GND_GFX
GND_GFX GND_GFX
+VDC
2010-3-16
GFX_IMON_R 0 R1180
GFX_IMON 7
UMA
GFX CORE Debug
R1181
34K,1% C1281
UMA 1000pF/50V,X7R VID6 VID5 VID4 VID3 VID2 VID1 VID0 Vout
UMA
0 0 1 1 0 0 0 1.2000V
GND_GFXGND_GFX

0 1 1 0 0 0 0 0.9000V

A A

CZC Technology
Title

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 37 of 56


5 4 3 2 1
GND_CPU +V5S 14,15,16,17,18,19,20,21,23,25,26,28,29,35,36,37
+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,48
+VDC 19,22,28,30,32,33,34,35,37,39
Set Loadline
+VCORE 7,28
-1.9mV/A
+V1.1S 7,13,14,16,17,34,35,36
TO CPU
7 VCC_SENSE
C1173
C1172 22pF/50V,NPO
C1174 R1014 1000pF/50V,X7R +VDC
330pF/50V,X7R 1.5K,1%

CSN_CPU

CSP_CPU
ns GND_CPU
D GND_CPU CORE_RSP
+V3.3S D
2010-3-17 Soft star C1177 C1178 C1179 C1180
C1206 C1206 C0603 C0402
C1175 C1176 1000pF/50V,X7R 30V/20V 10uF/25V,X5R 10uF/25V,X5R 0.1uF/25V,X7R1000pF/50V,X7R
330pF/50V,X7R 2200pF/25V,X7R RG C1182 R1015 30A/10mohm
ns R1016 C1181 2.2K 8.8nC
1K,1% 0.01uF/25V,X7R
7 VSS_SENSE

5
IMVP_OK 14,19,27,28

D
CORE_IMON_R CORE_HDR1 4 Q145

30

29

28

27

26

25

24

23

22

21
SiR462DP

G
PWRPAK_SO8

S
RSP

CSP

COMP
NC4

NC3

RSP_LL

CSN

SLEW

PG65

NC2
L28

3
2
1
+V5S R1017 CORE_LX1 VCORE
10 31 20 C1184 +VCORE
RSN HDR1 0.56uH/25A
CKS2D100
32 IMON BST1 19 CC:36A

5
C1183 Q146 Q147 1.8mohm
1uF/10V,X5R CORE_VDD 1uF/10V,X5R CORE_LX1 SiR466DP SiR466DP OC:50A

D
2010-1-7 33 18
VDDA LX1 PWRPAK_SO8 PWRPAK_SO8 C1186 C1188
34 17 CORE_LDR1 4 ns 4 R1018 + + 220uF/2.5V,POSCAP
+ + 220uF/2.5V,POSCAP
GND_CPU 5 H_PROCHOT# VR_TTb LDR1 51.1K,1% C1185 C1187 CT7343_19

G
220uF/2.5V,POSCAP220uF/2.5V,POSCAP

S
12 CLKEN# 35 CLK_ENb GNDP 16
U63 1uF/10V,X5R 30V/20V

3
2
1

3
2
1
CORE_VREF 36 OZ8292LN 15 C1189 40A/5.1mohm
VREF VDDP
C CORE_VBT 37 14
+V5S 21.5nC
RT1 R1134 C

t
VBT LDR2
R1019 38 13 C1191 2010-1-7 100K,1% 100K,1%
300KHz OVP LX2
36.5K,1%
CORE_TSET 39 12
C1192 TSET BST2
1uF/10V,X5R 1.1V +V5S 40 11 1uF/10V,X5R
DSLP HDR2

VR_ON
R1039 R1020
R1021 41 C1190
VID0

VID1

VID2

VID3

VID4

VID5

2.2K GNDA VID6

NC1
VIN

100K,1% 47

2010-3-16 +VDC 0.012uF/50V,X7R


1

10
C1197
GND_CPU GND_CPU 0.01uF/25V,X7R
C1193 C1194 C1195 C1196 2010-3-16
CORE_IN

C1206 C1206 C0603 C0402

CSN_CPU
CSP_CPU
GND_CPU 10uF/25V,X5R 10uF/25V,X5R 0.1uF/25V,X7R1000pF/50V,X7R

+VDC 30V/20V
R1022 30A/10mohm
10K,1% 8.8nC
7 H_VID0 R1023

5
51.1K,1%

D
7 H_VID1
CORE_HDR2 4 Q148
SiR462DP

G
B PWRPAK_SO8 B

S
7 H_VID2
L29

3
2
1
CORE_LX2 CORE_LX2
7 H_VID3 0.56uH/25A
CKS2D100

5
7 H_VID4 Q149 Q150 1.8mohm
CORE_VREF CORE_TSET SiR466DP SiR466DP

D
R1155 PWRPAK_SO8 PWRPAK_SO8
0 7 H_VID5 CORE_LDR2 4 ns 4
G

G
S

S
R1156 7 H_VID6 30V/20V
3
2
1

3
2
1
100K,1% C1278 40A/5.1mohm
ns 0.1uF/16V,X7R 21.5nC
ns 27,28 VR_ON R1083 0 CORE_EN

GND_CPU

CORE_IMON_R 0 R1183
CORE_IMON 7

R1024
A R1184 A
34K,1% C1282
1000pF/50V,X7R 0
R0603

2010-3-16
GND_CPU
CZC Technology
GND_CPU GND_CPU
Title

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 38 of 56


5 4 3 2 1
BATT+
BATT+ 30,31
+VDC
+VDC 19,22,28,30,32,33,34,35,37,38

D D
+VDC

1000pF/50V,X7R
C1147 C1198 C1199
32 ACAV
0.1uF/25V,X7R 10uF/25V,X5R
C0603 C1206
30V/20V
GND_CHR GND_CHR

5
30A/10mohm
8.8nC R1056

D
0.005,1% R1206
4 Q174 ns

CHR_ICHP
C1200 SiR462DP

G
WK_TH
PWRPAK_SO8 BATT+

S
0.1uF/16V,X7R
L30

3
2
1
CHR_LX CHR_LX CC:4A
10uH
CV:12.6V

5
30V/20V CKS2D100 0.015,1%

24

23

22

21

20

19
40A/5.1mohm R1025 R1206

D
GND_CHR D64 21.5nC

ICHP

IWK

ACAV

LX
BST
WK_TH
1N4148WS 4 Q175 R1185 R1026 R1027
SiR466DP 10,1% 10 10

G
SOD323
CHR_ICHM 18 CHR_HDR PWRPAK_SO8 C1202 C1203

S
1 2010-1-8
C1201 ICHM HDR 0.1uF/25V,X7R
10uF/25V,X5R

3
2
1
0.01uF/25V,X7R IAD_MAX 2 17 CHR_LDR 1000pF/50V,X7R C0603
IAD_MAX LDR C1148 C1206
C0402 2.2uF/6.3V,X7R
3 U64 16 C1204
IAC VDDP
C 30 Iac_M 4
OZ8618LN
QFN24_P5 15 +VDC C
IACM VAC R1028 C0603
CHR_REF 100,1%

CHR_ICHM
5 14

CHR_ICHP
30 Iac_P IACP REF
R1029
CHR_ISET 6 13
27 CC_SET ISET VDDA
CELLS

COMP
IBATT
10K
BASE

VSET
R0402 C1205 C1206 C1207 C1208

PA

PB
2.2uF/6.3V,X7R 1uF/10V,X5R 10uF/25V,X5R 2.2uF/6.3V,X7R
C0603 C0402 C1206 C0603
25
7

10

11

12
CHR_VSET
3

C1210
R1031
R1030 C1209 0.01uF/25V,X7R
1 0.01uF/25V,X7R C0402 GND_CHR GND_CHR
27 CHA_OFF C0402
1K Q152 0 CHR_PB 30
2

R0402 2N7002K R0402 R1032


SOT23 0
R1037 R0402
10K CHR_PA 30
R0402
ns R1033
GND_CHR GND_CHR GND_CHR C1211 100K,1% R1034
CHR_REF

2.2uF/6.3V,X7R R0402 10K,1%


C0603 CHR_VSET CHR_REF IAD_MAX CHR_REF

B R1035 R1036 B
GND_CHR C1212 100K,1%
0.01uF/25V,X7R R0402
0 C0402
R0603

R1038 C1213 GND_CHR


49.9K,1% 0.01uF/25V,X7R
GND_CHR R0402 C0402

GND_CHR

2010-1-7

CC_SET Charge Current SystemState Cells


3.0V 4.17A S3,S4,S5 6Cells
2.0V 2.78A S0 6Cells
1.5V 2.08A S0,S3,S4,S5 3Cells State CELLS
A A
0.375V 521mA PreCharge 3Cells/6Cells Hi_Z 2
<0.15V =CHA_OFF 3Cells/6Cells LOW 3
CZC Technology
Title

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 39 of 56


5 4 3 2 1

OZ8618LN
CC_SET
CHA_OFF

Adapter SI4812BDY SI4812BDY Battery


D POWER RAILS CURRENT TOTAL CURRENT D
CHR_PA CHR_PB

SI4800BDY +V5S +V5S 4A


MAIN_ON
5A

+V5AUX +V5AUX 1A

ALWAYS_ON
OZ815LN
ACAV +V3.3AUX +V3.3AUX
PWRSWVCC_MBXP 1A

SI4800BDY +V3.3S +V3.3S 4A


MAIN_ON

7A
OZ8033GN +V1.8S +V1.8S 0.5A
MAIN_ON

C VDDC_VR_EN
OZ8033GN 1.8V_REG 1.8V_REG 1.5A C

+V0.75S +V0.75S 2A 2A

V1_5_ON
OZ812LN
MAIN_ON +V1.5 +V1.5
V1_1S1_5S_PWROK 4A

OZ8033GN 1.0V_REG 1.0V_REG 1.6A


VDDC_VR_EN

7A
SI4800BDY MVDDQ MVDDQ 1A
VDDC_VR_EN

SI4800BDY +V1.5S +V1.5S 0.4A


MAIN_ON
B B

+V1.1S +V1.1S 2A

V11S_ON OZ8111LN
SIR466DP +V1.1S_VTT +V1.1S_VTT 8A 30A
V1_1S_PWROK

SIR466DP VDDC VDDC 20A


VDDC_VR_EN

+VCC_GFXCORE +VCC_GFXCORE
18A 18A
OZ8291LN
GFXVR_EN

+VCORE +VCORE 36A 36A


OZ8292LN
A VR_ON A

CZC Technology
Title

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 40 of 56


5 4 3 2 1

GU1A

PEG_TXP0 AA38 Y33 PEG_RXP0_C 0.1uF/16V,X7R GC1 PEG_RXP0


PEG_TXN0 PCIE_RX0P PCIE_TX0P PEG_RXN0_C 0.1uF/16V,X7R GC2 PEG_RXN0
Y37 PCIE_RX0N PCIE_TX0N Y32
D D

PEG_TXP1 Y35 W33 PEG_RXP1_C 0.1uF/16V,X7R GC3 PEG_RXP1


PEG_TXN1 PCIE_RX1P PCIE_TX1P PEG_RXN1_C 0.1uF/16V,X7R GC4 PEG_RXN1
W36 PCIE_RX1N PCIE_TX1N W32
PEG_RXN[15:0]
PEG_RXN[15:0] 5
PEG_TXP2 W38 U33 PEG_RXP2_C 0.1uF/16V,X7R GC5 PEG_RXP2
PEG_TXN2 PCIE_RX2P PCIE_TX2P PEG_RXN2_C 0.1uF/16V,X7R GC6 PEG_RXN2
V37 PCIE_RX2N PCIE_TX2N U32
PEG_RXP[15:0]
PEG_RXP[15:0] 5
PEG_TXP3 V35 U30 PEG_RXP3_C 0.1uF/16V,X7R GC7 PEG_RXP3
PEG_TXN3 PCIE_RX3P PCIE_TX3P PEG_RXN3_C 0.1uF/16V,X7R GC8 PEG_RXN3 PEG_TXN[15:0]
U36 PCIE_RX3N PCIE_TX3N U29 PEG_TXN[15:0] 5

PEG_TXP4 U38 T33 PEG_RXP4_C 0.1uF/16V,X7R GC9 PEG_RXP4 PEG_TXP[15:0]


PCIE_RX4P PCIE_TX4P PEG_TXP[15:0] 5
PEG_TXN4 T37 T32 PEG_RXN4_C 0.1uF/16V,X7R GC10 PEG_RXN4
PCIE_RX4N PCIE_TX4N

PCI EXPRESS INTERFACE


PEG_TXP5 T35 T30 PEG_RXP5_C 0.1uF/16V,X7R GC11 PEG_RXP5
PEG_TXN5 PCIE_RX5P PCIE_TX5P PEG_RXN5_C 0.1uF/16V,X7R GC12 PEG_RXN5
R36 PCIE_RX5N PCIE_TX5N T29

PEG_TXP6 R38 P33 PEG_RXP6_C 0.1uF/16V,X7R GC13 PEG_RXP6


PEG_TXN6 PCIE_RX6P PCIE_TX6P PEG_RXN6_C 0.1uF/16V,X7R GC14 PEG_RXN6
C P37 PCIE_RX6N PCIE_TX6N P32 C

PEG_TXP7 P35 P30 PEG_RXP7_C 0.1uF/16V,X7R GC15 PEG_RXP7


PEG_TXN7 PCIE_RX7P PCIE_TX7P PEG_RXN7_C 0.1uF/16V,X7R GC16 PEG_RXN7
N36 PCIE_RX7N PCIE_TX7N P29

PEG_TXP8 N38 N33 PEG_RXP8_C 0.1uF/16V,X7R GC17 PEG_RXP8 1.8V_REG


PCIE_RX8P PCIE_TX8P 1.8V_REG 35,36,42,43,44
PEG_TXN8 M37 N32 PEG_RXN8_C 0.1uF/16V,X7R GC18 PEG_RXN8
PCIE_RX8N PCIE_TX8N 1.0V_REG
1.0V_REG 35,36,42,43,44
PEG_TXP9 M35 N30 PEG_RXP9_C 0.1uF/16V,X7R GC19 PEG_RXP9
PCIE_RX9P PCIE_TX9P VDDR3 16,36,42,43,45,48
PEG_TXN9 L36 N29 PEG_RXN9_C 0.1uF/16V,X7R GC20 PEG_RXN9
PCIE_RX9N PCIE_TX9N

PEG_TXP10 L38 L33 PEG_RXP10_C 0.1uF/16V,X7R GC21 PEG_RXP10


PEG_TXN10 PCIE_RX10P PCIE_TX10P PEG_RXN10_C 0.1uF/16V,X7R GC22 PEG_RXN10
K37 PCIE_RX10N PCIE_TX10N L32

PEG_TXP11 K35 L30 PEG_RXP11_C 0.1uF/16V,X7R GC23 PEG_RXP11


PEG_TXN11 PCIE_RX11P PCIE_TX11P PEG_RXN11_C 0.1uF/16V,X7R GC24 PEG_RXN11
J36 PCIE_RX11N PCIE_TX11N L29

PEG_TXP12 J38 K33 PEG_RXP12_C 0.1uF/16V,X7R GC25 PEG_RXP12


PEG_TXN12 PCIE_RX12P PCIE_TX12P PEG_RXN12_C 0.1uF/16V,X7R GC26 PEG_RXN12
B H37 PCIE_RX12N PCIE_TX12N K32 B

PEG_TXP13 H35 J33 PEG_RXP13_C 0.1uF/16V,X7R GC27 PEG_RXP13


PEG_TXN13 PCIE_RX13P PCIE_TX13P PEG_RXN13_C 0.1uF/16V,X7R GC28 PEG_RXN13 VDDR3
G36 PCIE_RX13N PCIE_TX13N J32

PEG_TXP14 G38 K30 PEG_RXP14_C 0.1uF/16V,X7R GC29 PEG_RXP14


PEG_TXN14 PCIE_RX14P PCIE_TX14P PEG_RXN14_C 0.1uF/16V,X7R GC30 PEG_RXN14
F37 PCIE_RX14N PCIE_TX14N K29

C313
PEG_TXP15 F35 H33 PEG_RXP15_C 0.1uF/16V,X7R GC31 PEG_RXP15 0.1uF/16V,X7R
PEG_TXN15 PCIE_RX15P PCIE_TX15P PEG_RXN15_C 0.1uF/16V,X7R GC32 PEG_RXN15 ns
E37 PCIE_RX15N PCIE_TX15N H32

5
5,15 BUF_PLT_RST_L 1 VCC
4 PEG_RST#
CLOCK 2
16 DGPU_HOLD_RST# GND
12,14 PCIE_REFCLKP AB35 PCIE_REFCLKP
AA36 U19
12,14 PCIE_REFCLKN PCIE_REFCLKN

3
SOT23_5
R306 SN74AHC1G08DBV
CALIBRATION 1.0V_REG 100K ns
For Broadway, Madison and Park AJ21 Y30 PCIE_CALRP GR153 1.27K,1% ns
NC#1 PCIE_CALRP
the PWRGOOD ball must be conneccted to ground AK21 NC#2
A PWRGOOD_BUF AH16 Y29 PCIE_CALRN GR1 2K,1% A
PWRGOOD PCIE_CALRN

GR154
AA30 PERSTB
CZC Technology zw
10K Title
Madison PCI-E
Broadway
Size Project Name Rev
R1152 0 PEG_RST# B R48 C
5,15 BUF_PLT_RST_L
Date: Thursday, April 22, 2010 Sheet 41 of 56
5 4 3 2 1
5 4 3 2 1

GU1B

+V5S
+V5S 14,15,16,17,18,19,20,21,23,25,26,28,29,35,36,37,38
AU24 TXCAP_DPA3P 1.8V_REG
TXCAP_DPA3P TXCAP_DPA3P 18 1.8V_REG 35,36,43,44
AV23 TXCAM_DPA3N
TXCAM_DPA3N TXCAM_DPA3N 18
1.0V_REG
1.0V_REG 35,36,41,43,44
AT25 TX0P_DPA2P
TX0P_DPA2P TX0P_DPA2P 18
MUTI GFX AR24 TX0M_DPA2N
TX0M_DPA2N TX0M_DPA2N 18 VDDR3 16,36,41,43,45,48
DPA GU1G
AU26 TX1P_DPA1P GR5 10K
TX1P_DPA1P TX1P_DPA1P 18
AV25 TX1M_DPA1N GR2 10K
TX1M_DPA1N TX1M_DPA1N 18
AR8 AT27 TX2P_DPA0P LVDS CONTROL AK27
DVPCNTL_MVP_0 TX2P_DPA0P TX2P_DPA0P 18 VARY_BL BLON_PWM 19
AU8 AR26 TX2M_DPA0N AJ27 GPU_FPVCC
DVPCNTL_MVP_1 TX2M_DPA0N TX2M_DPA0N 18 DIGON
AP8
1.8V_REG NC on PARK AW8
DVPCNTL_0
AR30
DVPCNTL_1 TXCBP_DPB3P
D
AR3 DVPCNTL_2 TXCBM_DPB3N AT29 D
AR1 DVPCLK
GR3 10K MEM_ID0 AU1 AV31 AK35
GR6 10K ns MEM_ID1 DVPDATA_0 TX3P_DPB2P TXCLK_UP_DPF3P
AU3 DVPDATA_1 TX3M_DPB2N AU30 TXCLK_UN_DPF3N AL36
GR7 10K ns MEM_ID2 AW3 DPB
GR4 10K ns MEM_ID3 DVPDATA_2
AP6 DVPDATA_3 TX4P_DPB1P AR32 TXOUT_U0P_DPF2P AJ38
AW5 DVPDATA_4 TX4M_DPB1N AT31 TXOUT_U0N_DPF2N AK37
AU5 DVPDATA_5
AR6 DVPDATA_6 TX5P_DPB0P AT33 TXOUT_U1P_DPF1P AH35
GR8 GR9 GR10 GR11 AW6 AU32 AJ36
DVPDATA_7 TX5M_DPB0N TXOUT_U1N_DPF1N
AU6 DVPDATA_8
AT7 DVPDATA_9 TXCCP_DPC3P AU14 TXOUT_U2P_DPF0P AG38
10K 10K 10K 10K AV7 AV13 AH37
ns DVPDATA_10 TXCCM_DPC3N TXOUT_U2N_DPF0N
AN7 DVPDATA_11
AV9 DVPDATA_12 TX0P_DPC2P AT15 TXOUT_U3P AF35
AT9 DVPDATA_13 TX0M_DPC2N AR14 TXOUT_U3N AG36
AR10 DVPDATA_14
AW10 DPC AU16
VDDR3 DVPDATA_15 TX1P_DPC1P LVTMDP
AU10 DVPDATA_16 TX1M_DPC1N AV15
AP10 DVPDATA_17
AV11 DVPDATA_18 TX2P_DPC0P AT17 TXCLK_LP_DPE3P AP34 TXCLK_L+ 19
AT11 DVPDATA_19 TX2M_DPC0N AR16 TXCLK_LN_DPE3N AR34 TXCLK_L- 19
AR12
NC on PARK AW12
DVPDATA_20
AU20 AW37
DVPDATA_21 TXCDP_DPD3P TXOUT_L0P_DPE2P TXOUT_L0+ 19
AU12 DVPDATA_22 TXCDM_DPD3N AT19 TXOUT_L0N_DPE2N AU35 TXOUT_L0- 19
MAD_CLKREQ# GR109 10K ns AP12 DVPDATA_23
TX3P_DPD2P AT21 TXOUT_L1P_DPE1P AR37 TXOUT_L1+ 19
TX3M_DPD2N AR20 TXOUT_L1N_DPE1N AU39 TXOUT_L1- 19
DPD AU22
DP Channel D is NC on PARK AP35
TX4P_DPD1P TXOUT_L2P_DPE0P TXOUT_L2+ 19
GR118 0 Madison AV21 AR35
19 SCL_LVDS TX4M_DPD1N TXOUT_L2N_DPE0N TXOUT_L2- 19
GR119 0 Madison
19 SDA_LVDS I2C
TX5P_DPD0P AT23 TXOUT_L3P AN36
TX5M_DPD0N AR22 TXOUT_L3N AP37
SCL AK26
48 SCL SCL
SDA AJ26
48 SDA SDA
AD39 R313 0
R R_DAC1 20
C GENERAL PURPOSE I/O AD37 1.8V_REG AVDD C
GPIO0 RB Broadway
48 GPIO0 AH20 GPIO_0 (1.8V@65mA A2VDD)
GPIO1 AH18 AE36 R314 0 GFB1 120ohm/100MHz,1A
48 GPIO1 GPIO_1 G G_DAC1 20
GPIO2 AN16 AD35
48 GPIO2 GPIO_2 GB
AH23

4.7uF/10V,X5R

0.1uF/16V,X7R
ns T43 GPIO_3_SMBDATA
AJ23 AF37 R315 0

1uF/10V,X5R
ns T44 GPIO_4_SMBCLK B B_DAC1 20
GPIO5_AC_BATT

GC33

GC34

GC35
48 GPIO5_AC_BATT AH17 GPIO_5_AC_BATT BB AE38
14,27 AC_PRESENT_EC GR123 0 ns AJ17 DAC1
GPU_BLON GPIO_6
AK17 GPIO_7_BLON HSYNC AC36 HSYNC_DAC1 20,48
GPIO8_ROMSO AJ13 AC38 R636 R639 R637 NS1
48 GPIO8_ROMSO GPIO_8_ROMSO VSYNC VSYNC_DAC1 20,48
GPIO9_ROMSI AH15 150,1% 150,1% 150,1% 1 2
48 GPIO9_ROMSI GPIO_9_ROMSI
ns T54 AJ16 GPIO_10_ROMSCK
GPIO11 AK16 AB34 RSET GR15 NS_VIA AVSSQ
48 GPIO11 GPIO_11 RSET
GPIO12 AL16 499,1% AVDD
48 GPIO12 GPIO_12
GPIO13 AM16 AD34 (1.8V@100mA VDD2DI) VDD1DI
48 GPIO13 GPIO_13 AVDD
AM14 AE34 GFB2 120ohm/100MHz,1A
GPIO_14_HPD2 AVSSQ VDD1DI
ns T52 AM13 GPIO_15_PWRCNTL_0
AK14 AC33 AVSSQ

4.7uF/10V,X5R

0.1uF/16V,X7R
GPIO17_THERMAL_INIT GPIO_16_SSIN VDD1DI
AG30 AC34

1uF/10V,X5R
48 GPIO17_THERMAL_INIT GPIO_17_THERMAL_INT VSS1DI

GC36

GC37

GC38
AN14 GPIO_18_HPD3
GPIO19_CTF AM17 VSS1DI
ns T42 GPIO_19_CTF
JTAG DEBUG PORT AL13 AC30
ns T53 GPIO_20_PWRCNTL_1 R2
GR120 10K ns BB_EN AJ14 AC31
GPIO22_ROMCS# GPIO_21_BB_EN R2B NS2
48 GPIO22_ROMCS# AK13 GPIO_22_ROMCSB
GR108 0 ns MAD_CLKREQ# AN13 AD30 1 2
12,14 PEG_CLKREQ#_CLK GR125 10K ns GPIO24_TRSTB GPIO_23_CLKREQB G2
AM23 JTAG_TRSTB G2B AD31
GPIO25_TDI AN23 NS_VIA VSS1DI
ns T40 JTAG_TDI
XTALOUT_R GR126 33 ns GPIO26_TCK AK23 AF30
GR127 10K ns GPIO27_TMS JTAG_TCK B2
VDDR3 AL24 JTAG_TMS B2B AF31
GPIO28_TDO AM24 (1.8V@100mA VDD2DI) A2VDDQ
ns T9 JTAG_TDO
AJ19 GFB12 120ohm/100MHz,1A
GENERICA
AK19 GENERICB C AC32
GENERICC AJ20 AD32

0.1uF/16V,X7R
48 GENERICC GENERICC Y
AK20 AF32 VDD1DI

1uF/10V,X5R
GENERICD COMP

GC58

GC60
AJ24 GENERICE_HPD4
AH26 DAC2
GENERICF H2SYNC
GenericF/G is NC on PARK AH24 AD29

0.1uF/16V,X7R
GENERICG H2SYNC H2SYNC 48
AC29 V2SYNC
B V2SYNC V2SYNC 48 B
NS14

GC99
HPD1 AK24 1 2
18 HPD1 HPD1
VDD2DI AG31
1.8V_REG AG32 VDDR3 NS_VIA
VSS2DI A2VDD A2VSSQ
PLACE VREFG DIVIDER
AND CAP GFB16 120ohm/100MHz,1A
A2VDD AG33
GR16 CLOSE TO ASIC A2VDDQ
499,1% AD33

0.1uF/16V,X7R
1.8V_REG VREFG A2VDDQ
AH13 VREFG

GC85
A2VSSQ AF33
(1.8V@150mA DPLL_PVDD) DPLL_PVDD GR17 0.1uF/16V,X7R
GFB3 249,1% GC39
AA29 GR124
4.7uF/10V,X5R

0.1uF/16V,X7R

300ohm/100MHz,1A R2SET 715,1%


AM32
1uF/10V,X5R

DPLL_PVDD
GC40

GC41

GC42

AN32 DPLL_PVSS
DPLL_VDDC A2VSSQ
DDC/AUX AM26 DDC1CLK
DDC1CLK DDC1CLK 18
NS3 AN31 PLL/CLOCK AN26 DDC1DATA VDDR3
DPLL_VDDC DDC1DATA DDC1DATA 18
1 2 VDDR3
AM27 DDC1 AND AUX1 CAN BE JOINTED TOGETHER FOR DUAL DCC/AUX FUNCTION DDC1CLK GR110 4.7K
NS_VIA XTALIN AUX1P REFER THE DATABOOK FOR DETAIL DDC1DATA GR111 4.7K
AV33 XTALIN AUX1N AL27
DPLL_PVSS XTALOUT GR18 0 XTALOUT_R AU34 DDC6CLK GR112 4.7K
R0402_0 XTALOUT DDC2 AND AUX2 CAN BE JOINTED TOGETHER FOR DUAL DCC/AUX FUNCTION DDC6DATA GR113 4.7K
DDC2CLK AM19
AL19 REFER THE DATABOOK FOR DETAIL SCL_LVDS GR117 4.7K
GR19 0 XO_IN AW34 DDC2DATA SDA_LVDS GR116 4.7K C315
1.0V_REG DPLL_VDDC GR20 1M R0402_0 XO_IN
AUX2P AN20 0.1uF/16V,X7R
(1.1V@300mA DPLL_VDDC) GR21 0 SS_IN AW35 AM20
SS_IN AUX2N

5
GFB4 GY1 R0402_0
2 1 AL30 1 VCC
4.7uF/10V,X5R

0.1uF/16V,X7R

DDCCLK_AUX3P 16,36 MADISON_POWOK


300ohm/100MHz,1A AM30 4
1uF/10V,X5R

DDCDATA_AUX3N FPVCC 19,44


27MHz VDDR3 GPU_FPVCC
GC43

GC44

GC45

2
x2s60x35 GND
DDCCLK_AUX4P AL29 DDCxx_AUX4x is NC on PARK
GC46 GC47 AF29 AM29 U27
48 GPU_DPLUS DPLUS DDCDATA_AUX4N

3
18pF/50V,NPO 18pF/50V,NPO AG29 THERMAL SOT23_5
48 GPU_DMINUS DMINUS
AN21 GR114 0 Park SCL_LVDS R307 SN74AHC1G08DBV
DDCCLK_AUX5P SCL_LVDS 19
AM21 GR115 0 Park SDA_LVDS 10K
DDCDATA_AUX5N SDA_LVDS 19
A AK32 C316 A
DPLL_PVSS TS_FDO DDC6CLK
DDC6CLK AJ30 DDC6CLK 20 0.1uF/16V,X7R
1.8V_REG AL31 AJ31 DDC6DATA
TS_A DDC6DATA DDC6DATA 20

5
TSVDD GR121 0 ns
(1.8V@15mA TSVDD) AK30 GPU_BLON 1 VCC
GFB5 120ohm/100MHz,1A DDCCLK_AUX7P
AJ32 TSVDD DDCDATA_AUX7N AK29 DDCxx_AUX7x is NC on M9x and PARK 4 GPIO7_BLON 19
AJ33 2
4.7uF/10V,X5R

0.1uF/16V,X7R

TSVSS GND
1uF/10V,X5R

U29
GC48

GC49

GC50

3
SOT23_5

NS4
Broadway R308 SN74AHC1G08DBV CZC Technology zw
10K
1 2 Title
GR122 0 ns Madison IO
NS_VIA
TSVSS Size Project Name Rev
C R48 C

Date: Thursday, April 22, 2010 Sheet 42 of 56


5 4 3 2 1
5 4 3 2 1

GU1E

MVDDQ MEM I/O PCIE_VDDR 120ohm/3A 1.8V_REG +V1.5S


For DDR3/GDDR5, MVDDQ = 1.5V PCIE (1.8V@504mA PCIE_VDDR)
+V1.5S 7,16,21,22,28,35,36
AC7 AA31 GFB6 1.8V_REG
VDDR1#1 PCIE_VDDR#1 1.8V_REG 35,36,42,44
AD11 AA32

1uF/10V,X5R
0.1uF/16V,X7R

4.7uF/10V,X5R
2.2uF/6.3V,X5R 2.2uF/6.3V,X5R 2.2uF/6.3V,X5R

2.2uF/6.3V,X5R

2.2uF/6.3V,X5R 2.2uF/6.3V,X5R

2.2uF/6.3V,X5R 2.2uF/6.3V,X5R 2.2uF/6.3V,X5R

2.2uF/6.3V,X5R 2.2uF/6.3V,X5R 2.2uF/6.3V,X5R

2.2uF/6.3V,X5R

2.2uF/6.3V,X5R 2.2uF/6.3V,X5R 2.2uF/6.3V,X5R

2.2uF/6.3V,X5R
VDDR1#2 PCIE_VDDR#2 100ohm/100MHz,3A 1.0V_REG

GC55

GC75

GC76

GC77
AF7 VDDR1#3 PCIE_VDDR#3 AA33 1.0V_REG 35,36,41,42,44

GC51

GC53

GC71

GC72

GC73

GC74

GC54
AG10 VDDR1#4 PCIE_VDDR#4 AA34
AJ7 V28 VDDC
VDDR1#5 PCIE_VDDR#5 VDDC 35,36
AK8 VDDR1#6 PCIE_VDDR#6 W29
AL9 VDDR1#7 PCIE_VDDR#7 W30 VDDR3 16,36,41,42,45,48
G11 VDDR1#8 PCIE_VDDR#8 Y31
G14 1.0V_REG MVDDQ

2.2uF/6.3V,X5R 2.2uF/6.3V,X5R
VDDR1#9 MVDDQ 35,36,45,46,47
G17 VDDR1#10 (1.1V@1920mA PCIE_VDDC) For M96/M92 PCIE_VDDC = 1.1V

GC56

GC57

GC59

GC78

GC79

GC61
G20 VDDR1#11 PCIE_VDDC#1 G30 For M97/RV8xx PCIE_VDDC = 1.0V
G23 G31

1uF/10V,X5R

1uF/10V,X5R
0.1uF/16V,X7R

4.7uF/10V,X5R
2.2uF/6.3V,X5R
VDDR1#12 PCIE_VDDC#2

GC80

GC62

GC63

GC81

GC64
D
G26 VDDR1#13 PCIE_VDDC#3 H29 D
G29 VDDR1#14 PCIE_VDDC#4 H30
H10 VDDR1#15 PCIE_VDDC#5 J29
J7 J30

2.2uF/6.3V,X5R

2.2uF/6.3V,X5R
VDDR1#16 PCIE_VDDC#6
J9 VDDR1#17 PCIE_VDDC#7 L28

GC65

GC66

GC67

GC82

GC69

GC70

GC83
K11 VDDR1#18 PCIE_VDDC#8 M28
K13 VDDR1#19 PCIE_VDDC#9 N28
K8 VDDR1#20 PCIE_VDDC#10 R28
L12 VDDR1#21 PCIE_VDDC#11 T28
L16 U28 VDDC
VDDR1#22 PCIE_VDDC#12
L21 VDDR1#23
L23 VDDR1#24
L26 VDDR1#25 VDDC#1 AA15
L7 CORE AA17
VDDR1#26 VDDC#2
M11 AA20

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R
VDDR1#27 VDDC#3

GC84

GC86

GC87

GC88

GC89

GC90

GC91

GC92

GC93
N11 VDDR1#28 VDDC#4 AA22
P7 AA24 CT5 CT6
VDDR1#29 VDDC#5 22uF/6.3V,TAN 22uF/6.3V,TAN
R11 VDDR1#30 VDDC#6 AA27
U11 AB16 ns ns
VDDR1#31 VDDC#7
U7 VDDR1#32 VDDC#8 AB18
Y11 VDDR1#33 VDDC#9 AB21
Y7 AB23

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R
VDDR1#34 VDDC#10

GC94

GC95

GC96

GC97

GC98

GC100

GC101

GC102

GC103
VDDC#11 AB26
VDDC#12 AB28
1.8V_REG AC17
VDDC#13
VDDC#14 AC20
VDDC_CT LEVEL AC22
TRANSLATION VDDC#15
(1.8V@110mA VDD_CT) VDDC#16 AC24

POWER
GFB7 AF26 AC27

2.2uF/6.3V,X5R 2.2uF/6.3V,X5R

2.2uF/6.3V,X5R 2.2uF/6.3V,X5R

2.2uF/6.3V,X5R

2.2uF/6.3V,X5R 2.2uF/6.3V,X5R

2.2uF/6.3V,X5R 2.2uF/6.3V,X5R

2.2uF/6.3V,X5R 2.2uF/6.3V,X5R
VDD_CT#1 VDDC#17
AF27 VDD_CT#2 VDDC#18 AD18
120ohm/100MHz,1A

GC104

GC105

GC107

GC108

GC109

GC110
AG26 AD21
1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

4.7uF/10V,X5R
VDD_CT#3 VDDC#19
GC111

GC112

GC114

GC115
AG27 VDD_CT#4 VDDC#20 AD23
VDDC#21 AD26
VDDC#22 AF17
I/O AF20
VDDC#23
AF23 AF22

2.2uF/6.3V,X5R
VDDR4 VDDR3 VDDR3#1 VDDC#24
AF24 VDDR3#2 VDDC#25 AG16

GC116

GC117

GC118

GC120

GC121

GC122
AG23 VDDR3#3 VDDC#26 AG18
C GFB8 AG24 AG21 C
VDDR3#4 VDDC#27
VDDR5 for M96 AH22
4.7uF/10V,X5R

120ohm/100MHz,1A VDDR4 VDDC#28


AH27
1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

4.7uF/10V,X5R
VDDC#29
GC123

GC124

GC125

GC126

GC127

GC128

GC129
AF13 VDDR4#4 VDDC#30 AH28
AF15 VDDR4#5 VDDC#31 M26
AG13 N24

22uF/6.3V,X5R

22uF/6.3V,X5R

22uF/6.3V,X5R

22uF/6.3V,X5R
VDDR4#7 VDDC#32

GC130

GC132

GC133

GC134
AG15 VDDR4#8 VDDC#33 N27
VDDC#34 R18
VDDC#35 R21
AD12 VDDR4#1 VDDC#36 R23
AF11 VDDR4#2 VDDC#37 R26
MVDDQ AF12 T17
VDDR4#3 VDDC#38
M96/92 ONLY AG11 VDDR4#6 VDDC#39 T20
VDDRHA T22
GFB9 120ohm/100MHz,1A VDDC#40
VDDC#41 T24
GC135 T27
1uF/10V,X5R VDDC#42
VDDC#43 U16
1 2 M20 NC_VDDRHA VDDC#44 U18
M21 U21

1uF/10V,X5R

1uF/10V,X5R
NS_VIA GND_VSSRHA VDDRHB NC_VSSRHA VDDC#45

GC136

GC137
VDDC#46 U23
VDDC#47 U26
GFB10 120ohm/100MHz,1A GC138 V12 V17
1uF/10V,X5R NC_VDDRHB VDDC#48
U12 NC_VSSRHB VDDC#49 V20
1 2 VDDC#50 V22
VDDC#51 V24
NS_VIA GND_VSSRHB V27
PCIE_PVDD PLL
VDDC#52
VDDC#53 Y16
Y18
VDDCI and VDDC should have seperate regulators with a merge option on PCB
(1.8V@40mA PCIE_PVDD) VDDC#54
GFB11 AB37 Y21
PCIE_PVDD VDDC#55
Y23 For Madison and Park, VDDCI and VDDC can share one common regulator
1uF/10V,X5R

1uF/10V,X5R

4.7uF/10V,X5R

120ohm/100MHz,1A VDDC#56
GC139

GC140

GC141

MPV18 H7 MPV18#1 VDDC#57 Y26


H8 Y28 (GDDR3/DDR3 1.12V@4A VDDCI) VDDC
MPV18#2 VDDC#58
SPV10 (GDDR5 1.12V@16A VDDCI) 120ohm/3A
(For M97, Broadway, Madison and Park SPV10 = 1.0V) SPV18 AM10 SPV18
1.0V_REG AA13 VDDCI FB95 120ohm/100MHz,2.5A
GFB13 VDDCI#1
(For M96 SPV10 = VDDC) AN9 AB13

2.2uF/6.3V,X5R

2.2uF/6.3V,X5R

2.2uF/6.3V,X5R

2.2uF/6.3V,X5R

2.2uF/6.3V,X5R

2.2uF/6.3V,X5R

2.2uF/6.3V,X5R
SPV10 VDDCI#2 FB96 120ohm/100MHz,2.5A
AC12
1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R
0.1uF/16V,X7R

4.7uF/10V,X5R

B
120ohm/100MHz,1A VDDCI#3 B
GC142

GC143

GC144

GC145

GC146

GC147

GC148

GC149

GC150

GC151

GC152

GC153
AN10 SPVSS VDDCI#4 AC15
VDDCI#5 AD13
NS5 AD16
VDDCI#6
1 2 VDDCI#7 M15
VDDCI#8 M16
NS_VIA VOLTAGE M18
SPVSS SENESE VDDCI#9
VDDCI#10 M23
VDDCI#11 N13
AF28 FB_VDDC VDDCI#12 N15
(1.8V@75mA SPV18) SPV18 N17
GFB14 VDDCI#13
VDDCI#14 N20
AG28 N22
1uF/10V,X5R
0.1uF/16V,X7R

4.7uF/10V,X5R

120ohm/100MHz,1A FB_VDDCI ISOLATED VDDCI#15


GC154

GC155

GC156

R12
CORE I/O VDDCI#16 R13
VDDCI#17
AH29 R16
FB_GND VDDCI#18
T12
NOTE1:
VDDCI#19
VDDCI#20 T15 Back Bias is not supported on M97, Broadway, Madison and Park
VDDCI#21 V15
MPV18
GFB15
(1.8V@500mA MPV18) VDDCI#22 Y13 For the M96 Back Bias circuitry, refer to REF134
1uF/10V,X5R
0.1uF/16V,X7R

4.7uF/10V,X5R

120ohm/100MHz,1A Broadway
GC157

GC158

GC159

NOTE2:
FB_VDDC, FB_VDDCI and FB_GND are not support on M96
M97, Broadway, Madison and Park only
NOTE3:
M97 VDDC and VDDCI ball assignments are different from M96.
If M96 is populated on this design, VDDC and VDDCI will be shorted on the substrate.
M97, Broadway, Madison and Park only NOTE4:
M96 do not support core vsense feature
For M2 design compatibility, refer to the document AN_M96_Ax and AN_M97_Ax
A A

VCORE_SEN/RTN and VDDCI_SEN/RTN route as differetial pair

CZC Technology zw
Title
Madison Power

Size Project Name Rev


C R48 C

Date: Thursday, April 22, 2010 Sheet 43 of 56


5 4 3 2 1
5 4 3 2 1

GU1F

1.8V_REG
1.8V_REG 35,36,42,43
GU1H AB39 A3
1.0V_REG PCIE_VSS#1 GND#1
1.0V_REG 35,36,41,42,43 E39 PCIE_VSS#2 GND#2 A37
DPC_VDD18 DP C/D POWER DP A/B POWER DPA_VDD18 F34 AA16
VDDC PCIE_VSS#3 GND#3
VDDC 35,36,43 F39 PCIE_VSS#4 GND#4 AA18
AP20 DPC_VDD18#1 DPA_VDD18#1 AN24 G33 PCIE_VSS#5 GND#5 AA2
1.0V_REG AP21 AP24 G34 AA21
DPC_VDD18#2 DPA_VDD18#2 PCIE_VSS#6 GND#6
H31 PCIE_VSS#7 GND#7 AA23
DPC_VDD10 DPA_VDD10 H34 AA26
1.0V_REG PCIE_VSS#8 GND#8
D
(1.0V@200mA DPC_VDD10) (1.0V@200mA DPA_VDD10) H39 PCIE_VSS#9 GND#9 AA28 D
AP13 AP31 GFB17 J31 AA6
DPC_VDD10#1 DPA_VDD10#1 PCIE_VSS#10 GND#10
AT13 AP32 J34 AB12

4.7uF/10V,X5R
DPC_VDD10#2 DPA_VDD10#2 120ohm/100MHz,1A PCIE_VSS#11 GND#11
K31 AB15

1uF/10V,X5R
0.1uF/16V,X7R

0.1uF/16V,X7R
PCIE_VSS#12 GND#12

GC160

GC163

GC164

GC165
K34 PCIE_VSS#13 GND#13 AB17
AN17 DPC_VSSR#1 DPA_VSSR#1 AN27 K39 PCIE_VSS#14 GND#14 AB20
AP16 DPC_VSSR#2 DPA_VSSR#2 AP27 L31 PCIE_VSS#15 GND#15 AB22
AP17 DPC_VSSR#3 DPA_VSSR#3 AP28 L34 PCIE_VSS#16 GND#16 AB24
AW14 DPC_VSSR#4 DPA_VSSR#4 AW24 M34 PCIE_VSS#17 GND#17 AB27
AW16 DPC_VSSR#5 DPA_VSSR#5 AW26 M39 PCIE_VSS#18 GND#18 AC11
N31 PCIE_VSS#19 GND#19 AC13
DPD_VDD18 DPB_VDD18 N34 AC16
PCIE_VSS#20 GND#20
P31 PCIE_VSS#21 GND#21 AC18
AP22 DPD_VDD18#1 DPB_VDD18#1 AP25 P34 PCIE_VSS#22 GND#22 AC2
DNI for M96/M92 AP23 DPD_VDD18#2 DPB_VDD18#2 AP26 P39 PCIE_VSS#23 GND#23 AC21
R34 PCIE_VSS#24 GND#24 AC23
DPD_VDD10 DPB_VDD10 1.0V_REG T31 AC26
1.8V_REG PCIE_VSS#25 GND#25
(1.0V@200mA DPD_VDD10) (1.1V@200mA DPB_VDD10) T34 PCIE_VSS#26 GND#26 AC28
AP14 DPD_VDD10#1 DPB_VDD10#1 AN33 T39 PCIE_VSS#27 GND#27 AC6
DPA_VDD18 AP15 AP33 U31 AD15
DPD_VDD10#2 DPB_VDD10#2 PCIE_VSS#28 GND#28
(1.8V@130mA DPA_VDD18) U34 AD17

0.1uF/16V,X7R

0.1uF/16V,X7R
GFB20 PCIE_VSS#29 GND#29

GC166

GC169
V34 PCIE_VSS#30 GND#30 AD20
V39 AD22
4.7uF/10V,X5R

120ohm/100MHz,1A PCIE_VSS#31 GND#31


AN19 AN29 W31 AD24
1uF/10V,X5R
0.1uF/16V,X7R

DPD_VSSR#1 DPB_VSSR#1 PCIE_VSS#32 GND#32


GC172

GC173

GC174

AP18 DPD_VSSR#2 DPB_VSSR#2 AP29 W34 PCIE_VSS#33 GND#33 AD27


AP19 DPD_VSSR#3 DPB_VSSR#3 AP30 Y34 PCIE_VSS#34 GND#34 AD9
AW20 AW30 1.8V_REG Y39 AE2
DPD_VSSR#4 DPB_VSSR#4 PCIE_VSS#35 GND#35
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32 GND#36 AE6
DPAPVDD AF10
GFB21 GND#37
GND#38 AF16
DPB_VDD18 AF18

0.1uF/16V,X7R

4.7uF/10V,X5R
GR22 150,1% DPCD_CALR DPAB_CALR GR23 150,1% 120ohm/100MHz,1A GND#39
AW18 AW28 AF21

1uF/10V,X5R
(1.8V@130mA DPB_VDD18) DPCD_CALR DPAB_CALR
GND GND#40

GC175

GC176

GC177
GND#41 AG17
DPE_VDD18 F15 AG2
GND#100 GND#42
F17 AG20
0.1uF/16V,X7R

DP E/F POWER DP PLL POWER NS6 GND#101 GND#43


GC178

LVDS mode AH34 AU28 (1.8V@20mA DPA_PVDD) F19 AG22


DPE_VDD18#1 DPA_PVDD GND#102 GND#44
(1.0V@120mA DPE_VDD10) AJ34 DPE_VDD18#2 DPA_PVSS AV27 2 1 F21 GND#103 GND#45 AG6
F23 GND#104 GND#46 AG9
C DP mode DPE_VDD10 DPBPVDD NS_VIA F25 AH21 C
DPAPVSS GND#105 GND#47
(1.0V@110mA DPE_VDD10) F27 GND#106 GND#48 AJ10
GFB23 AL33 AV29 (1.8V@20mA DPB_PVDD) F29 AJ11
DPE_VDD10#1 DPB_PVDD GND#107 GND#49
AM33 AR28 F31 AJ2

4.7uF/10V,X5R

0.1uF/16V,X7R
DPC_VDD18 120ohm/100MHz,1A DPE_VDD10#2 DPB_PVSS GND#108 GND#50
F33 AJ28

1uF/10V,X5R
0.1uF/16V,X7R GND#109 GND#51
GC181

GC182

GC183

GC184
(1.8V@130mA DPC_VDD18) F7 GND#110 GND#52 AJ6
F9 GND#111 GND#53 AK11
AN34 DPE_VSSR#1 DPC_PVDD AU18 (1.8V@20mA DPC_PVDD) NS7 G2 GND#112 GND#54 AK31
AP39 AV17 G6 AK7
0.1uF/16V,X7R

DPE_VSSR#2 DPC_PVSS GND#113 GND#55


GC187

AR39 DPE_VSSR#3 2 1 H9 GND#114 GND#56 AL11


AU37 DPE_VSSR#4 J2 GND#115 GND#57 AL14
NS_VIA J27 GND#116 GND#58 AL17
AV19 (1.8V@20mA DPD_PVDD) DPCPVDD DPBPVSS J6 AL2
DPE_VDD18 DPD_PVDD GND#117 GND#59
DPD_PVSS AR18 J8 GND#118 GND#60 AL20
LVDS mode K14 AL21
DPD_VDD18 DPE_PVDD GND#119 GND#61
(1.0V@120mA DPF_VDD10) AF34 DPF_VDD18#1 K7 GND#120 GND#62 AL23
(1.8V@130mA DPD_VDD18) AG34 L11 AL26

0.1uF/16V,X7R
DPF_VDD18#2 GND#121 GND#63

GC190
DP mode AM37 L17 AL32
DPF_VDD10 DPE_PVDD GND#122 GND#64
(1.0V@110mA DPF_VDD10) DPE_PVSS AN38 L2 GND#123 GND#65 AL6
L22 AL8
0.1uF/16V,X7R

NS8 GND#124 GND#66


DPF_PVDD NS_VIA
GC193

AK33 DPF_VDD10#1 L24 GND#125 GND#67 AM11


AK34 2 1 L6 AM31
4.7uF/10V,X5R

DPF_VDD10#2 GND#126 GND#68


AL38 M17 AM9
1uF/10V,X5R
0.1uF/16V,X7R

DPF_PVDD DPDPVDD GND#127 GND#69


GC196

GC197

GC198

DPF_PVSS AM35 M22 GND#128 GND#70 AN11


DPCPVSS M24 AN2
GND#129 GND#71
AF39 DPF_VSSR#1 N16 GND#130 GND#72 AN30
AH39 DPF_VSSR#2 N18 GND#131 GND#73 AN6
AK39 N2 AN8

0.1uF/16V,X7R
DPF_VSSR#3 GND#132 GND#74

GC199
DP mode AL34 N21 AP11
DPF_VSSR#4 GND#133 GND#75
(1.8V@130mA DPE_VDD18) AM34 DPF_VSSR#5 N23 GND#134 GND#76 AP7
NS9 N26 GND#135 GND#77 AP9
LVDS mode DPE_VDD18 N6 AR5
GND#136 GND#78
(1.8V@200mA DPE_VDD18) 2 1 R15 GND#137 GND#79 B11
GFB30 GR24 150,1% DPEF_CALR AM39 R17 B13
DPEF_CALR GND#138 GND#80
R2 B15
4.7uF/10V,X5R

300ohm/100MHz,1A DPDPVSS NS_VIA GND#139 GND#81


R20 B17
1uF/10V,X5R

1uF/10V,X5R
0.1uF/16V,X7R

Broadway GND#140 GND#82


GC202

GC203

GC204

GC205

DGPU R22 GND#141 GND#83 B19


(1.8V@20mA DPE_PVDD) GFB31 R24 B21
B GND#142 GND#84 B
R27 B23

4.7uF/10V,X5R
120ohm/100MHz,1A GND#143 GND#85
R6 B25

1uF/10V,X5R
0.1uF/16V,X7R
Q34 GND#144 GND#86

GC206

GC207

GC208
T11 GND#145 GND#87 B27
AO3415 T13 B29
GND#146 GND#88
T16 GND#147 GND#89 B31
2 3 For M97/M96, DPF_VDD18 can be shared with DPE_VDD18 NS10 T18 B33
GND#148 GND#90
2 1 T21 GND#149 GND#91 B7
For M97/M96, DPF_VDD10 can be shared with DPE_VDD10 T23 GND#150 GND#92 B9
NS_VIA T26 GND#151 GND#93 C1
SOT23 ns DPEPVSS U15 C39
GND#153 GND#94
1

GR164 U17 E35


10K GC301 GFB33 GND#154 GND#95
For dual link DVI using DPA AND DPB, DPA_VDDxx and DPB_VDDxx can be shared respectively (1.8V@20mA DPF_PVDD) U2 GND#155 GND#96 E5
ns 1000pF/50V,X7R U20 F11

4.7uF/10V,X5R
ns 120ohm/100MHz,1A GND#156 GND#97
U22 F13

1uF/10V,X5R
For dual link DVI using DPC AND DPD, DPC_VDDxx and DPD_VDDxx can be shared respectively

0.1uF/16V,X7R
GND#157 GND#98

GC213

GC214

GC215
DNI for M97/M96 U24 GND#158
U27 GND#159
For dual link LVDS, DPE_VDDxx and DPF_VDDxx can be shared respectively U6 GND#160
NS11 V11 GND#161
2 1 V16 GND#163
3

V18 GND#164
Q35 V21
DPFPVSS NS_VIA GND#165
2N7002K V23 GND#166
19,42 FPVCC 1 V26 GND#167
ns W2 GND#168
W6 GND#169
2

Y15 GND#170
Y17 GND#171
Y20 GND#172
Y22 GND#173 VSS_MECH#1 A39
Y24 GND#174 VSS_MECH#2 AW1
Y27 GND#175 VSS_MECH#3 AW39
U13 GND#152
V13 GND#162
Broadway

A A

CZC Technology zw
Title
Madison DP Power

Size Project Name Rev


C R48 C

Date: Thursday, April 22, 2010 Sheet 44 of 56


5 4 3 2 1
5 4 3 2 1

MVDDQ
MVDDQ 35,36,43,46,47
VDDR3 16,36,41,42,43,48

GU1C GU1D
D DDR2 DDR2 DDR2 DDR2 D
GDDR3/GDDR5 GDDR5/GDDR3 GDDR3/GDDR5 GDDR5/GDDR3
46 MDA[63:0] DDR3 DDR3 MAA[13:0] 46 47 MDB[63:0] DDR3 DDR3 MAB[13:0] 47
MDA0 C37 G24 MAA0 MDB0 C5 P8 MAB0
MDA1 DQA0_0/DQA_0 MAA0_0/MAA_0 MAA1 MDB1 DQB0_0/DQB_0 MAB0_0/MAB_0 MAB1
C35 DQA0_1/DQA_1 MAA0_1/MAA_1 J23 C3 DQB0_1/DQB_1 MAB0_1/MAB_1 T9
MDA2 A35 H24 MAA2 MDB2 E3 P9 MAB2
DQA0_2/DQA_2 MAA0_2/MAA_2 DQB0_2/DQB_2 MAB0_2/MAB_2

MEMORY INTERFACE A
MDA3 E34 J24 MAA3 MDB3 E1 N7 MAB3
DQA0_3/DQA_3 MAA0_3/MAA_3 DQB0_3/DQB_3 MAB0_3/MAB_3

MEMORY INTERFACE B
MDA4 G32 H26 MAA4 MDB4 F1 N8 MAB4
MDA5 DQA0_4/DQA_4 MAA0_4/MAA_4 MAA5 MDB5 DQB0_4/DQB_4 MAB0_4/MAB_4 MAB5
D33 DQA0_5/DQA_5 MAA0_5/MAA_5 J26 F3 DQB0_5/DQB_5 MAB0_5/MAB_5 N9
MDA6 F32 H21 MAA6 MDB6 F5 U9 MAB6
MDA7 DQA0_6/DQA_6 MAA0_6/MAA_6 MAA7 MDB7 DQB0_6/DQB_6 MAB0_6/MAB_6 MAB7
E32 DQA0_7/DQA_7 MAA0_7/MAA_7 G21 G4 DQB0_7/DQB_7 MAB0_7/MAB_7 U8
MDA8 D31 H19 MAA8 MDB8 H5 Y9 MAB8
MDA9 DQA0_8/DQA_8 MAA1_0/MAA_8 MAA9 MDB9 DQB0_8/DQB_8 MAB1_0/MAB_8 MAB9
F30 DQA0_9/DQA_9 MAA1_1/MAA_9 H20 H6 DQB0_9/DQB_9 MAB1_1/MAB_9 W9
MDA10 C30 L13 MAA10 MDB10 J4 AC8 MAB10
MDA11 DQA0_10/DQA_10 MAA1_2/MAA_10 MAA11 MDB11 DQB0_10/DQB_10 MAB1_2/MAB_10 MAB11
A30 DQA0_11/DQA_11 MAA1_3/MAA_11 G16 K6 DQB0_11/DQB_11 MAB1_3/MAB_11 AC9
MDA12 F28 J16 MAA12 MDB12 K5 AA7 MAB12
MDA13 DQA0_12/DQA_12 MAA1_4/MAA_12 A_BA2 MDB13 DQB0_12/DQB_12 MAB1_4/MAB_12 B_BA2
C28 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 H16 A_BA2 46 L4 DQB0_13/DQB_13 MAB1_5/BA2 AA8 B_BA2 47
MDA14 A28 J17 A_BA0 MDB14 M6 Y8 B_BA0
DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 A_BA0 46 DQB0_14/DQB_14 MAB1_6/BA0 B_BA0 47
MDA15 E28 H17 A_BA1 MDB15 M1 AA9 B_BA1
DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 A_BA1 46 DQB0_15/DQB_15 MAB1_7/BA1 B_BA1 47
MDA16 D27 MDB16 M3
DQA0_16/DQA_16 DQMA#[7:0] 46 DQB0_16/DQB_16 DQMB#[7:0] 47
MDA17 F26 A32 DQMA#0 MDB17 M5 H3 DQMB#0
MDA18 DQA0_17/DQA_17 WCKA0_0/DQMA_0 DQMA#1 MDB18 DQB0_17/DQB_17 WCKB0_0/DQMB_0 DQMB#1
C26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 C32 N4 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 H1
MDA19 A26 D23 DQMA#2 MDB19 P6 T3 DQMB#2
MDA20 DQA0_19/DQA_19 WCKA0_1/DQMA_2 DQMA#3 MDB20 DQB0_19/DQB_19 WCKB0_1/DQMB_2 DQMB#3
F24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 E22 P5 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 T5
MDA21 C24 C14 DQMA#4 MDB21 R4 AE4 DQMB#4
MDA22 DQA0_21/DQA_21 WCKA1_0/DQMA_4 DQMA#5 MDB22 DQB0_21/DQB_21 WCKB1_0/DQMB_4 DQMB#5
A24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 A14 T6 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AF5
MDA23 E24 E10 DQMA#6 MDB23 T1 AK6 DQMB#6
MDA24 DQA0_23/DQA_23 WCKA1_1/DQMA_6 DQMA#7 MDB24 DQB0_23/DQB_23 WCKB1_1/DQMB_6 DQMB#7
C22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 D9 U4 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 AK5
MDA25 A22 MDB25 V6
DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 QSA[7:0] 46 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 QSB[7:0] 47
MDA26 F22 C34 QSA0 MDB26 V1 F6 QSB0
MDA27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 QSA1 MDB27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 QSB1
D21 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 D29 V3 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 K3
MDA28 A20 D25 QSA2 MDB28 Y6 P3 QSB2
MDA29 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 QSA3 MDB29 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 QSB3
F20 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 E20 Y1 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 V5
MDA30 D19 E16 QSA4 MDB30 Y3 AB5 QSB4
MDA31 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 QSA5 MDB31 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 QSB5
E18 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 E12 Y5 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AH1
MDA32 C18 J10 QSA6 MDB32 AA4 AJ9 QSB6
MDA33 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 QSA7 MDB33 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 QSB7
A18 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 D7 AB6 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 AM5
C MDA34 F18 MDB34 AB1 C
DQA1_2/DQA_34 QSA#[7:0] 46 DQB1_2/DQB_34 QSB#[7:0] 47
MDA35 D17 A34 QSA#0 MDB35 AB3 G7 QSB#0
MDA36 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 QSA#1 MDB36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 QSB#1
A16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E30 AD6 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 K1
MDA37 F16 E26 QSA#2 MDB37 AD1 P1 QSB#2
MDA38 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 QSA#3 MDB38 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 QSB#3
D15 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C20 AD3 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 W4
MDA39 E14 C16 QSA#4 MDB39 AD5 AC4 QSB#4
MDA40 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 QSA#5 MDB40 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 QSB#5
F14 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 C12 AF1 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 AH3
MDA41 D13 J11 QSA#6 MDB41 AF3 AJ8 QSB#6
MDA42 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 QSA#7 MDB42 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 QSB#7
F12 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 F8 AF6 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7 AM3
MDA43 A12 MDB43 AG4
MDA44 DQA1_11/DQA_43 ODTA0 MDB44 DQB1_11/DQB_43 ODTB0
D11 DQA1_12/DQA_44 ADBIA0/ODTA0 J21 ODTA0 46 AH5 DQB1_12/DQB_44 ADBIB0/ODTB0 T7 ODTB0 47
MDA45 F10 G19 ODTA1 MDB45 AH6 W7 ODTB1
DQA1_13/DQA_45 ADBIA1/ODTA1 ODTA1 46 DQB1_13/DQB_45 ADBIB1/ODTB1 ODTB1 47
MDA46 A10 MDB46 AJ4
MDA47 DQA1_14/DQA_46 CLKA0 MDB47 DQB1_14/DQB_46 CLKB0
C10 DQA1_15/DQA_47 CLKA0 H27 CLKA0 46 AK3 DQB1_15/DQB_47 CLKB0 L9 CLKB0 47
MVDDQ MDA48 G13 G27 CLKA0# MDB48 AF8 L8 CLKB0#
DQA1_16/DQA_48 CLKA0B CLKA0# 46 DQB1_16/DQB_48 CLKB0B CLKB0# 47
MDA49 H13 MDB49 AF9
MDA50 DQA1_17/DQA_49 CLKA1 MDB50 DQB1_17/DQB_49 CLKB1
J13 DQA1_18/DQA_50 CLKA1 J14 CLKA1 46 AG8 DQB1_18/DQB_50 CLKB1 AD8 CLKB1 47
MDA51 H11 H14 CLKA1# MDB51 AG7 AD7 CLKB1#
DQA1_19/DQA_51 CLKA1B CLKA1# 46 DQB1_19/DQB_51 CLKB1B CLKB1# 47
GR25 MDA52 G10 MVDDQ MDB52 AK9
40.2,1% MDA53 DQA1_20/DQA_52 RASA0# MDB53 DQB1_20/DQB_52 RASB0#
G8 DQA1_21/DQA_53 RASA0B K23 RASA0# 46 AL7 DQB1_21/DQB_53 RASB0B T10 RASB0# 47
Madison MDA54 K9 K19 RASA1# MDB54 AM8 Y10 RASB1#
DQA1_22/DQA_54 RASA1B RASA1# 46 DQB1_22/DQB_54 RASB1B RASB1# 47
MDA55 K10 MDB55 AM7
MVDDQ MDA56 DQA1_23/DQA_55 CASA0# GR26 MDB56 DQB1_23/DQB_55 CASB0#
G9 K20 AK1 W10
1uF/10V,X5R

DQA1_24/DQA_56 CASA0B CASA0# 46 DQB1_24/DQB_56 CASB0B CASB0# 47


MDA57 A8 K17 CASA1# 40.2,1% MDB57 AL4 AA10 CASB1#
DQA1_25/DQA_57 CASA1B CASA1# 46 DQB1_25/DQB_57 CASB1B CASB1# 47
GR27 MDA58 C8 MDB58 AM6
MDA59 DQA1_26/DQA_58 CSA0#_0 MDB59 DQB1_26/DQB_58 CSB0#_0
GC216

E8 DQA1_27/DQA_59 CSA0B_0 K24 CSA0#_0 46 AM1 DQB1_27/DQB_59 CSB0B_0 P10 CSB0#_0 47


GR28 100,1% MDA60 A6 K27 MVDDQ MDB60 AN4 L10

1uF/10V,X5R
40.2,1% Madison Madison MDA61 DQA1_28/DQA_60 CSA0B_1 MDB61 DQB1_28/DQB_60 CSB0B_1
C6 DQA1_29/DQA_61 AP3 DQB1_29/DQB_61
Madison MDA62 E6 M13 CSA1#_0 GR29 MDB62 AP1 AD10 CSB1#_0
DQA1_30/DQA_62 CSA1B_0 CSA1#_0 46 DQB1_30/DQB_62 CSB1B_0 CSB1#_0 47
MDA63 100,1% MDB63

GC217
A5 DQA1_31/DQA_63 CSA1B_1 K16 AP5 DQB1_31/DQB_63 CSB1B_1 AC10
GR30
1uF/10V,X5R

MVREFDA L18 K21 CKEA0 40.2,1% Ra U10 CKEB0


MVREFDA CKEA0 CKEA0 46 CKEB0 CKEB0 47
GR31 MVDDQ MVREFSA L20 J20 CKEA1 MVREFDB Y12 AA11 CKEB1
MVREFSA CKEA1 CKEA1 46 MVREFDB CKEB1 CKEB1 47
100,1% MVREFSB AA12
GC218

Madison GR32 243,1% MEM_CALRN0 L27 WEA0# VDDR3 MVREFSB WEB0#


K26 N10

1uF/10V,X5R
MEM_CALRN0 WEA0B WEA0# 46 WEB0B WEB0# 47
GR33 243,1% MEM_CALRN1 N12 L15 WEA1# AB11 WEB1#
MEM_CALRN1 WEA1B WEA1# 46 WEB1B WEB1# 47
Madison GR34 243,1% MEM_CALRN2AG12 GR35 Rb GR165 10K ns
MEM_CALRN2 100,1%

GC219
B B
GR36 243,1% MEM_CALRP0 M12 H23 MAA13 TESTEN AD28 T8 MAB13
MEM_CALRP1 M27 MEM_CALRP1 MAA0_8 TESTEN MAB0_8
GDDR5

GDDR5
MEM_CALRP0 MAA1_8 J19 MAB1_8 W8
GR37 243,1% MEM_CALRP2AH12 TEST_MCLK AK10
GR38 243,1% MEM_CALRP2 TEST_YCLK AL10 CLKTESTA DRAM_RST_R GR39 680
CLKTESTB DRAM_RST AH11 DRAM_RST# 46,47

0.1uF/16V,X7R

0.1uF/16V,X7R
GR40

GC220

GC221
1K,1% GR41 GR42
GC222 4.7K 4.7K
68pF/50V,NPO
ns ns
Broadway Broadway

GR43 GR44 MVDDQ


FOR M97, Broadway, Madiso and Park ONLY 49.9,1% 49.9,1%
ns ns
This basic topology should be used for DRAM_RST for
DDR3/GDDR3/GDDR5.These Capacitors and Resistor values
are an example only. The Series R and || Cap values
will depend on the DRAM load and will have to be
route 50ohms single-ended/100ohms diff calculated for different Memory ,DRAM Load and board
and keep short to pass Reset Signal Spec.
Debug only, for clock observation, if not needed, DNI

Designator For M97-M2 For Mannhatton

DDR3/GDDR3 Memory Stuff Option R_MEM_1 10K 10K

GDDR5 GDDR3 DDR3 R_MEM_2 0R/Short 680R


A A

MVDDQ 1.5V 1.8V/1.5V 1.5V R_MEM_3 DNI DNI

Ra 40.2R 40.2R 40.2R C_MEM 2.2nF 68pF

Rb 100R 100R 100R


CZC Technology zw
Title
Madison Memory

Size Project Name Rev


C R48 C

Date: Thursday, April 22, 2010 Sheet 45 of 56


5 4 3 2 1
5 4 3 2 1

Samsung E-die
1GHz K4W1G1646E-HC1A
Qimonda A1-die IDGH1G-04A1F1C-18
CHANNEL A: 256MB/512MB DDR3 900MHz Samsung E-die
Hynix Orion-die
K4W1G1646E-HC11
H5TQ1G63BFR-12C
800MHz
DDR3 Qimonda A1-die IDGH1G-04A1F1C-16
Size per Part Configuration Row x Col x Bank bits 64M X 16bit Samsung E-die K4W1G1646E-HC12
1024 Mbit 8 M x 16 x 8 13 x 10 x 3
700MHz Hynix Tiva-die H5TQ1G63AFR-14C
Hynix Orion-die H5TS1G63BFR-1
Samsung D-die K4W1G1646D-EC15
D MDA[63:0] 667MHz D
45 MDA[63:0] Samsung E-die K4W1G1646E-HC15
QSA[7:0]
45 QSA[7:0] Qimonda A1-die IDGH1G-04A1F1C-13
QSA#[7:0] MVDDQ
45 QSA#[7:0] Parts in red print are assigned the highest priority for Manhattan qualification. MVDDQ 35,36,43,45,47
MVDDQ DQMA#[7:0] MVDDQ MVDDQ
45 DQMA#[7:0]
MVDDQ +V1.5_REG
+V1.5_REG

GR45 GR46 GR48


4.99K,1% GU2 4.99K,1% GU5 4.99K,1% GU3 GR47
4.99K,1% GU4
VREFC_U20 M8 E3 MDA20 VREFC_U21 M8 E3 MDA31 VREFC_U22 M8 E3 MDA35
VREFD_U20 VREFCA DQL0 MDA17 VREFD_U21 VREFCA DQL0 MDA24 VREFD_U22 VREFCA DQL0 MDA36 VREFC_U23 MDA51
H1 F7 H1 F7 H1 F7 M8 E3
0.1uF/16V,X7R

0.1uF/16V,X7R

0.1uF/16V,X7R
VREFDQ DQL1 MDA21 VREFDQ DQL1 MDA29 VREFDQ DQL1 MDA32 VREFD_U23 VREFCA DQL0 MDA52
GC223

GC224

GC225
F2 F2 F2 H1 F7

0.1uF/16V,X7R
45 MAA[13:0] DQL2 45 MAA[13:0] DQL2 45 MAA[13:0] DQL2 VREFDQ DQL1
GR54 MAA0 N3 MDA18 GR50 MAA0 N3 MDA26 GR55 MAA0 N3 MDA39 MDA49

GC226
A0 DQL3 F8 A0 DQL3 F8 A0 DQL3 F8 45 MAA[13:0] DQL2 F2
4.99K,1% MAA1 P7 H3 MDA23 4.99K,1% MAA1 P7 H3 MDA28 4.99K,1% MAA1 P7 H3 MDA34 GR51 MAA0 N3 F8 MDA53
MAA2 P3 A1 DQL4 MDA16 MAA2 P3 A1 DQL4 MDA27 MAA2 P3 A1 DQL4 MDA38 4.99K,1% MAA1 P7 A0 DQL3 MDA48
A2 DQL5 H8 A2 DQL5 H8 A2 DQL5 H8 A1 DQL4 H3
MAA3 N2 G2 MDA22 MAA3 N2 G2 MDA30 MAA3 N2 G2 MDA33 MAA2 P3 H8 MDA54
MAA4 P8 A3 DQL6 MDA19 MAA4 P8 A3 DQL6 MDA25 MAA4 P8 A3 DQL6 MDA37 MAA3 N2 A2 DQL5 MDA50
A4 DQL7 H7 A4 DQL7 H7 A4 DQL7 H7 A3 DQL6 G2
MAA5 P2 MAA5 P2 MAA5 P2 MAA4 P8 H7 MDA55
MVDDQ MAA6 R8 A5 MVDDQ MAA6 R8 A5 MVDDQ MAA6 R8 A5 MAA5 P2 A4 DQL7
MAA7 R2 A6 MDA0 MAA7 R2 A6 MDA15 MAA7 R2 A6 MDA43 MVDDQ MAA6 R8 A5
A7 DQU0 D7 A7 DQU0 D7 A7 DQU0 D7 A6
MAA8 T8 C3 MDA4 MAA8 T8 C3 MDA10 MAA8 T8 C3 MDA45 MAA7 R2 D7 MDA63
MAA9 R3 A8 DQU1 MDA1 MAA9 R3 A8 DQU1 MDA14 MAA9 R3 A8 DQU1 MDA40 MAA8 T8 A7 DQU0 MDA59
A9 DQU2 C8 A9 DQU2 C8 A9 DQU2 C8 A8 DQU1 C3
GR52 MAA10 L7 C2 MDA6 GR49 MAA10 L7 C2 MDA11 GR53 MAA10 L7 C2 MDA44 MAA9 R3 C8 MDA62
4.99K,1% MAA11 R7 A10/AP DQU3 MDA3 4.99K,1% MAA11 R7 A10/AP DQU3 MDA12 4.99K,1% MAA11 R7 A10/AP DQU3 MDA42 GR56 MAA10 L7 A9 DQU2 MDA56
A11 DQU4 A7 A11 DQU4 A7 A11 DQU4 A7 A10/AP DQU3 C2
MAA12 N7 A2 MDA7 MAA12 N7 A2 MDA8 MAA12 N7 A2 MDA47 4.99K,1% MAA11 R7 A7 MDA60
MAA13 T3 A12/BC DQU5 MDA2 MAA13 T3 A12/BC DQU5 MDA13 MAA13 T3 A12/BC DQU5 MDA41 MAA12 N7 A11 DQU4 MDA57
A13 DQU6 B8 A13 DQU6 B8 A13 DQU6 B8 A12/BC DQU5 A2
T7 A3 MDA5 T7 A3 MDA9 T7 A3 MDA46 MAA13 T3 B8 MDA61
0.1uF/16V,X7R

0.1uF/16V,X7R

0.1uF/16V,X7R
A14 DQU7 A14 DQU7 A14 DQU7 A13 DQU6 MDA58
GC227

GC228

GC229
M7 M7 M7 T7 A3

0.1uF/16V,X7R
GR57 A15 MVDDQ GR58 A15 MVDDQ GR59 A15 MVDDQ A14 DQU7

GC230
M7 A15
4.99K,1% 4.99K,1% 4.99K,1% GR60 MVDDQ
A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 4.99K,1%
45 A_BA0 BA0 VDD#B2 45 A_BA0 BA0 VDD#B2 45 A_BA0 BA0 VDD#B2
A_BA1 N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 A_BA0 M2 B2
45 A_BA1 BA1 VDD#D9 45 A_BA1 BA1 VDD#D9 45 A_BA1 BA1 VDD#D9 45 A_BA0 BA0 VDD#B2
A_BA2 M3 G7 A_BA2 M3 G7 A_BA2 M3 G7 A_BA1 N8 D9
45 A_BA2 BA2 VDD#G7 45 A_BA2 BA2 VDD#G7 45 A_BA2 BA2 VDD#G7 45 A_BA1 BA1 VDD#D9
C K2 K2 K2 A_BA2 M3 G7 C
VDD#K2 VDD#K2 VDD#K2 45 A_BA2 BA2 VDD#G7
VDD#K8 K8 VDD#K8 K8 VDD#K8 K8 VDD#K2 K2
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#K8 K8
CLKA0 J7 N9 CLKA0 J7 N9 CLKA1 J7 N9 N1
45 CLKA0 CK VDD#N9 45 CLKA0 CK VDD#N9 45 CLKA1 CK VDD#N9 VDD#N1
CLKA0# K7 R1 CLKA0# K7 R1 CLKA1# K7 R1 CLKA1 J7 N9
45 CLKA0# CK VDD#R1 45 CLKA0# CK VDD#R1 45 CLKA1# CK VDD#R1 45 CLKA1 CK VDD#N9
CKEA0 K9 R9 CKEA0 K9 R9 CKEA1 K9 R9 CLKA1# K7 R1
45 CKEA0 CKE VDD#R9 45 CKEA0 CKE VDD#R9 45 CKEA1 CKE VDD#R9 45 CLKA1# CK VDD#R1
MVDDQ MVDDQ MVDDQ CKEA1 K9 R9
45 CKEA1 CKE VDD#R9 MVDDQ
56.2,1%

56.2,1%

56.2,1%

56.2,1%
ODTA0 K1 A1 ODTA0 K1 A1 ODTA1 K1 A1
45 ODTA0 ODT VDDQ#A1 45 ODTA0 ODT VDDQ#A1 45 ODTA1 ODT VDDQ#A1
CSA0#_0 L2 A8 CSA0#_0 L2 A8 CSA1#_0 L2 A8 ODTA1 K1 A1
45 CSA0#_0 CS VDDQ#A8 45 CSA0#_0 CS VDDQ#A8 45 CSA1#_0 CS VDDQ#A8 45 ODTA1 ODT VDDQ#A1
RASA0# J3 C1 RASA0# J3 C1 RASA1# J3 C1 CSA1#_0 L2 A8
45 RASA0# RAS VDDQ#C1 45 RASA0# RAS VDDQ#C1 45 RASA1# RAS VDDQ#C1 45 CSA1#_0 CS VDDQ#A8
CASA0# K3 C9 CASA0# K3 C9 CASA1# K3 C9 RASA1# J3 C1
45 CASA0# CAS VDDQ#C9 45 CASA0# CAS VDDQ#C9 45 CASA1# CAS VDDQ#C9 45 RASA1# RAS VDDQ#C1
WEA0# WEA0# WEA1# CASA1#
GR61

GR62

GR63

GR64
45 WEA0# L3 WE VDDQ#D2 D2 45 WEA0# L3 WE VDDQ#D2 D2 45 WEA1# L3 WE VDDQ#D2 D2 45 CASA1# K3 CAS VDDQ#C9 C9
E9 E9 E9 WEA1# L3 D2
VDDQ#E9 VDDQ#E9 VDDQ#E9 45 WEA1# WE VDDQ#D2
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#E9 E9
QSA2 F3 H2 QSA3 F3 H2 QSA4 F3 H2 F1
GC231 QSA0 DQSL VDDQ#H2 QSA1 DQSL VDDQ#H2 GC232 QSA5 DQSL VDDQ#H2 QSA6 VDDQ#F1
C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 F3 DQSL VDDQ#H2 H2
0.01uF/25V,X7R 0.01uF/25V,X7R QSA7 C7 H9
DQSU VDDQ#H9
DQMA#2 E7 A9 DQMA#3 E7 A9 DQMA#4 E7 A9
DQMA#0 D3 DML VSS#A9 DQMA#1 D3 DML VSS#A9 DQMA#5 D3 DML VSS#A9 DQMA#6 E7
DMU VSS#B3 B3 DMU VSS#B3 B3 DMU VSS#B3 B3 DML VSS#A9 A9
E1 E1 E1 DQMA#7 D3 B3
VSS#E1 VSS#E1 VSS#E1 DMU VSS#B3
VSS#G8 G8 VSS#G8 G8 VSS#G8 G8 VSS#E1 E1
QSA#2 G3 J2 QSA#3 G3 J2 QSA#4 G3 J2 G8
QSA#0 DQSL VSS#J2 QSA#1 DQSL VSS#J2 QSA#5 DQSL VSS#J2 QSA#6 VSS#G8
B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 G3 DQSL VSS#J2 J2
M1 M1 M1 QSA#7 B7 J8
VSS#M1 VSS#M1 VSS#M1 DQSU VSS#J8
VSS#M9 M9 VSS#M9 M9 VSS#M9 M9 VSS#M1 M1
VSS#P1 P1 VSS#P1 P1 VSS#P1 P1 VSS#M9 M9
DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 P1
45,47 DRAM_RST# RESET VSS#P9 45,47 DRAM_RST# RESET VSS#P9 45,47 DRAM_RST# RESET VSS#P9 VSS#P1
T1 T1 T1 DRAM_RST# T2 P9
VSS#T1 VSS#T1 VSS#T1 45,47 DRAM_RST# RESET VSS#P9
L8 ZQ VSS#T9 T9 L8 ZQ VSS#T9 T9 L8 ZQ VSS#T9 T9 VSS#T1 T1
Should be 240 Should be 240 L8 ZQ VSS#T9 T9
Should be 240 Ohms +-1% Ohms +-1% Should be 240
GR65 B1 GR66 B1 GR67 B1
Ohms +-1% 243,1% VSSQ#B1 243,1% VSSQ#B1 243,1% VSSQ#B1 Ohms +-1% GR68
VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B1 B1
D1 D1 D1 243,1% B9
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#B9
VSSQ#D8 D8 VSSQ#D8 D8 VSSQ#D8 D8 VSSQ#D1 D1
B VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#D8 D8 B
J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 VSSQ#E2 E2
L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 J1 NC#J1 VSSQ#E8 E8
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 L1 NC#L1 VSSQ#F9 F9
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 J9 NC#J9 VSSQ#G1 G1
L9 NC#L9 VSSQ#G9 G9
100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 100-BALL
23E22387MNG8 23E22387MNG8 23E22387MNG8 SDRAM DDR3
23E22387MNG8

MVDDQ
MVDDQ MVDDQ
MVDDQ

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R
GC245

GC246

GC247

GC233

GC248
1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R
GC238

GC239

GC250

GC240

GC251

GC241

GC242

GC243

GC244

GC252
1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R
GC234

GC235

GC236

GC249

GC237

MVDDQ MVDDQ
10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R
GC253

GC254

GC255

GC256

GC257

GC258

GC259

GC260
A CT4 CT3 A
All component should no stuff for PARK. 22uF/6.3V,TAN 22uF/6.3V,TAN
ns ns

CZC Technology zw
Title
Madison Memory DDR3 Channel A

Size Project Name Rev


C R48 C

Date: Thursday, April 22, 2010 Sheet 46 of 56


5 4 3 2 1
5 4 3 2 1

CHANNEL B: 256MB/512MB DDR3


MDB[63:0]
45 MDB[63:0]
MVDDQ
QSB[7:0] MVDDQ 35,36,43,45,46
45 QSB[7:0]
QSB#[7:0]
45 QSB#[7:0]
DQMB#[7:0]
45 DQMB#[7:0]

D D

MVDDQ MVDDQ
MVDDQ MVDDQ

GR69 GR70
4.99K,1% GU6 4.99K,1% GU7 GR71 GR72
4.99K,1% GU9 4.99K,1% GU8
VREFC_U24 M8 E3 MDB31 VREFC_U25 M8 E3 MDB20
VREFD_U24 VREFCA DQL0 MDB24 VREFD_U25 VREFCA DQL0 MDB18 VREFC_U26 MDB34 VREFC_U27 MDB51
H1 F7 H1 F7 M8 E3 M8 E3
0.1uF/16V,X7R

0.1uF/16V,X7R
VREFDQ DQL1 MDB30 VREFDQ DQL1 MDB22 VREFD_U26 VREFCA DQL0 MDB37 VREFD_U27 VREFCA DQL0 MDB52
GC261

GC262
F2 F2 H1 F7 H1 F7

0.1uF/16V,X7R

0.1uF/16V,X7R
45 MAB[13:0] DQL2 45 MAB[13:0] DQL2 VREFDQ DQL1 VREFDQ DQL1
GR74 MAB0 N3 MDB26 GR75 MAB0 N3 MDB16 MDB32 MDB49

GC263

GC264
A0 DQL3 F8 A0 DQL3 F8 45 MAB[13:0] DQL2 F2 45 MAB[13:0] DQL2 F2
4.99K,1% MAB1 P7 H3 MDB28 4.99K,1% MAB1 P7 H3 MDB21 GR73 MAB0 N3 F8 MDB39 GR76 MAB0 N3 F8 MDB55
MAB2 P3 A1 DQL4 MDB27 MAB2 P3 A1 DQL4 MDB17 4.99K,1% MAB1 P7 A0 DQL3 MDB36 4.99K,1% MAB1 P7 A0 DQL3 MDB48
A2 DQL5 H8 A2 DQL5 H8 A1 DQL4 H3 A1 DQL4 H3
MAB3 N2 G2 MDB29 MAB3 N2 G2 MDB23 MAB2 P3 H8 MDB38 MAB2 P3 H8 MDB54
MAB4 P8 A3 DQL6 MDB25 MAB4 P8 A3 DQL6 MDB19 MAB3 N2 A2 DQL5 MDB33 MAB3 N2 A2 DQL5 MDB50
A4 DQL7 H7 A4 DQL7 H7 A3 DQL6 G2 A3 DQL6 G2
MAB5 P2 MAB5 P2 MAB4 P8 H7 MDB35 MAB4 P8 H7 MDB53
MVDDQ MAB6 R8 A5 MVDDQ MAB6 R8 A5 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
MAB7 R2 A6 MDB15 MAB7 R2 A6 MDB1 MVDDQ MAB6 R8 A5 MVDDQ MAB6 R8 A5
A7 DQU0 D7 A7 DQU0 D7 A6 A6
MAB8 T8 C3 MDB10 MAB8 T8 C3 MDB7 MAB7 R2 D7 MDB43 MAB7 R2 D7 MDB63
MAB9 R3 A8 DQU1 MDB14 MAB9 R3 A8 DQU1 MDB0 MAB8 T8 A7 DQU0 MDB45 MAB8 T8 A7 DQU0 MDB59
A9 DQU2 C8 A9 DQU2 C8 A8 DQU1 C3 A8 DQU1 C3
GR77 MAB10 L7 C2 MDB11 GR78 MAB10 L7 C2 MDB4 MAB9 R3 C8 MDB42 MAB9 R3 C8 MDB62
4.99K,1% MAB11 R7 A10/AP DQU3 MDB12 4.99K,1% MAB11 R7 A10/AP DQU3 MDB3 GR79 MAB10 L7 A9 DQU2 MDB44 GR80 MAB10 L7 A9 DQU2 MDB56
A11 DQU4 A7 A11 DQU4 A7 A10/AP DQU3 C2 A10/AP DQU3 C2
MAB12 N7 A2 MDB8 MAB12 N7 A2 MDB6 4.99K,1% MAB11 R7 A7 MDB40 4.99K,1% MAB11 R7 A7 MDB60
MAB13 T3 A12/BC DQU5 MDB13 MAB13 T3 A12/BC DQU5 MDB2 MAB12 N7 A11 DQU4 MDB47 MAB12 N7 A11 DQU4 MDB57
A13 DQU6 B8 A13 DQU6 B8 A12/BC DQU5 A2 A12/BC DQU5 A2
T7 A3 MDB9 T7 A3 MDB5 MAB13 T3 B8 MDB41 MAB13 T3 B8 MDB61
0.1uF/16V,X7R

0.1uF/16V,X7R
A14 DQU7 A14 DQU7 A13 DQU6 MDB46 A13 DQU6 MDB58
GC265

GC266
M7 M7 T7 A3 T7 A3

0.1uF/16V,X7R

0.1uF/16V,X7R
GR81 A15 MVDDQ GR82 A15 MVDDQ A14 DQU7 A14 DQU7

GC267

GC268
M7 A15 M7 A15
4.99K,1% 4.99K,1% GR83 MVDDQ GR84 MVDDQ
B_BA0 M2 B2 B_BA0 M2 B2 4.99K,1% 4.99K,1%
45 B_BA0 BA0 VDD#B2 45 B_BA0 BA0 VDD#B2
B_BA1 N8 D9 B_BA1 N8 D9 B_BA0 M2 B2 B_BA0 M2 B2
45 B_BA1 BA1 VDD#D9 45 B_BA1 BA1 VDD#D9 45 B_BA0 BA0 VDD#B2 45 B_BA0 BA0 VDD#B2
B_BA2 M3 G7 B_BA2 M3 G7 B_BA1 N8 D9 B_BA1 N8 D9
45 B_BA2 BA2 VDD#G7 45 B_BA2 BA2 VDD#G7 45 B_BA1 BA1 VDD#D9 45 B_BA1 BA1 VDD#D9
K2 K2 B_BA2 M3 G7 B_BA2 M3 G7
VDD#K2 VDD#K2 45 B_BA2 BA2 VDD#G7 45 B_BA2 BA2 VDD#G7
VDD#K8 K8 VDD#K8 K8 VDD#K2 K2 VDD#K2 K2
C
VDD#N1 N1 VDD#N1 N1 VDD#K8 K8 VDD#K8 K8 C
CLKB0 J7 N9 CLKB0 J7 N9 N1 N1
45 CLKB0 CK VDD#N9 45 CLKB0 CK VDD#N9 VDD#N1 VDD#N1
CLKB0# K7 R1 CLKB0# K7 R1 CLKB1 J7 N9 CLKB1 J7 N9
45 CLKB0# CK VDD#R1 45 CLKB0# CK VDD#R1 45 CLKB1 CK VDD#N9 45 CLKB1 CK VDD#N9
CKEB0 K9 R9 CKEB0 K9 R9 CLKB1# K7 R1 CLKB1# K7 R1
45 CKEB0 CKE VDD#R9 45 CKEB0 CKE VDD#R9 45 CLKB1# CK VDD#R1 45 CLKB1# CK VDD#R1
MVDDQ MVDDQ CKEB1 K9 R9 CKEB1 K9 R9
45 CKEB1 CKE VDD#R9 45 CKEB1 CKE VDD#R9
MVDDQ MVDDQ
56.2,1%

56.2,1%

ODTB0 ODTB0 K1

56.2,1%

56.2,1%
45 ODTB0 K1 ODT VDDQ#A1 A1 45 ODTB0 ODT VDDQ#A1 A1
CSB0#_0 L2 A8 CSB0#_0 L2 A8 ODTB1 K1 A1 ODTB1 K1 A1
45 CSB0#_0 CS VDDQ#A8 45 CSB0#_0 CS VDDQ#A8 45 ODTB1 ODT VDDQ#A1 45 ODTB1 ODT VDDQ#A1
RASB0# J3 C1 RASB0# J3 C1 CSB1#_0 L2 A8 CSB1#_0 L2 A8
45 RASB0# RAS VDDQ#C1 45 RASB0# RAS VDDQ#C1 45 CSB1#_0 CS VDDQ#A8 45 CSB1#_0 CS VDDQ#A8
CASB0# K3 C9 CASB0# K3 C9 RASB1# J3 C1 RASB1# J3 C1
45 CASB0# CAS VDDQ#C9 45 CASB0# CAS VDDQ#C9 45 RASB1# RAS VDDQ#C1 45 RASB1# RAS VDDQ#C1
WEB0# WEB0# L3 CASB1# CASB1#
GR85

GR86

45 WEB0# L3 WE VDDQ#D2 D2 45 WEB0# WE VDDQ#D2 D2 45 CASB1# K3 CAS VDDQ#C9 C9 45 CASB1# K3 CAS VDDQ#C9 C9
WEB1# WEB1#

GR87

GR88
VDDQ#E9 E9 VDDQ#E9 E9 45 WEB1# L3 WE VDDQ#D2 D2 45 WEB1# L3 WE VDDQ#D2 D2
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#E9 E9 VDDQ#E9 E9
QSB3 F3 H2 QSB2 F3 H2 F1 F1
GC269 QSB1 DQSL VDDQ#H2 QSB0 DQSL VDDQ#H2 QSB4 VDDQ#F1 QSB6 VDDQ#F1
C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 F3 DQSL VDDQ#H2 H2 F3 DQSL VDDQ#H2 H2
0.01uF/25V,X7R GC270 QSB5 C7 H9 QSB7 C7 H9
0.01uF/25V,X7R DQSU VDDQ#H9 DQSU VDDQ#H9
DQMB#3 E7 A9 DQMB#2 E7 A9
DQMB#1 D3 DML VSS#A9 DQMB#0 DML VSS#A9 DQMB#4 DQMB#6
DMU VSS#B3 B3 D3 DMU VSS#B3 B3 E7 DML VSS#A9 A9 E7 DML VSS#A9 A9
E1 E1 DQMB#5 D3 B3 DQMB#7 D3 B3
VSS#E1 VSS#E1 DMU VSS#B3 DMU VSS#B3
VSS#G8 G8 VSS#G8 G8 VSS#E1 E1 VSS#E1 E1
QSB#3 G3 J2 QSB#2 G3 J2 G8 G8
QSB#1 DQSL VSS#J2 QSB#0 DQSL VSS#J2 QSB#4 VSS#G8 QSB#6 VSS#G8
B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 G3 DQSL VSS#J2 J2 G3 DQSL VSS#J2 J2
M1 M1 QSB#5 B7 J8 QSB#7 B7 J8
VSS#M1 VSS#M1 DQSU VSS#J8 DQSU VSS#J8
VSS#M9 M9 VSS#M9 M9 VSS#M1 M1 VSS#M1 M1
VSS#P1 P1 VSS#P1 P1 VSS#M9 M9 VSS#M9 M9
DRAM_RST# T2 P9 DRAM_RST# T2 P9 P1 P1
45,46 DRAM_RST# RESET VSS#P9 45,46 DRAM_RST# RESET VSS#P9 VSS#P1 VSS#P1
T1 T1 DRAM_RST# T2 P9 DRAM_RST# T2 P9
VSS#T1 VSS#T1 45,46 DRAM_RST# RESET VSS#P9 45,46 DRAM_RST# RESET VSS#P9
L8 ZQ VSS#T9 T9 L8 ZQ VSS#T9 T9 VSS#T1 T1 VSS#T1 T1
Should be 240 Should be 240 L8 ZQ VSS#T9 T9 L8 ZQ VSS#T9 T9
Ohms +-1% Ohms +-1% Should be 240 Should be 240
GR89 B1 GR90 B1
243,1% VSSQ#B1 243,1% VSSQ#B1 Ohms +-1% GR91
Ohms +-1% GR92
VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B1 B1 VSSQ#B1 B1
D1 D1 243,1% B9 243,1% B9
VSSQ#D1 VSSQ#D1 VSSQ#B9 VSSQ#B9
VSSQ#D8 D8 VSSQ#D8 D8 VSSQ#D1 D1 VSSQ#D1 D1
VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#D8 D8 VSSQ#D8 D8
J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 VSSQ#E2 E2 VSSQ#E2 E2
B
L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 B
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9
100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 100-BALL 100-BALL
23E22387MNG8 23E22387MNG8 SDRAM DDR3 SDRAM DDR3
23E22387MNG8 23E22387MNG8

MVDDQ
MVDDQ MVDDQ
MVDDQ

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R
GC284

GC285

GC271

GC279

GC289
1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R
GC287

GC273

GC274

GC282

GC275

GC288

GC276

GC277

GC278

GC283
1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R
GC272

GC286

GC280

GC290

GC281

MVDDQ MVDDQ

A A
10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R

10UF/6.3V,X5R
GC291

GC292

GC293

GC294

GC295

GC296

GC297

GC298
CZC Technology zw
Title
Madison Memory DDR3 Channel A

Size Project Name Rev


C R48 C

Date: Thursday, April 22, 2010 Sheet 47 of 56


5 4 3 2 1
5 4 3 2 1

+V3.3S 5,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38
VDDR3 16,36,41,42,43,45

VDDR3
D
PIN STRAPS D

GPIO0 GR93 10K ns


42 GPIO0 Supports Half Swing “low-power/low-voltage” mode.
GPIO1 GR94 10K ns
42 GPIO1
GPIO2 GR95 10K ns
CONFIGURATION STRAPS RECOMMENDED SETTINGS
Arrandale Gen1
42 GPIO2 Clarksfield Gen2 0= DO NOT INSTALL RESISTOR
GPIO8_ROMSO GR96 10K ns 1 = INSTALL 10K RESISTOR
42 GPIO8_ROMSO
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, X = DESIGN DEPENDANT
GPIO9_ROMSI GR97 10K ns NA = NOT APPLICABLE
42 GPIO9_ROMSI THEY MUST NOT CONFLICT DURING RESET
GPIO11 GR98 10K ns
42 GPIO11
GPIO12 GR99 10K ns STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
42 GPIO12
GPIO13 GR100 10K ns
42 GPIO13
VSYNC_DAC1 GR101 10K
20,42 VSYNC_DAC1
HSYNC_DAC1 GR102 10K
20,42 HSYNC_DAC1

42 GENERICC GR103 10K ns


TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 1
V2SYNC GR104 10K ns
42 V2SYNC
TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 1
H2SYNC GR105 10K ns
42 H2SYNC
BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 1
GPIO22_ROMCS# GR106 10K ns
42 GPIO22_ROMCS#
BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0
GR107 10K BIF_VGA DIS GPIO9_ROMSI VGA ENABLED 0
42 GPIO5_AC_BATT
BIF_RX_PLL_CALIB_BP GPIO21 BIF_RX_PLL_CALIB_BP 0

BIOS_ROM_EN GPIO22_ROMCS# ENABLE EXTERNAL BIOS ROM 1

ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT X X X

C VDDR3 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0 C


VDDR3
SMS_EN_HARD H2SYNC 0
CCBYPASS GENERICC 0
GR155 VDDR3_TS R517 AUD[1] HSYNC_DAC1 built-in HDMI connector 1
GR156 100 AUD[0] VSYNC_DAC1 Audio functiuon present 1
1

2.2K GR163 C142


2.2K 2.2K
0.1uF/16V,X7R
2

GR157 ns
42 SCL
0 GC299
GR158 ns GU30 2200pF/25V,X7R
42 SDA
1

0 ns
VCC

GR161 clk 8 2
27,31 BAT_CLK SMBCLK DXP GPU_DPLUS 42
0
dat
27,31 BAT_DATA
GR162
0
7 SMBDATA DXN 3 GPU_DMINUS 42 AMD RESERVED CONFIGURATION STRAPS
G781
6 ADM1032AR VDDR3_TS ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
42 GPIO17_THERMAL_INIT ALERT# LM86CIM
TP17 G781_PULLHIGH 4 MAX6657MSA THEY MUST NOT CONFLICT DURING RESET
GND

THERM# SOIC-8
U18
1

TSSOP8_P65_3P0 H2SYNC GENERICC


5

W83L771 TSSOP8
VCC

clk 8 2 GPU_DPLUS
SMBCLK DXP
dat GPU_DMINUS
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
7 SMBDATA DXN 3
THEY MUST NOT CONFLICT DURING RESET
G781
GPIO17_THERMAL_INIT 6 ADM1032AR
ALERT# LM86CIM GPIO_28_TDO GPIO21_BB_EN
G781_PULLHIGH 4 MAX6657MSA
GND

THERM# SOIC-8

SOIC8_1P27_3P9 W83L771ASG
5

B B

+V3.3S
GR160 0 VDDR3

Q24
AO3415

2 3

GR159 SOT23
1

10K GC300 ns
ns 0.1uF/16V,X7R
ns
16 DGPU_PWR_EN#_VDDR3

A A

CZC Technology zw
Title
Madison Thermal Straps

Size Project Name Rev


C R48 C

Date: Thursday, April 22, 2010 Sheet 48 of 56


5 4 3 2 1
5 4 3 2 1

8
G_AUD 1 8
MIC1_L USB_FB1 220ohm/100MHz,2A 2 L G_AUD 1
FB0603 6 LINEOUT_L USB_FB2 220ohm/100MHz,2A 2 L
MIC1_R USB_FB3 220ohm/100MHz,2A 3 FB0603 6
FB0603 4 R LINEOUT_R USB_FB4 220ohm/100MHz,2A 3
MIC1_JD 5 FB0603 4 R
7 HP_JD 5 USB_HP_OUT1
USB_C1 USB_C2 USB_MIC_IN1 7
D phoneJack phoneJack D
USB_C4 100pF/50V,NPO 100pF/50V,NPO Audio8P2 Audio8P2
C0402 C0402 USB_C5 USB_C6
0.1uF/16V,X7R USB_C3
100pF/50V,NPO 100pF/50V,NPO
0.1uF/16V,X7R C0402 C0402 PJ3043T
PJ3043T USB_R1 0
G_AUD R0603
G_AUD ns

G_AUD
GND_JACK

R1135 0
Vbus R1136 0 USB_eSATA_CN
Vbus

100uF/10V,TAN
P1 VBUS
USB_PN7 4 3 P2
C419 USB_PP7 D-

CT7343_28
1 2 P3 USB
0.1uF/16V,X7R + 90ohm@100MHz,0.5A D+

C1270
P4 GND1
CHK15 L4S2012 P12
ns GND5
GND6 P13
P5 GND2 GND7 P14
1 1 eSATA_TXP2 P6 P15
eSATA_TXN2 A+ GND8
P7 A-
D76 D77 P8 eSATA
EGA10603V05A1-B EGA10603V05A1-B eSATA_RXN2 GND3
P9 B-
GND_JACK eSATA_RXP2 P10
C B+ C
2 2 P11 GND4
USB_eSATA CONN
ESATA_USBD11
GND_JACK GND_JACK
GND_JACK

B B
C10756-10403-L
Vbus USB2
SINGLE USB PORT
FB101 R1131 0 USB4H49IN
1 120ohm/100MHz,2.5A R1132 0 USB_VCC 1
1 USB_VCC VCC1
2 2 HOLE0 5
3 FB102 USB_PN6 1 2 2 6
3 120ohm/100MHz,2.5A USB_PP6 -DATA1 HOLE1
4 4 3

100uF/10V,TAN
4 3 +DATA1 HOLE2 7
5 5 HOLE3 8
L4S2012

CT7343_28
6 6 4 GND
90ohm@100MHz,0.5A C1268

C1266
7 7 +
8 GND_JACK eSATA_RXN2 CHK14 0.1uF/16V,X7R
8 eSATA_RXP2 1 1
9 9 ns
27 10 GND_JACK
27 10 eSATA_TXN2 D74 D75
11 11
12 eSATA_TXP2 EGA10603V05A1-B EGA10603V05A1-B
12 GND_JACK
13 13
14 USB_PP7 2 2
14 USB_PN7 H1 GND_JACK
15 15
16 GND_JACK BOSS
16 USB_PP6 MH28X40X65
17 17
28 18 USB_PN6 ns GND_JACK
28 18
19 19
20 GND_JACK MIC1_L
20 MIC1_R H2
21 21
MIC1_JD
1

22 BOSS
22 MH28X40X65
23 23 G_AUD
1

A 24 LINEOUT_L ns A
24 LINEOUT_R
25 25
GND_JACK 26 HP_JD
26
USB_R2 0 R0603
1

85201-26XX
85201-26xx
ns
CZC Technology
1

FPC26_1P0RT USB_R3 0 R0603


USB_CN3 ns zw
Title
USB AUDIO board
G_H GND_JACK
G_AUD Size Project Name Rev
A3 R48 C

Date: Thursday, April 22, 2010 Sheet 49 of 56


5 4 3 2 1
5 4 3 2 1

D D

R1143 0 R0402_0
R1144 0 R0402_0 CASE_GND
L4S2012

10
B_MDI0+ 1 2 RJ45_MDI0+
B_MDI0- 4 3 RJ45_MDI0-
16

VUSB TestP TPC60 ns ns


90ohm@100MHz,0.5A
1 DC_CHK1 RJ45_MDI0+ 1 TX+
2 RJ45_MDI0- 2 TX- C100G6 alltop
USB_PN11 TP35 R1145 0 R0402_0 RJ45_MDI1+ TX+
3 3 RX+
TX-
Wafer15P1 4 USB_PP11 TP36 R1146 0 R0402_0 RJ45_MDI2+ 4 NC RX+
DC_DCINCN1 5 L4S2012 RJ45_MDI2- 5 NC RJ45 NC
GND_DC NC
6 B_MDI1+ 1 2 RJ45_MDI1+ RJ45_MDI1- 6 RX-
B_MDI3- B_MDI1- RX-
7 4 3 ns RJ45_MDI1- RJ45_MDI3+ 7 NC NC
8 B_MDI3+ 90ohm@100MHz,0.5A RJ45_MDI3- 8 NC NC
9 B_MDI2- DC_CHK2
10 B_MDI2+
11 B_MDI1- R1147 0 R0402_0 DC_LAN1
12 B_MDI1+ R1148 0 R0402_0 RJ45
13 B_MDI0- L4S2012 RJS45P8H68

9
C 14 B_MDI0+
15SMH_SPLANE
B_MDI2+
B_MDI2-
1
4
2
3 ns
RJ45_MDI2+
RJ45_MDI2- C
DC_CHK3 90ohm@100MHz,0.5A
17

R1149 0 R0402_0 CASE_GND


R1150 0 R0402_0
L4S2012
B_MDI3+ 1 2 RJ45_MDI3+
GND_DC
87213-xxx0x-x B_MDI3- 4 3 ns RJ45_MDI3-
ACES DC_CHK4 90ohm@100MHz,0.5A

DC_C1 1000pF/50V,X7R

DC_C2 1000pF/50V,X7R

DC_C3 4.7uF/10V,X5R
DC_C4 C0603
SMH_SPLANE CASE_GND DC_C5 4.7uF/10V,X5R
C0603
2200pF/2KV,X7R

C1808
GND_DC

H3
B BOSS B
MH28X40X65
ns

11
CASE_GND

A A

CZC Technology
Title
RJ45

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 50 of 56


5 4 3 2 1

BT_CN2 +V3.3AUX_Q
88511-12XX
FPCE12_P5R
Iac_P_R T46 ns
1 1 T45 ns
2 2 PWR_LED T47 ns +V3.3AUX_Q
13 13 3 3
SLP_LED T48 ns BT_R7 10K BT_R8 1K QKEY1_B
4 4 R0402
5 5 LIDSW#_IO
D
6 6 D

3
QKEY1_B BT_QKEY1
7 7 GPU_LED BT_C8
8 8 SLIDE_INTR# T49 ns
3 4
Button_4P BT_D1 100pF/50V,NPO
9 9 EC_SMB1_DAT T50 ns BAT54SPT C0402
14 1410 10 1 2
EC_SMB1_CLK T51 ns SOT23
11 11 SWS6D50 ns
12 12

5
6

2
GND_Q
+V3.3AUX_Q
GND_Q GND_Q
GND_Q GND_Q
88511
ACES
+V3.3AUX_Q

BT_R9
330
R0402

GPU+
C C
LED_GPU
BL-HB336G-7-TRB
LED2_0603

3
BT_R10
1K BT_Q3
R0402 2N7002K
GPU_LED 1 SOT23
2

BT_R11
1uF/10V,X5R
R0402

GND_Q
GND_Q

H8
BOSS H6
MH24X40X70 BOSS
B ns MH24X40X70 B
ns

1
1

1
GND_Q
GND_Q

+V3.3AUX_Q

GPU+ BT_C9 1000pF/50V,X7R


C0402

DC_R1 DC__C1
51K 0.1uF/16V,X7R
DC_U1 C0402
GND_Q OCH168TWAD
A
SOT23 A
VS+ 1 GND_Q
2 LIDSW#_IO
Output
3 DC_C6
GND 1000pF/50V,X7R
C0402
CZC Technology zw
Title
QKey LID Board

Size Project Name Rev


GND_Q A3 R48 C

Date: Thursday, April 22, 2010 Sheet 51 of 56


5 4 3 2 1
5 4 3 2 1

GND_PWR

IacP_PWR

D PWRKEY1 D

5
6
3 4 BT_R12 0 R0402

1 2 BT_R13 20K R0402 PWRSWVCC_S5

Button_4P
SWS6D50
BT_C10 BT_C11
1000pF/50V,X7R
C0402 C0402
1000pF/50V,X7R

GND_PWR

C +V3.3AUX_PWR +V3.3AUX_PWR C

BT_R14
330 BT_R15
PWR_LED+

R0402 330
R0402
slp+

LED_PWR LED_SLP
BL-HB336G-7-TRB BL-HB336G-7-TRB
LED2_0603 LED2_0603
PWR_LED_B

PWR_LED_B

B B

87213-xxx0x-x
IacP_PWR
Aces
7

slp+ BT_C12 1000pF/50V,X7R 6 +V3.3AUX_PWR


C0402 5 PWRSWVCC_S5
PWR_LED+ BT_C13 1000pF/50V,X7R 4
C0402 3 PWR_LED_B
2 SLP_LED_B
T13 ns
1

GND_PWR Wafer6P10
8

A PWRBTN_CN1 A
hws6_1p0r

GND_PWR

CZC Technology zw
Title
PWR_BTN Board

Size Project Name Rev


A3 R48 C

Date: Thursday, April 22, 2010 Sheet 52 of 56


5 4 3 2 1
5 4 3 2 1

BATT+
Q?
BATT+
2 +VDC AUX Power 4B +VDC Charge
AD+ +V3.3AL
OZ8618LN AC_IN#
D Q? OZ815LN 3A +V5AL D

CHARGE ON
AC_IN#
AD+ 1 AC_ON
4A 5B PM_RSMRST# PM_RSMRST# 4A 5B

PWRSWVCC2 PWRSW#
+VDC
3B 5A 6

7 ALWAYS_ON

PWRSW# PWR_BTN# 8

SLP_S3# 9
13 12 MAIN ON
PCH
+V1.8S OZ8033
SLP_S4# 9
C 11 V11S_ON WPC8763L C
+VCC_CORE
SYS Power
+V_S

DRAM_PWROK
IMVP_ON 17

CPU_PWROK
CPU Power IMVP_OK

PLT_RST#
SYS_PWROK
13 OZ8111 16 OZ8292 AND
Delay 100ms
MAIN_PWROK PCH_PWROK
12 ME_PWROK
+V3.3S
+V5S +V1.1S/V1.1S_VTT 17
CLK_EN
+V1.5S
V1_8_ON
1.1S_PWR_OK 10

10
OZ812LN +V1.5
0.75_ON 14 18 19 20
AND +V1.5 +0.75S
1.5S_PWROK

VCCP_PWRGD_1
DRAM_PWROK

RSTIN#
VCCP_PWRGD_0
B 14 B
+V0.75S

MCP
RST_OBS#
21

CPU_RST#
+V1.5_PWROK
15 +V1.1S_15S_PWROK
+V1.1S_PWROK MAIN_PWROK VTT_PWROK
AND
13
+V1.8S_PWROK
+V1.5S_PWROK

SLP_S3#

Note:
*A:For adapter in
*B:For battery only
A * :For all A
CZC Technology zw
Title

<Title>
Size Project Name Rev

A4 R48 C
Date:
Thursday, April 22, 2010 Sheet
53 of
56
5 4 3 2 1

4. Schematic modify Item and history;


2009-12-03:
1. first Release and generate netfile.
2010-01-08:
1. P13 stuff R97。
2. P14 Add R359 R360
3. P16 Change R1005 pull high to VDDR3.
D No stuff R204 D
4. P19 Change D62 to R299
Correct channel A/B connection of GPU LVDS.
5. P21 ns R457 R458
6. P22 Change NEW_CARD_CLKREQ# pull high to +V3.3S(R282)
7. P25 Add MDCCN1
ns D26
7. P27 Add R436 1K,
Add BT_LED# to EC

8. P29 change wifi LED connection,Touchpad CONN connection.


9. P42 Add GR125 GR126 GR127 for the Ver A11 of PARK. U27.1 change to Madison_pwrok.
10. P43 Add CT5 CT6 reserved.
11. P44 Add Q34 Q35 GR164 GC301
12. P45 Add GR165 for the Ver A11 of PARK.
13. P46 Add CT3 CT4 reserved.
14. P30-P40 change refer to SCH.

VerC change list:


hw:
1,修改部分0ohm电阻封装为R0402_0
2,ns thermal sensor for DIMM(P09)
3,ADD BIOS_LOCK SWITCH。(P13)
4,ns MiniPCIE slot for 3G.(P21)
C 5,ns C1280 C1230 C1234(P24) C
6,Reserved TPA6017A2,adjust amp out(p25)
7,add R524,change R449 to 200K,for fan(p28)
8,ns U19,stuff R1152(p41)
9,add R517 (P48)
10,del BT_Z1 (P52)

pwr:
1、更改R917 R919阻值,设定DDR3电源1.54V
2、1.1S电源增加R1187 R1186 C1296频率调整电路
3、更改R939 R937阻值,调整1.1S电源为1.129V
4、去掉电阻R1179 0ohm电阻,去掉D69续流二极管,更改R978 1K 5%为1K 1%,
5、R1153,R1154,C1277更改value设定GFX电源频率在350KHz
6、OZ8291 DSLP pin改成2.2Kohm下拉到地
7、R1181阻值更改以满足IMONITOR
8、去掉OZ8291 VID 测试电路
9、更改R1014阻值以满足cpucore的loadline,更改R1016 1K 5%为1K 1%,去掉R1182 0ohm电阻
10、OZ8292 DSLP pin接2.2K电阻上拉到5VS以满足imvp6.5
11、更改R1184阻值以满足IMONITOR,去掉D70 D71续流二极管,去掉OZ8292 VID 测试电路

B B

A A
CZC Technology zw
Title

<Title>
Size Project Name Rev

A4 R48 C
Date:
Thursday, April 22, 2010 Sheet
56 of
56

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