Structural Modeling

using
Module Instantiation
Prof. A. K. Swain
Asst. Prof., ECE Dept., NIT Rourkela

EC6203: Reconfigurable System Design

 Module Instantiation
Learning Objectives:
o Describing the continuous assignment (assign) and multiple assignment
statement.
o Explaining net declaration assignment
o Explaining the delays: inertial, transport and net delays.
o Using data flow constructs to model digital circuits.

Module instantiation EC6203 Reconfigurable System Design

 Module Instantiation
• A module can be instantiated in another module, thus creating hierarchy.
Syntax:
module_name instance_name ( port_associations );
• Port associations can be by position or by name; however, associations cannot be mixed.
Port association is of the form:
port_expr // By position.
. PortName ( port_expr ) // By name.

where port_expr can be any of the following:

i. an identifier (a register or a net)
ii. a bit-select
iii. a part-select
iv. a concatenation of the above
v. an expression (only for input ports)
• In positional association, the port expressions connect to the ports in the specified order.
• In association by name, the connection is explicitly specified (order is not important).

Module instantiation EC6203 Reconfigurable System Design

 Ports
• A port can be declared as input, output or inout. (port by default is a net).
• An output or an inout port can optionally be redeclared as a reg register.
• In declaration net or register must have the same size.
Examples:
module Micro {PC, Instr, NextAddr);
// Port declarations
input [3:1] PC,
output [1:8] Instr;
inout [16:1] NextAddr;
// Redeclarations:
wire [16:1] NextAddr; // same range as in its port declaration.
reg [1:8] Instr;
/* Instr has been redeclared as a reg so that it can be
assigned a value within an always statement or an initial
statement. */
endmodule

Module instantiation EC6203 Reconfigurable System Design

 Module Instantiation
module HA (A, B, S, C);
Input A, B;
output S, C;
parameter AND_DELAY = 1 , XOR_DELAY = 2 ;
assign #XOR_DELAY S = A ^ B;
assign #AND_DELAY C = A & B;
endmodule

module FA (P, Q, Cin, Sum, Cout) ,

input P, Q, Cin;
output Sum, Cout;
parameter OR_DELAY = 1;
wire S1, C1, C2;
// Two module instantiations
HA h1 (P, Q, S1, C1); // Associating by position.
HA h2 (.A(Cin), .S(Sum), .B(S1), .C(C2)); //Associating by name.
// Gate instantiation
or #OR_DELAY o1 (Cout, C1, C2) ;
endmodule

Module instantiation EC6203 Reconfigurable System Design

 Unconnected Ports
• Port expression can be
• an identifier (TxData),
• a bit-select (Statas[0]),
• a part-select (Udln[3:0]),
• a concatenation ({WrN, RdN}), or
• an expression (& UdOut[0:l]); //an expression only be connected to an input port.

Unconnected ports in an instantiation can be specified by leaving the port expression blank.
DFF d1 (.Q(QS), . Qbar( ) , .Data(D), . Preset ( ), . Clock (CK)) ; //Byname.
DFF d2 (QS, , D, , CK) ; // By position.
// Output Qbar is not connected.
// Input Preset is open and hence set to value z.

In both the instantiations, ports Qbar and Preset are not connected.
Unconnected module inputs are driven to value z.
Unconnected module outputs are simply unused.

Module instantiation EC6203 Reconfigurable System Design

 Different port length
Port and the local port expression are of different lengths:
• Port matching is performed by (unsigned) right justification or truncation.
Example:
A 5 4 3 2 1 0 X 2 1 0
module test (A, X) ;
input [5:0] A; B 1 2 Y 2 3 4 5 6
output [2:0] X; B[2] <=> A[0] and
Y[6] <=> X[0]
endmodule B[1] <=>A[ 1]
Y[5] <=> X[ 1]
A[5], A[4], A[3] are not connected
module Top; Y[4] <=> X[2]
Remaining input ports=>z
wire [1:2] B;
wire [2:6] Y;
test C1 (.A(B), .X(Y));
endmodule

Module instantiation EC6203 Reconfigurable System Design

 Module Parameter Values
When a module is instantiated in another module, the higher level module can change the value of the parameters in a
lower level module.
This can be done in two ways. NA Ha1 NS
i. Defparam statement , ii. Module instance parameter value assignment. A S
HA
Defparam Statement: XOR_DELAY
AND_DELAY
Syntax: B C
defparam hier_path_name1 = value1 , NB NC
hier_path_name2 = value2,. . . ;
Example-1:
module TOP (NA, NB, NS, NC) ;
input NA, NB;
output NS, NC;
defparam Ha1. XOR_DELAY = 5, // Parameter XOR_DELAY in instance Ha1.
Ha1. AND_DELAY = 2; // Parameter AND_DELAY in instance Ha1.
HA Ha1 (NA, NB, NS, NC) ;
endmodule
* The hierarchical path names of the parameters in a lower level module can be set explicitly.

Module instantiation EC6203 Reconfigurable System Design

 Module Parameter Values
Example-2:
module TOP2 (NP, NQ, NCin, NSum, NCout) ;
input NP, NQ, NCin;
output NSum, NCout;
defparam Fa1.Ha1.XOR_DELAY =2, // Param XOR_DELAY in instance Ha1 of instance Fa1.
Fa1.Ha1.AND_DELAY =2, //Param AND_DELAY in instance Ha1 of instance Fa1.
Fa1.OR_DELAY= 3; // Parameter OR_DELAY in instance Fa1.
FA Fa1 (NP, NQ, NCin, NSum, NCout) ;
endmodule
Fa1
NP Ha1
A NSum
S A S
HA HA
XOR_DELAY
NQ AND_DELAY
XOR_DELAY
B AND_DELAY
C B C
NCout
NCin
OR_DELAY

Module instantiation EC6203 Reconfigurable System Design

 Module Parameter Values
Module Instance Parameter Value Assignment: The new parameter values are specified in the module instantiation itself.
Example-1:
module T0P3 (NA, NB, NS, NC) ;
input NA, NB;
output NS, NC;
HA #(5, 2) Ha1 (NA, NB, NS, NC); //First value 5, is for parameter XOR_DELAY (the first parameter declared in HA).
endmodule //Second value , 2, is for parameter AND_DELAY (the second parameter declared in HA).
Example-2:
module T0P4 (NP, NQ, NCin, NSum, NCout) ;
input NP, NQ, NCin;
output NSum, NCout;
defparam Fa1.Ha1.XOR_DELAY =2, //Parameter XOR_DELAY 11 in instance Ha1 of instance Fa1.
Fa1.Ha1.AND_DELAY=3; //Parameter AND_DELAY in instance Ha1 of instance Fa1.
FA #(3) Fa1 (NP, NQ, NCin, NSum, NCout) ; //Value 3 is the new value for parameter OR_DELAY.
Endmodule

*Notation for specifying parameter values appears identical to that of a delay specified in a gate instantiation.
*No case for concern in a module instantiation since delays cannot be specified for a module
Module instantiation EC6203 Reconfigurable System Design
 Module Parameter Values
Module Instance Parameter Value Assignment: Parameter values could also represent sizes.
Example-3:
module Multiplier (Opd_1 , Opd_2, Result);
parameter M = 4, N = 2; // Parameter is size.
input [M:1] Opd_l ; Defparam statement: No order dependency
input [N: 1] 0pd_2; Module instance parameter: Order dependent
output [M+N : 1] Result ;
assign Result = Opd_1 * Opd_2;
endmodule

An instantiation of an 8-by-6 multiplier.

wire [1:8] P_Reg;
wire [1:6] Dbus ;
wire [1:14] Addr_Counter ;
Multiplier # (8 , 6) M1 (P_Re g , Dbus, Addr_Counter) ;
*First value 8 => a new value for parameter M
* Second value 6 => a new value for parameter N.

Module instantiation EC6203 Reconfigurable System Design

 Design Example
Example-1: Design a decade counter using module instantiation.

Module instantiation EC6203 Reconfigurable System Design

References
Books:
A Verilog HDL Primer: by J Bhasker.
Design Through Verilog HDL: T.R. Padmanavan, B. Bala Tripura Sundari
Verilog Digital Design Synthesis: Samir Palnitkar.

website:
asic-world.com
www.xilinx.com