0

Linear Feedback Shift Register

v3.0
DS257 (v1.0) March 28, 2003 0 0 Product Specification

Features LFSR Type (Fibonacci or Galois)

The LFSR core has the following features: The LFSR can be created using the Galois or Fibonacci
• Drop-in module for Virtex™, Virtex-E, Virtex-II, Virtex-II configuration of gates and registers.
Pro™, Spartan™-II, Spartan-IIE, and Spartan-3 Fibonacci Functionality
FPGAs
• Optional SRL-16 implementation In the Fibonacci implementation, the outputs from some of
the registers are exclusive-ORed with each other and fed
• Choice of LFSR type (Fibonacci or Galois) back to the input of the shift register. Figure 1 shows a 3-bit
• Choice of feedback gate type (XOR or XNOR) Fibonacci LFSR.
• Configurable LFSR length
• Configurable initial tap positions
• Serial or parallel output
• Optional clock enable input
• Optional maximum length logic
• Optional load with configurable load type
• Optional data valid output XIP173

• Optional asynchronous reset Figure 1: 3-bit LFSR

• Optional synchronous reset
When the shift register is loaded with a seed value (any
• Optional counter implementation for maximum length
value except all zeros) and then clocked, the output from the
logic
LFSR (Q2) will be a pseudo-random sequence of 1’s and
• Optional new seed output 0’s. For example, Table 1 shows the sequence that is pro-
• Uses relationally placed macro (RPM) mapping and duced from the circuit in Figure 1 when the seed is 111.
placement technology, for maximum and predictable
performance Table 1: LFSR Sequence for Initial Seed 111
• Incorporates Xilinx Smart-IP™ technology for utmost Q2 Q1 Q0
parameterization and optimum implementation
1 1 1
• To be used with v5.2i and later of the Xilinx CORE
Generator System 1 1 0
1 0 0
Functional Description
0 0 1
The linear feedback shift register (LFSR) is a shift register
which, using feedback, modifies itself on each rising edge of 0 1 0
the clock. The feedback causes the value in the shift regis-
ter to cycle through a set of unique values. The choice of 1 0 1
LFSR length, gate type, LFSR type, maximum length logic, 0 1 1
and tap positions allows the user to control the implementa-
tion and feedback of the LFSR, which, in turn, controls the 1 1 1
sequence of repeating values the LFSR will iterate through.
The pseudo random sequence can also be generated using
exclusive-NOR gates. In this case the seed can be any
value except all 1’s. The sequence that is generated is of the
same length as the exclusive-OR example above.

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NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
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Product Specification 1-800-255-7778
Linear Feedback Shift Register v3.0

The length of the pseudo-random sequence is dependent
on the length of the shift register and the number and the
position of the feedback taps. The number and the position
of the taps are commonly represented by a polynomial. For
the Xilinx core, this is expressed in the form:
P(x) = X3 + X1 + 1
For more information on this polynomial notation and how it
relates to the LFSR implementation, refer to Appendix A:
LFSR Polynomial Notation.
Galois Functionality
In the Galois implementation, the gates are placed between
the registers. Figure 2 shows the Galois implementation of
the LFSR from the previous example. This configuration
produces the sequence shown in Table 2. This shows that
the output sequence (Q2) is the same as the previous
example, although time shifted by 1 cycle.
XIP174
Figure 2: Galois Implementation of a 3-bit LFSR
Feedback Gate Type (XOR or XNOR)
XOR or XNOR gates can be used in the feedback path.
Configurable LFSR Size
The LFSR supports sizes from 2 to 168. This is the number
of registers that make up the shift register. This value is
referred to as LFSR size or C_SIZE for this core, but might
also be referred to as the width or length of the LFSR by
other sources.
Configurable Initial Tap Positions
A series of ones and zeros represent the coefficients of the
LFSR polynomial. These values describe the location of
feedback taps for the LFSR. In the Fibonacci implementa-
tion, the output of some of the registers is combined using
XOR or XNOR gates, then fed back into the input of the first
(LSB) register. These feedback connections from the output
of these selected registers are the tap positions. In the
Galois implementation, the output of the last (MSB) register
is fed back into XOR or XNOR gates located between the
shift registers. In this case, the tap locations are the loca-
tions where the XOR/XNOR gates are located.
A defined polynomial provides a standard way of defining
the location of these taps for both Fibonacci and Galois
implementations. For more information on how this polyno-
mial correlates to the LFSR structure, see Appendix A:
LFSR Polynomial Notation.

Table 2: LFSR Sequence for Initial Seed 111 Serial or Parallel Output
Q2 Q1 Q0 The output of the LFSR can either be serial or parallel.

1 1 1 Optional SRL-16 Implementation

1 0 1 The LFSR can use either an SRL16 or a register implemen-
tation. Note that SRL16 is only possible for certain cases,
0 0 1 the core will revert to register implementation automatically
0 1 0 if an SRL16 implementation is not available.

1 0 0 Optional Clock Enable Input

0 1 1 If the optional clock enable input has been selected, then
the user can enable and disable the LFSR through use of
1 1 0
the clock enable.
1 1 1
Optional Maximum Length Logic
Again, the length of the pseudo-random sequence is
An LFSR iterates through a number of unique states, gener-
dependent on the length of the shift register and the number
ating a particular sequence of values, depending on its size,
and the position of the feedback taps. The number and the
implementation, gate type, and taps. This sequence is
position of the taps can again be represented as a polyno-
referred to as the LFSR sequence. The number of values in
mial. For the Xilinx core, this is expressed in the form:
the sequence is referred to as the LFSR sequence length.
P(x) = 1 + X1 + X3
The LFSR sequence can contain up to (2k – 1) unique val-
For more information on the polynomial notation, refer to ues (where k is the LFSR size). The sequence length will
Appendix A: LFSR Polynomial Notation. vary from 1 to (2k – 1) unique values, depending on LFSR
size, implementation, and tap positions. Often, it is desirable
to maximize the number of unique values in the LFSR

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1-800-255-7778 Product Specification

sequence by finding a set of tap positions which will cause
the LFSR to have its maximum sequence length of (2k – 1).
Appendix B: Maximum Sequence Length Polynomials, pro-
vides a table of tap positions that will cause the LFSR to iter-
ate through it’s maximum sequence length.
By default, an LFSR can have, at most, (2k – 1) unique val-
ues in its sequence. However, since the LFSR has k regis-
ters, it is capable of storing 2k unique values. If an
XOR-gate LFSR iterates through its maximum sequence of
(2k – 1), the state which will not be included will be the
all-zeros state. Using XOR gates in the feedback, the LFSR
can not generate an all-zeros value, and if the registers con-
tain an all-zeros value, they can not generate a ‘1’ bit in any
of the registers. This 2kth state is considered to be the
LFSR’s forbidden state, since it can not enter or exit this
state. For an LFSR with XNOR gates, the all-ones state is
the forbidden state.
Maximum Length Logic is a block of logic that can be added
to the LFSR to allow the LFSR to access the forbidden
state. It does not guarantee a certain sequence length or
that the core will ever enter or exit the forbidden state, but it
does increase the maximum possible sequence length to 2k
unique values. If the maximum sequence length is chosen
from Appendix B, and Maximum Length Logic is enabled,
the sequence length of the LFSR will increase from (2k-1) to
2k, thereby allowing the maximum possible length
sequence for an LFSR of size k.
The maximum length logic makes for an area inefficient
LFSR, since the logic to detect all zeros or all ones can
require numerous extra LUTs. It is also speed inefficient,
adding large delay along the critical path. In addition, the
SRL16 option would be unavailable, because every bit of
the SRL16 would need to be exposed to the maximum
length logic.
The maximum length logic is implemented using combina-
tional logic. A counter can be used for the maximum length
logic in certain conditions, which can help with performance
for larger LFSRs.
Optional Counter Implementation for
Maximum Length Logic
Maximum length logic can, in certain cases, be imple-
mented using a counter to improve efficiency.
This allows maximum length logic to be used while still
allowing the space-efficient use of SRL16s. This also
improves speed performance for larger LFSRs. For more
information see the Performance section of this datasheet.
Optional Load with Configurable Load Type
The core can have an optional load, which can load a new
seed value into the registers of the LFSR. Load can be
either serial or parallel.
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Product Specification 1-800-255-7778
Linear Feedback Shift Register v3.0
To complete a simple Pseudo-random Number (PN) gener-
ator we add the logic for serially loading the seed to the
LFSR. A DATA_VALID signal is optionally provided at the
output of the PN Generator. Figure 4 shows the block dia-
gram for the simple LFSR PN generator.
It should be understood that a serial load of a new seed, for
a Fibonacci-type LFSR, can behave as a “pseudo-parallel”
load. This option is preferred to a parallel load option since
a parallel load prevents the core from being implemented
using SRL16 primitives.
If the user determines that the serial load option is not ade-
quate, the core also has a parallel load option.
The DATA_VALID output signal performs differently
depending on the type of load. For more information see
Appendix C: Data Valid Output.
Optional Data Valid Output
The core can have the option of a DATA_VALID output pin.
This pin indicates to downstream logic whether the output is
valid. For a thorough description of the DATA_VALID and
NEW_SEED outputs, see Appendix C: Data Valid Output.
Optional New Seed Output
The core can have a NEW_SEED output that indicates the
completion of a load operation. For a thorough description
of the DATA_VALID and NEW_SEED outputs, see Appen-
dix C: Data Valid Output.
Optional Asynchronous Reset
The core can have an optional asynchronous reset.
Optional Synchronous Reset
The core can have an optional synchronous reset. A parallel
load of a constant value can be accomplished by using syn-
chronous reset, which is more efficient than using the paral-
lel load feature.
Clock - CLK
The input clock for the LFSR.
Serial Data Output - SD_OUT
This is the output from the last register in the LFSR. This
output is a pseudo-random number sequence of 1’s and 0’s.
Parallel Data Output Bus - PD_OUT [N-1:0]
This is an output bus of width N (LFSR size) where each bit
is the output of a register in the LFSR. By the nature of the
LFSR, this will produce a repeating finite set of unique val-
ues. The sequence depends on the initial seed and the taps
selected. This output can be used as a FIFO controller
since it behaves like an out-of-order binary counter.
3
Linear Feedback Shift Register v3.0

Load Control Input - LOAD
This input pin, when asserted high, begins the loading of a
seed value from the SD_IN or PD_IN input bus into the
LFSR. If the load input type is serial (core has a SD_IN
port), then the LOAD pin must be held high for a number of
clock cycles until the data to be loaded has been completely
clocked into the LFSR. If the load input type is parallel (core
has a PD_IN port), then the LOAD pin must be held high
one clock cycle while the data from the PD_IN port is written
into the LFSR on the rising edge of the clock.
Serial Data Input - SD_IN
When this input port is present, it is used to input data
bit-by-bit to initialize the LFSR when LOAD is high.
Parallel Data Input Bus - PD_IN[N-1:0]
When this input bus is present, it is used to load data of
width N (the LFSR size) into the LFSR in a single clock
cycle. The LFSR is loaded with this value when the LOAD
signal is high.
Clock Enable Input - CE
When CE=1 or when the CE port is not present, the core will
update its state on every rising edge of the clock. When
CE=0, the core will not change state or output values unless
an asynchronous reset is asserted.
the LFSR with a seed is needed, and it is acceptable to set
that value as a constant, SINIT should be used. Note that, if
the core does not have maximum length logic, it is possible
to initialize the core to a value that will “lock up” the LFSR. If
the LFSR uses XOR gates and no maximum length logic,
the all-zeros SINIT will freeze the core. For an LFSR with
XNOR, the forbidden state is the all-ones case.
Asynchronous Initialization Input - AINIT
When asserted, AINIT immediately resets the LFSR regis-
ters with the Asynchronous Reset Value. This is the same
value that the LFSR will assume on global reset/power up.
Terminal Count Output - TERM_CNT
This is an output that goes high every K clock cycles for two
clock cycles, where K is the number of values in the LFSR
number sequence. When present, the TERM_CNT output is
created by the Maximum Length Logic, asserting a logic ‘1’
whenever the Maximum Length Logic modifies the feed-
back to cause the LFSR to enter or exit the “forbidden”
state.
Logic Symbol

Data Valid Output - DATA_VALID

The DATA_VALID pin indicates to downstream logic that the
current output is the logical next member of the PN
sequence. See Appendix C for more information.

New Seed Output - NEW_SEED

The New Seed output goes high when a load operation has XIP175
successfully been completed. See Appendix C for more
Figure 3: LFSR Schematic Symbol
information.

Synchronous Initialization Input - SINIT Pinout

Port names for the core module are shown in Table 3 and
When asserted, the Synchronous Initialization input resets
Table 4. Table 3 lists the ports that are required for the core,
the LFSR registers with the Synchronous Reset Value on
while Table 4 lists ports that are optional based on the
the rising edge of the clock. This is useful as a way to seed
options selected in the CORE Generator.
the LFSR at run-time, without including the load logic (which
introduces significant overhead). When an ability to initialize

XIP176

Figure 4: LFSR used as a simple PN-Generator

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 Linear Feedback Shift Register v3.0

Table 3: Mandatory Pins

Port Name Port Width Direction Description

CLK 1 Input Clock

Table 4: Optional Pins

Port Name Port Width Direction Description
SD_OUT 1 Output Serial output
PD_OUT[N-1:0] LFSR Size (N) Output Parallel output
LOAD 1 Input Fill Enable for the LFSRs
SD_IN 1 Input Serial data input
PD_IN[N-1:0] LFSR Size (N) Input Parallel data input
CE 1 Input Clock Enable
DATA_VALID 1 Output High when output is valid
SINIT 1 Input Synchronous Initialization (constant value reload)
AINIT 1 Input Asynchronous Initialization (asynch constant reload)
NEW_SEED 1 Output High when a new seed has just been loaded.
TERM_CNT 1 Output High for two clock cycles every K clock cycles

CORE Generator Parameters parallel output bus.

The CORE Generator parameterization windows for this
module are described below. The first graphical user inter-
face allows the implementation, special features, and layout
to be defined. The second GUI allows the optional ports to
be chosen and configured. The last GUI allows the taps to
be chosen. The window below the tap polynomial displays
the X-terms for the polynomial. The implementation window
displays a simple diagram which describes how the LFSR
will be implemented. The available options are described
below.
Definition of GUI Interface Fields
• Component Name: Enter a name for the output files
generated for this module (up to 256 characters).
• Implementation: Select between the use of register or
SRL16 implementation of the LFSR.
- Registers: The shift chain of the LFSR will be
created from registers only. The number of
registers used is equal to the size of the LFSR.
- SRL16: SRL16 Virtex primitives will be used to
replace registers in the design whenever a series
of 3 or more registers are chained together without
combinational logic. The use of SRL16 primitives
can generate a substantial size improvement for
the core, depending on the taps and options
selected.
• LFSR Type: Choose the feedback type, either
Fibonacci or Galois
• LFSR Size: Length of the LFSR. A size from 2 to 168
can be chosen. The size determines the width of the
• Feedback Gate Type: This value selects the type of
gate used for the LFSR, XOR or XNOR. The type of
gate selected produces a completely different
sequence of values in the LFSR.
- XOR: If XOR is chosen, the all-zeros case can
never be entered from another state, and the core
can not exit an all-zeros state unless Maximum
Length Logic is enabled.
- XNOR: If XNOR is selected, the all-ones case can
never be entered from another state, and the core
can not exit an all-zeros state unless Maximum
Length Logic is enabled.
• Output Type: Indicates whether the LFSR has serial or
parallel output.
- Parallel: The output bus is formed by connecting
the outputs of the entire register chain.
- Serial: The serial output bit is connected to the
output of the most-significant bit of the LFSR.
• Load Type: Indicates the type of load for the LFSR.
The type of load directly affects the DATA_VALID
output. For more information, see Appendix C: Data
Valid Input.
- None: There is no way to load a value into the
LFSR. The PD_IN and SD_IN ports are not
connected when there is no load.
- Serial: The data on SD_IN will be written, one bit
at a time, to the LFSR registers when asserting the
LOAD input. Data is shifted directly into the LFSR
bit-by-bit on each clock cycle that LOAD is

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Product Specification 1-800-255-7778
Linear Feedback Shift Register v3.0
asserted. If the core has a serial load, the PD_IN
port is not connected.
- Parallel: The data on PD_IN will be written to the
LFSR registers on assert of the LOAD input and
will load in one clock cycle. If parallel load is used,
the SD_IN input is not used.
• Use Maximum Length Logic: Indicates whether the
core should incorporate logic to allow entry and exit
from the “lock-up” state. This adds a possible state to
the LFSR sequence, allowing the maximum possible
sequence of unique values to be 2n terms instead of
2n-1. (Where n is the number of registers in the LFSR).
Maximum length logic makes sense only for tap
polynomials that generate a maximum length
sequence, such as those found in Table 8 in Appendix
B. Since there are other tap polynomials not listed in
Table 8, which may also generate a maximum length
sequence, it is left to the user to decide whether
maximum length logic is appropriate for the desired
application.
• Use Counter For Max Length Logic: Indicates the
type of hardware used to implement the maximum
length logic (if present). If this option is selected, a
counter will be used to detect the all-zeros or all-ones
case. Otherwise, gates are used to detect the
all-zeros or all-ones case. For a Fibonacci LFSR with
maximum length logic, serial or no load, and no SINIT
or AINIT pins, a counter can be used to detect the
all-zeros or all-ones “lock-up” case. For large LFSRs, or
LFSRs which use SRL16s, the counter implementation
is recommended when selecting maximum length
logic.
• Create RPM: Enables relative placement directives for
the core. See the section on core performance for more
details.
• Asynchronous Reset: Check the box to add the
asynchronous port AINIT to the LFSR.
• Asynchronous Reset Value: The hexidecimal value
that specifies the asynchronous reset value of the
LFSR registers. This value is also used as the initial
state of the core, regardless of whether the AINIT port
is present. If Maximum Length Logic is not used, then
an Asynchronous Reset value of all-zeros (in the XOR
gate case) or all-ones (in the XNOR gate case) will
place the core in a “lock-up” state which it can not exit
until another seed value is loaded into the core (Using
load or SINIT).
• Synchronous Reset: Check the box to add the
synchronous port SINIT to the LFSR.
• Synchronous Reset Value: The hexidecimal value
that specifies the synchronous reset value of the LFSR
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1-800-255-7778
registers. If Maximum Length Logic is not used, then a
Synchronous Reset value of all-zeros (in the XOR gate
case) or all-ones (in the XNOR gate case) will place the
core in a “lock-up” state which it can not exit until
another seed value is loaded into the core (using load).
• Clock Enable: Check this box to add the CE input port
to the LFSR. If no clock enable input is present, the
core is enabled by default.
• New Seed Output: Check this box to add the
NEW_SEED output port to the LFSR. For more
information, see Appendix C: Data Valid Option.
• Data Valid Output: Check this box to add the
DATA_VALID output pin to the LFSR. For more
information, see Appendix C: Data Valid Output.
• Terminal Count Output: Check this box to add the
TERM_CNT output pin to the LFSR. This is only
present when Maximum Length Logic is used. It allows
the LFSR to be used as a repeating terminal count
counter, outputting a logic one once per cycle of the
LFSR’s sequence.
• Field Polynomial: The hexidecimal value that
specifies the polynomial of the LFSR. The polynomial
describes how the LFSR’s feedback is configured. The
polynomial that corresponds to the inserted hex value
is displayed in the small window below the field
polynomial textbox. For information on how to specify
the polynomial, see Appendix A: LFSR Polynomial
Notation.
• Implementation: This graphic is a basic block diagram
of how the polynomial maps to the hardware that will
be built. This graphic is dependant on the LFSR type
chosen. For information on how to specify the
polynomial, see Appendix A: LFSR Polynomial
Notation.
• Generate: Select to generate the LFSR module. Make
sure that the parameters are correctly selected for the
particular application before executing this option.
• Cancel: Select to close window and return to the
CORE Generator.
• Datasheet: Select to generate a PDF version of this
document.
Parameter Values in the XCO File
Names of the XCO parameters and their parameter values
are identical to the names and values shown in the GUI,
except that underscore characters (_) are used instead of
spaces. The text in an XCO file is case insensitive.
Table 5 shows the XCO file parameters and values, and
summarizes the GUI defaults. The following is an example
of the CSET parameters in an XCO file:
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Product Specification
 Linear Feedback Shift Register v3.0

CSET component_name = my_lfsr CSET asynchronous_reset = false

CSET implementation = registers CSET asynchronous_reset_value = FF
CSET lfsr_type = fibonacci CSET synchronous_reset = false
CSET lfsr_size = 8 CSET synchronous_reset_value = FF
CSET feedback_gate_type = xor CSET clock_enable = false
CSET output_type = output_type_serial CSET new_seed_output = false
CSET load_type = load_type_none CSET data_valid_output = false
CSET use_maximum_length_logic = false CSET terminal_count_output = false
CSET use_counter_for_max_length_logic = false CSET tap_locations = 1D
CSET create_rpm = false

Table 5: Parameter File Information

Parameter Name XCO Filename Values Default GUI Strings
component_name ASCII text starting with a letter and based upon the blank
following character set: a..z,0..9 and _.
implementation One of the following keywords: srl16, registers registers
lfsr_size Any integer 2 to 168 8
lfsr_type One of the following keywords: fibonacci, galois fibonacci
feedback_gate_type One of the following keywords: xor, xnor xor
output_type One of the following keywords: output_type_serial, output_type_serial
output_type_parallel
load_type One of the following keywords: load_type_none, load_type_none
load_type_serial, load_type_parallel
use_maximum_length_logic One of the following keywords: true, false false
use_counter_for_max_length_logic One of the following keywords: true, false false
create_rpm One of the following keywords: true, false false
asynchronous_reset One of the following keywords: true, false false
asynchronous_reset_value A hex value in the range of 0 to 2LFSR_size -1 FF
synchronous_reset One of the following keywords: true, false false
synchronous_reset_value A hex value in the range of 0 to 2LFSR_size -1 FF
clock_enable One of the following keywords: true, false false
new_seed_output One of the following keywords: true, false false
data_valid_output One of the following keywords: true, false false

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Linear Feedback Shift Register v3.0

Table 5: Parameter File Information (Continued)

Parameter Name XCO Filename Values Default GUI Strings
terminal_count_output One of the following keywords: true, false false
tap_locations A hex value in the range of 1 to 2LFSR_size -1. Note that 1D
the LSB of the polynomial must be ‘1’ because the X0
term is always in the polynomial.
Notes:
1. [A] The asynchronous and synchronous reset values are sometimes restricted:
IF Use_Maximum_Length_Logic=true AND Use_Counter_for_Max_Length_Logic=true THEN
IF feedback_gate_type=XOR THEN
Asynchronous Reset Value = Hex value (2LFSR_size-1)
Synchronous Reset Value = Hex value (2LFSR_size-1)
ELSE IF feedback_gate_type=XNOR THEN Asynchronous Reset Value = 0
Synchronous Reset Value = 0
ELSE
Asynchronous Reset Value = any value 0 to Hex value (2LFSR_size-1)
Synchronous Reset Value = any value 0 to Hex value (2LFSR_size-1)
2. [B] Use_SRL16 is unavailable if:
Output_type=Parallel
OR Load_type=Parallel
OR (Use_maximum_length_logic=Checked AND Use_counter_for_maximum_length_logic=Unchecked)
OR Synchronous_Reset=Checked
OR Asynchronous_Reset=Checked
3. [C] Use counter for max length logic is unavailable if:
Use_maximum_length_logic=Unchecked
OR LFSR_type=Galois
OR Load_type=Parallel

Dependencies
Some options in the CORE Generator GUI are limited in certain circumstances. The following tables help to clarify these
interactions.
Table 6: Summary of Permitted Async and Sync Reset Values
Gate SRL16 MaxLenCounter Allowed Values
XOR Unchecked No (0) to (2^LFSR_SIZE-1)
XOR Unchecked Yes (0) to (2^LFSR_SIZE-1) where LSB=1
XOR Checked No (2^LFSR_SIZE-1)
XOR Checked Yes (2^LFSR_SIZE-1)
XNOR Unchecked No (0) to (2^LFSR_SIZE-1)
XNOR Unchecked Yes (0) to (2^LFSR_SIZE-1) where LSB=0
XNOR Checked No 0
XNOR Checked Yes 0
Notes:
1. LFSR_SIZE is the size of the LFSR.

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 Linear Feedback Shift Register v3.0

Table 7: Summary of Allowed Feature Combinations

srl16 ainit sinit max len logic max len counter ser output par output no load ser load
par load no yes yes yes no yes yes no no
ser load yes yes yes yes yes yes yes no
no load yes yes yes yes yes yes yes
par output no yes yes yes yes no
ser output yes yes yes yes yes
max len counter X Y Y yes
max len logic X yes yes
sinit no Z
ainit no
Notes:
1. X: X is yes or no, but must be the same for every occurrence of X
2. Y: ainit/sinit can be used with maximum length logic counter, but only if the LSB of the synchronous/asynchronous reset value is 0
(when using XOR gates) or 1 (when using XNOR gates)
3. Z: Not recommended (increases size and decreases performance)

Resource Utilization Data Valid Output/New Seed Output

The following options increase the amount of on-chip
resources consumed by the LFSR:
- Register Implementation (vs SRL16)
- Larger LFSR sizes
- Maximum Length Logic
- BOTH Asynchronous and Synchronous Resets
- Parallel Output
- Data Valid/New Seed Outputs
Performance
The options chosen for the LFSR can significantly impact its
performance.
LFSR Type
For LFSRs with only a few taps, the Fibonacci implementa-
tion will generally achieve a faster clock speed than it's
Galois counterpart. Although faster for a small number of
taps, the Fibonacci implementation's performance
degrades as the number of taps increases.
The Galois implementation, however, sees hardly any per-
formance loss with an increase in the number of taps. So,
for a basic LFSR, the Galois implementation is recom-
mended to achieve desired speed results for more than 5
taps.
Initial Tap Locations (Tap Polynomial)
Especially for Fibonacci implementations, fewer taps
equates to faster speed.
Although they provide useful control signals for loading new
values into the LFSR, the logic used to provide these out-
puts is slower than the LFSR itself. As the LFSR size
increases, the performance of the Data Valid/New Seed
logic degrades further. If a highly optimized LFSR is impor-
tant, it is recommended that these outputs be disabled.
Asynchronous Reset/Synchronous Reset
Having BOTH an Asynchronous and a Synchronous Reset
input on the LFSR core causes an extra gate to be placed
between the shift registers. For small, fast LFSRs, this extra
gate will negatively affect the performance of the core. If the
LFSR's performance is already being degraded by another
feature, the effects of having BOTH an Asynchronous and a
Synchronous Reset input will be negligible. Note that having
EITHER an Asynchronous or Synchronous Reset, but not
both, has no noticeable effect on performance.
Use Maximum Length Logic
Because of the extra feedback logic added when using
Maximum Length Logic, the critical path through the LFSR
is increased, thus degrading performance.
Since the normal Maximum Length Logic is constructed
from combinational logic, its performance is optimal when
the LFSR size is small. For very large LFSRs, it is recom-
mended that the counter be used for Maximum Length
Logic.

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Use Counter for Maximum Length Logic
The typical combinational logic implementation of the Maxi-
mum Length Logic is faster than the counter implementation
for most LFSR sizes. However, the counter implementation
does not experience a significant performance loss as the
LFSR size increases, as does the combinational logic
implementation. Therefore, for very large LFSR cores, using
a counter for the Maximum Length Logic is recommended.
Terminal Count Output
The terminal count output does not directly have an impact
on performance. However, if the non-counter implementa-
tion of the Maximum Length Logic is used, the terminal
count output is an ASYNCHRONOUS output. To maximize
performance, it is recommended that this output be regis-
tered as soon as possible, or to simply not use this output.
Relative Placement (RPM) can be used with the LFSR core.
The core will not undergo a significant speed improvement
by using RPMs, but when used as a component in larger
designs, RPMs will help to keep the LFSR's performance
more consistent, and will allow the higher level design to be
placed and routed more efficiently.
Ordering Information
This core may be downloaded from the Xilinx IP Center for
use with the Xilinx CORE Generator System v5.2i and later.
The Xilinx CORE Generator System tool is bundled with all
Alliance Series Software packages, at no additional charge.
To order Xilinx software, please visit the Xilinx Silicon
Xpresso Cafe or contact your local Xilinx sales representa-
tive.
Information on additional Xilinx LogiCORE modules is avail-
able on the Xilinx IP Center.
Appendix A: LFSR Polynomial Notation
A polynomial notation is commonly used to describe the
functionality of an LFSR. It should be noted that this con-
vention is frequently ambiguous: presented with a polyno-
mial, there is confusion as to the look of the represented
LFSR. It is therefore necessary to define a convention that
will be used to describe an LFSR produced by the Xilinx
Figure 5: Galois Feedback Tap Notation
10 www.xilinx.com
1-800-255-7778
core. This clearly differentiates between a Fibonacci-type
and a Galois-type LFSR. This notation is also used by the
W-CDMA specification 3G TS 25.213.
Galois-type LFSR Notation
Figure 5 illustrates the tap numbering for a Galois-type
LFSR. The Gains (X) are binary, either producing a feed-
back tap or no connection. Figure 6 shows an example of a
Galois-type LFSR of length 3, with X0 = 1, X1 = 1, X2 = 0, X3
= 1. The example shown in Figure 6 is represented by the
polynomial:
p ( x) X0 X1 X3
This clearly shows the position of the taps to produce the
LFSR illustrated in Figure 6. Please note that X0 can also be
written as 1. Therefore, alternatively:
p( x) 1 X 1 X3
The taps polynomial can also be written as a string of bits,
where each bit corresponds to the coefficient of a term of
the polynomial. The highest-order terms correspond to the
most significant bits, while the least significant bit always
represents the X0 term.
It should be noted that the single highest-order term always
has a coefficient of 1, so this value is implied and not
included in the bit representation of the polynomial.
So, p(x) = X3 + X1 + X0 can be written as:
Polynomial String=”011”
where 1X3 is an implied 1, followed by 0X2, 1X1, and 1X0.
This string of bits is used to represent polynomials for
Fibonacci and Galois implementation. In the CORE Gener-
ator GUI and the XCO file, this string is written in hexideci-
mal:
tap_locations=”3”
XIP177
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 Linear Feedback Shift Register v3.0

XIP172

Figure 6: Galois Implementation of a 3-bit LFSR

Fibonacci-type LFSR Notation Comparison of Galois/Fibonacci Notation

Figure 7 illustrates the tap numbering for a Fibonacci-type The highest order factor within a polynomial implies the
LFSR. The Gains (X) are binary, either producing a feed- length of the LFSR. Polynomials representing the LFSR for
back tap or no connection. Figure 8 shows an example of a Figures 5 and 7 contain the term X3 as the highest factor.
Fibonacci-type LFSR of length 3, with X0 = 1, X1 = 1, X2 = 0, This implies the length of the LFSR is 3 in both cases.
X3 = 1. The example shown in Figure 8 is represented by the Both polynomials clearly represent the feedback taps when
polynomial: applied to Figures 4 and 6. For the Galois-type LFSR, feed-
back is in line with the direction of the shift register: feed-
back tap notation is incremented in line with the shift
p ( x) X3 X1 X0 direction.
For the Fibonacci-type LFSR, feedback is in opposition to
This clearly shows the position of the taps to produce the
the direction of the shift register: feedback tap notation dec-
LFSR illustrated in Figure 8. Please note that X0 can again
rements in line with the shift direction. This has the advan-
be written as 1. Therefore, alternatively:
tage of clearly defining the polynomial as implementing
either a Galois or a Fibonacci-type LFSR.
p( x) X3 X1 1

XIP178

Figure 7: Fibonacci Feedback Tap Notation

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XIP179

Figure 8: Fibonacci Implementation of a 3-bit LFSR

Appendix B: Maximum Sequence
Length Polynomials
In order for an LFSR to iterate through its largest possible
sequence of values, it must use a polynomial which will pro-
duce such a sequence. This maximum length sequence is
sometimes also referred to as a Maximal Length Codes.
Table 8 shows a sample set of polynomials which will pro-
duce maximum sequence lengths for a given LFSR size.
These are used as the default polynomial values in the
LFSR CORE Generator GUI.
The maximum possible number of values which can make
up the LFSR’s sequence is (2LFSR_SIZE-1). If Maximum
Length Logic is used, the maximum possible number of val-
ues in the LFSR sequence increases to (2LFSR_SIZE) (See
the section regarding the Maximum Length Logic option for
more information). By using the polynomials from Table 8,
the LFSR is able to have an ACTUAL sequence length
equal to its maximum possible sequence length.
Research has been done to determine the fewest number of
taps which can be selected for a given-sized LFSR to pro-
duce a Maximum Length Sequence. The polynomial used
to generate the maximum length sequence is the same for
Fibonacci/Galois implementations, and with XOR or XNOR
gates for feedback.
The following table is incorporated from Xilinx Application
Note 210 [5].

Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback
Fibonacci implementation with
LFSR Size (n) outputs from registers numbered Polynomial 1-Terms (Xn) Sequence Length
2 2 1 2 1 0 3
3 3 2 3 1 0 7
4 4 3 4 1 0 15
5 5 3 5 2 0 31
6 6 5 6 1 0 63
7 7 6 7 1 0 127
8 8 6 5 4 8 4 3 2 0 255
9 9 5 9 4 0 511
10 10 7 10 3 0 1023
11 11 9 11 2 0 2047
12 12 6 4 1 12 11 8 6 0 4095
13 13 4 3 1 13 12 10 9 0 8191
14 14 5 3 1 14 13 11 9 0 16383
15 15 14 15 1 0 32767
16 16 15 13 4 16 12 3 1 0 65535

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Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback (Continued)
Fibonacci implementation with
LFSR Size (n) outputs from registers numbered Polynomial 1-Terms (Xn) Sequence Length
17 17 14 17 3 0 131071
18 18 11 18 7 0 262143
19 19 6 2 1 19 18 17 13 0 524287
20 20 17 20 3 0 1048575
21 21 19 21 2 0 2097151
22 22 21 22 1 0 4194303
23 23 18 23 5 0 8388607
24 24 23 22 17 24 7 2 1 0 16777215
25 25 22 25 3 0 33554431
26 26 6 2 1 26 25 24 20 0 67108863
27 27 5 2 1 27 26 25 22 0 134217727
28 28 25 28 3 0 268435455
29 29 27 29 2 0 536870911
30 30 6 4 1 30 29 26 24 0 1073741823
31 31 28 31 3 0 2147483647
32 32 22 2 1 32 31 30 10 0 4294967295
33 33 20 33 13 0 8589934591
34 34 27 2 1 34 33 32 7 0 17179869183
35 35 33 35 2 0 34359738367
36 36 25 36 11 0 68719476735
37 37 5 4 3 2 1 37 36 35 34 33 32 0 1.37439E+11
38 38 6 5 1 38 37 33 32 0 2.74878E+11
39 39 35 39 4 0 5.49756E+11
40 40 38 21 19 40 21 19 2 0 1.09951E+12
41 41 38 41 3 0 2.19902E+12
42 42 41 20 19 42 23 22 1 0 4.39805E+12
43 43 42 38 37 43 6 5 1 0 8.79609E+12
44 44 43 18 17 44 27 26 1 0 1.75922E+13
45 45 44 42 41 45 4 3 1 0 3.51844E+13
46 46 45 26 25 46 21 20 1 0 7.03687E+13
47 47 42 47 5 0 1.40737E+14
48 48 47 21 20 48 28 27 1 0 2.81475E+14
49 49 40 49 9 0 5.6295E+14

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Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback (Continued)
Fibonacci implementation with
LFSR Size (n) outputs from registers numbered Polynomial 1-Terms (Xn) Sequence Length
50 50 49 24 23 50 27 26 1 0 1.1259E+15
51 51 50 36 35 51 16 15 1 0 2.2518E+15
52 52 49 52 3 0 4.5036E+15
53 53 52 38 37 53 16 15 1 0 9.0072E+15
54 54 53 18 17 54 37 36 1 0 1.80144E+16
55 55 31 55 24 0 3.60288E+16
56 56 55 35 34 56 22 21 1 0 7.20576E+16
57 57 50 57 7 0 1.44115E+17
58 58 39 58 19 0 2.8823E+17
59 59 58 38 37 59 22 21 1 0 5.76461E+17
60 60 59 60 1 0 1.15292E+18
61 61 60 46 45 61 16 15 1 0 2.30584E+18
62 62 61 6 5 62 57 56 1 0 4.61169E+18
63 63 62 63 1 0 9.22337E+18
64 64 63 61 60 64 4 3 1 0 1.84467E+19
65 65 47 65 18 0 3.68935E+19
66 66 65 57 56 66 10 9 1 0 7.3787E+19
67 67 66 58 57 67 10 9 1 0 1.47574E+20
68 68 59 68 9 0 2.95148E+20
69 69 67 42 40 69 29 27 2 0 5.90296E+20
70 70 69 55 54 70 16 15 1 0 1.18059E+21
71 71 65 71 6 0 2.36118E+21
72 72 66 25 19 72 53 47 6 0 4.72237E+21
73 73 48 73 25 0 9.44473E+21
74 74 73 59 58 74 16 15 1 0 1.88895E+22
75 75 74 65 64 75 11 10 1 0 3.77789E+22
76 76 75 41 40 76 36 35 1 0 7.55579E+22
77 77 76 47 46 77 31 30 1 0 1.51116E+23
78 78 77 59 58 78 20 19 1 0 3.02231E+23
79 79 70 79 9 0 6.04463E+23
80 80 79 43 42 80 38 37 1 0 1.20893E+24
81 81 77 81 4 0 2.41785E+24
82 82 79 47 44 82 38 35 3 0 4.8357E+24

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Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback (Continued)
Fibonacci implementation with
LFSR Size (n) outputs from registers numbered Polynomial 1-Terms (Xn) Sequence Length
83 83 82 38 37 83 46 45 1 0 9.67141E+24
84 84 71 84 13 0 1.93428E+25
85 85 84 58 57 85 28 27 1 0 3.86856E+25
86 86 85 74 73 86 13 12 1 0 7.73713E+25
87 87 74 87 13 0 1.54743E+26
88 88 87 17 16 88 72 71 1 0 3.09485E+26
89 89 51 89 38 0 6.1897E+26
90 90 89 72 71 90 19 18 1 0 1.23794E+27
91 91 90 8 7 91 84 83 1 0 2.47588E+27
92 92 91 80 79 92 13 12 1 0 4.95176E+27
93 93 91 93 2 0 9.90352E+27
94 94 73 94 21 0 1.9807E+28
95 95 84 95 11 0 3.96141E+28
96 96 94 49 47 96 49 47 2 0 7.92282E+28
97 97 91 97 6 0 1.58456E+29
98 98 87 98 11 0 3.16913E+29
99 99 97 54 52 99 47 45 2 0 6.33825E+29
100 100 63 100 37 0 1.26765E+30
101 101 100 95 94 101 7 6 1 0 2.5353E+30
102 102 101 36 35 102 67 66 1 0 5.0706E+30
103 103 94 103 9 0 1.01412E+31
104 104 103 94 93 104 11 10 1 0 2.02824E+31
105 105 89 105 16 0 4.05648E+31
106 106 91 106 15 0 8.11296E+31
107 107 105 44 42 107 65 63 2 0 1.62259E+32
108 108 77 108 31 0 3.24519E+32
109 109 108 103 102 109 7 6 1 0 6.49037E+32
110 110 109 98 97 110 13 12 1 0 1.29807E+33
111 111 101 111 10 0 2.59615E+33
112 112 110 69 67 112 45 43 2 0 5.1923E+33
113 113 104 113 9 0 1.03846E+34
114 114 113 33 32 114 82 81 1 0 2.07692E+34
115 115 114 101 100 115 15 14 1 0 4.15384E+34

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Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback (Continued)
Fibonacci implementation with
LFSR Size (n) outputs from registers numbered Polynomial 1-Terms (Xn) Sequence Length
116 116 115 46 45 116 71 70 1 0 8.30767E+34
117 117 115 99 97 117 20 18 2 0 1.66153E+35
118 118 85 118 33 0 3.32307E+35
119 119 111 119 8 0 6.64614E+35
120 120 113 9 2 120 118 111 7 0 1.32923E+36
121 121 103 121 18 0 2.65846E+36
122 122 121 63 62 122 60 59 1 0 5.31691E+36
123 123 121 123 2 0 1.06338E+37
124 124 87 124 37 0 2.12676E+37
125 125 124 18 17 125 108 107 1 0 4.25353E+37
126 126 125 90 89 126 37 36 1 0 8.50706E+37
127 127 126 127 1 0 1.70141E+38
128 128 126 101 99 128 29 27 2 0 3.40282E+38
129 129 124 129 5 0 6.80565E+38
130 130 127 130 3 0 1.36113E+39
131 131 130 84 83 131 48 47 1 0 2.72226E+39
132 132 103 132 29 0 5.44452E+39
133 133 132 82 81 133 52 51 1 0 1.0889E+40
134 134 77 134 57 0 2.17781E+40
135 135 124 135 11 0 4.35561E+40
136 136 135 11 10 136 126 125 1 0 8.71123E+40
137 137 116 137 21 0 1.74225E+41
138 138 137 131 130 138 8 7 1 0 3.48449E+41
139 139 136 134 131 139 8 5 3 0 6.96898E+41
140 140 111 140 29 0 1.3938E+42
141 141 140 110 109 141 32 31 1 0 2.78759E+42
142 142 121 142 21 0 5.57519E+42
143 143 142 123 122 143 21 20 1 0 1.11504E+43
144 144 143 75 74 144 70 69 1 0 2.23007E+43
145 145 93 145 52 0 4.46015E+43
146 146 145 87 86 146 60 59 1 0 8.9203E+43
147 147 146 110 109 147 38 37 1 0 1.78406E+44
148 148 121 148 27 0 3.56812E+44

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Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback (Continued)
Fibonacci implementation with
LFSR Size (n) outputs from registers numbered Polynomial 1-Terms (Xn) Sequence Length
149 149 148 40 39 149 110 109 1 0 7.13624E+44
150 150 97 150 53 0 1.42725E+45
151 151 148 151 3 0 2.8545E+45
152 152 151 87 86 152 66 65 1 0 5.70899E+45
153 153 152 153 1 0 1.1418E+46
154 154 152 27 25 154 129 127 2 0 2.2836E+46
155 155 154 124 123 155 32 31 1 0 4.56719E+46
156 156 155 41 40 156 116 115 1 0 9.13439E+46
157 157 156 131 130 157 27 26 1 0 1.82688E+47
158 158 157 132 131 158 27 26 1 0 3.65375E+47
159 159 128 159 31 0 7.30751E+47
160 160 159 142 141 160 19 18 1 0 1.4615E+48
161 161 143 161 18 0 2.923E+48
162 162 161 75 74 162 88 87 1 0 5.84601E+48
163 163 162 104 103 163 60 59 1 0 1.1692E+49
164 164 163 151 150 164 14 13 1 0 2.3384E+49
165 165 164 135 134 165 31 30 1 0 4.67681E+49
166 166 165 128 127 166 39 38 1 0 9.35361E+49
167 167 161 167 6 0 1.87072E+50
168 168 166 153 151 168 17 15 2 0 3.74144E+50

Appendix C: Data Valid Output Asynchronous Reset

The DATA_VALID pin indicates to downstream logic
whether the data on the output (SD_OUT or PD_OUT) is
valid.
Output data is considered valid if:
• The data was updated on the previous rising clock
edge
• The output is consistent with the previously output
values, constituting the next valid value in the
PN-sequence.
Data Valid is effected by CE, AINIT, SINIT, LOAD, and
LOAD_TAPS inputs.
Clock Enable
If clock enable goes low, DATA_VALID will go low on the fol-
lowing clock cycle to reflect that the output data has not
been updated. An example waveform is shown in
Figure 9.
If AINIT goes high, it immediately resets the LFSR, also
resetting DATA_VALID. DATA_VALID should go low, indicat-
ing that the reset value is not the next valid value in the
sequence. (Letters are used to show a sequence of values,
and do not equate to real values.) An example waveform is
shown in Figure 10.
Synchronous Reset
If SINIT is high on the rising edge of the clock, the LFSR
registers initialize to their synchronous reset value in the fol-
lowing clock cycle. This constant value is not the next
proper value in the sequence for the LFSR, so it is deemed
invalid. DATA_VALID should go low, indicating that the reset
value is not the next valid value in the sequence. (Letters
are used to show a sequence of values, and do not equate
to real values.) An example waveform is shown in
Figure 11.

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Figure 9: Example Waveform: Clock Enable effects on DATA_VALID and NEW_SEED

Figure 10: Example Waveform: AINIT effects on DATA_VALID Example

Figure 11: Example Waveform: SINIT effects on DATA_VALID

Load
If a parallel load is performed, the LFSR is loaded with the
parallel load value on the rising edge of the clock. Since the
loaded value is out-of-sequence from the preceding output
values, the DATA_VALID output goes low for one clock
cycle. This indicates to downstream logic that the new value
is not a valid member of the preceding sequence. See
Figure 12 Example Waveform: Parallel Load with both
Serial and Parallel Outputs shown.
If the LFSR is Fibonacci with serial input and output, a
pseudo-parallel load is possible. A Fibonacci LFSR shifts
bits from LSB to MSB without modification. This means that
all C_SIZE bits can be shifted into the registers before the
effects of this load can be seen on the serial output. On this
C_SIZEth clock cycle, the load is completed and the output
changes exactly as it would if a parallel load were performed
on this last clock cycle. Data valid will go low for
only one clock cycle after the load is complete to indicate
the presence of a value out-of-order from the previous
sequence.
If the pseudo-parallel load is not completed, data_valid
should go low until a valid value is successfully loaded into
the LFSR. An example is shown in Figure 13.
If the LFSR has a serial input, but either has a parallel out-
put or Galois implementation, then a pseudo-parallel load is
not possible. This case should be discouraged since it pre-
vents the use of SRL16 primitives. If this case is used, the
data_valid should go low from the start of the load until a
valid value is successfully loaded into the LFSR (recall
that the first value of a new sequence is not considered
valid).
If a serial load is not completed, data_valid should go low
until a valid value is successfully loaded into the LFSR. An
example is shown in Figure 14.
Alternate DATA_VALID Signal
The DATA_VALID output of the LFSR considers newly
loaded values to be invalid. This is because a newly loaded
seed is not the next logical value in the LFSR sequence. If it
is desired to consider a newly loaded value (via load, syn-
chronous reset, or asynchronous reset) a valid value, then
the output DATA_VALID can be ORed with the NEW_SEED
output to produce a new data valid signal which considers
new seeds to be valid.

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Figure 12: Example Waveform: Incomplete Serial Load

Figure 13: Example Waveform: Incomplete Pseudo-Parallel Serial Load

Figure 14: Example Waveform: Parallel Load with Serial and Parallel Output
(letters are used to show a sequence of values, and do not equate to real values)

Revision History
The following table shows the revision history for this document.

Date Version Revision

03/28/03 1.0 Initial revision history.

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Product Specification 1-800-255-7778