IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO.

2, FEBRUARY 2010 75

Kuijk Bandgap Voltage Reference With High

Immunity to EMI
Jean-Michel Redouté, Student Member, IEEE, and Michiel Steyaert, Fellow, IEEE

Abstract—This brief evaluates the effect of conducted electro-

magnetic interference (EMI) that is injected in the power supply
of a classic Kuijk bandgap reference voltage circuit. Two modified
Kuijk bandgap topologies with high immunity to EMI are intro-
duced and compared to the original structure. Measurements of a
test IC confirm the theoretical analyses.
Index Terms—Bandgap voltage references, electromagnetic
compatibility, electromagnetic interference.

I. I NTRODUCTION
Fig. 1. Basic Kuijk bandgap voltage reference circuit.
ANDGAP reference circuits were developed in the 1960s,
B while the first integrable circuit solutions emerged in the
early 1970s [1]–[3]. Although much attention is paid to many
precision enhancement aspects of bandgap reference circuits,
little or no influence of electromagnetic interference (EMI) is
usually considered during their design [4]: paradoxically, EMI
may impact and modify the reference voltage itself orders of
magnitude more than, e.g., a varying temperature range. With
effective temperature coefficients situated around a few parts
per million per degree Celsius [5], a strong EMI injection in
the power supply easily perturbs these high-precision bandgap
references. This brief evaluates the effect of conducted EMI
that is injected in the power supply of a classic Kuijk bandgap
reference circuit. The first improvement is made by modifying
the pass device type and by using the compensation capacitor
Fig. 2. NPD Kuijk bandgap voltage reference circuit.
of the operational transconductance amplifier (OTA) to keep
the gate–source voltage of the former at a constant value. II. C LASSIC K UIJK BANDGAP S TRUCTURE (NPD)
However, this structure is still susceptible to high-frequency
EMI disturbances because of the nonlinear output resistances A. Basic Principle
of the input transistors. The second circuit improvement intro- Among the various existing bandgap voltage reference ar-
duces an active load, which shields the input differential pair chitectures, one of the most prevalent ones is undoubtedly the
stage from EMI and keeps the average drain currents at equal Kuijk bandgap reference circuit (Fig. 1) [3]. The reference
values. Measurements of a test chip corroborate and confirm the voltage Vref can be expressed as the sum of the voltage drops
theoretical deductions. across R1 , R3 , and the base-emitter voltage of Q1 (Vbe1 ). As
long as the OTA gain is very high, Vref is expressed as
   
k.T R1 R1 IS1
Vref = Vbe1 + . 1+ .ln . (1)
q R3 R2 IS2
Manuscript received December 18, 2008; revised May 11, 2009, June 26, where IS1 and IS2 represent the saturation currents of Q1 and
2009, and November 3, 2009. First published January 22, 2010; current version
published February 26, 2010. This work was supported in part by the Institute Q2 . The first term in (1) is inversely proportional to absolute
for the Promotion of Innovation by Science and Technology in Flanders (IWT). temperature, and consequently, the sum of both can be trimmed
This paper was recommended by Associate Editor A. I. Karsilayan. to cancel out the inverse temperature dependence of Vbe1 .
The authors are with the Microelectronics and Sensors Division (MICAS),
Department of Electrical Engineering (ESAT), Katholieke Universiteit Leuven, To keep the subsequent EMI analysis compact, it has been
3001 Heverlee, Belgium (e-mail: jean-michel.redoute; michiel.steyaert@esat. considered that the OTA has been realized as a basic one-stage
kuleuven.be). OTA, driving a pass device transistor. The latter is very often
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. realized as an NMOS transistor connected in a source–follower
Digital Object Identifier 10.1109/TCSII.2009.2037991 configuration: this circuit is depicted in Fig. 2 [6], [7]. This

1549-7747/$26.00 © 2010 IEEE

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76 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 2, FEBRUARY 2010

Fig. 3. Comparative Bode magnitude plots of the open-loop transfer functions

associated to the NPD, PPD, and PPDAL bandgap references.

classic topology is referred to as the NMOS pass device (NPD)

bandgap circuit.
Fig. 4. Representation of the effect of large EMI injection levels on the
average drain currents of M1 and M2 .
B. EMI Behavior of the NPD Kuijk Bandgap Circuit
When EMI is injected in the positive power supply terminal 2) Large-Signal Analysis: As the injected EMI level in-
(represented by Vemi in Fig. 2), Vref is polluted by undesirable creases, small-signal analyses are no longer valid, since they
EMI components. do not include nonlinear phenomena like EMI-induced dc shift
1) Small-Signal Analysis: As long as the EMI is sufficiently [9]. The drain–source current of M1 (Id1 ) is equal to the
small, the open-loop transfer function from the EMI source to source–drain current of M3 (Id3 ) when there is no EMI, i.e.,
the reference voltage output node is calculated using a small- µCox W
signal approach. Five basic assumptions were made to simplify Id1_noEMI = . . (VSG3 − |Vtp |)2 . (4)
2 L
this calculation.
1) The feedback loop is interrupted at the gates of the input Assume now that the EMI is superposed on the power supply,
pair and replaced by a dc voltage source. as depicted in Fig. 2. In the event that the transistors in the OTA
2) R1 , R2 , R3 , Q1 , and Q2 are modeled by an equivalent are not forced out of their saturation region by the EMI, the
resistor RL . average drain current over time (Id1 ) is represented as follows:
3) The dominant parasitic capacitances in this circuit are T
2
represented by Cn1 , Cn2 , and Cn3 (dashed). These have 1
been identified using [6]. Id1_withEMI = lim Id1 (t).d(t)
T →∞ T
4) The output resistances (ro ) and transconductances (gm ) −T
2
of the MOS transistors are identical.
5) The output impedance of the tail current source transistor µCox W
= Id1_noEMI + . .(vsg3 )2 . (5)
(Mb1 ) is disregarded. 2 L
Following a similar approach as in [8], the resulting simpli- Clearly, EMI increases Id1 , which, in turn, increases the
fied open-loop transfer function has been calculated as follows: average value of Vref : this effect is identified as EMI-induced dc

s
 
s
 shift [9]. For even larger EMI levels, the output resistances of
vref (s) RL .gm ωz1 + 1 . ωz2 + 1 M1 and M2 no longer linearly behave, because of the consider-
ADD1 (s) = = . .
able voltage swings that are taking place at their drains. Refer to
 
vemi (s) 1 + RL .gm s
+1 . s +1 ωp1 ωp2
Fig. 4. The positive EMI swings generate velocity saturation in
(2)
the input pair transistors: this tends to decrease the large-signal
The pole and zero frequencies are expressed as follows: resistance of M1 and M2 . Since under normal circumstances,
 the drain of M2 lies at a higher voltage than the drain of
m .RL +1
ωp1 = Cd12.ro , ωp2 = gC d2 .RL M1 , the decrease of the large-signal output resistance is more
2.g (3)
ωz1 = Cn31.ro , ωz2 = Cd1m . pronounced for the former than for the latter. Conversely, the
negative EMI swings force the input pair transistors M1 –M2
Fig. 3 depicts the resulting Bode magnitude plot representing into their linear region, which increases their large-signal output
this open-loop transfer function. Observe that the dominant resistance. This increase is predominant for M1 , because of its
pole of ADD1 (s) coincides with the dominant pole of the OTA lower drain voltage. Consequently, as the EMI level increases,
and that the ratio between Cn3 and Cd2 determines the EMI the average drain current Id1 steadily decreases while Id2
injection at high frequencies. The EMI coupling at low EMI increases by the same amount, since their sum remains equal
frequencies is given by RL .gm /(1 + RL .gm ): this coupling is to the tail current. These combined effects decrease the average
responsible for an unwanted ripple at the reference node. gate voltage of M5 and, consequently, Vref at high EMI levels.

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REDOUTÉ AND STEYAERT: KUIJK BANDGAP VOLTAGE REFERENCE WITH HIGH IMMUNITY TO EMI 77

Fig. 5. PPD Kuijk bandgap voltage reference circuit.

Fig. 6. PPDAL Kuijk bandgap voltage reference circuit.
In addition, a portion of the interference that is injected into
the power supply couples into the reference node, resulting in
an EMI-induced ripple, as discussed in the previous paragraph:
moreover, depending on the magnitude of this injection, a dc
shift across the diode-connected bipolar transistors Q1 and Q2
is generated in the same way as derived in (5) for the MOS input
pair transistors.
3) Conclusion: As seen, it is of paramount importance to
perform the following.
1) Minimize the EMI coupling from the power supply to the
reference node to decrease the EMI-induced ripple and
the dc shift across Q1 and Q2 . Fig. 7. Active load using positive feedback.
2) Shield the drains of M1 and M2 to increase the large-
signal output resistance of the input differential pair. observed in Fig. 3. This implies that the EMI injection to Vref is
Both observations are tackled in the following designs. highly attenuated, which decreases the ripple on the reference
node, as well as the dc shift across Q1 and Q2 . Additionally,
the fact that the gate of M5 may be biased at a lower voltage re-
III. K UIJK BANDGAP R EFERENCES W ITH duces the dc shift on Vref owing to the clipping of M5 occurring
H IGH I MMUNITY TO EMI during the negative swings of very large EMI levels. However,
A. PPD Kuijk Bandgap Reference Circuit the nonlinear output resistances of M1 and M2 generate a dc
shift imbalance in the average drain currents of both transistors.
A first improvement is made by replacing the NMOS pass
transistor M5 by a PMOS transistor and by connecting the
compensation capacitance Cd1 between the gate and the source B. PPDAL Kuijk Bandgap Reference Circuit
of M5 (Fig. 5). This topology is referred to as the PMOS pass Since the nonlinear output resistance of the input pair is the
device (PPD) topology. Compensation capacitor Cd1 shorts the main cause of the dc shift in the PPD topology, an NMOS
ac gate–source voltage of M5 : this way, M5 sources a constant current mirror is added at the drains of input pair M1 –M2 . This
drain current. Applying the same basic abstractions anteriorly topology is identified as the PPD with active load (PPDAL) and
formulated, the transfer function between the EMI source and is depicted in Fig. 6. Transistors M6 and M7 mask the nonlinear
the reference voltage output node can be calculated as follows: output resistances of M1 and M2 by using positive feedback
[10]. The gate of M5 has been connected to the drain of M6
   
s s
vref (s) 2.RL ω + 1 . ω + 1
ADD2 (s) = = .
z1
 
z2
 . (6) and not to its source, as indicated in [10], because a voltage
vemi (s) ro s
+1 . s
+1 drop of at least one Vdssat and one Vgs is required across M3
ωp1 ωp2
and M6 , respectively. Consider the simplified structure depicted
The poles and zeros are now given by in Fig. 7. The output impedance Zout seen in the output node
 Vout equals
ωp1 = Cd12.ro , ωp2 = Cd21.RL
(7) r
4
ωz1 = ro .C , ωz2 = Cn31.ro . Zout =  o3  (8)
ro3 . RRba−R
d1 a
.Rb +1
Similar to what has previously been observed, the dominant
pole of ADD2 (s) coincides with the dominant pole of the OTA, where ro3 is the output resistance of M3 . In the particular case
and the ratio between Cn3 and Cd2 determines the EMI injec- that Ra and Rb are equal to each other, the output impedance
tion at higher frequencies. However, |ADD2 (s)| at low EMI fre- of this small structure is equal to ro3 : in other words, Ra and
quencies is much lower compared to |ADD1 (s)|. This is clearly Rb are masked by the positive feedback loop formed by M6

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78 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 2, FEBRUARY 2010

Fig. 9. Microphotograph of the bandgap test IC.

Fig. 8. Kuijk NPD bandgap voltage reference circuit with biasing of tail TABLE I
current transistor Mb1 and start-up circuit. D ESIGN VALUES

and M7 . Applying the same basic abstractions, the transfer

function from the EMI source to the reference voltage output
node is calculated as follows:
   
s s
vref (s) RL ωz1 + 1 . ωz2 + 1
ADD3 (s) = = .    . (9)
vemi (s) ro s
+1 . s +1 ωp1 ωp2

The poles and zeros are equal to


ωp1 = Cd11.ro , ωp2 = 1
Cd2 .RL
(10)
ωz1 = Cn31.ro , ωz2 = 2
ro .Cd1 .

Observe that the dominant pole frequency of ADD3 (s) and

the OTA pole frequency have been halved: refer to the Bode
plot in Fig. 3. Two major benefits can be expressed compared
to the previously discussed PPD structure. First, the output
resistances of differential pair transistors M1 –M2 are masked
from the EMI source: the OTA output impedance is equal to
ro3 owing to the positive feedback, and this is independent
of the output resistances of M1 –M2 . Additionally, the drain
voltages of input pair transistors M1 –M2 are kept at an equal
value. Second, if the drain currents Id1 and Id2 shift below or
above their original dc value owing to a particularly strong EMI
injection, the current mirror formed by M6 and M7 forces the
drain currents to an equal value so that they do not directly
contribute to a dc shift.

IV. B IASING AND S TART-U P C IRCUIT

The biasing has been performed using a current mirror topol- Fig. 10. DC shift of the reference voltage as a function of EMI frequency
(EMI level = 4 dBm).
ogy with high immunity to EMI [9], as illustrated for the NPD
bandgap topology in Fig. 8. Observing a careful dimensioning transistor design values are summarized in Table I. Since EMI
of Mb1 , Mb2 , Mb3 , Mb4 , Cb1 , and Cb2 , a high EMI suppression frequencies are currently limited to 1 GHz, as well as injected
at the gate of Mb1 is achieved. In addition, Kuijk bandgap from the outside of the chip, the EMI that is injected into the
circuits have a parasitic operating point at 0 V: for this reason, power supply has the same effect as the EMI that is injected into
a start-up circuit was internally foreseen by means of transistor the ground node. The EMI source is injected in the power sup-
Msu (refer to Fig. 8). ply through a resistor of 100 Ω according to the Direct Power
Injection (DPI) standardized measurement setup: the EMI fre-
quency ranges between 150 kHz and 1 GHz [11]. The resulting
V. M EASUREMENTS
dc shifts are plotted in Figs. 10 and 11 for an EMI power level
The three discussed Kuijk bandgap reference circuits (NPD, of, respectively, 4 and 10 dBm. Observe in these plots that the
PPD, and PPDAL) were integrated on a test IC, which was dc shift of the reference voltage generated by the NPD circuit
processed in the AMIS 0.35-µm technology (Fig. 9). The is the largest at low EMI frequencies, while it stays fairly small

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REDOUTÉ AND STEYAERT: KUIJK BANDGAP VOLTAGE REFERENCE WITH HIGH IMMUNITY TO EMI 79

Fig. 11. DC shift of the reference voltage as a function of EMI frequency Fig. 12. Peak-to-peak ripple on the reference voltage as a function of EMI
(EMI level = 10 dBm). frequency (EMI level = 10 dBm).

for the PPD and PPDAL structures. At higher EMI frequen- VI. C ONCLUSION
cies, the dc shift of the reference voltage associated with the The effect of EMI on a classic Kuijk bandgap reference NPD
PPD structure worsens starting from approximately 100 MHz structure has been studied from a small- and a large-signal point
because of the strong EMI injection that is taking place at of view. Both analyses have served to define two Kuijk bandgap
the drain of M1 –M2 , as anteriorly predicted. Conversely, the reference circuits with high immunity to EMI, namely, the PPD
dc shift in the PPDAL bandgap circuit stays relatively small and PPDAL circuits. Measurements of a test chip confirm the
because M1 –M2 are shielded by M6 –M7 . Adding a small superiority of the PPD and PPDAL bandgap circuits, and this is
internal decoupling capacitor in the power supply filtering up to high EMI injection levels (10 dBm, according to the DPI
EMI starting from 100 MHz would considerably improve this specification).
situation for high EMI frequencies; however, this decoupling
capacitor would be ineffective at low EMI frequencies, which
are therefore more critical. At an EMI injection of 10 dBm, the ACKNOWLEDGMENT
reference voltage generated by the PPDAL circuit is slightly The authors would like to thank ON Semiconductor Belgium
worse at low EMI frequencies than the one produced by its PPD for their cooperation.
counterpart: since the PPD circuit uses no cascoded devices, it
can therefore remain much longer in its operating region. The R EFERENCES
dc shift of the PPD circuit quickly increases for higher EMI
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