ATMega32 8bit Micro controller

The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC

architecture. By executing powerful instructions in a single clock cycle, the ATmega32 achieves

throughputs approaching 1 MIPS per MHz.

The AVR core combines a rich instruction set with 32 general purpose working registers. All

the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two

independent registers to be accessed in one single instruction executed in one clock cycle. The

resulting architecture is more code efficient while achieving throughputs up to ten times faster

than conventional CISC microcontrollers.

The ATmega32 provides the following features: 32K bytes of In-System Programmable

Flash Program memory with Read-While-Write capabilities, 1024 bytes EEPROM, 2K byte

SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for

Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters

with compare modes, Internal and External Interrupts, a serial programmable USART, a byte

oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input

stage with programmable gain (TQFP package only), a programmable Watchdog Timer with

Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle

mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM,

Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode

saves the register contents but freezes the Oscillator, disabling all other chip functions until the

next External Interrupt or Hardware Reset.

Pin Diagram of ATmega32
Pin Descriptions

VCC: Digital supply voltage.

GND: Ground.

PORTA (PA7...PA0): PORTA serves as the analog inputs to the A/D Converter. PORTA also

serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide

internal pull-up resistors (selected for each bit). The PORTA output buffers have symmetrical

drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used

as inputs and are externally pulled low, they will source current if the internal pull-up resistors

are activated. The PortA pins are tri-stated when a reset condition becomes active, even if the

clock is not running.

PORTB (PB7...PB0): PORTB is an 8-bit bi-directional I/O port with internal pull-up resistors

(selected for each bit). The PORTB output buffers have symmetrical drive characteristics with

both high sink and source capability. As inputs, PORTB pins that are externally pulled low will

source current if the pull-up resistors are activated. The PORTB pins are tri-stated when a reset

condition becomes active, even if the clock is not running. PORTB also serves the functions of

various special features of the ATmega32.

PORTC (PC7...PC0): PORTC is an 8-bit bi-directional I/O port with internal pull-up resistors

(selected for each bit). The PORTC output buffers have symmetrical drive characteristics with

both high sink and source capability. As inputs, PORTC pins that are externally pulled low will

source current if the pull-up resistors are activated. The PORTC pins are tri-stated when a reset

condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the

pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset

occurs. The TD0 pin is tri-stated unless TAP states that shift out data are entered. PORTC also

serves the functions of the JTAG interface and other special features of the ATmega32.

PORTD (PD7...PD0): PORTD is an 8-bit bi-directional I/O port with internal pull-up resistors

(selected for each bit). The PORTD output buffers have symmetrical drive characteristics with

both high sink and source capability. As inputs, PORTD pins that are externally pulled low will

source current if the pull-up resistors are activated. The PORTD pins are tri-stated when a reset

condition becomes active, even if the clock is not running. PORTD also serves the functions of

various special features of the ATmega32.

RESET: Input pin. A low level on this pin for longer than the minimum pulse length will

generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a

reset.

XTAL1: Input to the inverting Oscillator amplifier and input to the internal clock operating

circuit.

XTAL2: Output from the inverting Oscillator amplifier

SRAM Data Memory: Figure shows how the ATmega32 SRAM Memory is organized. The

lower 2144 Data Memory locations address the Register File, the I/O Memory, and the internal

data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 2048

locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with

Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the

Register File, registers R26 to R31 feature the indirect Addressing Pointer Registers. The direct

addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base-address

given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-

decrement and post-increment, the address registers X, Y, and Z are decremented or

incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 2048 bytes of

internal data SRAM in the ATmega32 are all accessible through all these addressing modes.
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. The DDxn bits are

accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn

bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin.

If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero,

Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as

an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to

be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated

when areset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero). When switching between tri-state ({DDxn, PORTxn} = 0b00) and

output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled

({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the

pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the

difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the

SFIOR Register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The

user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state

({DDxn, PORTxn} = 0b11) as an intermediate step.

A simplified block diagram of the USART transmitter is shown in Figure. CPU accessible

I/O Registers and I/O pins are shown in bold.

The dashed boxes in the block diagram separate the three main parts of the USART (listed from

the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.

The clock generation logic consists of synchronization logic for external clock input used by

synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only

used by Synchronous Transfer mode. The Transmitter consists of a single write buffer, a serial

Shift Register, parity generator and control logic for handling different serial frame formats. The

write buffer allows a continuous transfer of data without any delay between frames. The

Receiver is the most complex part of the USART module due to its clock and data recovery

units. The recovery units are used for asynchronous data reception. In addition to the recovery

units, the receiver includes a parity checker, control logic, a Shift Register and a two level

receive buffer (UDR). The receiver supports the same frame formats as the transmitter, and can

detect frame error, data overrun and parity errors.

Equations for Calculating Baud Rate Register Setting

 74HC138

The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with

low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no.

7A.

The 74HC/HCT138 decoders accept three binary weighted address inputs (A0, A1, A2) and

when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). The “138” features

three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will

be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy

parallel expansion of the “138” to a 1-of-32 (5 lines to 32 lines) decoder with just four “138” ICs

and one inverter.

The ”138” can be used as an eight output demultiplexer by using one of the active LOW

enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs

must be permanently tied to their appropriate active HIGH or LOW state.

Pin Diagram of 74HC138 3-8Decoder
Pin Description

PIN NO. SYMBOL NAME FUNCTION

1, 2, 3 A0 to A2 address inputs

4, 5 E1, E2 enable inputs (active LOW)

6 E3 enable input (active HIGH)

8 GND ground (0 V)

15, 14, 13,

12, 11, 10,

9, 7 Y0 to Y7 outputs (active LOW)

16 VCC positive supply voltage

HEF4094 SHIFT REGISTER

The HEF4094B is an 8-stage serial shift register having a storage latch associated with each

stage for strobing data from the serial input to parallel buffered 3-state outputs O0 to O7. The

parallel outputs may be connected directly to common bus lines. Data is shifted on positive-

going clock transitions. The data in each shift register stage is transferred to the storage register

when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs

whenever the output enable (EO) signal is HIGH. Two serial outputs (Os and O’s) are available

for cascading a number of HEF4094B devices. Data is available at Os on positive-going clock

edges to allow high-speed operation in cascaded systems in which the clock rise time is fast. The

same serial information is available at O’s on the next negative-going clock edge and provides

cascading HEF4094B devices when the clock rise time is slow.

 PIN DIAGRAM

Pins Description :

D data input

EO output enable input

CP clock input

Os, O’s serial outputs

STR strobe input

O0 to O7 parallel outputs
The ULN2003are high voltage, high current darlington arrays each containing seven open

collector darlington pairs with common emitters. Each channel rated at 500 mA and can

withstand peak currents of 600 mA. Suppression diodes are included for inductive load driving

and the inputs are pinned opposite the outputs to simplify board layout.

These versatile devices are useful for driving a wide range of loads including solenoids,

relays DC motors, LED displays filament lamps, thermal printheads and high power buffers.

Features:

 Seven Darlington’s per package

 Output current 500 mA per driver (600 mA peak)

 Output voltage 50 V

 Integrated suppression diodes for inductive loads

 Outputs can be paralleled for higher current

 TTL/CMOS/PMOS/DTL Compatible inputs

 Inputs pinned
PIN CONNECTIONS
2.1. GSM features

o Maximum data rate: 9600 bit/s (there are some extension

that allow now faster speeds)

o Maximum mobile terminal output power: 8 W

o Maximum hand-held mobile terminal output power: 2W

o Maximum cell radius: 30 km

o Minimum cell radius: 350 m

o Access method: TDMA/FDMA

o Number of radio channels in each direction: 124

o Number of speech channels per radio channel: 8

o Modulation: Minimum Shift Keying (GSMK)

GSM system uses a combination of time division multiple access and frequency division

multiple access to use the radio spectrum. TDMA is used to divide one carrier frequency to up to

8 users. Different frequencies used have many different frequency carriers on the same location

to get more capacity than 8 users. Transmitting and receiving uses different frequencies. The

common channel structure is a total of 156.25 bits, transmitted every 0.577 milliseconds, giving

a gross bit rate of 270.833 kbps. This bit rate is then divided with the data from 8 users, control

data, time delay control spare bits and bits used for equalization.

SMS

SMS is a bidirectional service for sending short alphanumeric (up to 160 bytes) messages

in a store and forward fashion. For point-to-point SMS, a message can be sent to another

subscriber to the service, and an acknowledgement of receipt is provided to the sender. SMS can

also be used in a cell broadcast mode, for sending messages such as traffic updates or news

updates. Short message service (SMS) is a messaging method included in GSM system, which

allows sensing short messages from one cellular phone to another. GSM Short Messages have a

maximum length of 160 characters (from the SMS character set). However, Short Messages can

be concatenated to form longer messages. Besides normal text based user-to-user messaging

SMS system has been used to implement interfaces to on-line services and for carrying other

kind of data (like alarm tones and logos to certain GSM phones). Short message service (SMS) is

a globally accepted wireless service that enables the transmission of alphanumeric messages

between mobile subscribers and external systems such as electronic mail, paging, and voice mail

systems. SMS has also been used for transporting data like cellular phone ring tones and screen
logos. SMS messages can be sent in several ways. The most typical way the users send them is

that they type those messages with their cellular phones and then send them from it. There are

also other ways to do this. The automated SMS based services need a computerized way to do

the same thing. There are several ways how a SMS can be sent from a computer. One of the

simplest methods for small volume SMS traffic sending is to use a GSM modem or GSM phone

connected to a PC serial port. With suitable software you can send SMS through them from

computer. For higher volume SMS sending quite many operators also provide a computer

interface that allows sending messages directly from computer to SMSC (Short Message Service

Center). There are several protocols that are designed for this. Examples of such protocols that

can be used are SMPP (Short Message Peer to Peer), CIMD, UCP/EMI (Universal Computer

Protocol / External Machine Interface) and HTTP (Hyper Text Transport Protocol).

Network operators in most of the world use the original GSM spectrum allocation at 900

MHz. The frequency range allocated for cellular telephony purposes (used now by GSM) in the

1978 World Administrative Radio Conference (WARC) was 890-915 MHz for transmissions

from mobile stations and 935-960 MHz for transmissions from fixed stations. In Europe the

GSM networks generally use 900 MHz frequency band. 1800 MHz frequency is used in places

where the capacity available at 900 MHz frequency band is not enough to cover the needs of the

users. Many modern European GSM phones are built as "dual-band" phones, which can use both

of those frequency bands, and automatically transparently to the user switch between those

frequency bands as needed.

 5x7 DOT MATRIX DISPLAY

The idea is to let a text scroll over the LED dot-matrix displays. A dot-matrix display is a display

which contains 5x7 dots (LEDs) in one case, the LEDs are connected like a matrix, there are two

types CC and CA, the LEDs are simply put the other way around, here the drawings (inside and

front)

If you put 5 Volt e.g. at the lines 4 and 10, that LED (dot) will lit, the trick of multiplexing

is to scan the columns (3) and set the data on the rows (5) , the multiplex-frequency must be

greater than approx. 40Hz else you will see the flickering of the LEDs to much (take about 3

msec per row, thats about 25 msec for one frame)

The scanning goes as follows, first set the columns data on the 5 columns e.g. 10100, then

activate (1 -> on CA = common cathode, or CC = common cathode) the first row, now these

LEDs (dots) will lit, wait 3 msec, then switch the row off, now load the next columns data, and

set the second row on, wait 3 msecs again, and switch it off again, if you repeat this sequence

very fast, you will see the data (character data) appear on the display (refresh frequency 40 -

70Hz is ok, don't take twice or half the artificial light-frequency of 50/60 Hz)

The trick is to build one character on the display by scanning the rows very fast, and let say

each 20 times (20 frames) scroll it one position to the left, this will give the effect of a walking

text accross the dot-matrix display. So first build one frame, repeat this 20 times, and after that,

read the data one address later, if you do this 5 times (5 columns) the character scroll from right

to left from the display.

/*****************************************************
Project : Moving Message Display
Version : 1.0
Date : 14/10/2009
Author : M Srinivas
Company : MIC Electronics Ltd
Comments:

Chip type : ATmega32

Program type : Application
Clock frequency : 16.000000 MHz
Memory model : Small
External SRAM size : 0
Data Stack size : 512
*****************************************************/

#include <io.h>
#include <delay.h>
#include <string.h>

#define tot_mod 10
/* Present Password "*789*#" (without quotations)*/
/* Message should be sent from a mobile number (+91xxxxxxxxxx) */

#define D PORTC.0 //DATA

#define CLK PORTC.1 //clk
#define A0 PORTC.2
#define A1 PORTC.3
#define A2 PORTC.4 //COMMON ANODE
#define STR PORTC.5 //str
#define OE PORTC.6 //oe

unsigned char msg_loc,dummy;

unsigned int x,k,display_dat,per;
unsigned char display_font_data[tot_mod*5],received_data[230],display_reci_data[230];
bit message=0,str_msg=0,new_message=0;

flash unsigned char caps[65][5] = {{0x00, 0x00, 0x00, 0x00, 0x00},//Space

{0x00, 0x7D, 0x00, 0x00, 0x00}, //!
{0x00, 0x70, 0x70, 0x00, 0x00}, //"
{0x14, 0x7F, 0x14, 0x7F, 0x14}, //#
{0x32, 0x49, 0x7F, 0x49, 0x26}, //$
{0x02, 0x14, 0x08, 0x14, 0x20}, //%
{0x26, 0x59, 0x59, 0x25, 0x02}, //&
{0x00, 0x70, 0x00, 0x00, 0x00}, //'
{0x00, 0x3E, 0x41, 0x00, 0x00}, //(
{0x00, 0x41, 0x3E, 0x00, 0x00}, //)
{0x49, 0x3E, 0x1C, 0x3E, 0x49}, //*
{0x00, 0x08, 0x7F, 0x08, 0x08}, //+
{0x00, 0x05, 0x06, 0x00, 0x00}, //,
{0x08, 0x08, 0x08, 0x08, 0x00}, //-
{0x00, 0x01, 0x00, 0x00, 0x00}, //.
{0x02, 0x04, 0x08, 0x10, 0x20}, // /
{0x3E, 0x41, 0x41, 0x3E, 0x00}, //0
{0x01, 0x21, 0x7F, 0x01, 0x00}, //1
{0x4F, 0x49, 0x49, 0x7B, 0x00}, //2
{0x49, 0x49, 0x49, 0x36, 0x00}, //3
{0x78, 0x08, 0x08, 0x7F, 0x00}, //4
{0x79, 0x49, 0x49, 0x46, 0x00}, //5
{0x3E, 0x49, 0x49, 0x26, 0x00}, //6
{0x41, 0x44, 0x50, 0x40, 0x00}, //7
{0x36, 0x49, 0x49, 0x36, 0x00}, //8
{0x32, 0x49, 0x49, 0x3E, 0x00}, //9
{0x00, 0x14, 0x00, 0x00, 0x00}, //:
{0x01, 0x16, 0x00, 0x00, 0x00}, //;
{0x08, 0x14, 0x22, 0x41, 0x00}, //<
{0x14, 0x14, 0x14, 0x14, 0x00}, //=
{0x41, 0x22, 0x14, 0x08, 0x00}, //>
{0x30, 0x45, 0x48, 0x30, 0x00}, //?
{0x3E, 0x4D, 0x53, 0x4D, 0x3E}, //@
{0x3F, 0x48, 0x48, 0x3F, 0x00}, //A
{0x7F, 0x49, 0x49, 0x3E, 0x00}, //B
{0x3E, 0x41, 0x41, 0x41, 0x00}, //C
{0x7F, 0x41, 0x41, 0x3E, 0x00}, //D
{0x7F, 0x49, 0x49, 0x49, 0x00}, //E
{0x7F, 0x48, 0x48, 0x48, 0x00}, //F
{0x3E, 0x41, 0x49, 0x4E, 0x00}, //G
{0x7F, 0x08, 0x08, 0x7F, 0x00}, //H
{0x00, 0x41, 0x7F, 0x41, 0x00}, //I
{0x41, 0x41, 0x7E, 0x40, 0x00}, //J
{0x7F, 0x08, 0x14, 0x22, 0x41}, //K
{0x7F, 0x01, 0x01, 0x01, 0x00}, //L
{0x7F, 0x20, 0x10, 0x20, 0x7F}, //M
{0x7F, 0x10, 0x08, 0x04, 0x7F}, //N
{0x3E, 0x41, 0x41, 0x3E, 0x00}, //O
{0x7F, 0x48, 0x48, 0x30, 0x00}, //P
{0x3C, 0x42, 0x46, 0x3E, 0x01}, //Q
{0x7F, 0x4C, 0x4A, 0x79, 0x00}, //R
{0x3A, 0x49, 0x49, 0x2E, 0x00}, //S
{0x40, 0x40, 0x7F, 0x40, 0x40}, //T
{0x7E, 0x01, 0x01, 0x7E, 0x00}, //U
{0x7C, 0x02, 0x01, 0x02, 0x7C}, //V
{0x7F, 0x02, 0x04, 0x02, 0x7F}, //W
{0x63, 0x14, 0x08, 0x14, 0x63}, //X
{0x60, 0x10, 0x0F, 0x10, 0x60}, //Y
{0x43, 0x45, 0x49, 0x51, 0x61}, //Z
{0x00, 0x00, 0x00, 0x00, 0x00}, //[
{0x00, 0x00, 0x00, 0x00, 0x00}, //\
{0x00, 0x00, 0x00, 0x00, 0x00}, //]
{0x00, 0x00, 0x00, 0x00, 0x00}, //^
{0x00, 0x00, 0x00, 0x00, 0x00}, //_
 {0x00, 0x00, 0x00, 0x00, 0x00}};//`

void address(unsigned char);

void display_data();
void mov_data();
void string(flash char*);
void check();
void serial_send(flash unsigned char *);
void serial_command(unsigned char);
void received_message();
void clear_display();

interrupt[USART_RXC] void usart_rx_isr(void)

{
if(!message)
{
received_data[k++] = UDR;
if(k>15)
{
check();
}
}
if(str_msg)
{
if(k > 62)
{
received_data[x] = UDR;
 x++;
}
else
{
dummy = UDR;
k++;
x=0;
}
}
}

interrupt[USART_TXC] void usart_tx_isr(void)

{
k = 0;
x = 0;
}

void check()
{
if((received_data[2]=='R')&(received_data[3]=='I')&(received_data[4]=='N')&(received_da
ta[5]=='G'))
{
delay_us(25);
serial_send("ATH");
serial_command(0x0D);
delay_ms(250);
message = 0;
x=0;
 k=0;
}

else
if((received_data[2]=='+')&(received_data[3]=='C')&(received_data[4]=='M')&(received_data[5
]=='T')&(received_data[6]=='I'))
{

delay_us(25);
message = 1;
str_msg = 1;
x = 0;
k = 0;
}
}

void serial_send(flash unsigned char *temp)

{
while(*temp)
{
UDR = *temp;
temp++;
delay_ms(1);
}
}

void serial_command(unsigned char temp)

{
 UDR = temp;
delay_ms(2);
}

void main(void)
{
SREG = 0x00;
STR = 0;
OE = 0;
CLK = 0;
D = 0;
DDRC = 0xFF;
delay_ms(500);

UBRRL = 0x67;
UBRRH = 0x00;
UCSRB = 0xD9;

SREG = 0x80;
serial_send("AT");
serial_command(0x0D);
delay_ms(30);
k = 0;
serial_send("AT+CMGD=1,4");
serial_command(0x0D);
delay_ms(6999);
k = 0;
 x = 0;
message = 0;
str_msg = 0;
new_message = 0;
STR = 1;
OE = 1;

while(1)
{

string("WELCOME TO MIC electronics ltd,hyderabad");

if(new_message)
{
received_message();
}
//else

}
}

void string(flash char *alpha)

{
while(*alpha)
{
display_dat = *alpha;
 if(display_dat > 0x60)
display_dat = display_dat-0x20;
display_dat = display_dat-0x20;
mov_data();
alpha++;
}
clear_display();
}

void clear_display()
{
unsigned char count;
unsigned int y = 0;
display_dat = 0;
for(count = 0; count < (tot_mod-per); count++) //clear display 8x5
{
mov_data();
}
if(str_msg)
{
msg_loc = received_data[14];
serial_send("AT+CMGR=");
serial_command(msg_loc);
message = 1;
x = 0;
k = 0;
serial_command(0x0D);
 delay_ms(500);
str_msg = 0;
message = 0;

if((received_data[0]=='*')&(received_data[1]=='7')&(received_data[2]=='8')&(received_
data[3]=='9')&(received_data[4]=='*')&(received_data[5]=='#'))
{
new_message = 1;
y = 0;
do
{
display_reci_data[y] = received_data[y+6];
display_reci_data[y+1] = received_data[y+7];
y++;
}
while((received_data[y+6]!=0x0D)&(received_data[y+7]!=0x0A));
k = 0;
x = 0;
}
/*serial_send("AT+CMGD=");
serial_command(msg_loc);
serial_command(0x0D);
delay_ms(350);*/

}
}
void received_message()
{
unsigned int y=0;
while((display_reci_data[y]!=0x0D)&(display_reci_data[y+1]!=0x0A))
{
display_dat = display_reci_data[y++];
if(display_dat >= 0x61)
display_dat = display_dat - 0x20;
display_dat = display_dat - 0x20;
mov_data();
}
k=0;
x=0;
clear_display();
}

void mov_data()
{
unsigned char i,count1;
for(i=0 ; i<5 ;i++)
{
for(count1 = 0; count1 < (tot_mod*5-1); count1++)
{
display_font_data[count1] = display_font_data[count1+1];
 }
display_font_data[tot_mod*5-1] = caps[display_dat][i];
display_data();
}
}

void display_data()
{
unsigned char j,disp_column,rotate;
for(j=0;j<5;j++)
{
for(rotate = 0; rotate < 7; rotate++)
{
for(disp_column=0; disp_column<(tot_mod*5); disp_column++)
{
D = (((display_font_data[disp_column]<<(rotate+1)))&0x80)?1:0;
CLK = 0;
CLK = 1;
}
address(rotate);
delay_ms(3);
address(7);
}
}
}

void address(unsigned char adr)

{
A0 = adr%2;
adr = adr/2;
A1 = adr%2;
adr = adr/2;
A2 = adr%2;
}
 LIST OF COMPONENTS USED

S.No component Component name

1 AT Mega 32k Micro controller

2 74HC138 3 to 8 Decoder

3 HEF4094 Shift register

4 ULN2003 Driver

5 MAX 232 Level converter

6 74HC04 HEX Inverter

7 7805 Regulator

8 RS232 9 pin connector