Beruflich Dokumente
Kultur Dokumente
Daniel Llamocca
FINITE STATE MACHINES (FSMs)
Classification:
Moore Machine: Outputs depend only on the current state of the
circuit.
Mealy Machine: Outputs depend on the current state of the
circuit as well as the inputs of the circuit.
The circuit must always start from an initial state. Thus, there should be
a ‘resetn’ signal. The figure depicts a generic state machine:
Only for Mealy Machine
clock
resetn
Daniel Llamocca
FINITE STATE MACHINES (FSMs)
VHDL Coding: There exist many different
styles. The style explained here considers two processes: one for
the state transitions, and another for the outputs.
The first step is to have the state diagram ready. The coding
then just simply follows the state diagram.
We need to define a custom user data type (e.g., “state”) to
represent the states
type state is (S1, S2, ... S10) – example with 10 states
signal y: state;
Daniel Llamocca
Example: 2-bit counter
Moore-type FSM
Count: 00 01 10 10 00 … 2-bit 2 Q
clock counter
library ieee;
use ieee.std_logic_1164.all; resetn
Custom datatype definition: ‘state’
entity my_2bitcounter is with 4 possible values: S1 to S4
port ( clock, resetn: in std_logic; resetn = '0'
Q: out std_logic_vector (1 downto 0)); S1 S2
end my_2bitcounter;
Q= 0 Q= 1
architecture bhv of my_2bitcounter is
Q= 0 Q= 1 Q= 2 Q= 3
1
S10 S5
stop=1 1 1 0
Q= 9 Q= 4
0 1 1 1
S9 S8 S7 S6
1 0
Q= 8 Q= 7 Q= 6 Q= 5
1 0 0 0
Daniel Llamocca
BCD Counter with stop signal
VHDL code: Moore FSM
library ieee;
use ieee.std_logic_1164.all;
entity bcd_count is
port ( clock, resetn, stop: in std_logic;
Q: out std_logic_vector (3 downto 0));
end bcd_count;
Custom datatype definition: ‘state’
with 10 possible values: S1 to S10
architecture bhv of bcd_count is
begin
S1 E=1 S2 E=1 S3
E=0 DO=00011000 DO=00111100 DO=01111110
my_ledseq.zip:
E=1 E=1
my_ledseq.vhd,
S6 E=1 S5 E=1 S4 tb_my_ledseq.vhd
DO=10000001 DO=11000011 DO=11100111
Notation: x/z
S1 S2
1/0
0/0 1/0
1/0 S3
0/1
0/0 0/0
S5 S4
1/0
Daniel Llamocca
Example: Sequence detector
with overlap
VHDL Code: Mealy FSM x
Detector z
library ieee; clock '11010'
use ieee.std_logic_1164.all;
resetn
entity my_seq_detect is
port ( clock, resetn, x: in std_logic;
z: out std_logic);
end my_seq_detect; Custom datatype definition: ‘state’
with 5 possible values: S1 to S5
architecture bhv of my_seq_detect is
begin
...
elsif (clock'event and clock='1') then Note that the
case y is state transitions
when S1 =>
depend on the
if x = '1' then y<=S2; else y<=S1; end if;
input signal ‘x’
when S2 =>
if x = '1' then y<=S3; else y<=S1; end if;
when S3 =>
if x = '1' then y<=S3; else y<=S4; end if; Process that
when S4 => defines the state
if x = '1' then y<=S5; else y<=S1; end if; transitions
when S5 =>
if x = '1' then y<=S3; else y<=S1; end if;
end case; Note that the
end if; state transitions
end process; only occur on the
... rising clock edge
Daniel Llamocca
Example: Sequence detector
with overlap
VHDL Code: Mealy FSM x z
Detector
clock '11010'
...
Outputs: process (x,y)
begin Note that the output
depends on the
z <= '0';
current state and the
case y is
input ‘x’, hence this is
when S1 => a Mealy machine.
when S2 =>
when S3 =>
when S4 =>
Process that
when S5 =>
defines the
if x = '0' then z <= '1'; end if; outputs
end case;
end process;
end bhv;
my_seq_detect.zip:
my_seq_detect.vhd,
Daniel Llamocca tb_my_seq_detect.vhd
ALGORITHMIC STATE MACHINE
(ASMs) charts
This is an efficient way to represent Finite State Machines.
We use the 11010 detector as an example here.
resetn=0
x z S1
Detector
clock '11010'
0
x
resetn 1
S2
resetn = '0'
0/0 1/0
0
x
Notation: x/z
1
S1 S2 S3
1/0
0/0 1/0
1
x
1/0 S3 0
S4
0/1
0/0 0/0
0
x
S5 S4 1
S5
1/0
1 0
x z1
Daniel Llamocca