Low-Cost Solutions for Video Compression Systems

Brian Jentz
Altera Corporation
101 Innovation Drive
San Jose, CA 95054, USA
(408) 544-7709
bjentz@altera.com

Overview

Memory
Many device applications utilize video
compression to reduce the amount of data
necessary to produce a sequence of images. Vide
FPGA
This array of applications ranges from high- o
DAC
Video

definition television to low-power wireless Video

Video
Video
ADC
video transmission. Implementation of real- Video
Ethernet
PHY
Video Strea
time video compression systems requires
high data throughput and complex
computational algorithms. Traditionally,
multiple device components have been Hard Disk

required to implement both the compression

and pre- and post-processing functionality,
but the increasing density of low-cost Functional Blocks include interface, video
FPGAs enables a cost-effective single-chip compression, video processing, and system
functions.
solution for the entire processing chain.
System File RTP/UDP
System
This paper will demonstrate that real-time Video De- Scaling Color Flicker Overlay Frame
Processing Interlacin Conversi Filtering Rate
video compression systems can be Video M-JPEG M- MPEG-4
Compression JPEG200
implemented in low-cost FPGAs. Starting Video BT-656 SD-SDI VGA DVI
Interfaces
from available compression IP cores I²S I²C DDR IDE PCI Ethernet
Interfaces
(MPEG4/JPEG2000), video processing SDRAM MAC

architectures for the surveillance and Hardware Software

security markets will be explored.

Video Compression Choices
Video Surveillance Case Study
One of the most important system decisions
Video surveillance is a good case study to is the choice of video compression used in
examine as it has many of the elements the system. The table below shows some of
common in other video applications. First, the key considerations in choosing a
let’s examine the top level block diagram of compression scheme.
a video surveillance system. This system has
1-4 camera inputs with D1 resolution, a hard
disk drive for storage, and a network
interface.

CP-LWCST05-1.0

Compression is defined as the amount of
compression achievable at a reasonable
picture quality for standard applications. The
bit rate is the bandwidth requirement needed
to get that quality (simply the raw size
divided by the compression ratio). Motion
compensation establishes a correspondence
between elements of nearby images in the
video sequence, allowing a useful prediction
for a given image from a reference image.
Variable Bit Rate (VBR) offers the
possibility of fixing a constant picture
quality by varying the bit-rate according to
the needs of the picture. This allows the
images that usually require little data, like
still frames, to use additional data only when
needed to maintain quality. The result is an
overall saving in storage or more efficient
allocation of total available bit-rate.
Constant Bit Rate (CBR) forces a fixed
output rate, regardless of compression
quality, with the goal of fitting within a
given bandwidth such as that on a constant
bit rate transmission channel. With video,
the useful information contained in the
material varies widely, both spatially and
with movement. For example, a football
game with crowds and grass texture as well
as fast-panning cameras typically contains
far more information than a largely static
head-and-shoulders shot of a newsreader.
Using CBR means that the quality is altered
to reduce the information to fit the fixed bit
rate. In the football case, the grass may go
flat during a pan with the texture
reappearing when the camera is still. As
overflowing the available bit rate could have
disastrous results with bits being lost, the
aim is always to use just under the available
bit rate. The degree of success in almost
filling the available space is a measure of the
quality and efficiency of the compression
system. Latency is essentially the total time
for encoding and decoding. Compression
algorithms work with blocks of data (8x8 for
JPEG) which can result in block artifacts in
the picture. Lossless compression refers to
compression where no data is lost – the
downside is that the compression is only 2x.
A compressed data stream is resolution
scalable if it contains identifiable subsets
that represent successively lower resolution
versions of the source; it is distortion
scalable (or SNR scalable) if it contains
identifiable subsets that represent the source
at full resolution, but with successively
lower quality (in other words, with more
distortion and coarser quantization).
Scalability can also describe other attributes.
Subsets of a JPEG2000 code-stream may be
extracted to represent the original image at a
reduced resolution, a reduced quality (higher
distortion), or over a reduced spatial region.
JPEG advantages are cost to implement and
low latency. Disadvantages are lack motion
compensation and CBR support, presence of
blocking artifacts. JPEG2000 advantages
include no blocking artifacts and lossless
support. Disadvantages are lack of motion
compensation and cost to implement.
MPEG4 advantages include high
compression, low bit rate and motion
compensation support. Disadvantages are
latency and blocking artifacts. JPEG,
JPEG2000, and MPEG4 have all been used
in video surveillance systems, with the
choice depending on what is most important
in that particular application. H.264 is an
advanced compression scheme which is also
starting to find its way into video
surveillance systems. H.264 offers very high External DDR DRAM memory is required
compression at the expense of additional for buffer memory.
hardware complexity. It is not examined in
Buffered Reference
this paper, but FPGA-based solutions exist DDR SDRAM
Frame

for H.264. SDRAM 2,000 LEs

Controller
31 MB/s 2,500 LEs
31 MB/s
FPGA Implementation MPEG-4
Encoder
−
Ethernet
This paper examines the use of Altera’s low- YUYV…
Raw to Block
Conversion
MAC

4:2:2
cost FPGA family to implement the digital Y Y
U V
portion of a video surveillance system in a 300 LEs
Y Y
4:2:0 18,000 LEs
2,000 LEs

92 M4K’s
single device. Altera’s Cyclone II family
scales from 4,600 logic elements (LEs) to
68,000 LEs. A table of resources for JPEG2000-Based System
Cyclone II is shown below.
The diagram below shows a JPEG2000-
Logic
Total 18x18 Maximum
Production
based implementation of a video
Device Memory Embedded PLLs User
Elements
Bits Multipliers I/O Pins
Availability
surveillance system with D1 resolution in an
EP2C5 4,608 119,808 13 2 142 July EP2C70 FPGA. External DDR DRAM
EP2C8 8,256 165,888 18 2 182 Now memory is also required for buffer memory
EP2C20 18,752 239,616 26 4 315 Now

EP2C35 33,216 483,840 35 4 475 Now In each of these implementations, a 32-bit

EP2C50 50,528 594,432 86 4 450 August RISC processor, Altera’s Nios II, is used to
EP2C70 68,416 1,152,000 150 4 622 Now implement the IP stack and system
initialization. Nios II is a soft processor,
meaning that it can be synthesized to any
JPEG-Based System Altera FPGA. It can easily run over 100
MHz in Cyclone II.
The diagram below shows a JPEG-based
implementation of a video surveillance All of the implementations shown are single
system with D1 resolution in an EP2C20 channel implementations, but multiple
FPGA. No external memory is required. channel implementations are possible. A 4-
DDR SDRAM Buffered Reference
channel JPEG-based system could be
Frame
implemented in the EP2C35. FPGAs also
31 MB/s
SDRAM
Controller
2,000 LEs
allow the scaling of the system feature set.
2,500 LEs
31 MB/s For example, if one wanted to add the ability
MPEG-4
Encoder
− to support multiple resolutions, along with
Raw to Block
Ethernet
MAC
dynamic overlay to the MPEG4-based
YUYV…
4:2:2
Conversion
system described earlier, it could still be
Y Y
Y Y
U V done in the Cyclone II family, using the
300 LEs 2,000 LEs
4:2:0 18,000 LEs
92 M4K’s EP2C70. A block diagram is shown below.

Horizontal Scaling May Be

Applied Here to Convert to
Square Pixels (12.27/14.75 MHz)
MPEG4-Based System
PAL/NTSC
Overl
Scali
Deint
lacin
Vide

Bloc

Raw

MPE
G-4
ng
I/F

ay

to
er
o

Video

The diagram below shows a MPEG4-based

implementation of a video surveillance Stream
Ethernet
MAC Memory I/F

system with D1 resolution in an EP2C35

FPGA, making this a $25 solution in volume. DVI
Scalin Frame Flicker Color
Vide

Overlay
I/F

Rate
o

g Filter Conv
Graphics
Conv
Conclusion

Compression-based video systems are

moving to higher resolutions, resulting in
implementations which often require
multiple device components. This paper
shows how a low-cost FPGA family can be
leveraged to meet a wide variety of system
requirements – multiple channels, multiple
resolutions, and overlay – in a single device.
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