Beruflich Dokumente
Kultur Dokumente
Jean Picard
Topic 1
ABSTRACT
A basic review of the flyback switching topology will be presented with an emphasis on not-so-obvious
design issues, such as effects of parasitics, fault protection, and EMI mitigation. Modeling and analysis
will be demonstrated and compared with physical hardware measurements. A major subtopic will be the
operation and characterization of the flyback transformer — considering leakage inductance, cross-
regulation, parasitic capacitance, and other performance-defining parameters.
1-1
occurring when the stored energy just reaches zero transformer designed for DCM operation requires
at the end of the switching period. a smaller inductance value than one designed for
Figs. 1 and 2 illustrate CCM, DCM, and TM CCM operation, since the current ripple ($IL) is
Topic 1
operation. Fig. 3 illustrates the current flow in much higher. In some applications, lower
CCM and DCM operation. inductance may result in a physically smaller
With DCM operation, when the primary transformer; assuming the efficiency and thermal
MOSFET turns on, the primary current starts at performance remain acceptable.
zero and rises to a peak value that can be more TM operation is similar to DCM except that
than twice the peak current in a comparable CCM the primary MOSFET turns on at the moment the
application. At turn off, the ampere-turns transfer drain voltage is at its minimum level. This timing
to the secondary and the secondary current offers minimum turn-on loss and a more efficient
decreases to zero where, it remains until the operation, however, the switching frequency
beginning of the next switching cycle. A flyback is variable.
Ts +Vi
Vdrain
Vo Io
Primary + Vi (1 – D) x Ts 1:n2 Vo
MOSFET D x Ts n2
Clamp
IP
Primary
Current m1P Ipk Vdrain
IP ΔIL Ipkmin
Secondary m2S RS
Current ΔILS
Io Io_avg
Time (t)
Fig. 1. Operation in CCM.
Ts Ts
Vdrain Vdrain
Vi D × Ts Vo Vi
Primary D × Ts Vo Primary Vi +
n2 + Vi n2
MOSFET MOSFET
Ipk
Ipk
Primary Primary
Current (1 – D) × Ts Current
IP
IP
Idle
Period
Secondary Secondary
Current Io_avg Current
Io Io_avg
Io
1-2
With CCM operation, the inductance value is where Vo is the output voltage, n2 = N2/N1 and ILS
large and the ripple component of the current and is the secondary magnetizing current (see Io in
magnetic field is relatively small. The following Fig. 2) .
Topic 1
limits are a good working compromise for Note that the coupling between the primary
acceptable primary peak current. and secondary sides of a flyback transformer is
I pk min imperfect because there is leakage inductance
35% d d 50% between them. During commutation from primary
I pk to secondary, the leakage energy cannot be directly
transferred to the secondary and consequently
This can also be used to define an appropriate
must be absorbed. Without a clamp circuit, the
trade-off between efficiency and transformer size.
only path the leakage-inductance current can
Neglecting the losses while the primary
circulate is by charging the parasitic drain-to-
MOSFET is on (see Fig. 1), the primary current
source capacitance of the MOSFET. If precautions
increases at a rate defined as
are not taken, the MOSFET switch can be destroyed
'I L Vi by voltage breakdown. Fig. 3 shows a generic
m1 , (1)
D u TS L clamp circuit example. Later in Section VI, several
clamp circuits are presented and explained.
where Vi is the input voltage, L is the inductance Note the discontinuous nature of the current
value measured at the primary of the transformer, on each side of the transformer, in CCM, DCM,
IL is the current circulating through the primary and TM. This is a fundamental difference when
(see IP in Fig. 1), and TS is the time period of one compared to other transformerless topologies like
switching cycle. buck or boost. The high ripple current on both
Following the same assumptions, while the sides of the transformer directly impacts the output
primary MOSFET is off and the transformer voltage ripple, the efficiency, and the differential-
current has been transferred to its secondary mode conducted EMI.
winding, the secondary current decreases at a Also, although there is current discontinuity
rate defined with Equation (2) unless it on both sides of the transformer, operating in
becomes discontinuous: CCM generally results in better efficiency than
'I LS Vo operating in DCM. The higher rms current in
m 2S , (2) DCM is one reason supporting this fact, as it
1 D u TS L u n 22
means a higher dissipation in the MOSFET, the
1-3
primary and secondary capacitors, and the primary the stored energy in the transformer. Increasing
clamp. However, because the inductance value is the ON time in fact decreases the OFF time. If
lower for DCM operation, a transformer that is the there is CCM operation, the energy delivered to
Topic 1
same physical size may have less conduction loss the load during the first few cycles decreases, and
for DCM operation than if it was designed for the initial reaction results in a larger output
CCM operation, even if its rms current is higher. voltage drop. The return to regulation is reached
In some AC-line applications and operating only after the energy from longer ON-time is
conditions, TM operation may be able to provide transferred to the load over several cycles. In
similar or even better efficiency than CCM. Core small-signal-analysis modeling, this behavior is
loss must also be considered when operating in referred to as a right-half-plane zero (RHPZ). With
DCM (and TM), given the large AC component of RHPZ, the phase decreases with increasing
the magnetic field. CCM operation usually gain, which must be considered when defining
corresponds to a lower AC magnetic field; thus, control-loop compensation.
the main limitation when designing the transformer Applicable to the test circuit used later in this
becomes core saturation rather than core losses. document (CCM operation), Fig. 4 illustrates the
While in DCM, transferred energy is dictated influence of input voltage and output load current
by ON time, input voltage, and inductance value. on the RHPZ frequency. The general rule for
There is always a complete energy transfer during converters regarding RHPZ is to design at the
every cycle, defined by: lowest input line voltage and at the maximum
load, restricting the bandwidth of the control
Vi 2 u D 2 feedback loop to about one-fifth the RHPZ
PDCM , (3)
2L u Freq frequency. The RHPZ equation is:
where PDCM is the load power while in DCM, L is
the inductance value measured at primary of the f RPHZ
1 D 2 u Vo . (6)
transformer, D is the control-switch duty cycle, 2SL u D u Iout u n 2 2
and Freq is the switching frequency. Even in DCM operation, RHPZ exists, but it is
This also means that in DCM, the following usually not a problem, normally exceeding half of
duty-cycle equation depends on the load current the switching frequency.
and input voltage:
2PDCM u L u Freq
D DCM . (4)
Vi 2
is:
Vo
DCCM . (5)
n 2 u Vi Vo
B. Control Aspects
One characteristic of the flyback topology
is that the energy is delivered to the load only
during the OFF time of the control switch; the
effect of any control action during the ON time
is delayed until next switch turn off. For
example, in response to a step increase in load
that causes a decrease in output voltage, the Fig. 4. An example of the influence of input voltage
controller increases the ON time to increase and load current on RHPZ frequency.
1-4
The two most popular ways of controlling the of an external ramp to the current-feedback signal,
operation of a flyback topology are voltage-mode creating a composite signal. A typical slope-
control (VMC) and peak current-mode control compensation circuit is described later as shown
Topic 1
(CMC). CMC uses the magnetizing current to in Fig. 20.
define the duty cycle, while VMC does not. When
operating in CCM, a design using VMC has a C. Summary of Fundamentals
relatively low-frequency double pole due to the Table 1 lists the advantages and disadvantages
transformer’s inductance and output capacitor. of CCM, DCM, and TM operating modes.
Consequently, it is more difficult to compensate More information about the basic aspects of
than peak-CMC, which basically consists of a flyback power-supply design can be found in
current source driving the same capacitor. previous TI Power Supply Design Seminar
Conversely, when using peak-CMC while literature. See References [1] and [2], as well as
operating in CCM, slope compensation is necessary the second topic of this seminar, Incorporating
to avoid subharmonic oscillation when the Active-Clamp Technology to Maximize Efficiency
operating duty cycle exceeds or even gets near in Flyback and Forward Designs.
50%. This is usually accomplished by the addition
TABLE 1. COMPARISON BETWEEN CCM, DCM, AND TM FOR A FLYBACK POWER SUPPLY
Operating
Mode Advantages Disadvantages
CCM Small ripple and rms current Slope compensation required at higher duty
Lower MOSFET conduction loss cycles (Peak CMC)
Lower primary MOSFET turn-off loss Diode reverse-recovery loss
Low core loss Higher voltage stress for secondary diodes
Better cross-regulation RHPZ
Lower capacitor dissipation 6\QFKURQRXVUHFWL¿HUVQXEEHUORVV
6PDOOHU(0,¿OWHUDQGRXWSXW¿OWHU /RZOLJKWORDGHI¿FLHQF\
Constant switching frequency
DCM No diode reverse recovery loss Large ripple and peak current
Slope compensation not required in CMC* Higher MOSFET conduction loss
No RHPZ problem* Higher core loss
Lower inductance may allow smaller Higher primary MOSFET turn-off loss
transformer size Higher capacitor dissipation
First-order system even in VMC* Higher MOSFET voltage stress
Constant switching frequency /DUJH(0,¿OWHUDQGRXWSXW¿OWHU
TM (CMC) No diode reverse-recovery loss Large ripple and peak current
Soft turn-on switching possible—MOSFETs Higher core loss
with lower RDS(on) can be used Higher primary MOSFET turn-off loss
No secondary snubber loss Higher MOSFET conduction loss**
Slope compensation not required Higher capacitor dissipation
No RHPZ problem /DUJH(0,¿OWHUDQGRXWSXW¿OWHU
First-order system Variable switching frequency
Transient response Primary MOSFET voltage stress may be higher
Lower inductance may allow smaller trans-
former size
*Valid only if DCM operation is maintained in all conditions of load current and input voltage.
**If TM is combined with soft switching, a larger and more efficient MOSFET could be selected for the primary switch to substantially reduce its
conduction loss.
1-5
III. UNDERSTANDING THE FLYBACK When the MOSFET switch is turned off, Lleak2
TRANSFORMER AND ITS IMPACT ON will oppose any secondary current increase from
POWER-SUPPLY PERFORMANCE zero, and any reduction of the primary current (IP),
Topic 1
1-6
Io During Primary-to-
Lleak2
N1:N2 Secondary Commutation
– + Vleak2 –
–
Vmag1
+ VD + ø
Topic 1
Clamp Lm Vmag2 Vout
+ –
Vi + +
–
W1
IP
FET W2
Leakage
Clamp Diode Inductance
Forward Recovery Demagnetization Leakage Inductance
Current Circulates in Resonates with Drain
Vi + Vclamp
Secondary Winding(s) Capacitance
Vi + Vclamp
0V
Vmag2
Vmag2 – VD – Vout
Vleak2 Reduction in Magnetizing Current
Due to Faster Commutation
IP
IP
Io Io
Lost Volt-Seconds
Dtr Dtr
Fig. 5. Effects of flyback-leakage inductance at primary turn off and the impact of clamp voltage.
1-7
shown in Fig. 5. Note that a higher clamp voltage storage gap because of physical separation between
may degrade cross-regulation performance. them. Also, additional amounts of magnetic energy
v Leakage inductance influences the rate of current are stored between the windings and are represented
Topic 1
rise during commutations, which could in turn as leakage inductances. Although not applicable to
influence the gate-drive strategy if a synchronous any transformer geometry, this model is a good
rectifier is used. tool to help understand how most of the common
v Higher radiated EMI from the transformer. flyback-transformer geometries work. The circuit
representation in Fig. 6 is only applicable to the
Leakage inductance between a primary and
transformer-winding stackup shown. A more
secondary winding can be minimized with a better
complex circuit representation will be needed if
physical coupling between them. The following
interleaving is used or if multiple secondary
design rules can help to achieve this:
windings are wound simultaneously (multifilar).
v Minimize the separation between the primary Also, this model does lack accuracy when eval-
and main secondary windings. uating lightly-loaded secondary outputs.
v Interleave the primary and main secondary. During commutation, the magnetizing flux
v Select a core with a long and narrow window. (Fm) in the gap decreases, which induces current
This increases the field length, minimizing the into the secondary windings. This induced current
flux density between primary and secondary helps maintain the magnetomotive force (MMF)
windings and reducing the number of layers. An in the gap. The rate of flux decrease (including
additional benefit is lower AC winding losses. leakage) within each secondary winding is limited
Note that leakage inductance is a function of by its output voltage, following the equation:
winding geometry, the number of turns, and the dIm
spacing between the primary and the secondary. e N u , (8)
dt
Leakage inductance is independent of the core
material and it will not be reduced by having the where N is the number of turns of a winding and e
winding tightly coupled to the core. is its induced voltage.
For example, once the primary voltage exceeds
C. Cross-Regulation W2’s reflected voltage, W2’s current increases
and in turn generates an increasing flux. Because
Theory of Operation of leakage flux between W1 and W2, the primary
The multiple-output flyback converter is a voltage goes up until the clamp voltage is reached.
popular topology because of its simplicity and low This defines a limit on dFm/dt in the gap.
cost. If perfect coupling between windings was The main secondary winding (W2), being next
possible, the output voltages would be directly to the primary (W1), dictates the dF/dt that the
defined by their respective turns ratio to the outer windings will see during commutation. With
winding supplying the regulated output. W3 and W4 located after the main output winding,
Unfortunately, perfect winding coupling is the generated winding voltage is lower than would
impossible and the coupling operation is very be expected if there was no leakage at all. The net
complex, which often results in poor cross- effect shown in Fig. 6 is that when the main switch
regulation. is turned off, the current commutates progressively
There are a few known models for cross- from near-to-remote secondary windings.
regulation analysis. For example, cross-regulation However, if interleaving was used such that
analysis using the extended cantilever model [3] is half of W1 is next to the low-power secondary
quite complex but has advantages such as geometry windings, part of the flux of W1 would not be
independence and its parameters can be directly sensed by W2, but it would be sensed by the
measured. On the other hand, the physical model lower-power secondary windings, thereby
(also called the “Ladder” model) shown in Fig. 6 increasing the voltage induced into these
is based on the fact that the transformer windings windings.
cannot all be equally well coupled to the energy-
1-8
lW4
+
N4 V4
–
Topic 1
lW3
lp +
N3 V3 I2
Primary
– lp
W1
W2
W3
W4
+
lW2
+ Vi V2
–
Clamp I3
– + N1:N2
I4
FET
– I3 N2:N3 N2:N4
Clamp Vmag1 Lm I4
+ I2 IW4
Vi + IW3
N1:N2
FET + + +
V2 V3 V4
– – –
In the model shown, when all leakages are light load, this ringing begins to charge up the
moved to W2’s side of the transformer, output storage capacitor to the ringing-voltage
Lleak12 corresponds to the leakage inductance overshoot through the output rectifier, which
between W2 and W1, while Lleak23 and Lleak34 blocks return of the energy. At light load, this
correspond to the leakage between W2 to W3 and results in a much higher auxiliary output voltage,
W3 to W4, respectively. which can sometimes even exceeding twice its
nominal value. This effect generally becomes
Ringing Caused by Leakage Inductance and worse as the primary clamp voltage gets higher.
Parasitic Capacitance Common to flyback power supplies, the light-
There is one behavior of the flyback trans- load cross-regulation problem can be mitigated,
former that most existing models fail to predict but not eliminated, by minimizing leakage
accurately—the light-load operation of auxiliary inductance between secondary windings. It also
windings while the main output is fully loaded. helps to locate the highest-power secondaries
When the main switch turns off, the primary closest to the primary. Other solutions to deal with
current causes the voltage to rise very quickly this problem include the use of a post regulator, a
when the main output is heavily loaded. Due to series resistor, or a minimum load. Some solutions
transformer leakage inductance and parasitic involve minimizing the effective winding capacity.
capacitance (winding and diode), the secondary See Reference [18] for details.
voltage tends to ring. If the auxiliary output is
fully loaded, this ringing is clamped. However, at
1-9
Operation with Combined Effects current is ramping down. Consequently, the flux
Corresponding with Fig. 6, Fig. 7 shows an lines created in the spacing (leakage) between the
example of the first three phases during windings are opposing each other. Note that the
Topic 1
commutation from primary to secondary. For amplitude of the leakage flux along a specific path
descriptive purposes, it is assumed that W2 is the is proportional to 3(N × I) and the spacing between
high current winding, I2_pk is not high enough the two layers, and it is inversely proportional to
because Lleak21 is too large, and W4 receives too dimension L of the window area shown in Fig. 7.
much energy during the commutation because of As mentioned before, during commutation, a
ringing at light load. W3 and W4 are low-current decrease of magnetizing flux (Fm) induces a rising
auxiliary secondary windings. current in the secondary windings. Due to leakage
Unlike a forward transformer, in a flyback between W1 and W2, the primary voltage goes up
transformer, both the primary and secondary until the clamp voltage is reached, which defines a
windings simultaneously produce a flux only limit on dFm/dt in the gap. The lower the clamp
during the commutation periods; this flux is the voltage, the lower the induced voltage in the
magnetizing flux. Another difference is that during secondary windings, and the softer the di/dt in
commutation periods, the flux created by each them will be. If there was no primary clamp
winding within the gap is in the same direction circuit, the commutation to W2 secondary would
because the windings all try to maintain the be instantaneous, but the MOSFET would be
magnetizing flux while the primary-winding destroyed by voltage stress.
m
I4_pk
IW4
W2
IW3 I3_pk W1 W3 W4 L
Effect of V3
V3 Capacitors ESR
Phase 1:
During Primary-to-Secondary Commutation
I2_pk Current in All Windings
IW2
m
Vmag1
W2
W1 W3 W4
IP_pk
IP
1-10
At the end of phase 1, the sum of the Obviously, operating the main output in CCM
reflected secondary currents is equal to total (using a synchronous rectifier is one example)
magnetizing current: guarantees that Vmag1 is maintained during the
Topic 1
(1 – D) period, helping to achieve better cross-
I P _ pk n 2 u I 2 _ pk n 3 u I3 _ pk n 4 u I 4 _ pk , (9)
regulation.
where Ix_pk and nx are respectively the current at How Cross-Regulation Can be Optimized
end of commutation interval and the primary-to- Ideally, the initial rising current rate would be
secondary turns ratio for secondary winding proportional to the amount of current the load
number x. needs, but in practice this is difficult to achieve.
From phase 2 and for the rest of the (1 – D) The current reached in each winding at the end of
period of the switching cycle, the secondary commutation depends on leakage inductances and
currents increase or decrease at rates that depend other parasitics.
on differences between the reflected output Good cross-regulation entails maintaining
voltages. It is assumed in this example that I4_pk good control of auxiliary output voltages in spite
has become too high and V4’s output capacitor of load variations at each output, as well as
received too much energy during phase 1. At controlling the main regulated output. Other
beginning of phase 2, a portion of magnetizing benefits of good cross-regulation related to
flux is coming from W4 and it starts decreasing at efficiency include:
a rate defined by W4’s voltage. Also, W2’s
v Operation closer to CCM resulting in lower rms
contribution increases to maintain the magnetizing
current and lower power dissipation in the output
flux in the gap. During that time, IW4 goes down
capacitors’ ESR.
until it crosses zero and stops decreasing because
v Lower gate-drive losses are realized because the
of the diode. If an output is very lightly loaded, its
voltage rail that provides gate drive for power
voltage will increase significantly during
switches becomes more stable for all load
commutation. This means a much steeper (faster)
conditions.
current decrease after phase 1.
The load at each output can greatly affect Also, limiting the initial energy delivered to
cross-regulation. The output-capacitor ESR also the VDD auxiliary rail can offer better protection
has non-negligible impact since it changes the by allowing the controller to more easily reach
slope as the current decreases. With lower current, hiccup mode during a short-circuit event.
the ESR voltage and the voltage across the leakage Various winding strategies can be considered
inductance will be lower, which means a lower in order to achieve acceptable cross-regulation.
di/dt. The waveforms for V3 and IW3 in Fig. 7 Here are some general design guidelines:
demonstrate this concept.
v The load range for each secondary output must
The change in slope of IW2 when IW4 crosses
be well known. The worst case for an auxiliary
zero can be explained with the following
secondary output is when it is lightly loaded
equation:
while the main output is fully loaded.
Im v The winding of the output with the widest load
HuG
AuP
uG ¦ (N u I), (10)
range (usually the regulated output) should have
the best coupling to the primary, which means it
where H is the magnetic field, D is the core gap, Fm should have the smallest leakage inductance to
is the magnetizing flux, A is the core cross-section, the primary.
μ is the gap permeability, and N × I is the
v The leakage between all secondary windings
ampere-turns of a winding. Equation 10 shows
should be minimized.
that a falling magnetizing flux (Fm) corresponds to
a falling magnetizing current which is shared
between all active windings.
1-11
If W3 is lightly
Primary A
Primary B
Primary A
Primary B
Primary A
Primary B
loaded and W2
Better
W2A
W2B
W2A
W2B
W2A
W2B
or
W3
W3
W3
is the high-
than
Topic 1
current main
output.
v Minimizing the leakage inductance of low- v Try to operate the secondary auxiliary outputs
current, auxiliary secondary windings to the close to the boundary between CCM and DCM.
primary is not a good strategy. Larger leakage This ensures that enough energy—but not too
inductance to the primary helps limit the energy much—is delivered to each. One way to
delivered to these windings during commutation accomplish this is by adding some series
by increasing their CCM load range and impedance and/or enough load current at
improving their cross-regulation (see Fig. 8). minimum load.
v Leakage inductance is influenced by winding v When secondary windings share the same ground
placement on the bobbin. The winding stackup and a similar polarity, AC or DC stack is another
(W4 compared to W3 in Fig. 6) defines how alternative to improve cross-regulation. (See
close each secondary winding is to the primary. Fig. 9.)
It is usually a good practice to spread a v Leakage inductance can vary from one production
winding over the full width of the bobbin for unit to the next. For predictable cross-regulation,
better coupling. some maximum leakage inductances need to be
v Winding more than one auxiliary secondary specified and controlled. For example, main
simultaneously using a multifilar technique output to primary, as well as between secondary
usually provides better cross-regulation control. windings.
v Operate the main output in CCM. This output
voltage then defines the magnetizing voltage
(Vmag) during the total cycle.
12 V 12 V
NS2 NS2
5V 5V
NP NS1 NP NS1
AC Stack DC Stack
1-12
Other parameters can have an impact on cross- Cross-Regulation’s Impact On
regulation, including: Short-Circuit Behavior
v Primary clamp voltage. A higher voltage means Short-circuit protection for a multioutput
Topic 1
a faster commutation and a stronger ringing flyback power supply poses many challenges.
effect. The current shared between secondary When relying solely on the primary current limit,
windings during commutation is more dependent the output current of a flyback power supply can
on transformer parasitics and has less tendency become quite high during a short circuit. The wire
to follow the load level of each output. This used for the main output winding is usually
means a stronger influence from leakage selected so that it is tolerant to strong overloads
inductances and parasitic capacitances on the until a hiccup mode is reached. But for a
initial peak current reached, and consequently low-current auxiliary output (see W3 and W4 in
worse cross-regulation from load variations. Fig. 7), the winding wire size is usually very small.
Note that with an RCD clamp circuit, the clamp When a strong overload or a short circuit occurs at
voltage normally increases when the input this output, particularly while the main output is
current is higher, which when combined with a lightly loaded, most of the power capability of the
higher magnetizing energy may worsen cross- power supply is available. Thus, the winding
regulation. dissipation of the output can become very high in
v Forward recovery of output diodes. Using a spite of the primary current limit, with potentially
diode with a faster turn on will result in more catastrophic results.
energy delivered to its output, resulting in a Some power supplies rely on the collapse of
higher output voltage at a light load. Diode the voltage rail used to power the controller during
parasitic capacitance also has some impact on a short circuit. However, this technique lacks
the result. accuracy and is often unreliable. One reason is
v A synchronous rectifier (if used on the main that because of the leakage inductance and parasitic
output) may be off during the commutation from capacity, not all the transformer energy
primary to secondary, with current circulating is delivered to the short-circuited output. Some
through the body diode. This results in more energy is still delivered to the auxiliary output
energy delivered to the other windings, since powering the controller and since the consumption
the reflected voltage is higher during on that rail is usually low, the delivered energy
commutation. Energy is also lost while the body can be high enough to keep the controller
diode conducts. alive indefinitely.
v Where tighter control is required and where the A much better way is to have short-circuit
load range is limited, a low-value resistor may detection for each output. For example, the use of
be inserted in series with the diode (before the a single, summing-current transformer is a
capacitor). Using a resistor constitutes an relatively simple solution. Note that in the partic-
acceptable trade-off, with a resistance value high ular case where the auxiliary output powering the
enough to limit the amount of energy delivered controller is short-circuited, an undervoltage
to the output capacitor during commutation and lockout condition will simply disable the
low enough to mitigate its impact on DC voltage controller.
droop and efficiency. This solution is often used
for the controller’s VDD voltage.
D. Test Results: Cross-Regulation
To illustrate the effect of winding strategy on
v When all else fails, a dummy load may be
cross-regulation, various flyback transformers
needed to limit the maximum voltage of lightly
were designed, built, and tested on a modified
loaded windings.
evaluation module (EVM) based on the TPS23754
controller. For oscilloscope measurements, current
transformers with sensing circuitry were built and
1-13
Current Probe
VDD V6
)
Topic 1
VAW3 "#$% R6
&'( &'(
Current
Probe
V4
36
R4
300 & ( "#$%
! 5V
-./0%1
I5 V
To CS Input *%
+, +
0-
)
Fig. 10. Cross-regulation test circuit using an RCD clamp and current-sense transformers.
W1B
W2
W4
W3
W6
1-14
IW6
(0.5 A/div)
IW6 (0.5 A/div)
Topic 1
2 IW4 2
IW2 IW2
(2.94 A/div) (2.94 A/div)
1 1
Cross-Regulation Tests:
IW6 (0.5 A/div)
As an example, the transformer’s leakage
inductance chosen was: Lleak21 = 43 nH (see
Fig. 11). Fig. 12 show what happens, while the 2
1-15
I5 V = 5 A, I5 V = 5 A, 20.6 V
Topic 1
V6 (10 V/div)
VW6
(10 V/div)
IW6
(200 mA/div)
Time (1 μs/div) Time (1 μs/div)
a. With V6 at 0.5 W and Vclamp = 70 V. b. With V6 less than 5 mW and Vclamp = 70 V.
I5 V = 5 A, I5 V = 5 A, 26 V
14.4 V
V4 at 0.3 W V4 at 0.3 W
V6 (10 V/div)
VW6
(10 V/div)
IW6
(200 mA/div)
Fig. 14 shows what happens when an auxiliary Output Current Overload Tests:
output (V6) is lightly loaded while the main The reaction of the power supply to current
output (V2) is fully loaded. The V6 output more overloads on various outputs was tested with the
than doubles as its load current decreases. Also, same transformer described earlier. A worst-case
the RCD clamp resistor was changed to show test condition was established with the main
the effect of primary clamp voltage on 5-V output unloaded, the load resistance at V6
cross-regulation — the higher clamp voltage also was decreased down to 1 7 (not low enough to
causes poorer cross-regulation. result in a VDD UVLO), and the load current
exceeded 3 A.
1-16
)LJ VKRZV WKDW HYHQ ZLWK D ORDG DW
W6, there was enough energy delivered to the
VDD output to maintain switching, VAW3 is the IW4 (1 A/div)
voltage measured at the anode of W3’s series
Topic 1
diode. The duty cycle is still fairly high because 4
= 5/4, 4/5
Wire type and size has a great influence on
these characteristics. “Litz” wire (made of multiple
10
strands woven in a pattern to reduce high- = 2, 1/2
frequency loss) usually provides the best
performance, while multifilar wound strands,
when carefully defined, can provide acceptable
= 0,
results. The strategy used in stacking winding 1
layers also influences proximity-effect losses.
Sometimes, evaluating the trade-off between = –1
proximity-effect losses and DC resistive losses
can determine the number of strands for a
0.1
minimum-loss winding. 0.1 1 10
Predicting proximity-effect losses for a flyback Layer Thickness Ratio, h/
converter is not trivial; it requires validation
through lab testing, since the current does not
Fig. 16. Normalized power dissipation per layer
circulate in the primary and secondary windings at
versus effective layer-thickness ratio.
same time. One prediction method entails using
the A-parameter graph (see Fig. 16).
In Fig. 16, Q´ is proportional to the power
dissipation in a layer and at a single frequency. It
is normalized to the dissipation associated with a
DC current in a one-skin-depth thick layer. Also in
1-17
Fig. 16, D represents the skin depth of the conductor direct impact on the gate-switching losses. Also,
at the frequency considered. The h parameter is poor cross-regulation can result in excessive rms
the effective layer thickness (assuming round current in low-power secondary windings and in
Topic 1
wires) and it can be estimated with the equation: their output capacitors’ ESR.
v High leakage between the primary and main
d
h 0.83 u d u , (11) secondary windings means more energy lost in
do clamps and snubbers.
where d is the wire diameter and do is the v CCM operation usually provides better efficiency
center-to-center wire spacing. (lower conduction and core loss) than DCM.
The A parameter for a layer is the ratio the v The effect of fringing flux from a gap. In a
tangential H-field’s AC component on one side of flyback transformer, it’s better (although maybe
the layer to the H-field’s AC component on the not always practical) to keep the windings
other side, at the frequency considered: away from the fringing field associated with
discrete gaps.
H t _ sideA v The transformer turns ratio, which must be
D . (12)
H t _ sideB carefully defined for an optimum duty cycle and
high efficiency. Fig. 17 shows that there is an
For each A value, an optimum thickness exists optimum duty cycle for which conduction losses
at which power dissipation is minimal. The can be minimized. The squared primary current
winding strategy and number of layers directly is multiplied by a factor of 20 and then compared
affect A. Having A = 0 or d usually minimizes the to the squared secondary current. The 20x factor,
AC copper loss related to the fundamental and the which is arbitrary, assumes that resistance in the
harmonics. One strategy against proximity-effect primary circuitry, including transformer winding
loss is to select a core shape that will minimize the and MOSFET, is 20x higher than in the secondary
number of layers. For more details on AC winding circuitry. The full input voltage range should be
losses, see References [4], [5], and [6]. considered during this analysis.
Other factors affecting efficiency are:
v Cross-regulation performance. For example, the
auxiliary rail used to power the controller has a
! "
#!
!
$
%##!
&
'!&())*
+
&$,-
!
$
1-18
Topic 1
Primary A
Primary B
Primary A
Primary B
W2 A
W2 B
W2 A
W2 B
W3
W3
a. Transformer 2xW2 (Interleaved). b. Transformer 2xW2_NI
(Not Interleaved).
Fig. 18. Flyback transformers used for efficiency tests.
1-19
using a core with a long and narrow window for v Always test the transformer performance in a
a minimum number of layers (this also reduces real test circuit in order to validate the analyses
proximity-effect losses). and optimize the design.
Topic 1
1-20
+Vi
Io
1:n2 Vo
Topic 1
Feedforward Rff
Clamp I out
Slope Comp
Clock Ramp
I_SENSE R
–
PWM +
C Rs
VC
COMP
(From Error
Amp) VC_LIM
!
"
Fig. 21. Peak CMC law: No parasitic or filter delays, no slope compensation, and no feedforward.
1-21
short-circuit can reach a much higher value than inductance detected at the primary, and D is the
the output load-current limit, which is the control-switch duty cycle. If the load current is
load-current level at which the output voltage exactly at the output load-current-limit threshold,
Topic 1
begins to fall. This can be explained as: the duty cycle is still defined by the regular
IA equation, which also defines (1 – D).
Iout Io _ avg u 1 D , (13)
n2 Vo
D (15)
n 2 u Vi Vo
where Iout is the output load current (assumed to
be constant), n2 = N2/N1, and IA is the average With a shorted output, however, Vo falls close
magnetizing current when measured at the to zero, which according to Equation 14 reduces
primary. the downslope to a very small number and drives
Neglecting the diode (or synchronous rectifier) the duty cycle to its minimum value (usually
forward voltage drop, a first approximation of the determined by delays through current-sense
magnetizing current downslope can be expressed filtering or leading-edge blanking). With a
as: minimum D, (1 – D) approaches unity, increasing
'I L Vo the average magnetizing current and allowing the
m2 | , (14) output current to increase to more than twice the
1 D u TS n 2 u L value defined by the onset of current limiting
where $IL is the peak-to-peak value of the (see Fig. 22). For better prediction accuracy, Vo
magnetizing current when measured at the primary should include the voltage drop of output series
during a switching cycle, L is the magnetizing elements, including the rectifier (or synchronous
rectifier) and output filters.
D x Ts
m2S
Secondary
Current
I o_avg
(1 – D) x Ts
Time (t)
Ipk_LIM
Primary
Current D x Ts
I o_avg
Secondary
Current
(1 – D) x Ts
Time (t)
Fig. 22. Output load current from overload to short circuit.
1-22
Topic 1
Fig. 23. Peak CMC law: no parasitic or filter delays, no slope compensation, but with feedforward.
A second characteristic of this topology and Also, when in current limit and referring to
operating mode is that the output load-current Equations (13) through (16), the output load
limit is highly dependent on the DC input bus current Iout_LIM is shown by Equation (17) below,
voltage. At a higher bus voltage, the duty cycle where IA_LIM is the average magnetizing current
gets lower, which means that the magnetizing limit at the primary and VC_LIM is the peak
energy is transferred to the load for a higher current-limit-voltage threshold (maximum V C
proportion of a cycle. Regular power supply value). If a lower inductance value is selected for a
controllers have a fixed-peak current-limit higher current ripple, the peak current-limit
threshold based on primary current measurement. threshold (Ipk_LIM) may need to be increased.
The threshold remains the same regardless of the
input bus voltage, which indicates an identical Impact of Feedforward
magnetizing current at the moment of turn off. When combined with peak CMC, a feedforward
Exactly at the peak current-limit operating point, technique allows the maximum power output to be
the average current provided to the load depends maintained relatively constant over a wide input-
mainly on the duration of the (1 – D) period; at a voltage range, thereby lowering the cost of
56-V input voltage, the available load current components that would otherwise have to handle
before reaching the current limit is significantly excessive power at high input voltages.
higher (50% is common) than at a 24-V input. Fig. 23 shows the impact of the feedforward
This can be explained with a simplified resistor (shown in Fig. 20) on the current-limit
equation based on Fig. 21: threshold. In this and subsequent illustrations, the
feedforward contribution (Kff × Vi) is subtracted
m 2 u 1 D u Ts from the error amplifier’s output VC so that it
IA I pk
2 becomes easier to define the duty-cycle equation.
(16) This representation is functionally equivalent to
VC m 2 u 1 D u Ts
, adding feedforward to the current feedback.
RS 2
The feedforward technique provides better
where Ts is the switching period, RS is the current control of the operating conditions during an
sense resistor value, and VC with RS defines the overload; consequently, it can reduce the amount
peak current-limit-voltage threshold. of stress on the power circuitry in worst-case
I A _ LIM u 1 D
Iout _ LIM
n2
(17)
Vi § VC _ LIM Vo Vi ·
u¨ u u Ts ¸ ,
n 2 u Vi Vo © R S 2L n 2 u Vi Vo ¹
1-23
situations. For example, reducing the maximum
transformer leakage energy at the maximum input
!
"
#
"$ %
voltage results in a lower MOSFET peak-drain
Topic 1
Slope Compensation
(Clock Ramp)
VC
(T – Tdis) m0
m0 x s K ff × Vi
2
R S × IA
RS × m 2
RS × m 1
R S × IL_pkmin
D × Ts Tdis
2
D × Ts
Gate Control
1-24
delay. The second one, tRC, is created by the RC
filter used at the current-sense input. It impacts
both the current-feedback signal as well as the
Topic 1
slope-compensation signal (the slope
compensation is connected to the current-sense
node). The third one, td_CT, is the primary FET
turn-on delay from the clock-ramp signal,
assuming that the clock ramp is used for slope
compensation (see Fig. 20). The complete model
is illustrated in Fig. 27.
Because of tdel_off and tRC , the primary FET
is turned off late, resulting in a higher current
limit than expected. Conversely, a higher td_CT
results in a higher contribution from the slope
compensation signal at the same duty cycle, Fig. 26. An example of the influence of slope
which means a lower current limit. The detailed compensation on current limit.
output load current limit equation becomes as
shown below in Equation (19).
Note that these equations are valid as long as due to parasitic turn-off delay (tdel_OFF), which
there is a volt-second balance in the transformer means that the current steps up higher with each
when the output voltage approaches zero volts. If succeeding switch period until there is a volt-
a short-circuit is applied, imbalance may occur seconds balance again.
Slope Compensation
(Clock Ramp) Current Sense
Filter Delay
m 0 tRC VC
m0 x (Ts – Tdis) RS x m 2 K ff x Vi
2
R S x IA
RS x m 1
R S x IL_pkmin
tdel _OFF
td_CT D x Ts
2
Delay from Clock D x Ts Tdis
to Output Turn ON
Gate Control
Fig. 27. Peak CMC law: With all delays, slope compensation, and feedforward effect.
ª VC _ LIM § Vo Vi · V K u Vi º
« ¨ u u TS ¸ i (t del _ OFF t RC ) ff »
Vi « RS © 2L n 2 u Vi Vo ¹ L RS »
(19)
Iout _ LIM u
n 2 u Vi Vo « m0 § Ts Tdis Vo u TS · »
« ¨ t del _ OFF t RC t d _ CT ¸ »
«¬ R S © 2 n 2 u Vi Vo ¹ »¼
1-25
Impact of Transformer Leakage on
Current Limit 25
One impact of leakage inductance in
Topic 1
1-26
From Error
Amplifier
CTL
Topic 1
VI
50 k 4-ms enb CMC
Feedforward Softstart Comparator
50 k VOFS
R109
ARTN 0.75 V
40 μA TPS23754
R21 (pk) Slope-
3.75 k Compensation
CS Ramp
Switch
Matrix
R22
RS
ARTN 0.55 V
With a 48-V input and 5.8-A load, the duty discussion on EMI, please refer to Reference [7].
cycle and the magnetizing current were 1.8% and Line rejection, also known as audio susceptibility,
2.2% higher, respectively, than if there had been will also be discussed.
no effect introduced by the transformer’s leakage
inductance. The observed Dtr was 1.75%. A. Minimizing EMI in Flyback
A similar test with a 24-V input produced an Applications
increase of 3.2% and 9.7%, respectively, which For many designers, the flyback converter
is significant. remains synonymous with a poor EMI signature.
EMI has many causes, although one major element
V. EMI AND LINE REJECTION is the flyback transformer. Its windings carry high-
frequency switched current, making it an H-field
This section provides design tips helpful to
(magnetic field) antenna. Some of its windings
minimize conducted and radiated EMI generation
generate a ringing voltage at frequencies much
for a flyback power supply. For a more general
higher than the switching frequency, making the
1-27
ICM
2 IP IS
N1:N2
Topic 1
+
–
Vi P S Vout
IDM
Clamp VD +
– – +
ICM
FET
2 Output to
Chassis CM
transformer an E-field (electric field) antenna as somewhat less than the calculated physical
well. Interwinding capacitance—specifically capacitance because the voltage across the
primary-to-secondary parasitic capacitance—can windings is not uniform. The voltage gradient
make the transformer a common-mode-conduction effect must always be considered. The average of
emission generator, as shown in Fig. 30. Other the AC voltages on facing portions of the capacitor
notable sources of EMI are MOSFET drain printed “plates” determines the stored charge and hence
circuit board (PCB) traces, catch diodes (in series the effective capacity (see Figs. 30 and 31).
with secondary windings), PCB trace loops, and An electrostatic shield referenced to the same
general PCB layout. ground potential as the primary MOSFET can
Transformer interwinding capacitance is neutralize this common-mode capacitance, forcing
influenced by how close two windings are to each any common-mode current to return to the primary
other. The effective capacitance is usually circuit through a local path.
+ Vi
Other Secondary
y
Secondary A
Secondary B
Primary A
Primary B
Primary C
–
FET
Vout
VD +
1-28
Topic 1
Fig. 32. Fringing flux in center gap of
flyback transformer.
Here is a list of standard techniques that help filters. Minimize the loop area of fast dI/dt
minimize EMI when using a flyback topology: current paths. Use a torroidal-core inductor for
v The transformer should be center-gapped output filters; and avoid rod inductors,
because the fringing fields from the exposed air which generate an H-field because of their
gap become a strong source of EMI. As explained open-core shape.
previously, this means additional loss related to v Pay attention to the reverse-recovery charac-
fringing-flux-induced currents in the winding teristic of catch diodes, which can be source of
turns closest to the center gap (see Fig. 32). H-field emissions. Forward recovery, if too slow,
v If the primary winding is on multiple layers, it will delay the transition time and increase the
should be wound starting at the winding’s end— E-field emission. Schottky diodes, although they
connected to MOSFET’s drain on the printed don’t have reverse-recovery issues, can introduce
circuit—so that the outer layers shield the a resonance with parasitic inductances because
E-field emanating from the drain voltage of their parasitic parallel capacitance. When
excitation. This can also help reduce the effect necessary, place an RC snubber across the catch
of interwinding capacitance related to the diodes.
voltage-gradient effect (see Fig. 31). v The primary MOSFET turn on (but not the turn
v A flyback converter is a strong source of ripple off) should be slower than the diode’s reverse
current at both its input and output. Use recovery time.
high-frequency, low-impedance capacitors at v The PCB layout should be done carefully to
both the input and output of a flyback transformer, minimize EMI. There are many papers written
combined with other types of capacitors and on the subject, such as Reference [7].
1-29
B. Optimizing Line Rejection for a inherent (KFF_in) feedforward, because when Vi
Flyback Converter increases, so does the rise rate of the magnetizing
The line rejection of a power supply, or audio current. The peak current threshold is reached
Topic 1
susceptibility, is the ability to reject noise applied earlier, which results in a reduced duty cycle.
to the voltage input. On the other hand, the Kvi2 block shows that,
A flyback converter operating in CMC when excluding the effect of the current loop,
inherently provides some (although imperfect) there is a natural direct impact from Vi to Vo. It is a
line rejection, however, accurately predicting the nonlinear relationship.
line rejection of a flyback converter is not straight- Using the same Kff external feedforward
forward; complex mathematical or simulation (introduced in the current-limit section) can help
models are required. Also, line rejection is highly improve line rejection. It cannot provide a perfect
dependent on parasitics; prediction accuracy cancellation in all operating conditions, however,
directly depends on accounting for the influence because of the nonlinear nature of noise
of each parasitic. For these reasons, lab tests are susceptibility in a flyback converter.
usually necessary in order to validate predictions. Still, the Kff feedforward constitutes a very
Fig. 33 on the next page shows a simplified flyback simple way, by using a resistor, to achieve very
schematic, with a control-loop block diagram. good line rejection for a specific input-voltage
In the block diagram of Fig. 33, the Kvi1 block range, sometimes improving the rejection by more
shows the influence of input-voltage variations on than 20 db and often removing the need for a
the small-signal changes of the magnetizing second-stage (and inefficient) linear regulator.
current. The following simple equation, applicable As shown in the KFF_in block (proportional to
during the ON time, can help clarify: a × D × Ts – tdelays), the line-rejection performance
of the flyback converter is dependent on turn-off
D u Ts
'I L Vi u . (20) delays, tdelays being in fact tdel_OFF + tRC discussed
L previously in the current-limit section.
The gain from a variation in Vi to IL is Fig. 34 illustrates the effects of feedforward
proportional to D. With peak CMC, there is and turn-off time delays in the TPS23754
application circuit.
–20 –20
–30
–30
–40
Line Rejection (dB)
–40
–50
tdel-off = 23 ns
–50 No Feedforward (FF)
–60 t del-off = 75 ns
–70
120-k FF Resistor –80
–80 –90
1 10 40 1 10 40
Frequency (kHz) Frequency (kHz)
1-30
+Vi
Io Vos Vo
FeedForward 1:n2
K ff Rff
Topic 1
Clamp
Slope Compensation
Clock Ramp
+ VC
C Rs
PWM
Vout
–
Galvanic
Isolation +
Error Amplifier
Vref
K EACL
i
in K EMI
Line Noise Injection
External Inherent
Feedforward Feedforward
K vi2
KFF_in K vi1 D × (1 – D)
K ff
(a × D × Ts – tdelays) =D
+
Kp
+
– –
d
i
(RHPZ)
+ Power
VC K1
Stage K3
– iL
io
GIOL(S)
KLCS
Ri ni He(S)
os
–
KLC
+ o
K EACL Vref Output Capacitor
+ Output Filter
(Compensation + Feedback)
Fig. 33. Peak CMC flyback simplified schematic and block diagram.
1-31
+Vi
Diode or
Synchronous
N1:N2 Rectifier Vo
Topic 1
–
R clamp V
+ clamp
IP
Vdrain
Clamp-Diode
Forward Recovery Leakage-Inductance
Demagnetization
Vi + Vclamp Vo
Vi +
n
RS Vdrain
Primary
MOSFET
Vclamp
Clamp-Capacitor
Voltage
Fig. 35. Primary MOSFET drain voltage while using RCD clamp circuit.
VI. SNUBBERS AND CLAMP CIRCUITS conditions. Also important is the type of diode,
since a slow forward recovery will affect the
Leakage energy in the flyback transformer
maximum drain voltage at turn off. Of course, the
requires the use of special clamp and/or snubber
power dissipation capability of the resistor needs
circuits in order to help protect the power switches
to be adequate for the application.
and diodes against voltage breakdown failures.
Knowing the leakage inductance, the resistance
There are many configurations for these
value can be estimated as follows, assuming there
circuits. The RCD clamp is a common approach
are no stray capacitances to charge and that all
for protecting the primary circuit. When efficiency
of the leakage energy is conducted into the
is a concern, the nondissipative clamp circuit
snubber capacitor:
offers several good trade-offs. RC snubbers are the
typical solutions for secondary protection. § V ·
2 u ¨ Vclamp o ¸ u Vclamp
© n ¹
A. RCD Clamp in Primary Circuit R clamp 2
, (21)
Freq u LleakP u I pkP
The RCD clamp works by creating a low-
impedance voltage source connected to the input where LleakP is the total leakage inductance when
voltage. The resistor, Rclamp, dissipates power moved to the primary side of transformer and IpkP
linked to the leakage energy, while the clamp is the primary current at the moment turn off
capacitor ensures low voltage ripple (see Fig. 35). occurs. This circuit also needs to be tested in order
The clamp-capacitor voltage, which is constant to verify the potential impact of other parasitics, as
during a switching cycle (with a large enough well as the contribution from the parameters
capacitance value), is maximum at full load and ignored in Equation (21), including diode forward
with minimum input voltage, which is the case voltage and recovery characteristics. Also, as
where leakage energy is at a maximum. mentioned earlier, the primary clamp-circuit
It is important to select the resistance value to design must be based on trade-offs between
guarantee acceptable drain voltage in the worst efficiency, peak drain voltage, output current limit,
case, which includes long-duration overload and cross-regulation.
1-32
+Vi +Vi +Vi
Vo Vo Vo
Topic 1
(5 V ) (5 V ) (5 V )
W1 W2 W1 W2 W1 W2
Vclamp Vclamp Vclamp
– + – + – +
a. Primary MOSFET turn off: b. Primary MOSFET turn off: If c. Primary MOSFET turn on.
Initial recharge of clamp Vclamp is too high, there is partial
capacitor. discharge before reaching final
voltage.
Fig. 36. Nondissipative clamp circuit.
1-33
MOSFET is turned back on, the clamp capacitor is Vo
+Vi (5 V )
then discharged, using forward coupling between
W4 and W1. This discharge is performed with
Topic 1
C. Voltage Stress at Secondary Windings, cross-conduction exists with the primary MOSFET
Snubbers during the commutation, there is then a direct
The semiconductors located on the secondary transformer coupling. This creates strong leakage
side of flyback transformers also are subject to energy in the secondary winding and increases the
voltage transients during commutations. In some voltage stress on the synchronous rectifier.
cases, protection circuits such as RC snubbers can Second, at full load, the dead time between
be useful (see Fig. 37). both MOSFETs during commutation will result in
When using a synchronous rectifier, voltage conduction—and thus reverse recovery issues—of
stress across the MOSFET may happen under two the synchronous rectifier’s body diode, leading to
different circumstances when there is commutation transient stress in the synchronous rectifier.
from secondary to primary. First, at no load, the Fig. 38 shows both situations. Notice that at
magnetizing current is changing polarity during a full load, the voltage stress happens well after the
switching cycle, reaching a peak negative value sync rectifier was turned off but exactly when the
until the synchronous rectifier is turned off, primary MOSFET is turned on, thus confirming
resulting in leakage energy. Also, if excessive reverse recovery. At no load, the effect of the
! "# !
1-34
negative magnetizing current results in leakage VIII. REFERENCES
energy at the time the synchronous rectifier is
turned off. For that particular case, there is no [1] Dan Mitchell and Bob Mammano, “Designing
Stable Control Loops,” TI Literature No.
Topic 1
overlapping of Vgs(Sync) and Vgs(FET), which
limit the voltage stress at no load. SLUP173.
There is an optimum value for resistance and [2] Lloyd Dixon, “Transformer and Inductor
capacitance beyond which the voltage stress Design for Optimum Circuit Performance,”
cannot be reduced further. It is important to TI Literature No. SLUP205.
optimize the snubber by testing, using the final [3] Dragan Maksimovic and Robert Erickson,
transformer and MOSFETs. Modeling of Cross-Regulation in Multiple-
Snubber turn-off loss can be estimated with Output Flyback Converters, University
this equation, excluding parasitic drain-to-source of Colorado.
capacitance: [4] Lloyd H. Dixon, Jr., “Eddy Current Losses in
ªC u V n u V 2 º Transformer Windings and Circuit Wiring,”
« sn o i
» TI Literature No. SLUP197.
Psn « 1 2 » u Freq, (22)
[5] Jean-Pierre Vandelac and Phoivos D. Ziogas,
u L u I
«¬ 2 leakS pkS »¼ “A Novel Approach for Minimizing High-
Frequency Transformer Copper Losses,”
where Csn is the snubber capacitance, IpkS is the
IEEE PESC, July 1988.
peak negative secondary current, and LleakS is the
secondary-to-primary leakage inductance when [6] Ray Ridley, “Proximity Loss in Magnetics
moved to the secondary side. It is important to test Windings,” Switching Power, Vol. 4, No. 4,
and look for voltage overshoot across 2003.
the output diodes to ensure that their voltage rating [7] Bob Mammano and Bruce Carsten,
is adequate. “Understanding and Optimize Electro-
Other types of snubbers could also be magnetic Compatibility in Switchmode
considered. A saturable core in series with the Power Supplies,” TI Literature No.
synchronous rectifier at secondary winding can SLUP202.
give good results, in addition to providing some [8] R. Prieto, J.A. Cobos, O. Garcia, R. Asensi,
immunity against excessive reverse recovery. The and J. Uceda, “Optimizing the Winding
behavior of saturable cores is not covered in this Strategy of the Transformer in a Flyback
topic. Converter,” IEEE, June 1996.
[9] Lloyd Dixon, “Magnetic Core Character-
VII. CONCLUSIONS istics,” TI Literature No. SLUP124.
Many design factors and parasitic elements [10] Christophe P. Basso, Switch-Mode
can strongly influence a flyback converter’s Power Supply SPICE Cookbook, 2001,
behavior, particularly with respect to the behavior McGraw-Hill Professional.
under overload or short-circuit conditions. The [11] Keith Billings, Switchmode Power Supply
flyback transformer is a major component of the Handbook, 1999. McGraw-Hill Professional.
converter and needs to be carefully designed and [12] Ray Ridley, “Snubber Design,” Switching
tested for good cross-regulation, maximum Power, Part XII, 2005.
efficiency, and low EMI. [13] A. Reatti, “Winding Losses Optimization in
The benefits of adding feedforward control do a Flyback Converter Transformer,” Power
offer improved line rejection, as well as allowing Conversion, June 1993.
the maximum power output to be held constant
over a wider input voltage range. This reduces the [14] Brian Lees, “Worst Case Flyback Current
cost of components that would otherwise be Levels and How to Deal with Them,” IBM,
required to handle the excessive power or voltage HFPC Proceedings, Sept 1997.
stress at high-input voltages.
1-35
[15] D.M. Mitchell, Switching Regulator Design [17] Bruce Carsten, “The low Leakage Inductance
& Analysis, distributed by E/J Bloom of Planar Transformers; Fact or Myth?,”
Associates, 2000. IEEE, 2001.
Topic 1
[16] Bruce Carsten, Magnetics Design for High- [18] Bruce Carsten, “Cross-Regulation Effects in
Frequency Applications, distributed by E/J Multiple ‘Batch Regulated’ Outputs,” HFPC,
Bloom Associates, 2000. 1993 Proceedings.
Apower-supply’s current-limiting characteristic configuration, the voltage (VC) cannot exceed the
determines the maximum power available at its maximum value set by the zener diode (VC_LIM),
output, beyond which the output voltage falls out which defines the peak current limit. The
of regulation. It is also used to predict the output feedforward resistor (Rff) provides a constant
current in overload situations like a short-circuit, power limit.
in which case the current may be significant. It is assumed for this analysis that the converter
Appendix A presents an in-depth mathematical operates with peak CMC in CCM. Its simplified
analysis for predicting the current-limiting CMC law is illustrated in Fig. A-2.
behavior of a flyback power supply.
Fig. A-1 illustrates a basic current-feedback I. Impact of Feedforward
circuitry for a flyback power supply using slope Combining the feedforward technique with
compensation (through R sc), with a single peak CMC allows the maximum power output
comparator used for both CMC and current to be maintained fairly constant over a wide
limiting. The RC filter is used to eliminate nuisance input-voltage range.
noise from the current feedback signal. In such a
+Vi
Io
1:n2 Vo
Feedforward Rff
Clamp I out
Slope Comp
Clock Ramp
I_SENSE R
–
PWM +
C Rs
VC
COMP
(From Error
Amp) VC_LIM
1-36
!
"
Topic 1
Fig. A-2. Peak CMC law: No parasitic or filter delays, no slope compensation, and no feedforward.
Fig. A-3 shows the impact of the feedforward becomes as shown below in Equation (A-1), where
resistor on the current limit. The feedforward Kff is the external feedforward gain. Referring to
contribution is subtracted from the error amplifier’s Fig. A-1, Kff can be calculated as:
output Vc so that it becomes easier to define the
R sc u R R S
duty-cycle equation. This representation is
functionally equivalent to adding the feedforward R sc R R S
K ff
to the current feedback. R sc u R R S (A-2)
The equation of the output load-current limit R ff
R sc R R S
R sc u R R S
.
R sc u R R S R ff u R sc R R S
Fig. A-3. Peak CMC law: No parasitic or filter delays, no slope compensation, but with feedforward.
I A _ LIM u 1 D Vi § VC _ LIM Vo Vi K u Vi ·
Iout _ LIM u¨ u u Ts ff ¸ (A-1)
n2 n 2 u Vi Vo © R S 2L n 2 u Vi Vo RS ¹
1-37
II. Adding Slope Compensation Fig. A-4. Also, m1 is defined as:
Slope compensation is used to avoid sub- 'I L V
harmonic oscillation when the operating duty cycle m1 | i. (A-4)
D u Ts L
Topic 1
Slope Compensation
(Clock Ramp)
VC
(T – Tdis) m0
m0 x s K ff × Vi
2
R S × IA
RS × m 2
RS × m 1
R S × IL_pkmin
D × Ts Tdis
2
D × Ts
Gate Control
Fig. A-4. Peak CMC law: No parasitic or filter delays, but with slope compensation and feedforward.
ª § D u Ts · º § T Tdis · (A-3)
R S u « I A m1 u ¨ ¸» Vc K ff u Vi mo u ¨ s D u Ts ¸ ,
¬ © 2 ¹¼ © 2 ¹
ª VC _ LIM Vo Vi K u Vi º
« u u Ts ff »
I A _ LIM u 1 D Vi « RS 2L n 2 u Vi Vo RS »
Iout _ LIM u (A-6)
n2 n 2 u Vi Vo « mo § Ts Tdis Vo u Ts · »
« u¨ ¸ »
¬« R S © 2 n 2 u Vi Vo ¹ ¼»
1-38
III. Including Delays the time delay td_CT from the slope compensation
For a more accurate prediction, time delays ramp to the control MOSFET turn on, the CMC
including parasitics must be included in the becomes as shown in Fig. A-6 on the next page.
Topic 1
analysis. The effect of parasitic turn-off delay is The detailed equation for CMC or current limit
illustrated in Fig. A-5 . becomes as shown below in Equation (A-9). The
As shown, the turn off of the control MOSFET detailed output load-current limit equation
is delayed by a time delay tdel_OFF . Note that Vc is becomes as shown in Equation (A-10). Note that
lower than in previous figure in order to maintain these equations are valid as long as there is a
regulation, assuming the same load current. volt-seconds balance at the transformer when the
The equation for CMC or current limit is output voltage approaches zero volts. If a
shown below in Equation (A-7). The output load- short-circuit is applied, imbalance may occur due
current limit becomes as shown in Equation (A-8). to parasitic turn-off delay.
If then we add the current filter time delay tRC and
Slope Compensation
(Clock Ramp)
VC
m0
m0 ×(Ts – Tdis) RS × m 2 K ff × Vi
2
tdel _OFF RS × m 1
R S × IL_pkmin
D × Ts
2
D × Ts Tdis
Gate Control
ª § D u Ts ·º § T Tdis ·
R S u « I A m1 u ¨ t del _ OFF ¸ » VC K ff u Vi mo u ¨ s D u Ts t del _ OFF ¸ . (A-7)
¬ © 2 ¹¼ © 2 ¹
ª VC _ LIM Vo Vi V K u Vi º
« u u Ts i u t del _ OFF ff »
Vi « RS 2L n 2 u Vi Vo L RS »
Iout _ LIM u (A-8)
n 2 u Vi Vo « mo § Ts Tdis Vo u Ts · »
« u¨ t del _ OFF ¸ »
«¬ R S © 2 n 2 u Vi Vo ¹ »¼
ª § D u Ts ·º §T T ·
R S u « IA m1 u ¨ t RC t del _ OFF ¸ » Vc K ff u Vi mo u ¨ s dis t d _ CT D u Ts t del _ OFF t RC ¸ . (A-9)
¬ © 2 ¹¼ © 2 ¹
ª VC _ LIM Vo Vi V K u Vi º
« u u Ts i u t del _ OFF t RC ) ff »
Vi « RS 2L n 2 u Vi Vo L RS »
Iout _ LIM u (A-10)
n 2 u Vi Vo « mo § Ts Tdis Vo Ts · »
« u¨ t del _ OFF t RC t d _ CT ¸ »
¬« R S © 2 n 2 u Vi Vo ¹ ¼»
1-39
Slope Compensation
(Clock Ramp) Current Sense
Filter Delay
VC
Topic 1
m 0 tRC
m0 x (Ts – Tdis) RS x m 2 K ff x Vi
2
R S x IA
RS x m 1
R S x IL_pkmin
tdel _OFF
td_CT D x Ts
2
Delay from Clock D x Ts Tdis
to Output Turn ON
Gate Control
Fig. A-6. Peak CMC law: With all delays and feedforward effect.
1-40
peak magnetizing current is estimated below by with each succeeding switch period until there is
Equation (A-16) volt-seconds balance again. The volt-seconds
The effects of leakage inductance must be balance equation is as shown below in Equation
Topic 1
considered when designing the flyback transformer (A-18).
in order to avoid risks of saturation. Adding the The transformer’s leakage inductance helps
influence of leakage inductance, the output load maintain that balance as indicated by the last
current-limit equation then becomes as shown component of Equation (A-18). There is rarely a
below in Equation (A-17). complete short-circuit situation given the effect
The current-limit equations shown previously of resistive series elements (including parasitics)
are valid as long as there is a volt-seconds balance and the catch diode’s forward voltage drop.
at the transformer when the output voltage They should be included when defining the
approaches zero. If a short circuit is applied, output voltage.
imbalance may occur due to parasitic turn-off
delay, which means that the current steps up higher
Iout V
I pk _ new | u n 2 i u Ts u D new (A-16)
1 Dnew 0.5 u D tr 2L
§ ·
¨ V ¸
¨ i D ' 0.5 u D tr ¸ ª V
¨ V Vo ¸ C _ LIM Vi u D new u Ts Vi K ff u Vi º
¨ i ¸ « u t del _ OFF t RC ) »
© n2 ¹ « RS 2L L RS » (A-17)
Iout _ LIM # u
n2 « m §T T · »
« o u ¨ s dis Dnew u Ts t del _ OFF t RC t d _ CT ¸ »
«¬ R S © 2 ¹ »¼
Vo _ short
u Ts t del _ OFF D tr u Ts ) Vi u t del _ OFF Vclamp u D tr u Ts . (A-18)
n2
1-41