DESIGNWARE IP DATASHEET

Duet Embedded Memories and

Logic Libraries for TSMC 28HP

Highlights
• Silicon-proven, shipping in billions of chips
• Broad portfolio of high-speed, high-density
and low-power memory compilers and
logic libraries
• Complete standard cell library supporting
multiple architectures, VTs, gate
biases, PVTs
• Integrated test and repair solution
delivers higher test quality and yield, while
lowering overall chip areas
Overview
Synopsys provides designers with a broad portfolio of high-speed, high-density
and low-power memory compilers and logic libraries. Optimized for TSMC’s
28-nm high-performance (HP) process technology, the DesignWare® Duet
Package of Embedded Memories and Logic Libraries includes standard
cells, SRAMs, register files, ROMs, High Performance Kits (HPKs) and Power
Optimization Kits (POKs)­—all the elements needed to implement a complete
SoC. Options for overdrive/ low voltage PVTs, high density SRAMs, multi-
channel cells, and memory built-in self test (BIST) and repair are also available,
enabling designers to achieve the best combination of performance, power and
area in their designs. DesignWare Embedded Memories and Logic Libraries are
extensively proven in silicon with billions of units shipping in volume production,
lowering project risk and speeding time-to-market.

High-density/high-
Dual/quad core CPU RAM speed logic libraries
High-speed SRAMs
• Single-port SRAM • Multi-VT
• Dual-port SRAM Cache Cache • Multi-channel
• Single-port register Test & repair SoC • Power optimization kit
file cache Logic • ECO kit
GPU GPU • Datapath library
RAM Reg file
Test & repair Test & repair High-density via ROM
Test & repair Test & repair ROM
High-density SRAMs • High-density single &
• Single-port SRAM Reg file Test
dual-port register files
• Dual-port SRAM Reg file • Ultra high-density
• High-capacity RAM dual-port register file
16Mb SRAM Test & repair
DSP
Reg file
Integrated embedded
Test & repair memory test and repair

Figure 1: The DesignWare Duet Packages with STAR Memory System offer optimized
logic libraries and embedded memories with built-in self-test (BIST) and repair capability

synopsys.com/designware
 High-Speed High-Speed Ultra High-
High-Density High-Density UHD 2P
SP/DP 1P RF ROM UHD 16M Density SP
DP SRAM 2PRF SRAM
SRAM cache SRAM
Total bits 256-1280K 64-128K 256-1280K 64-128K 256-1280K 256-1280K 128K-16M 256-2560K
Word range 32-16K 8-2K 32-16K 8-1K 64-64K 32-16K 4-32K 32-32K
I/O range 8-320 8-256 8-320 8-256 4-160 8-320 32-320 8-320
Column Mux 4,8,16 2,4 4,8,16 1,2,4 8,16,32,64 4,8,16 4,8,16 4,8,16
Bank 1,2,4,8 1,2 1,2,4,8 1,2 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8
Redundancy Column Column Column Column Column Column Column

Table 1: DesignWare Memory Compiler family configuration parameter

The DesignWare Memory Compiler and Logic Library IP portfolio for the TSMC 28HP process provides advanced, built-in power
management features that enable system-on-chip (SoC) designers to explore tradeoffs between performance, area and power
to generate optimal memory configurations. This dashboard control capability is critical at 28-nm where design and process
complexities require sophisticated management of the various tradeoffs to effectively meet stringent end-product requirements and
increasingly narrow time-to-market windows. In addition, the integrated STAR Memory System enables high-speed test and repair of
embedded memories, delivering higher test quality and yield. The DesignWare Memory Compiler and Logic Library IP solutions have
been silicon-proven with billions of units shipping in volume production, enabling designers to lower risk and speed time-to-market.

These high-density embedded SRAMs are optimized to generate memories with the absolute minimum area and power, enabling
designers to achieve aggressive critical path requirements. These compilers minimize both static and dynamic power consumption,
while the high-speed embedded memory compilers provide a much higher level of performance. The logic libraries include yield
optimized standard cells for a wide variety of design applications at 28-nm with multiple threshold process variants and multiple
channel lengths. The DesignWare Logic Libraries offer two separate architectures of 1,200 each to optimize circuits for high density
or high speed. The included POKs provide designers with the most advanced power management capabilities.

Memory Compiler Features

The configurable memory compilers deliver high speed and high density while consuming minimal power through the use of:

• Source biasing
• Power gating
• Multiple threshold voltages

These SRAMs include high-speed (HS), high-density (HD) and ultra-high-density (UHD) architectures.

100%

90%

80%

70%

60%
Normal mode
50%
Light sleep
40% Deep sleep
Shut down
30%

20%

10%

0%
Large instance Small instance

Figure 2: DesignWare Memory Compiler standby power savings with advanced power management features

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 Architecture 28 nm HD 28 nm HS
*Grid (X x Y) 135 nm x 100 nm 135 nm x 100 nm
Height 9.5 grids (95 nm) 12.5 grids (125 nm)
*M2/M1 VSS Rail 130 nm/70 nm 130 nm/70 nm
*M2 VDD Rail 50 nm 130 nm
*Optional M2 VDDR Rail 50 nm 50 nm
**Raw Gate Density 3490 K gates/mm2 2652 K gates/mm2

* Drawn ** Post-shrink on silicon, 60% NAND2, 40% DFF

HD HS
VDDR VDDR
(optional) (optional)
VDD VDD

VSS

VSS

Table 2: DesignWare Logic Library high-speed and high-density architecture comparison

Advanced Power Management

The DesignWare Memory Compilers offer multiple levels of power management features including Light Sleep, Deep Sleep and Shut
Down to enable array biasing with partial periphery shut down, full periphery shut down with data retention and a complete shut
down without data retention. The 28HP Memory Compilers support ultra-low voltage operation with characterization at 20% below
nominal voltage, where allowed by the foundry partner. An option for dual rail is also available to support Dynamic Voltage Frequency
Scaling (DVFS) where the periphery can go down to 30% below nominal voltage. Synopsys provides power saving design techniques
to implement these features including:

• Source biasing
• Fine-grained power gating
• Selective use of HVt and long L devices
• Integrated power gating
• Integrated level shifters

DesignWare Logic Library Features

Base Library Architectures
• High-speed (HS or 12.5 tracks) in up to 5 Vts and 3 channel length biases
• High-density (HD or 9.5 tracks) in up to 5 Vts and 3 channel length biases

Power Optimization Kits (POKs)

• Power-gating cells for sleep and shut down modes
• Up, down, up/down level-shifters with and without isolation
• Dedicated isolation cells
• Retention flip-flops for standby/sleep mode with always-on cells

Engineering Change Order (ECO) Library Kits

• Fast metal-only design modifications

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Logic Library Benefits
Maximum Performance
• Fastest library on the market for GHz processors, high-speed communications
• Achieve timing closure without sacrificing area or power
• Advanced flow enablement kit for high-speed datapath structures

Maximum Density
• NXT horizontal metal 2 architectures (9.5 and 12.5 track)
• Hand-crafted for highest routing density and utilization
• Deep cell set of functions and drive strengths in base library

Minimum Power
• Multi-channel libraries with up to 5 VTs and 3 gate length options for static power reduction
• POK with over 200 cells
• Support for low-power EDA flows with CPF and UPF

Highest Yield
• Design for Manufacturing (DFM) aware
• Redundant contacts
• Electromigration-compliant at highest speeds

Comprehensive Solution
• Electrically, physically and EDA-view aligned with memory products
• Multi-VDD characterization with low voltage and overdrive PVTs

Figure 3: HS flip flop

Summary
The DesignWare Memory Compiler and Logic Library portfolio for TSMC 28HP has been silicon-proven to address the increasingly
complex design requirements that are placed on physical IP at advanced process nodes. These power-optimized embedded SRAMs
for advanced processes minimize both static and dynamic power consumption. The logic library contains a large base cell library in
up to five VTs and three channel length biases with multiple cell variants and drive strengths to quickly achieve timing closure with
minimum area and power.

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About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP
portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP,
embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs,
Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP subsystems. Synopsys’
extensive investment in IP quality, comprehensive technical support and robust IP development methodology enable
designers to reduce integration risk and accelerate time-to-market.

For more information on DesignWare IP, visit synopsys.com/designware .

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available at synopsys.com/copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.
01/29/19.CS12995_28HP_memory_logic_DS.