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Generation in NanoTime
Application Note
Version A, September 2008
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Contents
Clock Pulse/Shaper Generation Support .............................................................. 1
How it Functions ................................................................................................ 2
Topology Reporting of Clock Shapers/Pulsers .................................................. 2
Attributes......................................................................................................... 3
Support of Feedback-based Clock Generators.................................................. 3
Debugging Clock Gaters .................................................................................... 4
Clock Gater Recognition ................................................................................. 4
Feedback on Clock Gater Circuits .................................................................. 4
General Clock attributes ................................................................................. 4
General Clock Arrivals ....................................................................................... 5
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Clock Pulse/Shaper Generation Support
NanoTime can support generic NAND/NOR pulse/shaper generation through two reconvergent
clock paths:
Page 1
How it Functions
Currently, clock/pulser generation functions as follows:
Only CMOS gates with 2 reconvergent paths are currently supported.
Automatically handles logic checking
Automatically handles the creation of timing checks
Automatically handles propagation of correct clock path edges based on the
length of reconvergent clock paths
Both odd (pulse generator) circuits and even (clock shaper) circuits are supported
automatically.
Requires the following variable be set to true before :
Page 2
Attributes
There is also a topology attribute that is accessible to customers to
describe what the clock gate type is as follows:
Page 3
The complete set of commands:
(b) Disable logic checking on the feedback loop and the inverter reconvergent path
(c) Allow inverting loop path propagation so the signal can propagate through the
feedback path back onto the clock nets for the closing clock pulse edge.
Page 4
All nets that gets a clock propagated to them get a net attribute:
All nets that are manually forced to a clock get a net attribute:
All nets that are manually stopped for clock prop gate a net attribute:
Pin attributes
All gate pins of nets that have clock propagation get a pin attribute:
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