Case Study of Complex Full Chip Low Power

Implementation in 16nm node

Aman Jain
Jay Shah
Pritesh Pawaskar
Seagate Technology
Mahesh Narayan
Synopsys

July 12-13, 2017

SNUG India

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 Agenda

Design Power Intent Overview

Low Power Implementation Challenges
- Power Switch implementation
- Bottom Up Hierarchical Flow
- DFT Challenges
Configuring low power modes for various IPs
Conclusions
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 Power Intent of Design

• Design has six power domains

– PD1 as Always-ON Power Domain
– PD2 as Mostly-ON Power Domain
– TOP as Switchable Domain-1
– PD4 as Switchable Domain-2
– PD5 as Switchable Domain-3
– PD6 as Switchable Domain-4

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 Low Power Implementation Challenges

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 Formal Verification failures

• Synthesis & DFT netlists were clean in VCLP

• Formality was passing on synthesis vs DFT
netlist without UPF
• Formality was failing on synthesis vs DFT
netlist with UPF on RM1 pins of memories

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 Resolution for Formal Verification failures

• Changed the UPF policy for RM1 pin of memories to change clamp value from
0 to 1

set_isolation iso_PD2toPD1_hi -domain AON_PD -isolation_power_net VDD_PD1 -

isolation_ground_net VSS -elements {AON_PD/RM1_test} -name_prefix PD2PD1 –
clamp_value 1

• Did functional ECO of swapping isolation cells from clamp value 0 to 1 in

existing netlists

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 Main Rail Violation

• VDD_PD1 -> Always On Rail, VDD_PD2 -> Switchable Supply

• DC version 2015.06 tool does not check for “Main Rail Violation” so it inserts
single rail isolation cell in switchable domain with VDD connected to VDD_PD1.
• in DC version 2016.03 onwards the tool properly checks for “Main Rail
Violation” and inserts dual rail isolation cell in core switchable domain

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 Need of creating Voltage Areas

• In the case where dual rail isolation cells are inserted ICC2 can place those
cells anywhere as SCMR VDD is connected to VDD_PD2 (switchable supply).
• Not honoring “Main Rail Rule” creates placement restriction in ICC2
• Need to create voltage areas/bounds in ICC2 which is cumbersome.

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 Dual Rail Isolation cells

• Issue with Dual Rail isolation cell library.

• 2 PG pins VDD (primary_power) -> switchable & VDDR (backup_power) ->
always on
• Input A pin of dual rail isolation cell was incorrectly mapped to VDDR in library

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 Dual Rail Isolation cells….

• DC & ICC2 was adding AON buffers on A pin of dual rail isolation cells
• So large number of AON buffers got inserted in netlist which were actually not
required.
• The library was manually hacked to map the A pin to VDD and not VDDR

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 Formal Verification failures at chip top

• During timing ECOs on test signal

JTAGA of IO buffer the polarity got
inverted.

• It was not caught in Chip Flat Formality

run with UPF all runs with UPF had
following constraint

• The mismatch in JTAGA at IO buffer

would not be propagated at PAD output because JTAGSEL is 0.
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 Formal Verification failures at chip top

• Even Chip Hier without UPF came out

clean
• The block ETMs were constraining
JTAGSEL to 1’b0

• .

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 Formal Verification failures at chip top

• Only Chip Top Flat without UPF was able

to report failures because of polarity change

• Lesson learned is to not make any

assumptions and do all exhaustive Formality
runs Hier/Flat with/without UPF to not miss
any corner cases as highlighted in this
example

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 Challenges in Hierarchical Implementation

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 Unconnected pins in ETM models

• Starting from PT 2016.03 version ETMs would not

contain the PG pin information

• The input pins bus_bit[18] & bus_bit[17] are

unconnected do not have related power pin

• The input pins bus_bit[16] is connected, so it has

related power pin information

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 Reason for MV-013 errors

• ICC2 mapping unconnected pins of ETM to primary AON supply (VDD_PD1).

• So switchable supply (VDD_PD2) is driving AON supply (VDD_PD1) which

becomes an issue

• Got MV-013 errors in ICC2

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 Resolution for MV-013 errors

• The following command in ICC2 resolves the issue

• We need to know the list of unconnected ports at ETM in design – so it is an

iterative process to code the UPF

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 ETM models with power switches

• VDD_PD1 -> Always On Rail,

VDD_PD2 -> Switchable Supply

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 UPF-119 errors in DC

• While doing synthesis at top level using block level ETMs with power switches
got UPF-119 errors

• Though internal pin VDD_PD2 was present it was missing the required attribute
of output of power switch

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 Resolution for UPF-119 errors

• The ETM model was hacked to add missing attributes shown below

• STAR filed with Synopsys for PT enhancement so that above hacking is not
required in future
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 DFT challenges in low power implementation

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 Design Challenges

• The channels between some of the switchable and always-on domains were
very narrow and the most congested regions in physical design

• Test logic to be added in such a manner to ensure minimum interaction

between always-on and switchable power domains

• Using traditional scan insertion approach there were many scan signals
crossing power domains causing large number of low power cells (ISO+LS)
getting used

• PD implementation became challenging since some of the channels were very

narrow
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 Design Challenges……. (contd)

Large Number of Low

Power Cells get
inserted making
challenging for PD
implementation

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 Optimized Solution
• Optimized UPF aware strategy was used by placing separate scan compressor
within big power domains.

• It reducing the scan signals crossing power domains and the number of low
power cells (ISO+LS) were significantly reduced

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 Configuring Low Power Modes of IPs

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 Memory low power mode configuration

• Two options to configure memories in low power

modes.

• Option-2 was used because it was much

simpler implementation from physical design
perspective.

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 Classification of Memories
Less AON memories (PD2)
Switchable memories (PD3)
AON memories (PD1)

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 Implementation of PD2 memories

• Few AON cells like MUX were required for implementation

• AON power library was only having NAND & NOR gates.

• But DC had used regular MUX with

connect_supply_net to VDD_PD1 in dumped UPF.
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 Solution at RTL level

• RTL was modified to hard code the instantation of AON NAND cells using which
MUX was designed

• In synthesis “set_dont_touch” constraint was set on these AON NAND cells.

• In physical design there was no need of creating many disjoint voltage areas

• Still working with Synopsys to come with better solution and not hard code the
AON cells directly in RTL

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 Conclusion

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 Conclusion

• Using dual rail low power cells having backup rail is always better option than
single rail low power cells

• All the combination of Formality runs with and without UPF should be done in
order to perform exhaustive check

• By making changes in DFT architecture we can considerably lower the total

number of low power cells which gets inserted by tool

• An example to configure Memories in core switchable domain in low power

modes by still connecting the memory in AO (Always ON) rail but using the
internal power switches
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 Thank You

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