Low Power Clock Gates Optimization For Clock Tree Distribution

Teng, Siong Kiong1, Dr Norhayati Soin2

1
Penang Design Center, Intel Microelectronics, Penang, Malaysia
2
Dept. of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia
1
siong.kiong.teng@intel.com 2norhayatisoin@um.edu.my

problem. [5] presented the gated clock planning algorithm

Abstract
Clock gating technique had become one of the major
dynamic power saving approaches in today low power digital
circuit design. In this paper, we present a new physical clock
gates optimization technique using splitting and merging
algorithm that works on both single level and multiple levels
clock gating design. The algorithm is built on top of the
standard EDA flow by running two passes clock tree
synthesis. The first pass is to obtain the clock buffer location
for clock gate swapping and the second pass will build the
clock tree based on the optimum clock gate location. The
merging algorithm will then be used to improve the overall
clock tree power. The results on the industrial design show
the improvement on overall clock tree power using
aforementioned algorithm.
Keywords
Clock gating, low power, clock tree synthesis
1. Introduction
In today advanced VLSI design environment, the VLSI
designers are not only facing the challenges of converging
the timing to meet the performance on the digital circuit but
also on power. On recent years, the low power initiative had
gained the focus with a lot of researchers start paying
attention on low power design optimizations. This has
prompted a shift on the digital design on joined optimization
on both power and performance.
Recent researches on low power VLSI design techniques
had established various innovations such as clock gating,
multi-threshold voltage transistors, multi-supply voltage,
dynamic voltage and frequency scaling, power shut-off and
etc [1,2]. The clock tree synthesis (CTS) is the process of
distribution clock signal from PLL to all the synchronous
components within a design. Clock gating is being used
widely in clock distribution as a method to reduce clock
network power dissipations [7-12]. The clock gating
components are part of the clock tree distribution
components during CTS process.
The clock root gating algorithm that is used to merge the
clock gates with different enables function had been
implemented by [3]. However, in [3] proposal, the initial
clock gates placement is not being optimized where merging
of the clock gates might not able to obtain the optimum clock
gate structure.
In [4], the clock gates are split based on the total number of
fanout of the individual clock gate. This is still not exploring
the clock gating power efficiency in physical domain. [4] also
did not mention the solution of multiple levels clock gating
during clock placement steps. The solution was based on
Capo placer [6] and will have limitation when we try to
optimize the clock tree in the existing design using standard
EDA tool.
1.1 Clock Gate Placement Problem
Clock gating components are being inserted on clock tree
to shut off part of the clock tree when it is idle. There will be
two possible clock gate operations that will affect the clock
tree power consumption. The two possible clock gating
operations, the dynamic and idle operations, which would be
referred to as clock gate ON (CGON) and clock gate OFF
(CGOFF) respectively. The dynamic power operation is
when all clock gates enabled to allow all registers to be
latching actively, while the idle operation is when all clock
gates disabled to achieve gating.
In the ASIC or SoC design, there will be gated and
ungated clocks. Some of the logics that can be shut off will
use gated clocks but some that cannot will use the ungated
clocks. The CGON power will be higher compare to CGOFF.
However, in recent industrial and research on the clock
gating design, the CGON power is always not optimized.
Figure 1 and Figure 2 show the clock tree topology with
clock gates before and after CTS. In Figure 1, the clock gate
CG_A placement is placed very close to the clock root and
clock gate CG_C is place relatively close to the loads. The
clock buffers are used to illustrate the last fanout buffers that
are going to drive the sequential elements. This is
corresponding to the post-CTS last level buffer placements.
Figure 1: Clock Tree Relative Placement before CTS
By using standard EDA tool CTS flow, the clock tree will
be built and yield the clock tree topology shown in Figure 2.
The gated and ungated clock trees are essentially overlapping
each other physically resulting in higher CGON power

978-1-4244-6455-5/10/$26.00 ©2010 IEEE 488 11th Int’l Symposium on Quality Electronic Design
during full operations. We will address this problem using
the clock gates synthesis algorithm during CTS.
Figure 2: Clock Tree Placement after CTS
2. Two Passes Low Power Clock Gate Synthesis
Flow
RTL codes
Logic Synthesis Flow
Placement and Logic Optimization Flow
First Pass Clock Tree Synthesis Flow
Low Power Multiple Level Clock
Gates Splitting Algorithm
Second Pass Clock Tree Synthesis Flow
Low Power Multiple Level Clock
Gates Merging Algorithm
Clock Tree Power
N The multiple level clock gates splitting algorithm can be
o Achieved
Lower Power?
Yes
End
Figure 3: Two Passes Low Power Clock Tree Synthesis
Flow
In this section, we introduce the two passes low power
clock tree synthesis flow as shown Figure 3. This flow is
proven working on the standard industrial design using the
electronic design automation (EDA) tool. The low power
clock gate synthesis algorithm is integrated into the clock tree
synthesis flow. The algorithm is implemented using the TCL
language that can be easily integrated into the EDA tool.
Teng, Low Power Clock Gates Optimization for Clock…
Start from the RTL coding, the normal SoC design flow
will run through logic synthesis to translate the system
verilog or VHDL behavior model into gate level netlist. The
gate level netlist will be optimized for timing and area
constraint to achieve the required design target. After
generating the optimized netlist, the netlist will then be
placed on the floorplan for physical optimization.
Once the design physical placement is completed, the
clock tree synthesis will be run to synthesize the clock tree
network to distribute the clock signal across the floorplan to
achieve low skew, low power clocking design. To obtain the
optimum clock gate design, we implement the two passes
clock tree synthesis flow. During the first pass, the traditional
clock tree synthesis methodology will be used. The clock tree
will be built using the default design constraint and yield the
standard clock tree structure with the clock gates being
placed at their initial location based on pre-CTS database.
We will then apply our split clock gate algorithm to
effectively splitting the clock gates to the nearest location to
their loads. The output of the algorithm will be a TCL format
engineering change order (ECO) script that can be used to
apply on the pre-CTS database. As the low power design
normally will have a lot of aggressive clock gating, there
might be multiple levels of clock gating a long the clock path.
The flow will be able to split each level of the clock gate
accordingly.
The TCL scripts will then be applied into the pre-CTS
database and we will have a new pre-CTS database for the
second iteration of clock tree synthesis. With the newly
created clock gate location, the design is once again running
through the clock tree synthesis flow and optimization to get
the final optimized clock tree design.
3. Multiple Levels Clock Gate Splitting
In this section, the multiple levels clock gate splitting
algorithm will be discussed. We presented the clock gate
splitting flow on post-CTS database to find out the optimum
locations of the clock gate. The newly created clock gates
and their location will be written into an ECO format in TCL.
This ECO TCL file will be applied to the pre-CTS database
for the second pass clock tree synthesis.
described as below.
Input: a digital circuit design.
Output: an ECO changes in TCL format.
I. Clock Tree Tracing Algorithm – For each clock
source, all clock gates are traced for connectivity and
each clock gate level are stored.
II. Clock Gate Reverse Splitting Algorithm – For the
clock source, starting from the last level (n) of the
clock gate
a. For each clock gate
i. Split the clock gate to its last level buffers
locations.
ii. Find the fanout loads of all the last level
buffers.
iii. Assign the fanout loads to the new clock
gate’s hash.
 iv. Find the fanin source of the original clock
gate.
v. Assign the fanin root driver to the new split
clock gate’s hash.
vi. Repeat for next clock gate
b. Repeat for next n-1 level clock gate until level 1
clock gate.
III. Generate the netlist connectivity changes and create
the split clock gate ECO changes.
IV. Done.
The output of the flow is the changes that will be applied
to the pre-CTS database for the second pass CTS flow.
Figure 4 shows the outcome of the design after applying the
ECO changes on the pre-CTS design. Compared to Figure 1,
the clock gate CG_A had been split to 3 copies namely
CG_A_S1, CG_A_S2 and CG_A_S3. For the placement of
the clock gate, it will be using the clock buffer or clock gates
placement shown in Figure 2. The CG_A_S1 will occupy the
placement of CG_C. The clock gates CG_A_S2 and
CG_A_S3 will occupy the Buf_D3 and Buf_D4 placement.
The second level clock gate CG_C will also be split into two
copies. The CG_C_S1 and CG_C_S2 will occupy Buf_D1
and Buf_D2 locations respectively.
Figure 4: Initial Clock Gate Placement after Applying
Multiple Level Split Clock Gate ECO changes.
The Figure 4 design will be used for second pass of CTS
optimizations. The final clock tree topology after CTS is
shown in Figure 5. Compare to Figure 2, the total number of
clock buffers needed to construct the clock tree topology is
less after using the split clock gate algorithm. The total
number of clock buffers and clock gates in Figure 2 are 17
while the total number of clock buffers and clock gates in
Figure 5 is only 14. Beside number of clocks components
saving, the overall wire routing will be reduced also as there
is less overlapping on gated and ungated clocks. The
theoretical analysis shows that our algorithm is able to reduce
the total clock tree power during CGON operation.
Teng, Low Power Clock Gates Optimization for Clock…
Figure 5: Clock Tree Topology after CTS
4. Multiple Levels Clock Gate Merging
From section 3, we proved that the multiple levels clock
gate splitting algorithm is able to reduce the CGON dynamic
power. However, during CGOFF operation, the clock tree is
actually burning more power due to the clock gates now is
sitting at the lower level of the clock tree. The clock tree
buffers from clock sources to the input of the clock gates will
be still toggling and consume power during CGOFF
operation. To solve the aforementioned problem, we used the
clock gates merging and relocating algorithm to merge the
same functional clock gates. After merging the clock gates,
we moved and relocated the clock gate closer to the clock
sources to improve the CGOFF power consumptions.
As oppose to [3] method, our method is built on the
existing clock tree topology. We do not optimize the clock
gates by ORing the enable of different clock gates because
this will induce formal verification failure where we will
need to reflect the changes into RTL to ensure the functional
logic correctness.
The clock gate merging and relocating algorithm can be
illustrated as below.
Input: a post-CTS digital circuit design.
Output: an optimized clock gates digital circuit design.
I. Clock Tree Merging and Relocating Algorithm – For
each clock source, all clock gates are traced for
connectivity and each clock gate level are stored.
II. For the clock source, starting from the last level (n), of
the clock gate,
a. For each clock gate
i. Find the driver of the clock gate.
ii. If clock gates are having same driver, the
clock gates will be merged.
iii. If the clock gate had one driver, relocated the
clock gate to the driver location.
iv. Apply ECO changes to the database.
v. Repeat for next clock gate
b. Repeat for next n-1 level clock gate until level 1.
III. Done
Figure 6 shows the clock tree structural after clock gate
splitting and CTS flow. The clock gates CG_A_S1 and
CG_A_S2 are the clock gates that can be merged to reduce
the total dynamic power during CGOFF operations. The
algorithm will merge both CG_A_S1 and CG_A_S2 to
become CG_A_M12. The CG_A_M12 clock gate will then
go through the relocating algorithm to move upward closer to
the clock source. When the clock gate hit the point of
divergence, it will stop and occupy the final location of the
clock buffer. The outcome of both the clock gate merging
and clock gate relocating algorithm is shown in Figure 7.
Figure 6: Clock Gates Placement after CTS that can be
merged Using Clock Gate Merging Algorithm
Figure 7: Clock Tree Topology after Clock Gate Merging
5. Results
The proposed algorithm had been tested on an industrial
standard VLSI digital design. The experimental is being run
on a design that consists of 1 million instances and 23K
flops. The result is being compared between the conventional
CTS flow and the new low power clock gate synthesis flow.
For each flow, the total clock buffers used and the clock tree
performance like clock skew, clock buffer area and total
clock power are analyzed.
Figure 8 shows the total number of clock buffers and
clock gates used in the design using conventional CTS flow,
clock gate splitting flow and clock gate merging flow. The
result showed that after clock gate splitting flow, total
number of clock gates increased while total number of clock
buffer decreased. The overall clock buffer count is also
decreased. Then we used the same split database and run
through clock gate merging flow. It showed that the total
number of clock gates decreased while the total number of
clock gate increased. The overall clock buffers count still
remained the same compared to split database. The results
Teng, Low Power Clock Gates Optimization for Clock…
clearly showed that the proposed flow is able to reduce the
overall clock buffer count in the design.
Figure 8: Number of Clock Tree Buffer Using Multiple
Levels Clock Gate Splitting and Merging Flow
Figure 9 shows the clock tree performance comparison on
conventional flow, clock gate splitting flow and clock gate
merging flow. The clock tree performance matrix is
measured based on clock skew, total clock buffer area,
CGON dynamic power, CGOFF dynamic power and overall
leakage power.
Figure 9: Clock Tree Performance on Skew, Area and
Power Using Multiple Levels Clock Gate Splitting and
Merging Flow
The graph showed that both clock skew and total buffers
area reduced with the clock gate splitting and merging flow.
A significant dynamic power reduction is observed during
clock gate ON operation. Meanwhile an increase in total
clock dynamic power is noticed for clock gate OFF
operations. The reduction in the clock gate ON operation is
clearly attributed to the avoidance of long overlapping
interconnects routing by the flow. However, the clock gate
OFF operation condition increased the dynamic power is
ascribed to the increase in pre-clock gate buffer stages,
brought around by the split clock gate effect to the lower
level of buffer trees. This problem had been addressed by Computer.-Aided Des Integr. Circ.Syst. June 2001
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7. Summary
In this paper, we present a new design flow for gated clock
tree synthesis that is able to effectively reduce total dynamic
power. We first spilt and duplicate the clock gates to
minimize clock tree overlapping on gated and ungated clock.
Then we create the new clock gates with optimize location on
pre-CTS design and reran the second pass of clock tree
synthesis. After that, we trigger the clock gate re-merging
algorithm to optimize for gated clock idle stage power. The
low power clock gate splitting algorithm is able to effectively
reduce the clock tree dynamic power during full operation
mode and idle mode. The paper also shows that with this
approach, the overall clock tree buffers are able to reduce
with less area. Therefore, the proposed algorithm is proven to
be able to reduce the gated clock tree power.
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[3] Qi Wang & Sumit Roy “Power Minimization by Clock
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[6] http://vlsicad.eecs.umich.edu/BK/PDtools/.
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Teng, Low Power Clock Gates Optimization for Clock…