Engineering Science and Technology, an International Journal 22 (2019) 1077–1086

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Engineering Science and Technology,

an International Journal
journal homepage: www.elsevier.com/locate/jestch

Full Length Article

A wide tuning range VCO design using multi-pass loop complementary

current control with IMOS varactor for low power applications
Vivek Jangra ⇑, Manoj Kumar
University School of Information, Communication and Technology, Guru Gobind Singh Indraprastha University, New Delhi, India

a r t i c l e i n f o a b s t r a c t

Article history: In this work a wide-bandwidth low-power voltage-controlled oscillator (VCO) design is presented using a
Received 9 September 2018 new differential delay cell with complementary current control mechanism and inversion mode MOSFET
Revised 3 February 2019 (IMOS) varactor. The variations in output oscillation frequency of the VCO has been achieved by changing
Accepted 26 February 2019
the capacitance of the delay cell with the usage of IMOS varactor containing two PMOS transistors con-
Available online 8 March 2019
nected in parallel. The proposed three-stage VCO has been designed with 1.8 V power supply in 180 nm
CMOS technology. Capacitance of IMOS varactor has been varied by altering the source/drain voltage
Keywords:
ðV control Þ and back-gate voltage ðV sb Þ of IMOS. The variations in power supply voltage from 1 V to 2.4 V
Complementary current control
Delay cell
provides output frequency from 1.893 GHz to 7.926 GHz with power dissipation of 0.953 mW to
IMOS 24.261 mW with IMOS varactor width of 5 mm. The results have been extended for the IMOS width of
Low power 10 mm, 15 mm and 20 mm. The tuning range of 122% has been achieved with the power supply tuning
Phase noise method. The variations in source/drain voltage of IMOS from 1 V to 2.4 V provides the output frequency
from 6.373 GHz to 5.460 GHz with power dissipation of 9.62 mW. The tuning range of 15.7%, 22.3%, 44%
and 40.6% has been obtained for IMOS with widths of 5 lm, 10 lm, 15 lm and 20 lm with the source/
drain voltage ðV control Þ variations. Further, frequency variation from 5.895 GHz to 6.406 GHz has been
obtained with back-gate voltage ðV sb Þ tuning of IMOS varactor from 0 V to 2.4 V. The phase noise mea-
sured for the VCO is 90.67 dBc/Hz@1 MHz and the figure of merit (FoM) for the VCO is 172.86 dBc/
Hz with supply voltage of 1.8 V. Proposed VCO circuit achieved a low power dissipation, wide tuning
range, better phase noise and figure of merit (FoM).
Ó 2019 Karabuk University. Publishing services by Elsevier B.V. This is an open access article under the CC
BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

1. Introduction capacitance resulting in narrower tuning range [4]. Alternatively,

Voltage controlled oscillator (VCO) is an imperative part of the
phase-locked loop (PLL) system which is designed for high speed
digital circuits, frequency synthesis, clock recovery and communi-
cation system as it provides the initial timing for systems such as
synchronization and clock control [1–3]. VCOs are the most power
starving block and therefore low power dissipation is a criterion for
good performance. In literature, VCOs can be designed using the
structure of inductor-capacitor (LC) tank-based circuits and com-
plementary metal oxide semiconductor (CMOS) ring-based topol-
ogy. LC tank-circuit VCO keeps higher operation frequency and
better noise performance but the combination of inductor and
capacitor requires large chip area which increases parasitic
⇑ Corresponding author.
E-mail address: vjangra@amity.edu (V. Jangra).
Peer review under responsibility of Karabuk University.
the CMOS-based ring VCO does not need on-chip inductors and
possesses wider tuning range with the advancement in packaging
density. In VLSI circuits, the commonly used technique to decrease
the power dissipation is voltage scaling. In addition, a positive gate
voltage is required to keep the transistors of delay cells in suitable
operating region as the control voltage of delay cells does not cover
the entire range of power supply voltage. The restricted output
voltage swing reduces VCO performance at low supply voltage.
The gradual downscaling of design technology and increasing need
for low voltage operation with excessive integration presents
numerous challenges to study low-power and wide tuning range
CMOS VCO. The operating frequency for high speed clock genera-
tion used in a single-ended ring oscillator has been insisted by neg-
ative skewed delay technique [5]. In case of ring VCO based on
differential delay cells, various schemes like dual-delay path,
multiple-feedback loop, multi-pass loop was proposed to control
the phase noise and to alleviate the operating frequency along
with the tuning range [6–8]. Generally, these VCOs have been

https://doi.org/10.1016/j.jestch.2019.02.011
2215-0986/Ó 2019 Karabuk University. Publishing services by Elsevier B.V.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
1078 V. Jangra, M. Kumar / Engineering Science and Technology, an International Journal 22 (2019) 1077–1086
implemented with active devices to regulate the operating fre-
quency while the conventional VCOs control voltage does not cover
the entire range of power supply voltage because of the positive
gate voltage needed for the active devices. Therefore, the control
voltage will get reduced with the lowering of the power supply
voltage. The variations in positive gate voltage changes the charac-
teristic of the control voltage that limits the useful range and the
maximum frequency has been achieved. To overcome these con-
straints a complementary current control structure is reported in
the literature [9] and this method improves the highest operating
frequency along with the tuning range of VCO. Likewise, scaling
also reduces the power supply voltage which limits the frequency
tuning. The dropping of power supply voltage lowers the effective
range of control voltage. Thus, low-loss varactors are required to
sustain wide frequency tuning in VCO. A varactor consists of vari-
able resistance and capacitance. MOS based varactors are generally
used for higher Q-factor which depends on higher levels of doping
in silicon as it reduces resistive losses and phase noise [10,11]. A
MOS based varactor is like a MOS transistor with source (S), bulk
(B) and drain (D) connected to form the first terminal and gate as
second terminal. The rate of change of MOS capacitance has been
controlled by the voltage V bg applied between bulk (B) and gate
(G) terminal. MOSFET varactor works in 4 regions: depletion, accu-
mulation, weak inversion and strong inversion. Generally, most
varactors operate in accumulation and strong inversion regions.
In case of accumulation and strong inversion regions, the capaci-
tance per unit area is found to be maximum [12]. All the four
modes of operation depend upon the value of V bg and jV th j. The
voltage between the accumulation and depletion regions is known
as flat-band voltage (V fb Þ. For MOS transistor based on two PMOS
transistors connected in parallel, accumulation region arises with
mobile holes and the threshold voltage V th is exceeded by the bulk
voltage which is much higher than the gate voltage i.e. V bg < V fb . In
case of MOS transistor working in depletion region, the bulk to gate
voltage V bg lies between the flat-band voltage V fb and threshold
voltage jV th j i.e. V fb < V bg < jV th j where few mobile charge carriers
exist at the gate oxide interface. An inversion channel with mobile
holes grows up for V bg > jV th j i.e. the voltage across bulk and gate
terminal V bg must be greater than the threshold voltage jV th j
[13–15]. The carrier concentration is more under the gate oxide
and the charge carriers moves freely for the MOS transistor to work
in inversion region. For weak inversion region, V bg > jV th j and for
strong inversion region V bg  jV th j. The performance parameters
like power dissipation has been improved by the control of the
bulk terminal in MOS transistors and reverse body biasing reduces
the standby leakage in CMOS circuits [16]. The Inversion-mode
varactor (IMOS) has been utilized to minimize the power dissipa-
tion. It also improves the phase noise at large offset frequencies
from the carrier [17,18].
A number of approaches to tune the VCO like multiple feedback
loops, multi-pass loops, delay paths, output load variations, com-
plementary current control and varactor tuning have been
reported in the literature [19–27]. For the proposed work, multi-
pass loop complementary current control scheme and IMOS varac-
tor with two PMOS transistors connected in parallel has been used
to design the delay stage. A three-stage VCO is reported in this
paper using the proposed delay stages. Variations in the source/
drain voltage ðV control Þ and the back-gate voltage ðV sb Þ of IMOS var-
actor allows to achieve fine frequency tuning. The proposed VCO
offers full range voltage controllability, wide tuning frequency
and low phase noise with good FoM. Remaining paper is organized
as follows: Section 2 reports a new delay cell based on multi-pass
loop complementary current control with IMOS varactor. A 3-stage
VCO design is also reported in this section. Section 3 provides the
circuit analysis of delay cell. Section 4 present results and
discussion extracted through simulation of VCO circuit. Finally,
Section 5 concludes the work.
2. System description
A ring oscillator comprises of delay stages and each stage offers
input to the following stage in the ring. For a conventional VCO, the
frequency of oscillation is given by the number of delay stages and
propagation delay time of the delay cell as shown in Eq. (1).
1
fo ¼ ð1Þ
2Nsd
where sd is the propagation delay time specified by each stage and
N is the total number of delay stages. The number of delay stages or/
and the propagation delay time are inversely proportional to the
frequency of oscillation.
The proposed three-stage ring VCO with multi-pass loop topol-
ogy is schematically depicted in Fig. 1. The multi-pass loop topol-
ogy decreases the delay time of each stage by introducing a pair
of secondary inputs to individual stage and swapping these sec-
ondary inputs prior to the primary inputs. The VCO has two oper-
ational loops. First one is the primary loop represented by solid
lines and the second one is the secondary loop represented by dot-
ted lines. For individual delay cell, Pr+ and Pr represents the
primary-loop inputs and Sr+ and Sr represents the secondary-
loop inputs. As NMOS has lower switching time than PMOS,
secondary-loop inputs get the delay signals ahead of the
primary-loop inputs that decreases the PMOS switching time. A
normal delay path is used to link the differential outputs of indi-
vidual delay stage with the primary-loop inputs of following stage
and a skewed delay path is used to link the secondary-loop inputs
of the same subsequent stage. The inputs of secondary-loop are
associated with every single stage and swapping these inputs prior
to the primary-loop inputs tends to achieve smaller delay time
which further decreases the VCO phase noise. Also, the control
voltage of VCO ensures linear control of the positive gate voltage
of the transistors of delay cells. The output frequency remains
uncontrolled when the control voltage is less than or higher than
positive gate voltage. So, more reduction in supply voltage
decrease the valuable range of control voltage. To put away such
dilemma of control voltage, a new delay stage has been proposed
as shown in Fig. 2. The delay stage has been designed using
multi-pass loop complementary current control scheme and IMOS
varactor with two PMOS transistors connected in parallel. The
usage of IMOS varactor advances the delay with addition of con-
trolled variable capacitive load.
The differential structure of this delay cell has offered another
current path by using complementary current control scheme to
enhance the control voltage range. In the proposed delay cell, N1
and N2 forms the input pair of delay loop whereas P3 and P4 forms
the input pair of skewed delay loop. The transistor N1 is in turn off
condition when the gate voltage of N1 i.e. Pr+ is lesser than the
threshold voltage. In the meantime, the input voltage at Sr+
reaches prior to the Pr+, the secondary input transistor P3 before
now directing its source current to the load at the output OUT+.
Accordingly, the output node rise time has been increased. The
load transistors P1 and P2 in the delay cell acts as a latch. The pass
transistors N3 and N4 are direct coupled to regulate the highest
voltages at the gate of the load transistors for tuning the power
of the latch. This adjustment of the latch power regulates the oper-
ating frequency. Transistors P7 and P8 connected in parallel acts as
an IMOS varactor to increase the power of the latch. Two comple-
mentary control transistors P5 and P6 are used in pair to deliver an
additional current to eliminate the low control voltage operation
and to enhance the operating frequency. If the control voltage is
 V. Jangra, M. Kumar / Engineering Science and Technology, an International Journal 22 (2019) 1077–1086 1079

Sr+ Sr+ Sr+

Pr+ Out- Pr+ Out- Pr+ Out-
Pr-
Out+ Pr- Out+ Pr- Out+
Sr- Vcontrol Vcontrol Vcontrol
Sr- Sr-

Vcontrol / Vsb Vcontrol / Vsb Vcontrol / Vsb

Fig. 1. Three-stage VCO structure.

Vdd concentration of the p-type substrate, esi be the dielectric constant

Sr +
P3 P1 P5
N3 N4
OUT -
Vsb
Pr + N1
P7 P8
Vcontrol
Fig. 2. Proposed differential delay cell.
less than the combined voltage due to gate to source voltage of
transistors (N3, N4), and drain to source voltage of transistors
(N1, N2), the power of the latch becomes less. Therefore, an addi-
tional current is provided by complementary current control tran-
sistors that increases the power of the latch and hence increase in
operating frequency. As the control voltage is higher than the com-
bined voltage due to gate to source voltage of transistors (N3, N4),
and drain to source voltage of transistors (N1, N2), the strength of
the complementary control transistors becomes less that increases
the power of latch and stops the switching of voltages in the differ-
ential delay cell. Therefore, the delay time increases.
The most important parameter which characterizes the MOSFET
operation is the threshold voltage (V th or V t ). For an inversion
mode MOS transistor, the threshold is given by Eq. (2).
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
   ffi
2esi qNA 2/f  þ jV C  V B j
V th ¼ V FB 
C ox
where Q i = (q  implant dose) is the charge due to ionized donors,
V FB is the flatband voltage, q is the electron charge, NA be the doping
of silicon, Cox be the gate oxide capacitance per unit area and /f
be the substrate Fermi potential. In this equation, V C ð< 0Þ is nega-
tively biased for PMOS because the inversion holes must be nega-
Sr - tively biased relating to the n-substrate to form a reverse biased
p-n junction. The channel length and width of the MOS transistor
P6 P2 P4
relates with the threshold voltage is given by Eq. (3) [28].
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi tox tox
Vth ¼ Vth0 þ c Vsb þ uo  al ðVsb þ uo Þ  av Vds
L L
tox
þ aw ðVsb þ uo Þ ð3Þ
W
OUT +
where V th0 is the zero bias threshold voltage, t ox is the width of
oxide, c is bulk threshold coefficient, uo is 2/f and /f is Fermi
Pr - potential, and al ; av and aw are the parameters given by process
N2
technology. In the proposed delay cell, all MOS transistors have
the gate length of 0.18 mm. The sizing of MOS transistors used in
delay stage is shown in Table 1.
In PMOS based IMOS varactor, an inversion channel grows up
with mobile holes for V gs < jV th j, where V th is the threshold voltage
and V gs is the voltage between gate and substrate. This condition
ensures that a MOS capacitor is working in strong inversion mode.
The capacitance in these regions is given by
e:W:L
C inv ;acc ¼ C ox ¼ ¼ C max ð4Þ
tox
where W:L is the area of transistor channel, e is the permittivity of
silicon dioxide and tox is the oxide thickness. This area depends
upon the width of the channel of the IMOS transistor. In IMOS var-
actor, out of two terminals, body terminal is linked to the back-gate
voltage ðV sb Þ and the source/drain terminal ðV control Þ acts as capaci-
tance control voltage. In an IMOS circuit, increasing the source/
drain voltage ðV control Þ brings more holes in the channel. Hence,
capacitance increases with the increase in source/drain volt-
ageðV control Þ and hence the output frequency decreases. Moreover,
increase in back gate voltage ðV sb Þ increases the depletion width
of source and drain end results in decrease in depletion capacitance.
Therefore, the overall capacitance of IMOS varactor decreases which
  Q reduces the delay time and hence the output frequency increases.
 2/f  þ V C  i ð2Þ The general equivalent model of IMOS capacitance [11] is shown
C ox
in Fig. 3.
In Fig. 3, C dep is the channel capacitance, Cox is the oxide capac-
itance between gate and substrate, C gs and C gd are the parasitic
1080 V. Jangra, M. Kumar / Engineering Science and Technology, an International Journal 22 (2019) 1077–1086

Table 1
Transistor size for VCO.

Transistors N1/N2 N3/N4 P1/P2 P3/P4 P5/P6 P7/P8

W(mm) 5 0.6 3 1 4 5
L(mm) 0.18 0.18 0.18 0.18 0.18 0.18

Gate
-gmSr+
S r+
Cox Cgd C R
Cgs Rsub
Rsub -gmPr+
P r+ VOUT-
Cdep Cbd
Csb
Rdep -gmCr

Vct
Vsb C variable
Rdep

Cbd -gmCr
Csb Cdep Rsub
-gmPr-
P r- VOUT+
Rsub
Cgs Cox Cgd
C R
-gmSr-
S r-
Gate

Fig. 3. Equivalent capacitance model for IMOS varactor.

Fig. 4. Equivalent model for IMOS capacitance.

capacitance between gate to source and gate to drain, C bs and C bd

are bulk to source and bulk to drain capacitance. Rdep is the para- the equivalent resistive load and C represents the equivalent
sitic resistance between gate and source/drain terminals and Rsub capacitive load seen at the output node.
is the resistance offered by the substrate. The variable capacitance Let the primary input node and the output node phase differ-
between the gate and the substrate in a MOS varactor is a series ence is represented by h, secondary input node and the output
combination of gate oxide capacitance Cox and depletion region node phase difference is given by / and the phase difference
capacitance C dep is given by Eq. (5). amongst the differential output nodes OUT+ and OUT is given
by p, the following equations for each stage may be derived as:
1
C eq ¼ ðC ox kC dep Þ ¼    C min ð5Þ V OUT ¼ V Prþ ejh ð6Þ
1
C ox
þ C1
dep

V OUT ¼ V Srþ ej/ ð7Þ

As source/drain voltage ðV control Þ increases, the width of the
depletion region at the source end will decrease which increases
V OUT ¼ V OUTþ ejp ð8Þ
source to bulk capacitance C dep . As a result, the capacitance
between the gate nodes increases. This increase the time delay of Applying KCL at the output node,
a delay cell which is proportional to the capacitance and hence,  
R
decreases the VCO output oscillation frequency. As the back-gate V OUT ¼ g mPrþ V Prþ  g mSrþ V Srþ  g mCr V OUTþ ð9Þ
1 þ jxRC
voltage ðV sb Þ increases, large number of electrons are attracted
towards the substrate terminal. This results in positive charge near Substituting the value of V Srþ from (7) and V OUTþ from (8) into
the surface and increase in the depletion width. So, increase in (9), we get
depletion width decreases the depletion capacitance that  
R
decreases the capacitance between bulk and source/drain terminal. V OUT ¼ g mPrþ V Prþ  g mSrþ V OUT ej/  g mCr V OUT ejp
1 þ jxRC
As the load capacitance decreases, the propagation delay of the
delay stage decreases and therefore output frequency increases. ð10Þ
Rearranging (10), we get
3. Circuit analysis of delay stage 
Rg V Prþ Rg mSrþ V OUT ej/ Rg mCr V OUT ejp
V OUT ¼  mPrþ   ð11Þ
1 þ jxRC 1 þ jxRC 1 þ jxRC
The reported delay cell is based on differential delay cells topol-
ogy. The variations in the frequency at low control voltage has  
1 þ jxRC þ Rg mSrþ V OUT ej/ þ Rg mCr V OUT ejp Rg V Prþ
been adjusted using complementary control technique in delay V OUT ¼  m Prþ
1 þ jxRC 1 þ jxRC
cell. The equivalent model as shown in Fig. 4 exhibits the small sig-
nal analysis of the proposed delay cell. g mPr and g mSr denotes the ð12Þ
transconductance from the primary input and the secondary input By rearranging, we get the transfer function as
to the outputs realized by pairing transistors N1/N2 and P3/P4
V OUT Rg mPrþ
respectively. g mCr denotes the transconductance within the differ- ¼ ð13Þ
ential outputs that is made up by pairing N3/N4. R represents V Prþ 1 þ jxRC þ Rg mSrþ ej/ þ Rg mCr ejp
 V. Jangra, M. Kumar / Engineering Science and Technology, an International Journal 22 (2019) 1077–1086 1081

By putting ej/ ¼ cos / þ j sin / and ejp ¼ 1, the transfer func- outputs at the equal voltage level. Also, the coupled NMOS pair
tion is given by decreases the slew rate of the output terminals for transitions of
states from high-to-low and vice-a-versa to attain improved phase
Rg mPrþ
HðjxÞ ¼ ð14Þ noise performance.
1  Rg mCr þ Rg mSrþ cos/ þ jðxRC þ Rg mSrþ sin/Þ
And the phase of HðjxÞ is given by
4. Results and discussions

xRC þ Rg mSrþ sin/
\HðjxÞ ¼  tan 1
ð15Þ
1  Rg mCr þ Rg mSrþ cos/ The proposed three-stage multi-pass loop complementary
current control VCO has been designed in TSMC 180 nm CMOS
The phase is equal to h i.e. given by (6). Hence, the equation technology and the results have been obtained with SPICE
becomes simulations in Mentor Graphics EDA tool. The results have been
xRC þ Rg mSrþ sin/ extracted with different power supply voltage ðV dd Þ, source/drain
tanh ¼ ð16Þ voltage ðV control Þ and back-gate voltage ðV sb Þ of IMOS transistors
1  Rg mCr þ Rg mSrþ cos/
at temperature of 27 °C. Various analysis like transient analysis,
According to Barkhausen criterion, the gain of the loop must DC analysis and noise analysis have been executed to get output
have not less than unity and the phase shift is a multiple of 2p. oscillation frequency, power dissipation and phase noise along
So, to fulfil this requirement with figure of merit (FoM) of the VCO with variations in IMOS
  widths such as 5 lm, 10 lm, 15 lm and 20 lm. Table 2 shows
Rg mPrþ 
jHðjxÞj ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2  2  1 the three-stage VCO outcomes with varying IMOS source/drain
1  Rg mCr þ Rg mSrþ cos/ þ xRC þ Rg mSrþ sin/ voltage ðV control Þ from 1 V to 2.4 V. As source/drain voltage
ð17Þ ðV control Þ increases, the capacitance of IMOS increases and therefore,
output oscillation frequency of the VCO declines. The results have
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 2  2 been extended with varying IMOS widths ðW I Þ.
Rg mPrþ  1  Rg mCr þ Rg mSrþ cos/ þ xRC þ Rg mSrþ sin/ As the IMOS width ðW I Þ increases, the capacitance of IMOS
ð18Þ increases and therefore output frequency decreases as compared
to the smaller width as presented in Table 2. The proposed differ-
Now simplify (17) by putting (16) and get equation between
ential ring VCO shows the total power dissipation of 9.62 mW.
tanh and cosh. We get
Fig. 5 shows the variations in output frequency for source/drain
 
1  Rg mCr þ Rg mSrþ cos/ voltage ðV control Þ with different IMOS widths ðW I Þ. The variations
Rg mPrþ   
 ð19Þ
cos h
This equation depicts that the minimum gain should match 6.5
with the oscillation principle. The oscillation frequency is given
by (10) and we get 6

xRC þ Rg mSrþ sin/ ¼ tanh  Rg mCr tanh þ Rg mSrþ cos/tanh ð20Þ

5.5
Output Frequency (GHz)

Finally, we get the relationship W I =5

5 W I =10
tanh Rg mSrþ g tanh
x¼ þ ½cos/tanh  sin/  mCr ð21Þ W I =15
RC C C 4.5 W =20
I
In the above equation, the first term signifies the oscillation fre-
quency of primary loop which is expressed in terms of time con- 4
stant along with the number of delay stages n. Also, h is related
 
to n as h ¼ nþ1 p i.e. the summation of dc phase shift of value p 3.5
n
 
and an ac phase shift of pn . The second term is the outcome of
the oscillation frequency given by the secondary loop. Therefore, 3

½cos/tanh  sin/ must be positive to enhance the speed of the

2.5
oscillator. The third term represents the change in frequency due 1 1.2 1.4 1.6 1.8 2 2.2 2.4
to coupled NMOS pair. The use of coupled pair decreases the circuit Control Voltage (V)
speed. This slowdown has been reduced by decreasing the transis-
tor size. However, this coupled NMOS pair lowers the circuit oper- Fig. 5. Output frequency variations for source/drain voltage V control with different
ating speed, but it is crucial as it stops the merging of differential IMOS widths (W I ).

Table 2
Source/drain Voltage ðV control Þ tuning of three-stage VCO with different IMOS widths at V dd = 1.8 V and V sb = 1.8 V.

Vcontrol (V) Frequency (GHz) Power Dissipation(mW)

WI = 5 mm WI = 10 mm WI = 15 mm WI = 20 mm
1.0 6.373 5.283 4.520 3.958 9.62
1.2 6.271 5.150 4.386 3.798 9.62
1.4 6.069 4.893 4.104 3.560 9.62
1.6 5.829 4.592 3.815 3.284 9.62
1.8 5.607 4.354 3.438 2.753 9.62
2.0 5.456 4.244 3.270 2.610 9.62
2.2 5.461 4.222 2.990 2.600 9.62
2.4 5.460 4.221 2.881 2.600 9.62
1082 V. Jangra, M. Kumar / Engineering Science and Technology, an International Journal 22 (2019) 1077–1086

Table 3
Power supply voltage ðV dd Þ tuning of three-stage VCO with different IMOS widths at V control = 1.5 V and V sb = 1.8 V.

Vdd (V) Frequency (GHz) Power Dissipation(mW) Phase Noise@1 MHz (dBc/Hz)
WI = 5 mm WI = 10 mm WI = 15 mm WI = 20 mm
1.0 1.893 1.422 1.153 0.982 0.95 87.23
1.2 3.005 2.280 1.901 1.437 2.13 86.07
1.4 4.100 3.167 2.633 2.239 3.88 87.61
1.6 5.059 3.986 3.314 2.840 6.34 89.12
1.8 5.943 4.728 3.984 3.407 9.62 90.93
2.0 6.647 5.402 4.528 3.967 13.71 92.67
2.2 7.312 6.011 5.106 4.439 18.59 96.64
2.4 7.926 6.642 5.526 4.963 24.26 97.48

in output oscillation frequency along with power dissipation of ations in output frequency for power supply voltage ðV dd Þ tuning
VCO for the power supply voltage ðV dd Þ tuning from 1 V to 2.4 V with different IMOS widths.
with different IMOS varactor widths ðW I Þ is shown in Table 3. Fur- The proposed VCO depicts the variations in power dissipation
ther, the phase noise variations through all the tuning range has against variations in power supply voltage in Fig. 7. The phase noise
been shown in Table 3. As the power supply voltage ðV dd Þ variations through all the tuning range has been shown in Fig. 8.
increases, the delay cell biasing current increases that increases Power dissipation varies from 0.95 to 24.26 mW for variations
the output oscillation frequency. This VCO shows the variations in supply voltage from 1 V to 2.4 V as shown in Table 3. Graph
in power dissipation from 0.95 mW to 24.26 mW for power supply between power dissipation and tuning frequency has been shown
ðV dd Þ tuning with different IMOS widths ðW I Þ. Fig. 6 shows the vari- in Fig. 9. Table 4 shows the variations in output oscillation fre-

8 -86

7
-88
6
Output Frequency (GHz)

Phase Noise (dBc/Hz)

-90
5

4 -92
W =5
I
W I =10
3
W =15
I -94
W =20
I
2

-96
1

0 -98
1 1.2 1.4 1.6 1.8 2 2.2 2.4 1 2 3 4 5 6 7 8
Tuning Voltage (V) Tuning Frequency (GHz)

Fig. 6. Output frequency variations for power supply voltage with different IMOS Fig. 8. Phase noise variations with power supply voltage for all tuning range.
widths ðW I Þ.

25
25

20
20
Power Dissipation (mW)
Power Consumption (mW)

15
15

10
10

5
5

0 0
1 1.2 1.4 1.6 1.8 2 2.2 2.4 1 2 3 4 5 6 7 8
Tuning Voltage (V) Tuning Frequency (GHz)

Fig. 7. Power dissipation variation with power supply voltage. Fig. 9. Power dissipation versus tuning frequency.
 V. Jangra, M. Kumar / Engineering Science and Technology, an International Journal 22 (2019) 1077–1086 1083

Table 4
Back-gate voltage ðV sb Þ tuning of three-stage VCO with different IMOS widths at V dd = 1.8 V, V control = 1 V.

Vsb (V) Frequency (GHz) Power Dissipation(mW)

WI = 5 mm WI = 10 mm WI = 15 mm WI = 20 mm
0 5.895 4.653 3.881 3.332 10.229
0.2 5.980 4.758 3.963 3.408 9.923
0.4 6.032 4.814 4.025 3.467 9.710
0.6 6.092 4.889 4.100 3.538 9.62
0.8 6.161 4.974 4.184 3.623 9.62
1.0 6.188 5.020 4.263 3.688 9.62
1.2 6.260 5.130 4.363 3.788 9.62
1.4 6.317 5.206 4.421 3.866 9.62
1.6 6.350 5.261 4.486 3.918 9.62
1.8 6.368 5.287 4.517 3.958 9.62
2.0 6.383 5.311 4.521 3.973 9.62
2.2 6.397 5.333 4.529 3.987 9.62
2.4 6.406 5.347 4.560 3.999 9.62

6.5 where f o is the carrier frequency, Df is the frequency offset, LfDf g is

the phase noise measured at an offset Df from the carrier and PDC is
6 the DC power dissipation in mW consumed by the VCO. In the
reported VCO, the FoM at 1 MHz offset frequency varies from
5.5 160.86 dBc/Hz to 182.86 dBc/Hz for different tuning conditions.
Output Frequency (GHz)

W I =5 The results of proposed VCO have been compared with previ-

5 W I =10 ously reported VCOs [4,5,7,8,15,17,20,21,25–29] in terms of output
W =15
I
frequency range, power dissipation, phase noise and FoM. The
4.5 W =20 compared results of the proposed VCO has been shown in Table 6.
I
The proposed VCO provides additional tuning with the source/
4 drain voltage (V control ) and back-gate voltage (V sb ). Further, tuning
of VCO with source/drain voltage (V control ) and back-gate voltage
3.5 (V sb ) shows the advantage of constant power dissipation as com-
pared to power supply (V dd ) variations. Previously reported VCO
3 with LC combination [8,12,23,24] as tuning element shows more
power dissipation as compared to reported work. Further, the area
2.5 taken by the LC based VCOs is more than that of the CMOS based
1 1.2 1.4 1.6 1.8 2 2.2 2.4
VCO circuits. The physical layout of the proposed VCO has been
Control Voltage (V)
drawn as shown in Fig. 13. The layout area of the proposed differ-
Fig. 10. Output frequency variations for back-gate ðV sb Þ voltage with different IMOS ential ring VCO is 50 mm  10 mm. The proposed VCO is offering
widths ðW I Þ. wide tuning range along with low power dissipation and good
phase noise.

quency along with power dissipation of the proposed three-stage

5. Conclusion
VCO with change in back-gate voltage ðV sb Þ from 0 V to 2.4 V with
different IMOS varactor widths ðW I Þ.
A three-stage CMOS differential VCO usingmultipass loop com-
With increase in back-gate voltage ðV sb Þ of IMOS, capacitance of
plementary current control scheme and using IMOS varactor in
MOS varactor decreases and consequently the output frequency of
delay cell has been designed using TSMC 180 nm CMOS process.
the VCO circuit increases. The variations in output frequency for
The control voltage in a conventional VCO is not able to compen-
change in back gate voltage ðV sb Þ has been shown in Fig. 10.
sate the entire range of power supply voltage. The complementary
Fig. 11(a)–(c) shows the output waveforms of the VCO for
current control expels the limit of the control voltage. The multi-
source/drain voltage tuning for V dd = 1.8 V and V sb = 1.8 V, power
pass loop topology has been used to obtain high-output oscillation
supply voltage tuning for V control = 1.5 V and V sb = 1.8 V and back
frequency. Transistors N3 and N4 offers supplementary load capac-
gate tuning for V dd = 1.8 V, V control = 1.5 V and V sb = 1.8 V.
itance at the output node of the delay cell, which decreases the
Phase noise is a significant factor to obtain the noise perfor-
gain of the oscillator and therefore the phase noise of VCO get min-
mance of the ring oscillator. For the reported VCO, the outcomes
imized. Transistors P7 and P8 coupled back-to-back to form an
of phase noise with an offset of 1 MHz from the carrier is shown
IMOS varactor to increase the tuning range of ring VCO. The oscil-
in Table 5. The phase noise performance of the reported VCO is
lation frequency range of the proposed differential ring VCO is
90.67 dBc/Hz@1 MHz. Results for different grouping of power
5.460 GHz to 6.373 GHz and power dissipation is 0.962 mW with
supply voltage, back gate voltage and source/drain voltage have
variations in control voltage from 1.0 V to 2.4 V with IMOS varactor
been reported in Table 5. Fig. 12(a) and (b) depicts the phase noise
width of 5 mm. Proposed VCO achieves output oscillation frequency
results for different combinations of tuning voltage. The phase
range from 1.893 GHz to 7.926 GHz and dissipates power from
noise has been normalized in terms of figure of merit (FoM) used
0.95 mW to 24.26 mW with a variation of the power supply volt-
for approximation of VCO performance. The figure of merit is given
age from 1.0 V to 2.4 V. Further, back-gate voltage tuning of IMOS
by Eq. (22) [29].
varactor with width of 5 mm gives fine tuning range with constant
 2 !
fo 1 power dissipation of 0.962 mW. The VCO shows phase noise of
FOM ¼ 10log ð22Þ 90.67 dBc/Hz at 1 MHz offset and FoM varies from 160.86 dBc/
Df LfDf gPDC ðmWÞ
Hz to 182.86 dBc/Hz for different tuning voltage. Hence, the
1084 V. Jangra, M. Kumar / Engineering Science and Technology, an International Journal 22 (2019) 1077–1086

Fig. 11. Waveforms of VCO for (a) Source/drain voltage tuning at V dd = 1.8 V, V sb = 1.8 V, (b) Power Supply voltage tuning at V dd = 1.8 V, V control = 1.5 V and V sb = 1.8 V and (c)
V dd = 1.8 V, V control = 1.0 V, and V sb = 1.8 V.

Table 5
Phase noise performance of VCO for 1 MHz offset from the carrier.

Power Supply Voltage (Vdd) Control Voltage (Vcontrol) of IMOS Back-gate Voltage (Vsb) of IMOS Width of IMOS (WI) (mm) Phase noise of VCO@1 MHz (dBc/Hz)
1.8 V 1.5 V 1.8 V 5 90.93
1.0 V 2.0 V 1.5 V 5 90.45
1.8 V 1.8 V 1.0 V 5 90.15
1.8 V 1.0 V 1.8 V 5 90.67
1.8 V 1.5 V 1.0 V 5 90.21
1.0 V 1.5 V 1.8 V 5 90.55
 V. Jangra, M. Kumar / Engineering Science and Technology, an International Journal 22 (2019) 1077–1086 1085

Fig. 12. Phase noise of the proposed VCO at (a) V dd = 1.8 V, V ct = 1.0 V & V sb = 1.8 V and (b) V dd = 1.8 V, V ct = 1.5 V & V sb = 1.8 V.

Table 6
Performance comparison with other VCOs.

References Frequency Range (GHz) Technology (mm) Phase Noise (dBc/Hz) Power Dissipation (mW) FoM (dBc/Hz)
[4] 0.02–0.80 0.18 108@1 MHz 22 150.6
[5] 0.89–2.4 0.18 97@1 MHz 14 –
[7] 7.3–7.86 0.18 103.@1 MHz 91.5 161.4
[8] 10.6–8.4 0.12 85.1@1 MHz 52.5 147.8
[15] 1.3–0.5 0.18 90@1 MHz 0.71 151.4
[17] 4.09–0.47 0.18 93.3@1 MHz 13 154.4
[20] 3.2–10 0.12 90@1 MHz 15 154.0
[21] 5.4 0.18 86.7@1 MHz 8.1 149.7
[23] 5.17–7.39 0.13 111.7@1 MHz 0.49 192.4
[24] 1.2–2.2 0.18 110@1 MHz – –
[25] 20.3–31.3 0.13 95.7@1 MHz 22 186.0
[26] 23.5 0.13 110.8@1 MHz 55 180.8
[27] 1.37–1.97 0.18 89.77@1 MHz 1.2 154.5
Proposed Work 1.893–7.926 0.18 90.67@1 MHz 0.95–24.26 182.8
(Power supply tuning)
6.373–5.460 93.45@1 MHz 9.62 172.8
(IMOS source/drain tuning)
5.895–6.406 86.53@1 MHz 9.62 160.8
(IMOS back gate tuning)
1086 V. Jangra, M. Kumar / Engineering Science and Technology, an International Journal 22 (2019) 1077–1086
Fig. 13. Physical layout of the proposed VCO.
obtained results of the proposed VCO has been found better in
terms of wider tuning range, lower power dissipation, lower phase
noise and good FoM.
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Vivek Jangra is a student of Ph.D (Electronics and communication Engineering) in
USICT, GGSIP University, Dwarka, New Delhi, India. He is doing his research work in
the field of low power CMOS circuit design. He is a Life Member of IETE (India) and
ISTE (India).
Manoj Kumar is working as an Associate Professor in USICT (ECE), GGSIPU, Dwarka,
New Delhi. He has more than 14 years of experience in teaching and research. He
has published 30 research papers in International/National journals. He has also
published more than 35 research papers in International/National conference. His
research interests include integrated circuit design, low power CMOS system and
microelectronics for communication systems. He is a Life Member of IETE (India),
ISTE (India), CSI (India) and Semiconductor Society of India.