P .

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Seat
Total No. of Pages :2
No.

T:E. @lectronics & Telecommunication) (semester - YI) (Revised)

Examination, APril' 2016
VLSI DESIGN
Sub. Code | 66917

Day and Date : Mondav, 18 - 04 - 20 t 6'

Time : 03.00 p.rn. to 06.00 P.ttt. Total Marks : 100

lnstructiolts: I) r\ll questions al'e compulsotl"

2) Assutne suitablc data lvhereYcr necessal'!"
3)Ncrrtdiagratnsltrustlredr:rrynlvherevernccessat},.
v 1) !'igurcs to thc right indicate lull marks'

p1) Solve any tltree : tlsl

a) Briefl-v u,rite about various f eatules and capabilities o1'VHDI- latl-{nage.
b) \\Ihich ale cliffereilt tvpes tll"O1'tg1'xtot's' titltt oile t'atc on siguals variables
a1cl colstants i1 \'HDL'l Surnnlarize ali types ltlld u'rtir stiitable
examples. Elaborate'Logical' operators'
c) Write VHDL code tor Mod-6 couttter'
cl) Write VHDI- cocle fbr 4:l multiplexer'

Q2) Solve any two : [16]

a) Which are the clifferelt types of 'Attributes' to which VHDL snpport'/
\t Elaborate 'Signal' type oi'attributes with proper syntax ancl its tirrlction.
b) Dr.aw VLSI systern clesign florv cliaglam ancl briefly explain each block.
- c) Wr-ite a VHDL coclc for 'D' llip-I1op with asyncltrouous sei, and resc:t
inputs. I)raw entity diagranr also'

03) Solve any two : [16]

a) Explail sequential staietlents n VFIDL rvith exatnple.
tol a sequelrce cletector '1011' r.r'ltich is fealized
b) Draw a state diagram \rVrite
as a Mealy tnacltine' VHDL code for sallle'
c) What is meant by 'Package' in VHDL'/ Witii the help of- plopel sytttitx
br.iefly rvr:ite paiLoge Lrody a,d package cleclaration.

P,TO.

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Q'l) Solve arly three ' I18l
a) Explail control statements usecl ir-r Veriiclg 'ul'ith exanrple.

b) Explain Half Adcler design using Verilog'

c) Explain Hot Electlon eftbct'
ci) Explain operators usecl irl \terilo-u'

t16l
B5) Solr,e any two :

a) NeatlY dral and explain functional block diagram of XC 9572

macrocel[.
b)' Explain brietly the concept of t-ault detection using path sensitization
technique os.d in combinational logic circuit testing.
c) With the help of typical boundary scan cell diagram and basic boundary
,run ur"hiteiture"&plain the concept of boundary scan testing'
t,
B6) Solve any two :
t16l
a) Brietly write about Built - In - Test used for testing digital IC',s.
b) Detine Power Delay Product in CMOS? Explain in detail'.
c) Draw and explain general arlhitectural block diagram of Spartan III
famiiY FF'GA.

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