5 4 3 2 1

D
MStar MSD7831_REV1.2 HD H.264 STB
D

Semiconductor
ChangeList:
---------------------------------------
REV1.0: MStar SZ Demo
REV1.1: Modify DRAM Layout
REV1.2: Modify DDR RESET
REV1.2: Circuit Optimizer

C C

---------------------------------------

B B

A ORG A
MStar Semiconductor(SZ),Inc.
Title
MSD7831 HD STB
Size Document Number Rev
E Block Diagram 1.1

Date: Friday, January 16, 2015 Sheet 1 of 10

5 4 3 2 1
 5 4 3 2 1

U6-A

ET_MDIO 181
ET_MDC 182
158 IF- ET_COL 183
157 184
IF+ ETHERNET ET_RXD0
185
ET_RXD1
DVB-C Demodulator ET_TX_CLK 186 D
ET_TXD0 189
156 IF_AGC ET_TXD1 190
ET_TX_EN_(HI-V_SENSE__NO_5V_TOLERANCE) 191

<10> TS_D0 TS_D0 155 TS_D0(GPIO) RN 164

<10> TS_D1 TS_D1 154 TS_D1(GPIO) RP 165
<10> TS_D2 TS_D2 153 TS_D2(GPIO) TN 166
<10> TS_D3 TS_D3 152 TS_D3(GPIO) PHY TP 167
<10> TS_D4 TS_D4 151 TS_D4(GPIO)
<10> TS_D5 TS_D5 150 TS_D5(GPIO) LED[0]_(GPIO) 176
<10> TS_D6 TS_D6 149 TS_D6(GPIO) TS Port LED[1]_(GPIO) 177
<10> TS_D7 TS_D7 148 TS_D7(GPIO)
<10> TS_SYNC TS_SYNC 147 TS_SYNC(GPIO)
<10> TS_VLD TS_VLD 146 TS_VLD(GPIO)
<10> TS_CLK TS_CLK 145 TS_CLK(GPIO) IDAC_OUT_X 2 IDAC_CVBS_OUT IDAC_CVBS_OUT <7>
IDAC_OUT_B 3
IDAC_OUT_G 4
PM_SPI_WPN PM_SPI_WPN 105 PM8_(SPI_WPN)
Video DAC IDAC_OUT_R 5
PM_SPI_DO PM_SPI_DO 104 PM7_(SPI_DO) R5 75R1%
PM_SPI_CZ PM_SPI_CZ 103 PM6_(SPI_CZ1)
PM_SPI_DI PM_SPI_DI 102 PM3_(SPI_DI) Serial Flash
PM_SPI_CK PM_SPI_CK 101 PM2_(SPI_CK)
LINEOUT_R0 10 LINE_R LINE_R <7> C
LINEOUT_L0 11 LINE_L LINE_L <7>
142 SM0_CLK
141 SM0_IO SPDIF_IN_(TDI) 198 R13 C8
139 SM0_VCC SPDIF_OUT 197 SPDIF 22R SPDIF_OUT <7>
138 SM0_RST
137 SM0_CD Smart Card Audio I2S_OUT_SD0_(TDO) 196
I2S_OUT_MCK_(TMS) 195 20pF
178 SM0_VCC_SWITCH_(GPIO) I2S_OUT_WS_(TCK) 194
C0402
<10> FE_RST FE_RST 179 SM0_C4_(GPIO) I2S_OUT_BCK_(RSTZ) 193
180 SM0_C8_(GPIO) I2S_OUT_MUTE_(DINT) 192

System XTAL <6> IR_IN

ANT_PWR_CTRL
IR_IN 95 IRIN
Debug port
HW_RESET 107 RESET
MSD7831 UART_TX/I2CS_SDA 98 UART-TX
UART UART_RX/I2CS_SCK 97 UART-RX
C16 XTAL_OUT 162
2
33pF 1
C0402 XTAL_OUT
XTAL_IN 161 XTAL_IN R174 4.7K
+3.3V_STANDBY
2

Y3 MSD7831 R188 4.7K

24M(20PF)(30R)(20PPM)
CRYSTAL_SMD
1

C14 33pF
Crystal: 2 1
C0402
24M B

+3.3V_STANDBY
Cl = 20pF
RR < 30R
20PPM
1

C72
R96
Reset Circuit 100nF
2

C0402
1K
+3.3V_STANDBY U24
R97 R0402
100K_5%
R0402 HW_RESET PM_SPI_CZ 1 8
CS VCC
PM_SPI_DO 2 DO HOLD 7
PM_SPI_WPN 3 WP/VPP CLK 6 PM_SPI_CK
4 VSS DI 5 PM_SPI_DI
C173 R249
33pF
C0402 SERIAL FLASH 10K EN25Q32B
R0402

ORG MStar Semiconductor(SZ),Inc.

Title
MSD7831 HD STB
Size Document Number Rev
E MSD7831_A(Input/Output) 1.1

Date: Friday, January 16, 2015 Sheet 2 of 10

5 4 3 2 1
 5 4 3 2 1

U6-B

GPIO NAND FLASH

11> PD_CTRL PD_CTRL 108 PM4_(PD_CTRL)
96 HDMI_CEC_(PM_GPIO) NAND_AD0_(GPIO) 128
99 129 D
<6> FP_DATA PM5_(PM_RX__LED[1]) NAND_AD1_(GPIO
<6> FP_CLK 100 PM1_(PM_TX__LED[0]) NAND_AD2_(GPIO) 130
> ANT_OVERLOAD ANT_OVERLOAD 115 SAR3_(AC_DET) NAND_AD3_(GPIO) 131
<7> MUTE_CTRL MUTE_CTRL 114 SAR2_(PM_GPIO) NAND_AD4_(GPIO) 132
113 SAR1_(PM_GPIO) NAND_AD5_(GPIO) 133
112 SAR0_(PM_GPIO) NAND_AD6_(LED[0]) 134
NAND_AD7_(LED[1]) 135
PWM2 111 PWM2_(SPI_CS1N) NAND_WEZ_(SPI_HOLDN) 126
PWM1 110 PWM1_(PM_GPIO) NAND_ALE_(SPI_SCK) 125
PWM0 109 PWM0_(PM_GPIO) NAND_CLE_(SPI_DI) 123
NAND_CEZ_(SPI_CZ2) 122
199 GPIO_(TRST_N) NAND_REZ_(SPI_DO) 121
NAND_WPZ_(GPIO) 127
10> FE_SDA FE_SDA 144 I2CM0_SDA NAND_RBZ_(SPI_WPN) 120
10> FE_SCL FE_SCL 143 I2CM0_SCL
MSD7831

<6> HDMI-TXHDP HDMI-TXHDP 200 HDMI_HPD

<6> HDMI-TXSDA HDMI-TXSDA 202 HDMI_SDA
<6> HDMI-TXSCL HDMI-TXSCL 204 HDMI_SCL DM_P0 170 USB0_DM USB0_DM <6>
<6> HDMI-TXCLKN HDMI-TXCLKN 206 HDMI_CLK_M DP_P0 171 USB0_DP USB0_DP <6> C
<6> HDMI-TXCLKP HDMI-TXCLKP 207 HDMI_CLK_P
<6> HDMI-TX0N HDMI-TX0N 209 HDMI_CH0_M HDMI USB PORT
<6> HDMI-TX0P HDMI-TX0P 210 HDMI_CH0_P DM_P1 118
<6> HDMI-TX1N HDMI-TX1N 212 HDMI_CH1_M DP_P1 119
<6> HDMI-TX1P HDMI-TX1P 213 HDMI_CH1_P
<6> HDMI-TX2N HDMI-TX2N 215 HDMI_CH2_M
<6> HDMI-TX2P HDMI-TX2P 216 HDMI_CH2_P

MSD7831

+3.3V_STANDBY

R69 1K B

CHIP_CONFIG[2]
R0402
HW STRAP
PWM2

R73 NC R2 4K7
R0402 R0402
R0402_1K_5%
CHIP_CONFIG[1]
PWM1
R82 1K
R0402
CHIP_CONFIG[0] HW CONFIG[2:0]
PWM0 [2:0]: PWM2, PWM1, PWM0
3¡¦h0 MIPS_SPI_NOR_NONPM
3¡¦h1 MIPS_SPI_NOR_PM
3¡¦h2 PM51_SPI_NOR_PM
3¡¦h3 MIPS_ROM_NAND A
3¡¦h4 MIPS_ROM_SPI_NAND
3¡¦h5 DBUS ORG MStar Semiconductor(SZ),Inc.
3¡¦h6 SBUS Title
MSD7831 HD STB
Size Document Number Rev
E MSD7831_B(GPIO/Memery) 1.1

Date: Friday, January 16, 2015 Sheet 3 of 10

5 4 3 2 1
 5 4 3 2 1

U6-C

VCC1_22V
VCC1_22V

<5> MDATA4 MDATA4 15 DDR3_DQ4/IO[48]

<5> MDATA6 MDATA6 16 DDR3_DQ6/IO[47] VDDP2 136 VCC3_3V_PD D
MDATA2 18 169 C33 C35 C36 C37 C38 C39 C41 C42
<5> MDATA2 DDR3_DQ2/IO[46] AVDD33_USB0 VCC3_3V_PD 10uF/10V 4.7uF/6.3V 100nF/10V 100nF/10V 100nF/10V 100nF/10V 100nF/10V 100nF/10V
<5> MDATA0 MDATA0 19 DDR3_DQ0/IO[45] VDDP1 188
DQM1 21 C0805 C0603 C0402 C0402 C0402 C0402 C0402 C0402
<5> DQM1 DDR3_DQM1/IO[44]
<5> MDATA11 MDATA11 22 DDR3_DQ11/IO[43] AVDD33_AUSDM 12 VCC3_3V_PD
<5> MDATA13 MDATA13 24 DDR3_DQ13/IO[42]
<5> MDATA15 MDATA15 25 DDR3_DQ15/IO[41] AVDD_PLL 54 VCC3_3V_PD VCC1_22V
<5> MDATA9 MDATA9 28 DDR3_DQ9/IO[40] AVDD_PLL 53
<5> DQS0P DQS0P 29 DDR3_DQS0/IO[39]
<5> DQS0M DQS0M 30 DDR3_DQSB0/IO[38] AVDD33_IDAC 1 VCC3_3V_PD
<5> DQS1P DQS1P 31 DDR3_DQS1/IO[37] (AVDD33_IDAC) 6
DQS1M 32 C43
<5> DQS1M DDR3_DQSB1/IO[36] 100nF/10V
<5> MDATA12 MDATA12 33 DDR3_DQ12/IO[35] AVDD33_HDMITX 205 VCC3_3V_PD
MDATA8 36 C0402
<5> MDATA8 DDR3_DQ8/IO[34] VCC3_3V_PD VCC3_3V_PD
<5> MDATA14 MDATA14 37 DDR3_DQ14/IO[33] AVDD33_DADC 159 VCC3_3V_PD VCC1_22V
<5> MDATA10 MDATA10 40 DDR3_DQ10/IO[32]
<5> DQM0 DQM0 41 DDR3_DQM0/IO[31] AVDD33_ETH 163 VCC3_3V_PD
<5> MDATA3 MDATA3 43 DDR3_DQ3/IO[30]
<5> MDATA1 MDATA1 44 DDR3_DQ1/IO[29]
<5> MDATA5 MDATA5 46 DDR3_DQ5/IO[28] AVDD33_USB1_NODIE 117 +3.3V_STANDBY
<5> MDATA7 MDATA7 47 DDR3_DQ7/IO[27]
MCLK 51 160 C63 C53
<5> MCLK DDR3_MCLK/IO[26] AVDD33_DMPLL +3.3V_STANDBY 100nF/10V 100nF/10V
<5> MCLKZ MCLKZ 52 DDR3_MCLKZ/IO[25] MSD7831 C0402 C0402

<5> MCSB MCSB 57 DDR3_CSB/IO[24] (VDDC2) 174 VCC1_22V VCC3_3V_PD

<5> MCKE MCKE 58 DDR3_CKE/IO[23] VDDC2 173
<5> MADR10 MADR10 59 DDR3_A10/IO[22] VDDC4 124
<5> MBA1 MBA1 60 DDR3_BA1/IO[21] VDDC3 140
VCC3_3V_PD VCC3_3V_PD
<5> MADR12 MADR12 61 DDR3_A12/IO[20] VDDC5 93
MADR4 62 92 C
<5> MADR4 DDR3_A4/IO[19] (VDDC5)
<5> MADR6 MADR6 66 DDR3_A6/IO[18] (VDDC5) 91
<5> MADR8 MADR8 67 DDR3_A8/IO[17] (VDDC5) 90
MADR11 68 65 C60 C66
<5> MADR11 DDR3_A11/IO[16] VDDC1 100nF/10V 100nF/10V
<5> MADR14 MADR14 69 DDR3_A14/IO[15]
MADR1 70 56 C0402 C0402
<5> MADR1 DDR3_A1/IO[14] DVDD_DDR VCC1_22V
<5> MWEZ MWEZ 71 DDR3_WEZ/IO[13]
<5> MBA2 MBA2 74 DDR3_BA2/IO[12] DVDD_DDR_RX 38 VCC1_22V
<5> MADR0 MADR0 75 DDR3_A0/IO[11]
<5> MADR2 MADR2 76 DDR3_A2/IO[10] AVDDL_HDMITX 211 VCC1_22V
<5> MADR13 MADR13 77 DDR3_A13/IO[9]
<5> MADR9 MADR9 78 DDR3_A9/IO[8] VDDIO_CMD 88 +1_5V_DDR VCC3_3V_PD VCC3_3V_PD
<5> MRST MRST 79 DDR3_RSTZ/IO[7] VDDIO_CMD 55 +1_5V_DDR
<5> MADR7 MADR7 80 DDR3_A7/IO[6] DDR3 x16 VDDIO_CMD 72 +1_5V_DDR
<5> MADR5 MADR5 81 DDR3_A5/IO[5] VDDIO_CMD 64
<5> MADR3 MADR3 82 DDR3_A3/IO[4] VDDIO_DATA 49 +1_5V_DDR
MBA0 83 42 C68 C73
<5> MBA0 DDR3_BA0/IO[3] VDDIO_DATA 100nF/10V 100nF/10V
<5> MCASZ MCASZ 84 DDR3_CASZ/IO[2] VDDIO_DATA 34
MODT 85 26 C0402 C0402
<5> MODT DDR3_ODT/IO[1] VDDIO_DATA
<5> MRASZ MRASZ 86 DDR3_RASZ/IO[0] VDDIO_DATA 20
(AVSS_USB_P0)
(AVSS_HDMITX)
(AVSS_HDMITX)
(AVSS_HDMITX)

(AVSSIO_DATA)

(AVSSIO_DATA)
(AVSSIO_DATA)
(AVSSIO_DATA)
(AVSSIO_DATA)

14
(AVSSIO_CMD)
(AVSSIO_CMD)

VDDIO_DATA
(AVSSIO_CMD

DVDD_NODIE
(DVSS_DDR)

GND_EFUSE
(EPAD_VSS)

(EPAD_VSS)
(AVSS_ETH)

(AVSS_AU)

VDDIO_MCLK 50 +1_5V_DDR
9 AU_VRM
AU_VAG

+3.3V_STANDBY
EPAD
(VSS)
(VSS)
(VSS)

(VSS)
(VSS)

VCC3_3V_PD VCC3_3V_PD +3.3V_STANDBY

AU_VAG
214
208
203
201
187
175
172
168
94
89

87
73
63

48
45
39
35
27
23
17
13
7

217

DVDD_NODIE 116

106

MSD7831
GND

C75 C80 B
100nF/10V 100nF/10V C59
C0402 C0402 100nF/10V
C156 C0402

1uF/10V
C0402 C175
1uF/6.3V/X5R
C0402

+1_5V_DDR
+1_5V_DDR +1_5V_DDR VCC3_3V_PD +3.3V_STANDBY
VCC3_3V_PD +3.3V_STANDBY

C47 C48 C49 C160 C50 C51 C54 C55 C56 C158
4.7uF/6.3V 100nF/10V 100nF/10V 100nF/10V 100nF/10V 100nF/10V 100nF/10V 100nF/10V 100nF/10V 100nF/10V
C0603 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C79
C76 C77 C78 100nF/10V
10uF/10V 100nF/10V 100nF/10V C0402
C0805 C0402 C0402

A
+1_5V_DDR +1_5V_DDR +1_5V_DDR

C176
100nF/10V C57 C155 C168 ORG MStar Semiconductor(SZ),Inc.
C0402 100nF/10V 100nF/10V 100nF/10V
C0402 C0402 C0402 Title
MSD7831 HD STB
Size Document Number Rev
E MSD7831_C(Power/DDR) 1.1

Date: Friday, January 16, 2015 Sheet 4 of 10

5 4 3 2 1
 5 4 3 2 1

MRASZ R150 56R DDR3_RASZ

DDR3 Damping Resistors
<4> MRASZ R0402
1V5D MODT R155 470R DDR3_ODT
<4> MODT R0402
Close to DDR Power Pin
R30 0RX4
8 6 4 2
7 5 3 1

D
C146 C147 C142 C141 C140 C139 C148 R115 56RX4 MDATA7 1 2 MDATA7
10uF/10V 100nF/10V 100nF/10V 100nF/10V 100nF/10V 100nF/10V 100nF/10V 8 7 <4> MDATA7 3 4
2 4 6 8

1 3 5 7

<4> MCASZ MCASZ DDR3_CASZ

C0805 C0402 C0402 C0402 C0402 C0402 C0402 MBA0 6 5 DDR3_BA0 MDATA3 5 6 MDATA3
<4> MBA0 4 3 <4> MDATA3 7 8
2 1

R29 0RX4
8 6 4 2
7 5 3 1

MADR3 R123 110R DDR3_A3 MDATA10 1 2 MDATA10

<4> MADR3 R0402 <4> MDATA10 3 4
1V5D MADR5 R125 56R DDR3_A5 MDATA14 5 6 MDATA14
<4> MADR5 R0402 <4> MDATA14 7 8

C159 C154 C167 C161 C172

100nF/10V 100nF/10V 100nF/10V 100nF/10V 100nF/10V MADR7 R147 56R DDR3_A7 R28 0RX4
C0402 C0402 C0402 C0402 C0402 <4> MADR7 R0402
8 6 4 2
7 5 3 1

MRST R148 1K DDR3_RESET DQS1M 1 2 DQS1M

<4> MRST R0402 <4> DQS1M 3 4
<4> DQS1P DQS1P DQS1P
5 6
7 8
R107 56RX4
8 7
2 4 6 8

1 3 5 7

<4> MADR9 MADR9 DDR3_A9

MADR13 6 5 DDR3_A13 MDATA9 R130 0R MDATA9
<4> MADR13 4 3 <4> MDATA9 R0402
1V5D 2 1 R24 0RX4
8 6 4 2
7 5 3 1

MDATA15 1 2 MDATA15
1V5D R105 56RX4 <4> MDATA15 3 4
U8 8 7 5 6 C
2 4 6 8

1 3 5 7

<4> MADR2 MADR2 DDR3_A2 <4> DQM1 DQM1 DQM1

DDR3_128mb/1600Mbps MADR0 6 5 DDR3_A0 7 8
<4> MADR0 4 3
IC-96P-TFBGA-DDR3
G7
D9

D2
C9
C1
R9
R1
N9
N1
K8
K2

B2

H9
H2

E9

A1
A8
F1

R90 2 1 R16 0RX4

1K_1%
8 6 4 2
7 5 3 1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

R0402 MDATA0 1 2 MDATA0

<4> MDATA0 3 4
MVREFCA
MBA2 R198 56R DDR3_BA2 MDATA4 5 6 MDATA4
1 2 3 7 8 9 C96 C97 <4> MBA2 R0402 <4> MDATA4 7 8
DDR3_A0 N3 A0 DMU D3 DQM1
DDR3_A1 P7 A C7 DQS1P R91 100nF/10V 1nF/50V MWEZ R186 150R DDR3_WEZ
A1 VDDQ DQU5 DQU7 DQU4 VDDQ VSS DQSU 1K_1% C0402 C0402 <4> MWEZ R0402
DDR3_A2 P3 A2 DQSU B7 DQS1M
DDR3_A3 N2 B R0402
A3 VSSQ VDD VSS DQSU# DQU6 VSSQ
DDR3_A4 P8 A4 DQU0 D7 MDATA8
DDR3_A5 P2 C C3 MDATA9 R101 56RX4 MDATA5 R113 0R MDATA5
A5 VDDQ DQU3 DQU1 DQSU DQU2 VDDQ DQU1 8 7 <4> MDATA5 R0402
2 4 6 8

1 3 5 7

DDR3_A6 R8 A6 DQU2 C8 MDATA10 <4> MADR1 MADR1 DDR3_A1

DDR3_A7 R2 D C2 MDATA11 MADR14 6 5 DDR3_A14
A7 VSSQ VDDQ DMU DQU0 VSSQ VDD DQU3 <4> MADR14 4 3
DDR3_A8 T8 A8 DQU4 A7 MDATA12 1V5D 7
R33 8
0RX4
E 2 1
1 3 5 7

2 4 6 8

DDR3_A9 R3 A9 DQU5 A2 MDATA13 <4> MDATA1 MDATA1 5 6 MDATA1

DDR3_A10 L7 VSS VSSQ DQL0 DML VSSQ VDDQ B8 MDATA14 3 4
A10 F DQU6
DDR3_A11 R7 A11 DQU7 A3 MDATA15 <4> DQM0 DQM0 1 2 DQM0
DDR3_A12 N7 VDDQ DQL2 DQSL DQL1 DQL3 VSSQ R99 56RX4
A12 G R106 8 7
2 4 6 8

1 3 5 7

<4> MADR11 MADR11 DDR3_A11

DDR3_BA0 M2 VSSQ DQL6 DQSL# VDD VSS VSSQ E7 DQM0 1K_1% MADR8 6 5 DDR3_A8
BA0 H DML R0402 <4> MADR8 4 3
DDR3_BA1 N8 BA1 DQSL F3 DQS0P
DDR3_BA2 M3 VREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ G3 DQS0M 2 1 7 8
BA2 J DQSL R75 0RX4
1 3 5 7

2 4 6 8

MVREFDQ <4> MDATA8 MDATA8 5 6 MDATA8

DDR3_CSZ L2 NC VSS RAS# CK VSS NC E3 MDATA0 3 4
CS K DQL0 C98 C99
DDR3_RASZ J3 RAS DQL1 F7 MDATA1 <4> MDATA12 MDATA12 1 2 MDATA12
DDR3_CASZ K3 ODT VDD CAS# CK# VDD CKE F2 MDATA2 R117 100nF/10V 1nF/50V R95 56RX4
CAS L DQL2 1K_1% C0402 C0402 8 7
2 4 6 8

1 3 5 7

DDR3_WEZ L3 WE DQL3 F8 MDATA3 <4> MADR6 MADR6 DDR3_A6 B

DDR3_ODT K1 NC CS# WE# A10 ZQ NC H3 MDATA4 R0402 MADR4 6 5 DDR3_A4
ODT M DQL4 <4> MADR4 4 3
DQL5 H8 MDATA5
MVREFCA M8 VSS BA0 BA2 NC VREFCA VSS G2 MDATA6 2 1 7 8
VREFCA N DQL6 R72 0RX4
1 3 5 7

2 4 6 8

DQL7 H7 MDATA7 <4> DQS0M DQS0M 5 6 DQS0M

J1 VDD A3 A0 A12 BA1 VDD DQS0P 3 4 DQS0P
NC1 P R85 56RX4 <4> DQS0P
J9 NC2 H1 MVREFDQ 1 2
VSS A5 A2 A1 A4 VSS VREFDQ 8 7
2 4 6 8

1 3 5 7

L1 NC3 <4> MADR12 MADR12 DDR3_A12

L9 R J7 DDR3_MCLK MBA1 6 5 DDR3_BA1
NC4 VDD A7 A9 A11 A6 VDD CK <4> MBA1 4 3
M7 NC5 CK K7 DDR3_MCLKZ
DDR3_A13 T3 T K9 DDR3_CKE 2 1
A13 VSS RST# A13 A14 A8 VSS CKE
DDR3_A14 T7 A14 RESET T2 DDR3_RESET 7
R81 8
0RX4
1 3 5 7

2 4 6 8

<4> MDATA13 MDATA13 5 6 MDATA13

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

3 4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

R144 R145 R262 MDATA11 1 2 MDATA11

ZQ

100R_5% 100R_5% 10K_5% R195 56R <4> MDATA11

<4> MADR10 MADR10 DDR3_A10
R0402 R0402 R0402 R0402
L8
T9
T1
P9
P1
M9
M1
J8
J2
G8
E1
A9
G9
G1
F9
E8
E2
D8
D1
B9
B3
B1

R146 CLK-T MCKE R196 130R DDR3_CKE

240R_1% <4> MCKE R0402
R0402 ZQ C100 7 8
10nF/16V R84 0RX4
1 3 5 7

2 4 6 8

<4> MDATA2 MDATA2 5 6 MDATA2

C0402 MCSB R102 56R DDR3_CSZ 3 4
<4> MCSB R0402
<4> MDATA6 MDATA6 1 2 MDATA6

MCLKZ R92 0R DDR3_MCLKZ

R143 <4> MCLKZ R0402
10K_5% MCLK R93 0R DDR3_MCLK
R0402 <4> MCLK R0402
MRST 1V5D A

ORG MStar Semiconductor(SZ),Inc.

Title
MSD7831 HD STB
Size Document Number Rev
E DDR3 1.1

Date: Friday, January 16, 2015 Sheet 5 of 10

5 4 3 2 1
 5 4 3 2 1
VCC5V_PD

CN6 VCC5V_PD
HDMI_CON J2
2

20 USB1
C26 SHIELD VCC5V_PD VCC5V_PD
R98 R124 10uF 21 SHIELD 1 5V
2

1K8 1K8 18 +5V <3> USB0_DM 2 DM

17 CEC/DDC_GND <3> USB0_DP 3 DP
1

15 4
G2
G1

<3> HDMI-TXSCL
HDMI-TXSCL DDC_SCL GND
<3> HDMI-TXSDA HDMI-TXSDA 16 DDC_SDA D
13
6
5

R0402 R0402 CEC

<3> HDMI-TXHDP HDMI-TXHDP 19 HPD
22 SHIELD
2

2 DAT2_SHIELD USB1A-TYPE
R137 5 DAT1_SHIELD
8 DAT0_SHIELD
100K 11 CLK_SHIELD
23
1

SHIELD
<3> HDMI-TX0P HDMI-TX0P HDMI-TX0P 7 DAT0+
<3> HDMI-TX0N HDMI-TX0N HDMI-TX0N 9 DAT0-
HDMI-TX1P HDMI-TX1P R0402 4
<3> HDMI-TX1P DAT1+
<3> HDMI-TX1N HDMI-TX1N HDMI-TX1N 6 DAT1-
<3> HDMI-TX2P HDMI-TX2P HDMI-TX2P 1 DAT2+
<3> HDMI-TX2N HDMI-TX2N HDMI-TX2N 3 DAT2-

<3> HDMI-TXCLKP HDMI-TXCLKP HDMI-TXCLKP 10 CLK+

<3> HDMI-TXCLKN HDMI-TXCLKN HDMI-TXCLKN 12 CLK-

HDMI-A01377

HDMI-TX2P HDMI-TX2P HDMI-TX0P HDMI-TX0P C

HDMI-TX2N HDMI-TX2N HDMI-TX0N HDMI-TX0N

U7
IR/RX
HDMI-TX1P HDMI-TX1P HDMI-TXCLKP HDMI-TXCLKP

HDMI-TX1N HDMI-TX1N HDMI-TXCLKN HDMI-TXCLKN

1
2
3
1
2
3

+3.3V_STANDBY
0.15pF ESD
<2> IR_IN IR_IN

USB POWER
USB
CONTROL
POWER CONTROL

B
VCC5V_PD VCC5V_PD
+3.3V_STANDBY

LED_BI-COLOUR
1

C25
LED4 100nF/10V C565
C0402 10uF
2

C0805

R10
470R LED1-R-B
.

PD_CTRL

R128 R129
470R 470R

<6> FP_DATA
. . R0402
<6> FP_CLK
R0402 A

ORG MStar Semiconductor(SZ),Inc.

Title
MSD7831 HD STB
Size Document Number Rev
E Digital_Port 1.1

Date: Friday, January 16, 2015 Sheet 6 of 10

5 4 3 2 1
 5 4 3 2 1

J4
<2> IDAC_CVBS_OUT IDAC_CVBS_OUT CVBS IDAC_CVBS_OUT RCA-413B

<2> SPDIF_OUT SPDIF_OUT

SPDIF 3 1 IDAC_CVBS_OUT IDAC_CVBS_OUT
C210 AUDIO_L AUDIO_L 4 2 AUDIO_R AUDIO_R
C0402 47pF
5
6

RCA2X2
.

R77 10K
R0402

BC74
.

AUDIO_R AUDIO_R
120PF . R11
C0402 620R . R89
100k
BC76 R80 DIO2112
.

<2> LINE_R LINE_R 2 -IN1

4.7K 1 3 R0402 C
1UF/16V +IN1 OUT1
.

VCC3_3V_PD 7 BC77 1UF

R0402 CN C0402
C0402 9 PVDD
8
.

CP
BC81 10 PGSS
1UF 4 SGND
BC79 5 MUTE_CTRL MUTE_CTRL <3> VCC3_3V_PD
.

EN
.

6 PVSS NC/UCP 11 1K R76

C0402 R0402
BC82 R86 14 +IN2
1UF 12
.

OUT2
.

<2> LINE_L LINE_L C0402 13 R79

-IN2
1K
4.7K U5
1UF/16V .
SGM8903_0
R0402
C0402
R0402
.

BC80 120PF
C0402
.

R88 10K AUDIO_L B

R0402
.
. R12 R94
620R 100k

R0402

ORG MStar Semiconductor(SZ),Inc.

Title
MSD7831 HD STB
Size Document Number Rev
E Video&Audio OUT 1.1

Date: Friday, January 16, 2015 Sheet 7 of 10

5 4 3 2 1
 5 4 3 2 1

D D

C C

3_3V_TU VDD_1_8V

+5VANT
C81 C82
B C30 0402 DNP 0402 DNP B
0402 C31 15PF 15PF
0.1uF 0402 2 1 SDA_TUNER
0.1uF SCL_TUNER
Y4
3_3V_TU 16MHZ
LOOP
1

R296 R302
C256 C255
C29
.

2 1 L29 100P 2.7K 2.7K 100P

2

C18 0402
10NF FB120
560pF
VCC3_3V_PD
C24 100PF
.

2
C12 1 L0402
0.1UF C21 C0402
25

24

23

22

21

20

19

100PF L0402 L28 U1

18NH
L8
.330NH

GND2

LT_OUT

LT_AC_GND

VDD_3P3_1

VDD_1P8_3

XTAL_P

XTAL_N

L27
R6
270R

33NH L26
R3

10K 15nH
R0402

L2 NC/0R L0402 C20

L3 . L1
5.6pF
L23 1NF
.

R8 9.1NH 1 18
.

C13 C15 68NH 68NH GND1 CLK_OUT

4.7NF 4.7NF L0402 L0402 C9 1nF
1 L0402 2
.

.
.

RFIN C6 C19 Q1
.

47pF 2
C1 1 4.7nF BFR196C0402 L0402
NPN-SOT143 2 LNA_INP SDA 17 SDA_TUNER SDA_TUNER
33pF C0402 C0402
C17
. 33pF
L30
1NF
3

3 LNA_INN SCL 16 SCL_TUNER SCL_TUNER

1 2
C0402
L20 15nH . L25 L0402
MxL608_24
BAV99 82nH
D3 4 15 3_3V_TU
VDD_1P8_1 VDD_IO
.

L0402
2

L0402 VDD_1_8V 5 GPO GND_DIG 14

C61
0402
0.1uF
6 13 C52
AGC VDD_1P2 0402
VDD_3P3_2

VDD_1P8_2

0.1uF
RESET_N
IF_OUTP

IF_OUTN

AS
7

10

11

12

C64 C65 L0402

0402 0402 FB1000R
4700pF 4700pF
C67 2 1 VDD_1_8V
IF_AGC_M
0402
RF1 0.1uF
L24

O23B C69
0402
1uF
TC22 TC23
1nF 1nF
OUT 1 RFIN RFIN LT LOOP
IN 2 LT
SHIELD_SS01

TD2
3 BAV99 3_3V_TU
GND
GND 4
GND 5
GND 6
7
DIF_IP_M

DIF_IM_M

GND +3.3V_STANDBY 3_3V_TU

GND 8
3_3V_TU
L6
A GZ2012D102

1 2
1

C4 C5
10uF 0.1uF 3_3V_TU
2

R43
0402
500K

VCC5V +5VANT C88

0402
1uF

R14 U3
2.7R L7
1 12 2 5 IN OUT 1
FB120R
.
1

C7 GND 2 C10
R18
10K

10uF 10uF
R15
10K

CAP_1 C11
C0603 4 EN ISET 3 C0603
2

2
R17
33K

0.1uF
2

STI9712

ANT_PWR_CTRL
5 3 2

Title

ANT_OVERLOAD
Size Document Number Rev
E ?

Date: Friday, January 16, 2015 Sheet 8 of 10

 5 4 3 2 1
VCC3_3V_PD
. VCC3_3V_PD

VCC1_22V
XTALO

XTALI
FB120R

VCC1_22V
L0402

XTALI
L5

XTALO
C2 0.1uF
2 1

2 1 VCC3_3V_PD
1M R299
C3
10NF
2 1
D R311 R310 D
1

C267
30.4M(20PF)(30R)(20PPM)
1

C268
2.7K 2.7K
CRYSTAL_SMD

36

35

34

33

32

31

30

29

28

27

26

25

VCC3_3V_PD 12pF U2
VCC3_3V_PD 12pF
2
2

GND

AVDD33

CAVDD

ADDR

XTALO/CLK_OUT

XTALI

DISEQC_IN

DISEQC_OUT

GPO1

VDD33

TSET_MODE

CVDD

FE_SDA
Y6

VCC3_3V_PD
FE_SCL
2

C279 C281 C282 C283

0.1uF 0.1uF 0.1uF 0.1uF 37 24

1

SIFIP SDAS 10K

38 23
SIFIN SCLS R306
39 22 VCC1_22V
SIFQP CVDD
40 21 FE_RST
SIFQN RESET
41 20
RSSI CVDD VCC1_22V
42 19
49

CLK_IO VDD33 VCC3_3V_PD

STATUS

IP_M 43 18
VCC1_22V VCC1_22V 2 1 TIFP TS7 TS_D7
100NF C303
IM_M 100NF
2 C300
1 44
TIFN TS6
17
TS_D6
45 16
VCC3_3V_PD VCC3_3V_PD VCC3_3V_PD VDD33 TS5 TS_D5
C277
1

46 15
VCC1_22V CVDD TS4 TS_D4
10uF/16V
47 14 2.7K
GPO2 TS3 TS_D3 R9
1

C298 C299 C297 IF-AGC 48 13

2

VCC1_22V 10uF/16V 0.1uF 0.1uF GPO3 TS2 TS_D2

2

TSSYNC
STATUS
VDD33

TSVLD

TSCLK
2

C286 C287C288C289C290 C294

SDAM

CVDD
SCLM

GPO4

GPO5

TS0

TS1

0.1uF0.1uF0.1uF0.1uF0.1uF 0.1uF
1

C ATBM7812_7X7 C
1

10

11

12
R295
R309

2
100R

100R

1
R297
100K

<10> FE_SDA FE_SDA

<10> FE_SCL FE_SCL
VCC3_3V_PD
VCC1_22V

TS_D1
TS_VLD
TS_SYNC

TS_CLK

TS_D0
STATUS
SDA_TUNER

SCL_TUNER

<2> FE_RST FE_RST

<2> TS_D7 TS_D7 TS_D7

<2> TS_D6 TS_D6 TS_D6
<2> TS_D5 TS_D5 TS_D5
<2> TS_D4 TS_D4 TS_D4
<2> TS_D3 TS_D3 TS_D3
<2> TS_D2 TS_D2 TS_D2 R304
TS_D1 TS_D1 1K R303
<2> TS_D1 10K
<2> TS_D0 TS_D0 TS_D0 IF_AGC_M IF-AGC
<2> TS_SYNC TS_SYNC TS_SYNC
2

TS_VLD TS_VLD C271

2

<2> TS_VLD
<2> TS_CLK TS_CLK TS_CLK C269
0.1uF 0.1uF
1
1

B B

Closed demod
IF_AGC_M IF_AGC_M

DIF_IM_M DIF_IM_M
DIF_IP_M DIF_IP_M

R57
DIF_IP_M 0R IM_M
R0402
1

C92 L19
NC NC/1u8H
C0402 L0402 ORG MStar Semiconductor(SZ),Inc.
R56 Title
2

DIF_IM_M 0R IP_M MSD7C51G HD STB

R0402
Size Document Number Rev
E Front End 1.1

Date: Friday, January 16, 2015 Sheet 9 of 10

A A

Title

Size Document Number Rev

E ?

Date: Friday, January 16, 2015 Sheet 9 of 10

5 4 3 2 1
 5 4 3 2 1

VCC5V
J7 VCC5V
+ 1
VCC5V VCC5V_PD
R1
NC
3
2 . BC1
+ EC16
390K
R0402 RCR1528SJ/AO3401A 2
Q8
3
100nF/16V 470UF/16V
1

KD-017
C83.5MM R7 R206 SOT-23
ANT_OVERLOAD
1

<3>
1

DC_JACK R0402 1K
R201 100K
GND GND R4 R0402
2

100K_1% 1K POWER_ON/OFF
R0402 R0402
2

D
PD_CTRL R203 10K 1 Q17
<3> PD_CTRL 1 2 2N3904
R0402
2

0: OFF Soft Start

1: ON

VCC5V
+3.3V_STANDBY +3.3V_STANDBY VCC3_3V_PD
U9
+3.3V_STANDBY
STI3470 L11
5 IN
SY8113:3A
4.5V-18V INPUT LX 6 . 2
Q14
3

.BC153 VFB = 0.6V

4.7UH
.

SOT-23
.

4 EN 500KHZ 1 SMD0505
. .
1

10UF/16V R19 BS C27 BC155 BC154 RCR1528SJ/AO3401A

R164
10nF .
1

100K C623 C631

2 3 100nF/16V
10UF/16V 10uF 10uF R764
C0603 GND FB C0603 C0603
100K/1%
2

150K
GND C0402 C0603 R0402
2

.
R0402 GND
R163 POWER_ON/OFF
22K/1%

GND
R0402

Soft Start
L4
U10 2.2uH/4.8A-L6.0W6.0H4.5 1.22V@1.3A
VCC5V SMD0505 VCC1_22V
STI3470
5 IN
SY8113:3A LX 6
4.5V-18V INPUT
VFB = 0.6V C22 C23 R23
PD_CTRL 4 EN 500KHZ 1 10uF 10uF 100K_1%
BS C0603 C0603 R0402
C28
100nF
2 3
R1
GND FB
5V-1_2V_FB
C0603
10uF/16V
C178

close to SY8088 R27 R1=((Vout-0.6V)xR2)/0.6V

100K_1%
R0402
B
R2

+1.5V Power

1V5D
VCC3_3V_PD To Prevent Power Noise
U22 AP1117-ADJ
3 VIN VOUT 2
ADJ/GND

VOUT 4
1
1

C625 C627 C626

10uF 10uF C0603

100nF C0402
2

C0805

ORG MStar Semiconductor(SZ),Inc.

Title
MSD7831 HD STB
Size Document Number Rev
E System Power 1.1

Date: Friday, January 16, 2015 Sheet 10 of 10

5 4 3 2 1