Received: 22 August 2019 Revised: 13 December 2019 Accepted: 29 December 2019

DOI: 10.1002/cta.2744

RESEARCH ARTICLE

Low power and area efficient error tolerant adder for image
processing application

M Priyadharshni Sundaram Kumaravel

Department of Micro and Nano

electronics, School of Electronics
Engineering, Vellore Institute of
Techonology, Vellore, India
Correspondence
Sundaram Kumaravel, Department of
Micro and Nano Electronics, School of
Electronics Engineering, Vellore Institute
of Techonology , Vellore, Tamil Nadu,
India.
Email: kumaravel.s@vit.ac.in
Summary
Approximate computing-based arithmetic units are oriented towards reduction
in power, delay, and area. Intrinsic error tolerance capability of emerging appli-
cation domains, like multimedia, Internet of Things (IoT), and image processing
provides better opportunities for optimization of approximate arithmetic units.
In this paper, a novel 1-bit imprecise full adder (IFA) is proposed with less
gate count. Also, two versions of 16-bit error tolerant adders (ETAs), namely
a low power and area efficient error tolerant adder (LETA) and improved low
power and area efficient error tolerant adder (ILETA), are proposed. In these
proposed ETAs, the most significant bit (MSB) segments are realized in same
approach, whereas the least significant bit (LSB) segment of LETA and ILETA
are realized using an existing modified full adder (MFA) and proposed IFAs,
respectively. The proposed and existing ETA adders are implemented using a
Verilog hardware description language (HDL) and synthesized in a Synopsys
electronic design automation (EDA) Tool using Taiwan Semiconductor Man-
ufacturing Company (TSMC) 65nm technology. The proposed (ILETA, LETA)
adders exhibit (55%, 50%) reduction in power consumption and achieve signif-
icant reduction in area (68%, 61%). Further, in this work, a new performance
metric namely power and error product (PEP) is proposed in order to evaluate
the approximate adders in terms of power and error metrics. It is found that the
proposed ILETA achieves a low PEP of 1.05×10−5 compared with other ETAs. To
study the efficacy of the proposed ETA adders in image processing application,
an image blending algorithm is implemented and simulated using MATLAB.
From simulation results, it is observed that the proposed ETA adders exhibit a
high peak signal-to-noise ratio (PSNR).

K E Y WO R D S
approximate carry select adder, approximate computing, approximate full adder, imprecise full
adder, error tolerant adder

1 I N T RO DU CT ION

In error tolerant applications, digital signal processors (DSPs) are used to process digital signals. Error resilience emerging
application such as multimedia, Internet of Things (IoT), and image processing accept the results with some degradation
in the output.1 The arithmetic and logic operations in DSP are performed by using arithmetic units such as adders and

Int J Circ Theor Appl. 2020;1–13. wileyonlinelibrary.com/journal/cta © 2020 John Wiley & Sons, Ltd. 1
2 PRIYADHARSHNI AND KUMARAVEL

multipliers. These arithmetic units determine the computational complexity and performance of the processors. Hence,
optimization of these arithmetic units are necessary to enhance the performance of DSP processors.
In order to process volumnous data in DSP processors, multi-bit high-speed adders are required. Among the existing
multi-bit adders, a carry select adder is the fastest with complexity in hardware. The adders can be realized with lesser
complexity in hardware by adopting approximate computing.
Approximate computing2 provides the best solution in designing arithmetic and logical units by compromising the
accuracy of desired outputs that is suitable for error resilient applications. It supports both the hardware and software
level of abstraction.2 Software level of abstraction is achieved by removing some levels of algorithm. Hardware-level of
abstraction is attained by modification in the hardware architecture. Because the adders are basic units in designing DSP
processors, hardware level of abstraction is adopted for designing approximate adders/multipliers.3,4
The key feature in designing a approximate full adder (AFA) is to reduce the carry propagation time5 and hardware
reduction. A survey of approximate adders are presented in previous studies.6-9 Approximate mirror adders (AMAs)10
are realized with lesser number of transistors. This results in reduction of circuit complexity, node capacitance, and
dynamic power dissipation. Three inexact full adders11 are formulated by adopting the approximation in gate level. The
assumptions made in the above approximate adders increases the probability of error in the output.
The AFA12 is designed to reduce the error probability in outputs with two errors in sum signal and error free carry signal.
In AFA, the carry signal is generated based on the carry generation circuit. Hence, the computational delay of the AFA adder
is more. A modified full adder (MFA)13 is implemented to eliminate the computational delay of carry generation in AFA.
However, the MFA suffers from high error distance compared with its counter parts. The multiplexer based on approximate
full adders (MBAFA)14 is realized with better structural metrics and with less error distance compared with MFAs. As
AFAs are meant for power efficiency, DSP processors can greatly benefit from approximate adders by replacing some of its
arithmetic units. In this paper, an imprecise full adder (IFA) is proposed and utilized in a 16-bit improved low power and
area efficient error tolerant adder (ILETA), and the performances are evaluated based on structural and error analyses.
The paper is organized as follows, section 2 discuss about the existing architecture of error tolerant adders. Section 3
elaborates about the proposed architectures. Section 4 narrates result exploration in terms of structural, error, and image
quality metrics. The conclusion of this paper is explored in section 5.

2 PROPOSED WORKS

2.1 Proposed 1-bit imprecise full adder

As discussed earlier, AFAs are used for realizing the arithmetic units involved in error resilient applications. Hence,
the various AFAs existing in the literatures, namely AFA, MFA, and MBAFA, are shown in Figure 1. For the sake of
comparison of AFAs with regards to exact full adders, the logical expressions for sum and carry signal, no. of gates used
for realizing these adders, and logical gate delays are reported in Table 1.

FIGURE 1 Existing
approximate full adders, A,
approximate full adder (AFA),12
B, modified full adder
(MFA),13 C, multiplexer based on
approximate full adders
(MBAFA)14 (A) (B) (C)

TABLE 1 Logical expression and gate count calculation for exact and existing approximate full adders
Total Logical gate Logical gate
Logical expression Logical expression gate delay in delay in Transistor
Designs for carry signal for sum signal count sum signal carry signal count
EXACT FULL ADDER X1 .X2 + X2 .X3 + X3 .X1 X1 ⊕ X2 ⊕ X3 13 6 5 28
AFA12 X1 .X2 + X2 .X3 + X3 .X1 Carr𝑦 6 4 3 32
MFA13 X1 X1 ⊕ X2 ⊕ X3 8 6 0 20
MBAFA14 X1 X1 .(X2 + X3 ) + X1 (X2 .X3 ) 6 4 0 26

Abbreviations: AFA, approximate full adder; MBAFA, multiplexer based on approximate full adders; MFA, modified full adder.
PRIYADHARSHNI AND KUMARAVEL 3

From Table 1, it is observed that MBAFA outperforms the exact full adder, AFA, and MFA in terms of no. of gate count
and delays. In this paper, an IFA is proposed which is further optimized with less no. of gate counts and delays is shown in
Figure 2. The logical expressions for sum and carry signals, no. of gates used for realizing IFA, and logical gate delays are
reported in Table 2. Table 2 shows that IFA achieves a lower gate count of 5 and logical gate delay of 3 in the sum signal.
Compared to Table 1 and Table 2, it maybe noted that IFA realization is better in terms of no. of gate counts and
delay. Also, the error of IFA is similar to MBAFA. The truth table of the existing AFAs and proposed IFA are shown in
Table 3. From Table 3, it is noted that error distance is calculated for the proposed and existing adders. Error distance15,16
is defined as the difference between inaccurate outputs to the accurate outputs of an approximate adder.

FIGURE 2 Proposed imprecise full adder

TABLE 2 Logical expression and gate count calculation for imprecise full adder (IFA)
Logical expression Logical expression Total gate Logical gate delay Logical gate delay Transistor
Designs for carry signal for sum signal count in sum signal in carry signal count
Proposed IFA X1 X1 (X2 + X3 ) + (X2 .X3 ) 5 3 0 16

TABLE 3 Truth table of Eeact and existing approximate full adders

INPUTS EXACT AFA ED MFA ED MBAFA ED Proposed ED
OUTPUTS 12 13 14 IFA
x1 x2 x3 Carry Sum Carry Sum Carry Sum Carry Sum Carry Sum
0 0 0 0 0 0✓ 1× +1 0✓ 0✓ 0 0✓ 0✓ 0 0✓ 0✓ 0
0 0 1 0 1 0✓ 1✓ 0 0✓ 1✓ 0 0✓ 1✓ 0 0✓ 1✓ 0
0 1 0 0 1 0✓ 1✓ 0 0✓ 1✓ 0 0✓ 1✓ 0 0✓ 1✓ 0
0 1 1 1 0 1✓ 0✓ 0 0× 0✓ −2 0× 1× −1 0× 1× −1
1 0 0 0 1 0✓ 1✓ 0 1× 1✓ +2 1× 0× +1 1× 0× +1
1 0 1 1 0 1✓ 0✓ 0 1✓ 0✓ 0 1✓ 0✓ 0 1✓ 0✓ 0
1 1 0 1 0 1✓ 0✓ 0 1✓ 0✓ 0 1✓ 0✓ 0 1✓ 0✓ 0
1 1 1 1 1 1✓ 0× −1 1✓ 1✓ 0 1✓ 1✓ 0 1✓ 1✓ 0

Abbreviations: AFA, approximate full adder; ED, error distance; IFA, imprecise full adder; MBAFA, multiplexer based on approximate full adders;
MFA, modified full adder.

FIGURE 3 Optimized imprecise full adder

4 PRIYADHARSHNI AND KUMARAVEL

For the sake of clarity, the transistor level schematic of the proposed IFA using 2-NAND gates, 1-OAI logic, and 1-NOT
gate is shown in Figure 3. In that OAI logic needs 6 transistors, NAND gate needs 4 transistors, and NOT gate needs 2
transistors. Therefore, the proposed IFA needs 16 transistors in total, which is less when compared to the transistor count
of existing AFAs.

2.2 Proposed 16-bit low power and area efficient error tolerant adders
Different types of exact multi-bit high speed adders such as a ripple carry adder, carry look ahead adder, carry select
adder, and carry skip adder are realized in the literature. Among all the exact adders, carry select adder remains as a high
speed adder with area overhead. The drawback of area overhead in a carry select adder (CSLA) is overcome by adopting
approximate computing and then named as error tolerant carry select adder (ET_ CSLA). Similar to this realization,
various error tolerant adders are realized in the literature. The brief description of the existing error tolerant adders are
explained below. The analysis of ETAs in terms of gate count are given in Table 4.

2.2.1 Error tolerant carry select adder

A detailed block diagram of the ET_ CSLA is shown in Figure 4. From Figure 4, it may be observed that the ET_ CSLA12 is
formulated by using the AFA as a building block. For A 16-bit ET_ CSLA, it requires 28 AFA and 15 multiplexers. A 1-bit
AFA requires 6 basic gates, whereas one 2:1 multiplexer requires 4 basic gates. Hence, total gate count requires to imple-
ment the 16-bit ET_ CSLA is 228 basic gates and is given in Table 4. The ET_ CSLA is implemented with approximately
50% lesser gates compared to the exact carry select adder (conventional CSLA [Conv CSLA]).

2.2.2 Significant approximation error tolerant carry select adder

A significant approximation error tolerant carry select adder (SAET_ CSLA)12 is implemented to improve the error
probability of ET_ CSLA. The input operand to a 16-bit SAET_ CSLA adder is segregated into a least sig-

TABLE 4 Gate count calculation of 16-bit error tolerant adder

DESIGNS ADDERS MULTIPLEXERS
Adder No of adder Total gates per Total gates No of Gates per Total gates Total gates
Type block adder block (1) mux mux (2) (1+2)
Conv CSLA FA 28 13 364 15 4 60 424
ET_ CSLA12 AFA 28 6 168 15 4 60 228
SAET_ CSLA12 ACC FA 16 13 208 15 4 60 340
INACC AFA 12 6 72
HSETA15 ACC FA 16 13 208 10 4 40 312
INACC MFA 8 8 64
HPETA14 ACC FA 12 13 156 5 4 20 224
INACC MBAFA 8 6 48
LETA ACC LCSLA 8 11 88 - - - 148
INACC MFA,MHA 7,1 8,4 56,4
ILETA ACC LCSLA 8 11 88 - - - 128
INACC IFA 8 5 40

Abbreviations: AFA, approximate full adder; conventional CSLA, Conv CSLA; ED, error distance; ET_ CSLA, error tolerant carry select adder; FA, full adder;
HPETA, high-performance error tolerant adder; HSETA, high-speed error tolerant adder; IFA, imprecise full adder; ILETA, improved Low power and area
efficient error tolerant adder; LETA, low power and area efficient error tolerant adder; MBAFA, multiplexer based on approximate full adders; MFA, modified
full adder; MHA, modified half adder; SAET_ CSLA, significant approximation error tolerant carry select adder.

FIGURE 4 Block diagram of error tolerant carry select adder (ET_ CSLA).12 AFA, approximate full adder
PRIYADHARSHNI AND KUMARAVEL 5

FIGURE 5 Block diagram of significant approximation error tolerant carry select adder (SAET_ CSLA).12 AFA, approximate full adder;
FA, full adder

FIGURE 6 Block diagram of high-speed error tolerant adder (HSETA).15 FA, full adder; MFA, modified full adder

FIGURE 7 Block diagram of high-performance error tolerant adder (HPETA).14 FA, full adder; MBAFA, multiplexer based on
approximate full adders

nificant bit (LSB) segment and most significant bit (MSB) segment. The LSB segment is termed as inac-
curate part because its results in less weight in the output, and the MSB segment is termed as accu-
rate part. The detailed block diagram of SAET_CSLA is shown in Figure 5.
In the SAET_ CSLA, the inaccurate and accurate part is realized by using the AFA and Conv CSLA, respectively. From
Table 4, it may be noted 340 basic gates are used to implement the SAET_ CSLA.

2.2.3 High-speed error tolerant adder

Further, the hardware complexity of the SAET_ CSLA is reduced in a high-speed error tolerant adder (HSETA).15 The
inaccurate part is designed by using 64 basic gates whereas the accurate part is realized by using 248 gates, and it is shown
in Table 4. 312 basic gates are utilized to realize HSETA. The detailed block diagram of HSETA is shown in Figure 6.

2.2.4 High-performance error tolerant adder

The inaccurate part of a 16-bit high-performance error tolerant adder (HPETA)14 is designed by cascading several MBAFA,
and the accurate part is based on Conv CSLA and ripple carry adder and is shown in Figure 7. The gate count of HPETA
is 224 basic gates, it is far less compared with other existing error tolerant adders.
6 PRIYADHARSHNI AND KUMARAVEL

FIGURE 8 Block diagram of low power and area efficient error tolerant adder (LETA). LCSLA, Low power and area efficient carry select
adder; MFA, modified full adder

FIGURE 9 Block diagram of improved low power and area efficient error tolerant adder (ILETA). LCSLA, Low power and area efficient
carry select adder; MFA, modified full adder

2.2.5 Proposed low power and area efficient error tolerant adder
In this paper, two variants of error tolerant adders are proposed, namely an low power and area efficient error tolerant
adder (LETA) and improved low power and area efficient error tolerant adder (ILETA).

LETA
The LETA is constructed by using a MFA and a modified half adder (MHA) in the inaccurate part. In MHA, the sum is
equal to EXOR of both the inputs and the carry signal is equal to the input of the MHA. The MHA produces a one-bit
error in the carry signal. A low power and area efficient carry select adder (LCSLA)17 is utilized in the MSB segment of the
proposed LETA. The LCSLA is implemented by using 7 basic gates and 1 multiplexer. Hence, the accurate part of LETA
is executed with 88 basic gates, and inaccurate part is implemented with 60 basic gates. 148 basic gates are required to
implement LETA, which shows significant reduction in area. The error probability is similar to HSETA. The structure of
LETA adder is shown in Figure 8

ILETA
The ILETA is formulated with a proposed 1-bit IFA in the inaccurate part and accurate part of the ILETA is identical to
the LETA. The advantage of ILETA is that it requires only 40 basic gates for accurate part and 88 basic gates for inaccurate
part with regards to its counter models. The detailed block diagram of the ILETA is shown Figure 9 .
The logical gate count calculation15 of existing error tolerant adders, namely the ET_ CSLA, SAET_ CSLA, HSETA,
HPETA, and proposed error tolerant adders, namely the LETA and ILETA, are compared with the Conv CSLA and is
given in Table 4.
From Table 4, it may be noted that the proposed adders LETA and ILETA achieves the reduction in terms of gate count
compared to existing ETAs.12,14

3 R E S U LT AN D ANALY SIS

3.1 Structural metrics of approximate full adders and ETA in ASIC platform
For the purpose of comparison of existing 1-bit approximate adders and the proposed 1-bit IFA adder is implemented
using a Verilog hardware description language (HDL). Functional verification of these adders are carried out in Ver-
ilog Compiler Simulator (VCS). The synthesized results obtained from Synopsys Design Compiler (DC) using Taiwan
Semiconductor Manufacturing Company (TSMC) 65nm technology are tabulated in Table 5.
Table 5 compiles and compares the proposed IFA with the existing AFAs such as AMA1 , AMA2 , AXA1 , AXA2 , AFA,
MFA, MBAFA in terms of performance metrics like area-delay product (ADP), power-area product (PAP) and power-delay
product (PDP). From the results, the MFA occupies larger area(26.4 𝜇m2 ) and consumes more delay of 0.13 ns, and more
PRIYADHARSHNI AND KUMARAVEL 7

DESIGNS AREA DELAY POWER ADP PDP PAP TABLE 5 Structural analysis of
(𝜇m2 ) (ns) (𝜇W) (𝜇m2 ns) (fJ) (𝜇W.𝜇 m2 ) approximate full adder
Exact fulladder 36 0.13 0.086 4.68 0.011 3.097
AMA1 10 20 0.09 0.0388 1.8 0.003492 0.776
AMA2 10 16.8 0.1 0.0287 1.68 0.00287 0.48216
AXA1 18 19.2 0.1 0.0334 1.92 0.0033 0.641
AXA2 18 21.6 0.1 0.0402 2.16 0.00402 0.868
AFA12 13.2 0.1 0.033 1.32 0.0033 0.430
MFA13 26.4 0.13 0.069 3.43 0.0089 1.808
MBAFA14 13.6 0.1 0.022 1.36 0.0022 0.302
Proposed IFA 10.8 0.1 0.02 1.08 0.002 0.220

Abbreviations: ADP, area delay product; AFA, approximate full adder; ED, error distance; IFA, imprecise full adder;
MBAFA, multiplexer based on approximate full adders; MFA, modified full adder; PAP, power area product; PDP,
power delay product.

FIGURE 10 Comparison of ADP, PDP and

PAP for existing and proposed approximate full
adders. ADP, area-delay product; PAP,
power-area product; PDP, power-delay product
[Colour figure can be viewed at
wileyonlinelibrary.com]

power is consumed by AXA2 . The results of the proposed IFA shows considerable reduction in ADP, PDP, and PAP mea-
sures. The proposed IFA model is found to reduction in area and power by 46%, 48% with increase in delay of 11% when
compared with AMA1 . On comparison with AMA2 , The IFA achieves a reduction in area and power by 35.71% and 30.31%.
The proposed IFA model shows better results than AXA1 by minimizing the area and power by 43.75%, 40.12%. The IFA
accomplishes reduction in area and power of 59%, 23%, and 71% with respect to MFA and 20.59% and 9.09% with respect
to MBAFA.
From Table 5, it is found that the IFA also achieves a reduction in ADP of 40%, 35%, 43.75%, 50%, 18.18%, 68%, and
20% with respect to AMA1 , AMA2 , AXA1 , AXA2 , AFA, MFA, and MBAFA. Similarly, the proposed IFA achieves a lower
PDP of range from 9% to 77% with respect to existing designs. With respect to PAP, the proposed IFA achieves a reduction
of 71.65% compared with AMA1 , 65.68% compared with AXA1 , 48% compared to AFA, 87.84% with respect to MFA, and
27.15% with respect to MBAFA. The comparative analysis of the compound measures of AFAs are given in Figure 10.
From the tabulated values shown in Table 5, it is observed that the proposed IFA outperforms other existing designs with
the minimized measures in ADP, PDP, and PAP, and it is best suited for realizing multi-bit error tolerant adders.
Similarly, the structural analysis for all the ETA is carried out with the netlist and the constraint (SDC file) obtained
from DC are sourced to ICC compiler to generate the layout. The parasitic extraction file (Standard Parasitic Exchange
Format [SPEF] file), netlist, constraint file (SDC file), and the Switching Activity Interchange Format (SAIF) file acquired
from ICC is fed back to prime time for elaborative power analysis. 216 stimulus vectors are generated in VCS and recorded
in a SAIF file. The area, delay values are obtained from ICC and total power attained from prime time (PT) are tabulated
in Table 6. The layout of ILETA which is acquired from ICC is shown in Figure 11
Compound metrics such as Area-Delay Product, Power-Delay Product, and Power-Area Product are calculated and
shown in Figure 11.The layout of ILETA which is acquired from ICC compiler is shown in Figure 12.
8 PRIYADHARSHNI AND KUMARAVEL

TABLE 6 Structural analysis of 16-bit error tolerant adder DESIGNS AREA DELAY POWER PEP
(𝜇m2 ) (ns) (𝜇W) (𝜇 W)
Conv CSLA 1094 0.5 0.013 -
ET_ CSLA12 517.6 0.42 0.0085 7.12×10−3
SAET_ CSLA12 833.2 0.42 0.013 2.19×10−4
HSETA15 691.6 0.4 0.0082 3.03×10−5
HPETA14 550 0.31 0.0092 1.65×10−5
Proposed LETA 422 0.45 0.0066 2.43×10−5
Proposed ILETA 354.4 0.45 0.0058 1.05×10−5
Abbreviations: CSLA, Conv CSLA; ED, error distance; ET_ CSLA, error tolerant carry
select adder; HPETA, high-performance error tolerant adder; HSETA, high-speed error
tolerant adder; ILETA, improved Low power and area efficient error tolerant adder;
LETA, low power and area efficient error tolerant adder; PEP, power errror product.

FIGURE 11 Layout of improved low power

and area efficient error tolerant adder (ILETA)
[Colour figure can be viewed at
wileyonlinelibrary.com]

FIGURE 12 Comparison of ADP, PDP and

PAP for existing and proposed error tolerant
adders. ADP, area-delay product; PAP,
power-area product; PDP, power-delay product
[Colour figure can be viewed at
wileyonlinelibrary.com]
PRIYADHARSHNI AND KUMARAVEL 9

From Table 6, the proposed LETA offers the saving of 28%, 19%, 50%, and 23% power with respect to the HPETA, HSETA,
SAET_ CSLA, ET_ CSLA. It also achieves reduction of 18%, 49%, 38%, and 23% in area with significant increase in delay
of 7%,7%, 12%, and 45% with respect to ET_ CSLA, SAET_ CSLA, HSETA, and HPETA. It also realized with reduction of
ADP by 13%, 46%, 31.35%, and 11.38% and reduction in PDP by 15.97%, 44.65%, 9.09%, and 7.14%, with respect to the ET_
CSLA, SAET_ CSLA, HSETA, HPETA. The LETA is accomplished by consuming 37.05%, 74.35%, 51.15%, and 45.15% PAP
with respect to ET_ CSLA, SAET_ CSLA, HSETA, and HPETA.
Similarly, proposed ILETA provides the area reduction of 31%, 57%, 48%, and 35% with the significant power reduction
of 31%, 55%, 28%, and 36% with respect to the ET_ CSLA, SAET_ CSLA, HSETA, and HPETA. It also shows reduction in
ADP values of 26.64%, 54.43%, 42.35%, and 6.46% and decrease in PDP of 27.17%, 52.29%, 21.21%, and 7.14% in respect of
the ET_ CSLA, SAET_ CSLA, HSETA, and HPETA. The ILETA offers the savings of 52%, 80%, 63%, and 59% PAP values
with respect to the ET_ CSLA, SAET_ CSLA, HSETA, and HPETA.

3.2 Error metrics of approximate full adders and ETA in MATLAB

In this section, to show the compatibility of proposed adders for error tolerant applications, the benchmark metrics are
adopted19-22 and analysed.
From Table 7, it may be noted that the Column 2 represents the number of nonzero error distance in AFAs,
whereas column 3 describes the error rate at the outputs of the adder. Error rate (ER)23 of an approximate adder is
defined as probability of nonzero error distance, ie, the number of incorrect results for different input combinations. It is
calculated as
ER = P(ED ≠ 0) (1)
When compared with existing AFAs, the proposed IFA achieves reduction in gate count by maintaining the same
error rate.
Table 8 reports the erroneous study about mean error distance (MED), normalized error distance (NED), mean absolute
error (MAE), mean squared error (MSE), worst case error (WCE), worst case relative error (WCRE), and mean relative
error distance (MRED) values of existing and proposed adders. For the elaborate error analysis, 1,00,000 random stimulus
vectors are generated and used for the calculation of error metrics of AFAs in MATLAB. From Table 8, the ET_ CSLA with

Designs Number of Nonzero ED Error rate in % TABLE 7 Comparison of existing and proposed approximate full adder
10 in terms of error rate
AMA1 2 25
AMA2 10 2 25
AXA1 18 4 50
AXA2 18 2 25
AFA12 2 25
MFA13 2 25
MBAFA14 2 25
IFA 2 25

Abbreviations: ADP, area delay product; AFA, approximate full adder;

ED, error distance; IFA, imprecise full adder; MBAFA, multiplexer
based on approximate full adders; MFA, modified full adder.

DESIGNS MED NED MAE MSE WCE WCRE MRE TABLE 8 Comparison of existing and
12 proposed adders in terms of Error Metrics
ET_ CSLA 12, 299.95 0.8383 345.95 1.69 65478 0.99 3.56
SAET_ CSLA12 1.64 0.0169 911.39 0.017 255 0.004 0.0139
HSETA15 0.026 0.0037 27.42 0.018 340 0.0052 0.0208
HPETA14 0.013 0.0018 684.08 0.0098 170 0.0026 0.0104
LETA 0.026 0.0037 27.42 0.018 340 0.0052 0.0208
ILETA 0.013 0.0018 684.08 0.0098 170 0.0026 0.0104
Abbreviations: CSLA, Conv CSLA; ED, error distance; ET_ CSLA, error tolerant carry select adder; HPETA,
high-performance error tolerant adder; HSETA, high-speed error tolerant adder; IFA, imprecise full adder;
ILETA, improved Low power and area efficient error tolerant adder; LETA, low power and area efficient
error tolerant adder; MBAFA, multiplexer based on approximate full adders; MAE, mean absolute error;
MED, mean error distance ; MRE, mean relative error; MSE, mean squared error; NED, normalized error
distance; SAET_ CSLA, significant approximation error tolerant carry select adder; WCE, worst case error;
WCRE, worst case relative error.
10 PRIYADHARSHNI AND KUMARAVEL

FIGURE 13 Ranking of existing and

proposed error tolerant adders based on
different metrics. ADP, area-delay
product; MRED, mean relative error
distance; NED, normalized error
distance; PAP, power-area product; PDP,
power-delay product; PEP, power and
error product [Colour figure can be
viewed at wileyonlinelibrary.com]

more NED value compared with all other existing adders. The SAET_ CSLA adder attains only 2% error with respect to
the ET_ CSLA, whereas the HSETA, HPETA, LETA, and ILETA gains 0.4%, 0.2% , 0.4% , and 0.2% NED values. The least
WCE value is achieved by the proposed ILETA and HSETA adders.
The LETA has comparatively higher value in error metrics compared with the ILETA. The ILETA achieves a reduction
in MSE of 99%, 43%, and 74% with respect to ET_ CSLA, SAET_ CSLA, and HSETA, respectively. Similarly, in MRE and
WCRE, the ILETA shows a reduction of 99%, 25%, and 50% and 99%, 30%, and 50% with respect to the ET_ CSLA, SAET_
CSLA, and HSETA. The error value of HSETA and LETA are similar. In the same manner, HPETA and ILETA have their
same error values.
Further, the study about the existing and proposed adders is extended based on a new performance metrics, namely
Power and Error Product (PEP). PEP is calculated as the product of total power consumed by the adder that is obtained
from the PT to the NED and is reported in Table 6. PEP is directly proportional to structure and error metrics. PEP is
described as
PEP = Power ∗ Error. (2)
From Table 6, the ILETA achieves lower PEP value. The SAET_ CSLA shows approximately 90% reduction in PEP value
compared with the ET_ CSLA. The HSETA and LETA shows improvement of 95% compared with the ET_ CSLA. The
HPETA and ILETA bring about 99% improvement in accuracy compared to the existing adders.
The ranking of proposed and existing adders based on structural and error metrics is shown in Figure 13. From
Figure 13, the ILETA delivers the lowest compound metrics. The LETA provides the lowest MRED value. Overall, the
ILETA offers lower PEP over the HPETA.

3.3 Image quality metrics of approximate full adders and error tolerant adders
Image blending application is adapted to analyse the computational accuracy of the proposed and existing adders. Image
blending application is coded in MATLAB, and two test images (I and J) are chosen from the database. The size of the
chosen image is 512 × 512. The total number of pixels is 262 144. The size of each pixel is 8 bits.
The architecture of image blending algorithm is shown in Figure 14. From the figure, the first test image (I) is converted
into one-dimensional array and it is multiplied with the blending factor (1 − 𝛼). Similarly, 𝛼 is multiplied with another
test image (J). The resulting images are added by utilizing the existing and proposed 16-bit error tolerant adders. The pixel
value of input images are mapped from 8 bit data type to 16 bit data type for performing 16 bit addition. The resulting
pixel value of image (R) is a summation of corresponding pixel values of two input test images in linear combinations.
PRIYADHARSHNI AND KUMARAVEL 11

The operation of image blending application is shown in Equation 3.

R(x, 𝑦) = (1 − 𝛼)I(x, 𝑦) + (𝛼)J(x, 𝑦) (3)

Figure 15 shows the two input test images and the resulting images after performing blending using proposed 16-bit
ILETA. Figure 15 C-E shows the resulting images when blending factors (𝛼 = 0.2, 0.5, 0.75) respectively.
The evaluation of proposed and existing error tolerant adders are carried out based on pa eak signal to noise ratio (PSNR)
value that is an important image quality metrics. The PSNR and MSE is given as

( )
MAX
PSNR = 20log10 √ (4)
MSE

FIGURE 14 Block diagram of image blending

algorithm

(A) (B) (C) (D) (E)

FIGURE 15 Image blending application, A, Image(I), B, Image(J), Output images of improved low power and area efficient error tolerant
adder (ILETA) using different values of 𝛼 C, 𝛼 = 0.2 D, 𝛼 = 0.5 E, 𝛼 = 0.75

16-Bit ETA 𝛼 = 0.2 𝛼 = 0.5 𝛼 = 0.75 TABLE 9 Image quality metrics

PSNR (dB) PSNR (dB) PSNR (dB)
ET_CSLA12 5.32 3.94 3.94
SAET_CSLA12 7.48 5.27 6.22
HSETA15 13.48 15.83 15.3
HPETA14 18.6 18.63 16.56
LETA 13.48 15.83 15.3
ILETA 18.6 18.63 16.56
Abbreviations: CSLA, Conv CSLA; ED, error distance; ETA, error tol-
erant adder; ET_ CSLA, error tolerant carry select adder; HPETA,
high-performance error tolerant adder; HSETA, high-speed error tol-
erant adder; IFA, imprecise full adder; ILETA, improved Low power
and area efficient error tolerant adder; LETA, low power and area effi-
cient error tolerant adder; MBAFA, multiplexer based on approximate
full adders; PSNR, peak signal-to-noise ratio.
12 PRIYADHARSHNI AND KUMARAVEL

where max = maximum pixel value of the original image.

1 ∑ ∑[
m−1 n−1
]2
MSE = Re (x, 𝑦) − Rapp (x, 𝑦) (5)
mn i=0 𝑗=0

where Re = output image obtained using the exact adder and Rapp = output image obtained using the ETA.
PSNR is inversely propositional to MSE. Higher PSNR value indicates the better quality of an image. The adder with less
errors will result in a higher PSNR value. The PSNR values of output image is obtained using existing and the proposed
error tolerant adders for various blending factors 𝛼 = 0.2, 0.5, 0.75 are reported in Table 9. From Table 9, it is found that
the the ET_CSLA and SAET_CSLA provides a lower PSNR value. The HSETA and LETA has a reasonable PSNR value
whereas HPETA and ILETA yields a higher PSNR value compared with other ETA.
The overall analysis infers that the proposed LETA and ILETA achieve a low power and area efficient for error resilient
image applications.

4 CO N C LUSION S

In this paper, the design of the LETA and ILETA is proposed with the modification on the accurate part and utilizing
the proposed IFA in the inaccurate part of the ETA. The proposed IFA achieves the least gate count with same error
distance as the MBAFA. Several well known approximate error tolerant adders, namely the ET_CSLA, SAET_CSLA,
HSETA, and HPETA are reviewed and analysed in terms of their gate count, structural metrics, error metrics, and image
quality metrics. Further, ETAs are compared with a new performance metric PEP and is observed that the ILETA achieves
a lower PEP value compared with existing ETAs. Also, the PSNR value is higher for the proposed ILETA, which is essential
for image processing application.

ACKNOWLEDGMENT
The authors would like to thank Dr V Nithish Kumar from the Department of Micro & Nanoelectronics, School of
Electronics Engineering, Vellore Institute of Techonology, for his timely assistance and valuable suggestions.

ORCID
Sundaram Kumaravel https://orcid.org/0000-0003-2171-9420

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How to cite this article: Priyadharshni M, Kumaravel S. Low power and area efficient error tolerant adder for
image processing application. Int J Circ Theor Appl. 2020;1–13. https://doi.org/10.1002/cta.2744