BUFFER STAGE FOR FAST RESPONSE LDO

C. Stanescu
Catalyst Semiconductor Romania S.R.L., Bucharest, Romania
E-mail: cornel.stanescu@catsemi.ro

Abstract-The paper presents a buffer stage used 2. LDO ARCHITECTURE

in a fast response LDO processed in a double-
metal 0.8 pm CMOS process. The stage consists
of a transconductance amplifier (OTA) in a
unity-gain configuration. The buffer has a wide-
band architecture and is designed to drive the
parasitic gate-to-source capacitance of the power
transistor. Output impedance is lower than 2kR
and current consumption is less than 2OpA.
1. INTRODUCTION
The low dropout voltage regulators
(LDOs) are widely used in cell phones and
portable equipment.
In order to fulfil the need of fast transient
response, with small undershoot and
overshoot, LDOs must include a special buffer
stage enabling fast-slewing drive, and
optimization of the frequency compensation.
The architecture of a fast response LDO
is presented in Fig. 1 .
Between the error amplifier EA, and the
power transistor P1, there is a voltage follower
VF [I]. This is the buffer stage. Its role is to
maintain a low capacitive load for the EA,
while fast-slew driving the parasitic capacitor
CP (tens of pF). This stage should also have
high input impedance, low output impedance,
and a wide bandwidth.
The output swing should be as wide as
possible, in order to drive the gate of the
power P1 close to GND (for high load currents
and low input voltages), or to VW (for low
load currents).
These performances should be obtained
for low current consumption, and using the
chosen, less expensive, N-well CMOS process,
without any additional steps.

Fig. 1. Basic architecture of a fast response LDO

0-7803-7821-0/03/$17.00 0 2003 IEEE

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 VI I<
INVF
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Fig. 2. Schematic of the buffer stage
3. BUFFER SCHEMATIC
The buffer stage can be'implemented in
many ways. One could be a'classical common-
drain NMOS voltage follower stage, but the
NMOS should be in a separate well, other way
the power supply rejection ratio becomes poor,
due to back-gate effect. Using a common-drain
PMOS voltage follower is not a desirable
choice, because at least a voltage equal with
the threshold voltage of PMOS is lost from an
already narrow output swing.
The best choice 'is to :usc an operational
amplifier, unity-gain configured. When using a
CMOS technology without additional steps,
the use of a wide band configuration becomes
a 11111St.
FIG. 2 is showing the architecture chosen
for the buffer stage: a wide-band OTA.
In order to extend the common mode
range (CMR), which affects the output swing
in the case of a unity-gain-configuration, the
-.
input stage comprises natural low-threshold
voltage (V.,) NMOS transistors 01 and 0 2 ,
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which drive a load comprising two diode-
connected PMOS transistors P I 0 and PI I.
A second stage of the buffer comprises
PMOS transistors P12 and P13, which drive a
current mirror load of NMOS transistors N2
and N3. An additional PMOS transistor P I 4
keeps the drain-to-source voltage of transistor
P I 2 less dependent upon VIN variations.
The closed-loop output resistance (ROUT)
in FIG. 2 can be expressed as:
ROUT= Il(gmoiN) (1)
where gmOlis the transconductance of 01, and
N is the current multiplication factor of the
output branch of the OTA:
N= ( W L )r13W'k) rI I (2)
In order to assure a low value for ROUT,N
was chosen to be 15, giving a maximum output
current:
IOU+ VF~~~
= NIDNI (3)
which is almost double the operating point
supply current ( ( N + I ) I D N ~ ) / ~ .
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. 4. SIMULATED TRANSIENT terminals are almost the same, a slight and

RESPONSE acceptable degradation due to slew-rate being
observed at the output.
In order to fully characterize the The lower graphs of Fig. 3 are showing
behaviour of the buffer stage, closed-loop the balance of currents: drain currents of N3
simulations were made for the entire LDO and PI3 from Fig. 2, and the output current at
circuit. the buffer output.
A transient. simulation was made When the load current is swept to
considering that the output current is swept maximum, the drain current of N3 becomes
within 0 . l p from O.lmA to 150mA, and back. almost double the stand-by value, while P I 3
As shown in Fig. 3, the upper graphs are the goes almost off, charging the parasitic
transient voltages at the input (WVF), and the capacitance of the power transistor with the
output (OUTVF) of the stage. The gate-to- maximum available current. There is a short
source voltage of the power transistor, whose modification in the opposite direction, and
overdrive increases dramatically due to load after that, the loop is almost stable, with zero
modification, gives the DC level modification. output current at the output, after less than
There is an undershoot, but no overshoot, this 6ps.
phenomenon being related to frequency The process is repeated when load is
compensation of the entire loop, i.e. at high swept to minimum; in this case the output
load current the phase margin is lower leading current is discharging the parasitic
to undershoot. At low load current the phase capacitance, while. PI3 is delivering the
margin is close to 90°, avoiding any overshoot. current, and N3 being almost off.
Nevertheless, the bandwidth at low load The stand-by current through N3 and PI 3
current is much lower, which brings a longer was 15yA, while CP was 30pF.
recovery time. The voltages at both buffer

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 Fig: 4. Measured transient load regulation o f a fast response LDO using the presented buffer stage.

5. EXPERIMENTAL RESULTS A LDO using this stage was fabricated in

a double-metal 0.8 p m CMOS process, and it
Using the presented ;buffer stage, a fast
shows good transient load regulation, while
response LDO was fabricated in a double-
maintaining a low overall GND current.
metal 0.8
p m CMOS process.
The circuit has the transient load
regulation presented in Fig. 4. .Measurement References
was done considering: VOuT=3V, VIN=4V,
[I] C . Stanescu; “A 150mA LDO in 0.8pin
IL=O. 1 mA to 150mA, CL=lpF, and ESR=O.ZR.
CMOS process”, Proceedings of CAS 2000
The measured transient .load regulation International Semiconductor Corfere,rc<,,
c m be favourably compared with other pp. 83-86, Oct. 2000.
presented LDOs [2], [3]. The buffer stage [2] G. A. Rincon-Mora, P. E. Allen, “A low
gives most of the transient performance of the voltage, low quiescent current, low dropout
circuit. The buffer needs almost 20kA from regulator”, IEEE J . Solid-State Circairs, 33,
t h e 70pA overall GND current of the LDO. pp. 36-44, Jan. 1998.
[3] G. A. Rincon-Mora, “Active Capacitor
Multiplier in Miller-Compensated Circuits”,
6. CONCLUSIONS IEEE J. Solid-State Circuits, 35, pp. 26-32,
Jan. 2000.
A CMOS buffer stage for LDOs was
developed and verified. It offers good
performances in terms of bandwidth, voltage
swing and slew-rate, all these for a low 20pA
current consumption.

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