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irq_status = fpga_read(uiodev->mem[FPGA_REG_AREA].internal_addr +
CASH3_FPGA_IRQ_STATUS_ADDR);
dev_info(&pdev->dev, "1. Interrupt %d received, CASH3_FPGA_IRQ_STATUS =0x%0x",
irq, irq_status);
/*
* Get interrupt source and save it to scractch register
* 0 : host command
* 1 - 6: can commands
*/
status = irq_status;
for (irq_src = 0; irq_src <= CASH3_CAN_MAX; irq_src++) {
if (status & 1) {
if (irq_src == 0) {
/* process command based on type */
} else {
/* process CAN command based on type */
p_cmd = uiodev->mem[FPGA_CAN_AREA].internal_addr +
(irq_src - 1) * CASH3_FPGA_CAN_TX_BUFFER_SIZE;
header = *p_cmd++; // Should be CAN_Traffic command
payload = (struct cash3_host_cmd_can_payload *)p_cmd++;
if(header.cmd == CASH3_HOST_CMD_TRIGGER_DUMMY_EVENT)
payload->can_subcmd = CASH3_CAN_CMD_TEST;
// Pre-process sub-command
switch (payload->can_subcmd) {
case CASH3_CAN_CMD_TEST:
p_test = (struct cash3_host_cmd_can_cmd_test_t *)&(payload->test);
dev_warn(&pdev->dev, "2.1 UIO received CAN[%d] CASH3_CAN_CMD_TEST, backRef = %lld",
irq_src - 1, p_test->backReference);
p_test->ticks[0] = current_ts.tv_nsec;
p_test->ticks[1] = current_ts.tv_sec;
break;
case CASH3_CAN_CMD_SEND:
break;
default:
break;
}
// Wake up CAN threads
spin_lock(&cmd_flag_slock);
fpga_host_cmd_flag |= (1u << (irq_src - 1));
spin_unlock(&cmd_flag_slock);
wake_up(&fpga_host_cmd_que);
// clear CAN interrupt bit here
fpga_clear_host_interrupt(1u << irq_src);
// dev_info(&pdev->dev, "2. UIO waked up task and cleared irq status with mask 0x%0x"
, 1u << irq_src);
1
} // end CAN
} // if (status & 1)
// Get next interrupt bit
status >>= 1;
} // for (irq_src
while (!kthread_should_stop()) {
/* Wait for host cmd from UIO module */
wait_event(fpga_host_cmd_que, fpga_host_cmd_flag & chan_mask);
spin_lock(&cmd_flag_slock);
fpga_host_cmd_flag &= ~chan_mask;
spin_unlock(&cmd_flag_slock);
// Get cmd_payload
cmd_payload = (struct cash3_host_cmd_can_payload *)p_cmd;
dev_info(priv->dev, "3. axcan-%d starts processing command %d", chan
, cmd_payload->can_subcmd);
switch (cmd_payload->can_subcmd) {
case CASH3_CAN_CMD_TEST:
/* Process test command */
axcan_debug_save_event_buf_idx(priv);
p_event->head.event = CASH3_FPGA_EVENT_DUMMY;
p_event->head.event_count = 1;
p_event->head.reserved = 0;
// Send event
2
acash_qdma_frame_start(chan + 9);
dev_notice(priv->dev,
"5. axcan-%d sends CAN dummy event to host: queue %d, buf %d, backRef %lld"
, priv->can_chan, priv->can_chan + 9, (priv->rx_buf_idx - 1) & 3
, test_event->backReference);
break;
} // Swicth
if (ret == 0)
cmd_status = 0;
else
cmd_status = axcan_update_cmd_status(priv, msgs_sent) | (ret & 0xFF);
return ret;
}
3
[ 217.778022] cash3_uio a0900000.pcie_ss_top: 1. Interrupt 69 received, CASH3_FPGA_IRQ_STATUS
=0x2
[ 217.778026] axcan a0360000.can: 8. axcan-1 cleared cmd_status: 0x0
[ 217.778029] cash3_uio a0900000.pcie_ss_top: 2.1 UIO received CAN[0] CASH3_CAN_CMD_TEST,
backRef = 40
[ 217.778039] cash3_uio a0900000.pcie_ss_top: 2. UIO waked up task and cleared irq status with mask 0x2
[ 217.778044] axcan a0350000.can: 3. axcan-0 starts processing command 0
[ 217.778049] axcan a0350000.can: 4. axcan-0 processes CASH3_CAN_CMD_TEST, backRef 40
[ 217.778054] axcan a0350000.can: 5. axcan-0 sends CAN dummy event to host: queue 9, buf 1, backRef 40
4
[ 217.778198] cash3_uio a0900000.pcie_ss_top: 1. Interrupt 69 received, CASH3_FPGA_IRQ_STATUS
=0x4
[ 217.778200] axcan a0350000.can: 5. axcan-0 sends CAN dummy event to host: queue 9, buf 3, backRef 38
[ 217.778205] axcan a0350000.can: 8. axcan-0cleared cmd_status: 0x0
[ 217.778207] cash3_uio a0900000.pcie_ss_top: 2.1 UIO received CAN[1] CASH3_CAN_CMD_TEST,
backRef = 38
[ 217.778216] cash3_uio a0900000.pcie_ss_top: 2. UIO waked up task and cleared irq status with mask 0x4
[ 217.778221] axcan a0360000.can: 3. axcan-1 starts processing command 0
[ 217.778226] axcan a0360000.can: 4. axcan-1 processes CASH3_CAN_CMD_TEST, backRef 38
5
[ 217.778336] cash3_uio a0900000.pcie_ss_top: 2.1 UIO received CAN[1] CASH3_CAN_CMD_TEST,
backRef = 36
[ 217.778343] cash3_uio a0900000.pcie_ss_top: 2. UIO waked up task and cleared irq status with mask 0x4
[ 217.778347] axcan a0360000.can: 3. axcan-1 starts processing command 0
[ 217.778352] axcan a0360000.can: 4. axcan-1 processes CASH3_CAN_CMD_TEST, backRef 36
[ 217.778358] axcan a0360000.can: 5. axcan-1 sends CAN dummy event to host: queue 10, buf 1, backRef 36
[ 217.778365] axcan a0360000.can: 8. axcan-1 cleared cmd_status: 0x0