CS-213 COAL

Chapter 5
Internal Memory
Overview
• Dynamic RAM (DRAM) & Static RAM (SRAM)
— Properties
— Structure
— Difference
— Chip Logic
— Chip Packaging
— Module Organization
• Error Detection & Correction
— Hamming Code
— Single Error Correcting & Detecting (SEC-SED)
• Advanced DRAM Organization
— Synchronous DRAM (SDRAM)
— Double Data Rate DRAM (DDRRAM)
— Rambus RAM (RDRAM)
— Cache DRAM (CDRAM)
Semiconductor Memory
• Earlier computers had an array of doughnut-
shaped ferromagnetic loops called core used as
RAM - vanquished by microelectronics
• Two basic forms of semiconductor random access
memory are DRAM & SRAM
• Another form of semiconductor random access
memory is ROM
— ROM
— PROM
— EPROM
— EEPROM
— Flash Memory
Semiconductor Memory Types

• Word RAM misused as all semiconductor memory is random access

RAM
• RAM
—Read/Write
—Volatile
—Temporary storage
—Static or dynamic
• Basic element of semiconductor memory
is a memory cell
—Exhibits two stable states 0, 1
—Capable of being written (set the state)
—Capable of being read (sense the state)
Memory Cell Operation

• Three functional terminals capable of carrying the signal

• The details of the internal organization depend on the IC technology used and is out
of the scope of this course, except for a brief summary
Dynamic RAM
• DRAM is made with cells that store data as charge
in capacitors

• Capacitors have natural tendency to discharge

• Need refreshing even when powered
• Simpler construction
• Smaller per bit why?
• Less expensive why?
• Need refresh circuits
• Slower why?
• Main memory
• Essentially analogue - Level of charge determines
value
Dynamic RAM
Structure & Operation

• Address line active when bit read or

written
— Transistor switch closed (current
flows)
• Write
— Voltage to bit line
– High for 1 low for 0
— Then signal address line
– Transfers charge to capacitor
• Read
— Address line selected
– transistor turns on
— Charge from capacitor fed via bit
line to sense amplifier
– Compares with reference value to
determine 0 or 1
— Capacitor charge must be restored
Static RAM
• Bits stored as on/off switches
• No charges to leak
• No refreshing needed when powered
• More complex construction
• Larger per bit
• More expensive
• Does not need refresh circuits
• Faster
• Cache
• Digital
—Uses flip-flops
Static RAM Structure
& Operation

• Transistor arrangement
gives stable logic state
• State 1
— C1 high, C2 low
— T1 T4 off, T2 T3 on
• State 0
— C2 high, C1 low
— T1 T4 on, T2 T3 off
• Address line transistors T5 T6
is switch
• Write – apply value to B &
compliment to B
• Read – value is on line B
SRAM v DRAM
• Both volatile
—Power needed to preserve data
• Dynamic cell
—Simpler to build, smaller
—More dense How?
—Less expensive
—Needs refresh
—Larger memory units
• Static
—Faster
—Cache
Read Only Memory (ROM)
• Permanent storage
—Nonvolatile
• Applications
—Microprogramming (see later)
—Library subroutines
—Systems programs (BIOS)
—Function tables
• Data is actually wired into the chip as part
of the fabrication process
Types of ROM (1/2)

• Written during manufacture

—Very expensive for small runs
• Programmable (once)
—PROM
– Needs special equipment to program
– Electrically written
– Can be performed after fabrication but only once
• Read ―mostly‖
—Erasable Programmable (EPROM)
– Erased by Ultraviolet radiations
– Before write, all the storage cells must be erased to
the same initial state by exposing the chip to UV
– Erasure process can take as long as 20 minutes
Types of ROM (2/2)

• Read ―mostly‖
—Electrically Erasable (EEPROM)
– Takes much longer to write than read
– Write operation does not need prior erasing of cells
– Only the addressed bytes can be updated
—Flash memory
– Introduced in mid 1980s
– Erase whole memory electrically in few seconds
– Can allow to erase individual blocks but no byte level
erasure
– Can erase a section of memory in one action or flash
– One transistor per bit, so high density
Organisation in detail (1/2)

• As with other IC products, semiconductor

memory comes in packaged chips
• Each chip contains an array of memory cells
• Key design issue for semiconductor memory is
the number of bits that can be read/written at a
time… i.e. how these arrays of cells are arranged
• For example a 16Mbit chip can be organised:
— as 1M of 16 bit words i.e 1M x 16
— as 4M of 4 bit words i.e 4M x 4
— as 16M of 1 bit words i.e 16M x 1 (1 bit per chip
organization)
• A bit per chip system has 16 lots of 1Mbit chip
with bit 1 of each word in chip 1 and so on
Organisation in detail (2/2)

• A 16Mbit chip can be organised as a 2048 x 2048

x 4bit array
— Reduces number of address pins
– Multiplex row address and column address
– 11 pins to address (211=2048)
– Adding one more pin doubles range of values so x4
capacity
• Refreshing
— Refresh circuit included on chip
— Disable chip
— Count through rows
— Read & Write back
— Takes time
— Slows down apparent performance
Typical 16 Mb DRAM (4M x 4) – Chip Logic
• Horizontal line connects to sel terminal
• Vertical line connects to sense terminal
• Row decoder selects the row
• Column decoder selects the cell in row
• The 22 required address lines are
passed through select logic external to
chip and multiplexed onto 11 pins
Packaging
• 1M x 8 EPROM • 4M x 4 DRAM
• One word per chip package •11 pins used for address
• 20 Address lines needed to address 1 M words • 4 data pins
• 8 Data pins • NC is no connect to make the pins even
256kByte Module
Organisation

• If a RAM chip contains 1 bit per word, then

we need number of chips equal to number of bits
per word
• Example: Memory module consisting of 256 K
8-bits words is organized into 512 x 8
• For 256 words, 18 bits address is supplied to
the module from external source
• The address is presented to all the chips , each
of which inputs/outputs one bit
 1MByte Module Organisation
• The organization works as long as the memory
is small
• if larger memory is required then we organize
the chips in arrays
•256 K is organized into 512 x 8
Error Correction
• Hard Failure
—Permanent physical defect
—Caused by wear, manufacturing defect etc
• Soft Error
—Random, non-destructive
—No permanent damage to memory
—Caused by power supply problem, or alpha
particles
• Most modern main memory systems
include logic for both detecting and
correcting
Error Correcting Code Function

•Bit by bit comparison gives Syndrome word

•If all zeros, no error
Hamming Code (1)

• The simplest of the error correcting code

is the Hamming code by Richard Hamming
• Venn Diagram for 4 bit word with parity
bits
Hamming Code (2)

• Develop code
• First find how long the code would be
— 2k -1 >= M + K
• Say M = 8 bit
—K=3, is it ok? Or k=4 is ok?
Hamming Code (3)

• Let’s see how it works on 8 bit word

• M= 8, k= 4, total 12
• How to place check bits? See below
• Check bit is placed at every bit position
which is power of 2 and calculated as follow
— C1= D1 D2 D4 D5 D7
— C2= D1 D3 D4 D6 D7
— C4=
— C8=
Hamming Code (4)

• Let’s see an example of 8 bit word 00111001

— C1= D1 D2 D4 D5 D7 = 1
— C2= D1 D3 D4 D6 D7 = 1
— C4= D2 D3 D4 D8 =1
— C8= D5 D6 D7 D8 =0

• Suppose bit 3 has error retrieved word: 00111101

• XOR of check bits is 0110 means bit position 6
Hamming Code (5)

• Example of SEC-DED on 4 bit data

Advanced DRAM Organization
• Basic DRAM same since first RAM chips
1970s

• Two measures taken to improve

performance of DRAM
—Insert more levels of SRAM caches
– Costlier, expanding beyond a certain limit useless

—Enhance basic DRAM

– S DRAM, DDR SDRAM, R DRAM, Cache DRAM

• Drawback of Basic DRAM

— Address is presented to RAM, RAM finds data – access time delay
— During this access time delay DRAM performs various internal
functions
– Activating high capacitance of the row and columns
– Sensing the data
– Routing the data out to buffers
— CPU waits – wastage
Synchronous DRAM (SDRAM)
• Access is synchronized with an external clock
• Employs burst mode to eliminate address setup time, row
column pre-charge time
— In burst mode a series of data can be clocked out rapidly after
first bit is accessed
— This mode is useful when…..?
• Benefits
— Since SDRAM moves data in time with system clock, CPU
knows when data will be ready - CPU does not have to wait, it can
do something else
— Burst mode allows SDRAM to set up stream of data and fire it
out in block
— Mode register – allows to customize DRAM
– Burst mode or interleaved & adjusting latency
— DDR-SDRAM sends data twice per clock cycle- Data is
transferred on both the rising and falling edges of the clock signal, a
technique known as Double Data Rate
IBM 64 Mb SDRAM
SDRAM Read Timing
• Burst length 4, Latency 2
• Read command initiated at rising edge of first cycle
• Since latency is set to 2, so the data appears after the delay of 2 cycles
• Burst length is 4 so only 4 col read
RAMBUS (1/2)
• Adopted by Intel for Pentium & Itanium
• Main competitor to SDRAM
• The first PC motherboards with support
for RDRAM debuted in 1999
• They support PC-800 RDRAM, which
operates at 400 MHz and deliver 1600
Mb/s over a 16-bit bus
• Double Data Rate Technique
• Significantly faster than the previous
standard, PC-133 SDRAM, which operates
at 133 MHz and delivered 1066 Mb/s
RAMBUS (2/2)
• Vertical package – all pins on one side
• Data exchange over 28 wires < 12cm long
• Bus addresses up to 320 RDRAM chips at
1.6Gbps
• RDRAM delivers address & control
information using asynchronous block
oriented protocol
—480ns access time, then 1.6 Gbps
• RDRAM module sends data synchronously
RAMBUS Diagram
DDR SDRAM
• SDRAM can only send data once per clock
• Double-data-rate SDRAM can send data
twice per clock cycle
—Rising edge and falling edge
Cache DRAM
• Developed by Mitsubishi
• Integrates small SRAM cache (16 kb) onto
generic DRAM chip
• Can be used in two ways
— Used as true cache
– Consisting of 64-bit lines
– This cache mode is effective for ordinary random access
— Used as buffer to support serial access of block of data
• E.g. refresh bit-mapped screen
– CDRAM can pre-fetch data from DRAM into SRAM buffer
– Subsequent accesses solely to SRAM
Self search
• Graded:
—Home work No 1: Write the summary of the
research paper: The Cache DRAM Architecture
- A DRAM with an On-Chip Cache Memory

• Not graded:
Do some search activity on net and find
some details about the following. Write
one paragraph about each:
—DIP
—SIMM
—DIMM
—RIMM