A B C D E

1 1

PHQAA
2
Marseille 10R/10RG 2

LA-6831P REV 0.1 Schematic

3
Intel Processor(Sandy Bridge) / PCH(Cougar Point) 3

2010-07-05 Rev 0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 1 of 58
A B C D E
 A B C D E

Fan Control VGA Thermal Sensor

APL5607 ADM1032ARMZ-2
Intel CPU page 6 page 14
PCI-Express 16X 5GHz Sandy Bridge
1

rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1

37.5mm*37.5mm Dual Channel BANK 0, 1, 2, 3 page 11,12

page 5,6,7,8,9,10 1.5V DDRIII 1066/1333/1600 MT/s

VGA (DDR3)
NVIDIA N12M-GE, 64bit with 512MB/1GB CRT USB/B Right Left USB FingerPrinter
FDI X8 DMI X4 USB port 0,1 USB port 2 USB port 8
page 26 page 37 page 37 page 38
2.7GT/s 5GT/s
NVIDIA N12P-GS/GE, 128bit with 1GB/2GB
IR Emitter Felica Int. Camera
page 13,14,15,16,17,18,19,20,21,22,23,24
USB port 5 USB port 9 USB port 11
USB page 38 page 38 page 25
5V 480MHz
LVDS Conn.
page 25
PCIeMini Card PCIeMini Card Express Card
2
USB WiMax USB port 13 3G/TV#1
TV#2
USB port 12
USB port 10
USB USB port 4 2

5V 480MHz page 39 page 39 page 39

EC SMBus HDMI-CEC HDMI Conn. PCIe 1x PCIeMini Card PCIeMini Card Express Card
page 27 1.5V 5GT/s
WLAN PCIe port 2 JET PCIe port 4
PCIe PCIe port 3
page 27 Intel PCH page 39 page 39 page 39

Cougar Point - M
RTL8105E 10/100M SATA port 0 SATA HDD B-CAS SIM
RJ45 PCIe 1x 5V 6GHz(600MB/s) page 38 page 39
SATA port 1
page 40 RTL8111E 1G PCIe port 1 1.5V 5GT/s page 37
page 40
FCBGA-989
25mm*25mm SATA port 2 SATA ODD
5V 3GHz(300MB/s) SATA port 4
Cardreader PCIe 1x page 37
JMB389C 1.5V 5GT/s
PCIe port5 page 28,29,30,31,32,33,34,35,36 PCIe 1x
page 41
3
1.5V 5GT/s USB3.0 3
TUSB7320
PCIe port6
page 42
LPC BUS HD Audio 3.3V 24MHz
3.3V 33 MHz
TP& Light Pipe/B
LS-6061P page 46 MDC 1.5 Conn HDA Codec
ALC269
Cap Sensor SPI ROM Debug Port ENE KB930 page 38 page 43
page 45 page 44
& Light Sensor/B (4MB)
page 28
RTC CKT. LS-6062P page 46
page 28
Touch Pad Int.KBD EC ROM CIR G-Sensor Int. SPK Conn JPIO
page 43
LED/B page 46 page 45 page 44 page 45 MIC Conn (HP &page
MIC)
DC/DC Interface CKT. LS-6063P page 36
(128KB)
page 45
page 25 37

page 47 EC SMBus
Audio & USB/B
4 4

Power Circuit DC/DC LS-6064P page 37

page 48,49,50,51,52
53,54,55,56,57 Finger Printer/B
LS-6065P page

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38 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

Power On/Off CKT. Power/B_FPC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
page 46 DA300006JM0 page 46 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B 0.1

Date: Monday, August 02, 2010 Sheet 2 of 58

A B C D E
 5 4 3 2 1

DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 0.1A +5VL
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW
SUSP#

DESIGN CURRENT 2A +1.8VS

SY8033BDBC
SUSP

N-CHANNEL DESIGN CURRENT 4A +5VS

D D
SI4800 BCPWON
DESIGN CURRENT 0.5A +5VS_L_BCAS
P-CHANNEL
AO-3413
KB_LED

RT8205EGQW DESIGN CURRENT 400mA +5VS_LED

P-CHANNEL
AO-3413
+5VS
DESIGN CURRENT 300mA +3VS_HDP
LDO
G9191
ODD_EN#
DESIGN CURRENT 1.6A +5VS_ODD
P-CHANNEL
AO-3413

Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW

WOL_EN#

P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

SUSP AO-3413

N-CHANNEL DESIGN CURRENT 4A +3VS

SI4800 LCD_ENVDD

P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD

C
AO-3415 C
BT_PWR#
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413
FELICA_PWR
DESIGN CURRENT 0.5A +FLICA_VCC
P-CHANNEL
AO-3413
DGPU_PWR_EN
DESIGN CURRENT 0.5A +3VS_DGPU
P-CHANNEL
AO-3413
VR_ON

DESIGN CURRENT 48A +CPU_CORE

ISL62883HRZ
SUSP# or DGPU_PWR_EN

DESIGN CURRENT 28A +VGA_CORE

APW7138NITRL
VTTP_EN

Ipeak=18A, Imax=12.6A, Iocp min=19.8 DESIGN CURRENT 18A +VTT

APW7138NITRL
SUSP#

B DESIGN CURRENT 7A B
Ipeak=7A, Imax=4.9A, Iocp min=7.7 +1.05VS
RT8209BGQW
DGPU_PWR_EN
DESIGN CURRENT 3A +1.05VS_DGPU
P-CHANNEL
AO-3413
SUSP#
Ipeak=15A, Imax=10.5A, Iocp min=16.5 DESIGN CURRENT 15A +1.5V
RT8209BGQW SUSP

N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

FDS6676AS
SUSP

N-CHANNEL DESIGN CURRENT 2A +1.5VS

FDS6676AS
VGA_PWROK

N-CHANNEL DESIGN CURRENT 10A +VRAM_1.5VS

FDS6676AS
SUSP or 0.75VR_EN#

DESIGN CURRENT 1.5A +0.75VS

G2992F1U
A GFXVR_EN A

DESIGN CURRENT 22A +GFX_CORE

ADP3211AMNR2G

www.vinafix.vn
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 3 of 58
5 4 3 2 1
 A B C D E

Platform SKU CPU PCH VGA

( O MEANS ON X MEANS OFF ) UMA(OPT@) Arrandale HM55@/HM57@ N/A
Voltage Rails
Discrete Clarksfield/
HM55@/HM57@/PM55@ N11P@/N11M@
+5VS Calpella (DIS@) Arrandale
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS Optimus
+3VL +3VALW Arrandale HM55@/HM57@ N11P@/N11M@
+1.8VS (OPT@)
+VSB
power +1.5VS
1 plane +1.05VS
1

+0.75VS BTO Option Table

+CPU_CORE
+VGA_CORE Function HDMI CPU
+GFX_CORE
description HDMI Arrandale Clarksfield
+VTT
State Discrete/ Clarksfield with
+VRAM_1.5VS explain UMA Optimus COMMON CEC Arrandale Clarksfield S3 Power Saving
+3VS_DGPU
BTO IHDMI@ DHDMI@ HDMI@ CEC@ M1@ M3@ PSM3@
+1.05VS_DGPU

Function MINI PCI-E SLOT LAN Fingerprint Modem CIR KB Light

S0 description SLOT2 SLOT1 LAN Fingerprint Modem CIR KB Light

O O O O O O
explain 3G TV Tuner WIMAX 10/100M Giga Fingerprint Modem CIR KB Light
S1
O O O O O O
BTO 3G@ TV@ WIMAX@ 8105E@ 8111E@ FP@ MDC@ CIR@ KBL@
2 2
S3 O O O O O X
Function Felica BLUE TOOTH G-SENSOR SKU LVDS Camera & Mic
S5 S4/AC
O O O O X X
description Felica BLUE TOOTH G-SENSOR SKU 3D Panel Camera & Mic
S5 S4/ Battery only O O O X X X explain Felica BLUE TOOTH G-SENSOR Discrete Optimus Discrete Optimus Camera & Mic

S5 S4/AC & Battery BTO FELICA@ BT@ GSENSOR@ DIS@ OPT@ 3D@ NO3D@ OPTFH@ CAM@
don't exist
O X X X X X
Function S3 Power Saving GPU

description S3 Power Saving N11P & N11E N11M

PCH SM Bus Address
explain No Power Saving Power Saving VRAM N11P N11E N11M-GE1 N11M-GE2 N11M-OP1
Power Device HEX Address NOPS@ PS@ 8PCS@ N11P@ N11E@ N11MGE1@ N11MGE2@ N11MOP@
BTO
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b
3
Function Card reader New Card 3

+3VS Clock Generator D2 H 1101 0010 b

+3VS New Card description JMB385C/389C New Card
+3VS WLAN/WIMAX
explain JMB385C JMB389C New Card
+3VS Clock Generator
+3VS 3G BTO JMB385@ JMB389@ NEW@

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
Full ON HIGH HIGH HIGH

Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH

+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH
+3VL HDMI-CEC 34 H 0011 0100 b +3VS NVIDIA GPU 9A H 1001 1010 b
S4 (Suspend to Disk) LOW LOW HIGH
+3VS G-Sensor 40 H 0100 0000 b
+3VS Light Sensor 52 H 0101 0010 b S5 (Soft OFF) LOW LOW LOW
4
Power Device HEX Address 4

G3 LOW LOW LOW

+3VL Cap. Sensor Virtual I2C

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Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 4 of 58
A B C D E
 5 4 3 2 1

JCPUB

100 MHz
@ PROC_SELECT# A28 CLK_CPU_DMI Stuff R41 and R42 if do not support eDP
BCLK CLK_CPU_DMI <29>

MISC

CLOCKS
1000P_0402_50V7K 2 1 C487 PM_DRAM_PWRGD_R H_SNB_IVB# C26 A27 CLK_CPU_DMI#
<32> H_SNB_IVB# SNB_IVB# BCLK# CLK_CPU_DMI# <29>
@ 120 MHz +1.05VS_VCCP
1000P_0402_50V7K 2 1 C488 H_PWRGOOD T1 PAD TP_SKTOCC# AN34
SKTOCC# CLK_CPU_DPLL
A16
DPLL_REF_SSCLK CLK_CPU_DPLL# CLK_CPU_DPLL# R42 1
A15 2 1K_0402_5%
DPLL_REF_SSCLK#
D CLK_CPU_DPLL R41 1 D
2 1K_0402_5%
T2 PAD H_CATERR# AL33 CATERR#

THERMAL
H_PECI AN33 R8 H_DRAMRST#
<33,44> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>

DDR3
MISC
+1.05VS_VCCP R450
<44> H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R1437 2 1 140_0402_1% DDR3 Compensation Signals
56_0402_5% PROCHOT# SM_RCOMP[0] SM_RCOMP_1 R1438 2
SM_RCOMP[1] A5 1 25.5_0402_1% Layout Note:Place these
R47 2 1 62_0402_5% H_PROCHOT# A4 SM_RCOMP_2 R1439 2 1 200_0402_1% resistors near Processor
R14 SM_RCOMP[2]

<33> H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 THERMTRIP#

0_0402_5%
R51 2 1 10K_0402_5% H_PWRGOOD

AP29 XDP_PRDY#_R R1 1 @ 2 0_0402_5% XDP_PRDY#

PRDY# XDP_PREQ#_R R2 1 @ XDP_PREQ#
AP27 2 0_0402_5%
PREQ#
AR26 XDP_TCK_R R4 1 @ 2 0_0402_5% XDP_TCK
TCK

PWR MANAGEMENT
AR27 XDP_TMS_R R6 1 @ 2 0_0402_5% XDP_TMS

JTAG & BPM

H_PM_SYNC TMS XDP_TRST#_R R7 1 @ XDP_TRST# Routed as a single daisy chain
<30> H_PM_SYNC AM34 PM_SYNC TRST# AP30 2 0_0402_5%

AR28 XDP_TDI_R R8 1 @ 2 0_0402_5% XDP_TDI

TDI XDP_TDO_R R10 1 @ XDP_TDO
AP26 2 0_0402_5%
H_PWRGOOD TDO R36
<33> H_PWRGOOD AP33 UNCOREPWRGOOD
1 2 +3VS
1K_0402_5%
AL35 XDP_DBRESET#_R R11 1 @ 2 0_0402_5% XDP_DBRESET#
PM_SYS_PWRGD_BUF 1 DBR# XDP_DBRESET# <30>
2 PM_DRAM_PWRGD_R V8 SM_DRAMPWROK
C R454 130_0402_5% C
AT28 XDP_BPM#0_R R12 1 @ 2 0_0402_5% XDP_BPM#0
BPM#[0] XDP_BPM#1_R R13 1 @ 0_0402_5% XDP_BPM#1
BPM#[1] AR29 2
AR30 XDP_BPM#2_R R15 1 @ 2 0_0402_5% XDP_BPM#2
BUF_CPU_RST# BPM#[2] XDP_BPM#3_R R18 1 @ 0_0402_5% XDP_BPM#3
AR33 RESET# BPM#[3] AT30 2
AP32 XDP_BPM#4_R R19 1 @ 2 0_0402_5% XDP_BPM#4 R24 1 @ 2 0_0402_5%
BPM#[4] CFG12 <10>
AR31 XDP_BPM#5_R R20 1 @ 2 0_0402_5% XDP_BPM#5 R25 1 @ 2 0_0402_5%
BPM#[5] CFG13 <10>
AT31 XDP_BPM#6_R R21 1 @ 2 0_0402_5% XDP_BPM#6 R26 1 @ 2 0_0402_5%
+3VALW BPM#[6] XDP_BPM#7_R XDP_BPM#7 CFG14 <10>
AR32 R23 1 @ 2 0_0402_5% R27 1 @ 2 0_0402_5%
BPM#[7] CFG15 <10>

+1.5V_CPU
Close to CPU side
1
C93
0.1U_0402_16V4Z Sandy Bridge_rPGA_Rev0p61 @
1

2
U10 R339
R312 74AHC1G09GW_TSSOP5 200_0402_5%
5

0_0402_5%
2

1 2 1
P

<30,44> PM_PWROK B
4 PM_SYS_PWRGD_BUF
O
<30> DRAMPWROK 2
A PU/PD for JTAG signals
G

+1.05VS_VCCP
1
3

R340 XDP_TMS_R R28 2 1 51_0402_5%

39_0402_5%
@ XDP_TDI_R R29 2 1 51_0402_5%
R3841 @ 2 0_0402_5%
1 2

XDP_TDO R30 2 1 51_0402_5%

D Q5
SUSP 2 2N7002_SOT23 XDP_TCK_R R31 2 1 51_0402_5%
<9,47,54> SUSP
G @
B XDP_TRST#_R R32 B
S 2 1 51_0402_5%
3

JXDP @
XDP Connector XDP_PREQ# 1 +5VS
FAN Control Circuit
XDP_PRDY# 2
3 1A
XDP_BPM#0 4
XDP_BPM#1 5
6
Buffered Reset to CPU XDP_BPM#2 7
XDP_BPM#3 8 2
9
H_PWRGOOD R35 1 @ 2 1K_0402_5%XDP_CPU_HOOK0 10 C3 JFAN
+3VS PBTN_OUT# R152 1 @ 2 0_0402_5% XDP_CPU_HOOK1 11 10U_0805_10V6K +FAN1 1
<30,44> PBTN_OUT# 1 1
CFG0 R37 1 @ 2 1K_0402_5%XDP_CPU_HOOK2 12 2
<10> CFG0 VGATE 2
<30,44,55> VGATE R451 1 @ 2 0_0402_5% XDP_CPU_HOOK3 13 2 3
CLK_CPU_ITP U1 C4 3
<29> CLK_CPU_ITP 14
1 0.1U_0402_16V4Z CLK_CPU_ITP# 15 1 8 1000P_0402_50V7K 4
<29> CLK_CPU_ITP# EN GND GND
C84 +1.05VS_VCCP 16 2 7 @ 5
+1.05VS_VCCP PLT_RST# @ XDP_CPU_HOOK6 +FAN1 VIN GND 1 GND
PLT_RST# <32,39,40,41,42,44,45> 1 2 17 3 VOUT GND 6
R40 1K_0402_5% XDP_DBRESET# 18 4 5 ACES_85204-0300N
2 <44> EN_DFAN1 VSET GND
19 1
1

U3 XDP_TDO 20 10mil APL5607KI-TRG_SO8

PLT_RST# 1 R69 XDP_TRST# 21 C1
OE# 75_0402_5% XDP_TDI R3 10K_0402_5%
VCC 5 1 22 10U_0805_10V6K
C8 XDP_TMS 23 2 2 1 +3VS
2 R155 0.1U_0402_10V6K 24
2

IN 43_0402_1% @ 25 FAN_SPEED1 <44>

A
4 BUFO_CPU_RST# 1 2 BUF_CPU_RST# 2 XDP_TCK 26 A
OUT 1
3 27 C6
GND
1

28 0.01U_0402_25V7K
74AHC1G125GW_SOT353-5 R209 @
0_0402_5% 2
@ MOLEX 52435-2671
2

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_JTAG/XDP/FAN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 5 of 58
5 4 3 2 1
 5 4 3 2 1

PEG_ICOMPI and RCOMPO signals should be

+1.05VS_VCCP shorted and routed
with - max length = 500 mils - typical

1
impedance = 43 m ohm (4 mils)
R34
24.9_0402_1% PEG_ICOMPO signals should be routed with -
max length = 500 mils
JCPUA
- typical impedance = 14.5 m ohm (12 mils)

2
D J22 PEG_COMP D
PEG_ICOMPI
J21
DMI_PTX_CRX_N0 PEG_ICOMPO
<30> DMI_PTX_CRX_N0 B27 H22
DMI_PTX_CRX_N1 DMI_RX#[0] PEG_RCOMPO
<30> DMI_PTX_CRX_N1 B25
DMI_PTX_CRX_N2 DMI_RX#[1]
<30> DMI_PTX_CRX_N2 A25 PCIE_GTX_C_CRX_N[0..15] <13>
DMI_PTX_CRX_N3 DMI_RX#[2] PCIE_GTX_C_CRX_N0
<30> DMI_PTX_CRX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33
M35 PCIE_GTX_C_CRX_N1 C39 C40 C41 C42
DMI_PTX_CRX_P0 PEG_RX#[1] PCIE_GTX_C_CRX_N2 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K
<30> DMI_PTX_CRX_P0 B28 DMI_RX[0] PEG_RX#[2] L34
DMI_PTX_CRX_P1 B26 J35 PCIE_GTX_C_CRX_N3 OPT@ OPT@ OPT@ OPT@
<30> DMI_PTX_CRX_P1 DMI_RX[1] PEG_RX#[3]

DMI
DMI_PTX_CRX_P2 A24 J32 PCIE_GTX_C_CRX_N4
<30> DMI_PTX_CRX_P2 DMI_RX[2] PEG_RX#[4]
DMI_PTX_CRX_P3 B23 H34 PCIE_GTX_C_CRX_N5 C43 C44 C45 C46
<30> DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5]
H31 PCIE_GTX_C_CRX_N6 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K
DMI_CTX_PRX_N0 PEG_RX#[6] PCIE_GTX_C_CRX_N7 OPT@ OPT@ OPT@ OPT@
<30> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33
DMI_CTX_PRX_N1 E22 G30 PCIE_GTX_C_CRX_N8
<30> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
DMI_CTX_PRX_N2 F21 F35 PCIE_GTX_C_CRX_N9 C47 C48 C49 C50
<30> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
DMI_CTX_PRX_N3 D21 E34 PCIE_GTX_C_CRX_N10 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K
<30> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
E32 PCIE_GTX_C_CRX_N11 OPT@ OPT@ OPT@ OPT@
DMI_CTX_PRX_P0 PEG_RX#[11] PCIE_GTX_C_CRX_N12
<30> DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33
DMI_CTX_PRX_P1 D22 D31 PCIE_GTX_C_CRX_N13 C51 C52 C53 C59
<30> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
DMI_CTX_PRX_P2 F20 B33 PCIE_GTX_C_CRX_N14 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K

PCI EXPRESS* - GRAPHICS

<30> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
DMI_CTX_PRX_P3 C21 C32 PCIE_GTX_C_CRX_N15 OPT@ OPT@ OPT@ OPT@
<30> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_GTX_C_CRX_P[0..15] <13>
J33 PCIE_GTX_C_CRX_P0 C60 C72 C73 C74
PEG_RX[0] PCIE_GTX_C_CRX_P1 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K
PEG_RX[1] L35
K34 PCIE_GTX_C_CRX_P2 OPT@ OPT@ OPT@ OPT@
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_GTX_C_CRX_P3
<30> FDI_CTX_PRX_N0 A21 H35
FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3] PCIE_GTX_C_CRX_P4 C75 C76 C77 C78
<30> FDI_CTX_PRX_N1 H19 FDI0_TX#[1] PEG_RX[4] H32
FDI_CTX_PRX_N2 E19 G34 PCIE_GTX_C_CRX_P5 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K
<30> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
FDI_CTX_PRX_N3 PCIE_GTX_C_CRX_P6 OPT@ OPT@ OPT@ OPT@

Intel(R) FDI
<30> FDI_CTX_PRX_N3 F18 G31
C FDI_CTX_PRX_N4 FDI0_TX#[3] PEG_RX[6] PCIE_GTX_C_CRX_P7 C
<30> FDI_CTX_PRX_N4 B21 FDI1_TX#[0] PEG_RX[7] F33
FDI_CTX_PRX_N5 C20 F30 PCIE_GTX_C_CRX_P8 C61 C62 C66 C67
<30> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
FDI_CTX_PRX_N6 D18 E35 PCIE_GTX_C_CRX_P9 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K
<30> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
FDI_CTX_PRX_N7 E17 E33 PCIE_GTX_C_CRX_P10 OPT@ OPT@ OPT@ OPT@
<30> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
F32 PCIE_GTX_C_CRX_P11
PEG_RX[11] PCIE_GTX_C_CRX_P12 C68 C69 C70 C71
PEG_RX[12] D34
FDI_CTX_PRX_P0 A22 E31 PCIE_GTX_C_CRX_P13 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K
<30> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
FDI_CTX_PRX_P1 G19 C33 PCIE_GTX_C_CRX_P14 OPT@ OPT@ OPT@ OPT@
<30> FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
FDI_CTX_PRX_P2 E20 B32 PCIE_GTX_C_CRX_P15
<30> FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
FDI_CTX_PRX_P3 G18
<30> FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_C_GRX_N[0..15] <13>
FDI_CTX_PRX_P4 B20 M29 PCIE_CTX_GRX_N0 C39 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N0
<30> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
FDI_CTX_PRX_P5 C19 M32 PCIE_CTX_GRX_N1 C40 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N1
<30> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
FDI_CTX_PRX_P6 D19 M31 PCIE_CTX_GRX_N2 C41 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N2
<30> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
FDI_CTX_PRX_P7 F17 L32 PCIE_CTX_GRX_N3 C42 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N3
<30> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
L29 PCIE_CTX_GRX_N4 C43 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N4
FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_N5 C44 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N5
<30> FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2
<30> FDI_FSYNC1 FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_N6 C45 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N6
FDI1_FSYNC PEG_TX#[6] PCIE_CTX_GRX_N7 C46 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N7
J30 1 2
FDI_INT PEG_TX#[7] PCIE_CTX_GRX_N8 C47 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N8
<30> FDI_INT H20 J28 1 2
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_N9 C48 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N9
PEG_TX#[9] H29 1 2
eDP_COMP signals should be <30> FDI_LSYNC0 FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_N10 C49 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N10
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PCIE_CTX_GRX_N11 C50 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N11
<30> FDI_LSYNC1 H17 E29 1 2
shorted near balls and FDI1_LSYNC PEG_TX#[11]
F27 PCIE_CTX_GRX_N12 C52 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N12
PEG_TX#[12]
routed with typical PEG_TX#[13] D28 PCIE_CTX_GRX_N13 C51 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N13
F26 PCIE_CTX_GRX_N14 C59 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N14
impedance <25m ohm PEG_TX#[14]
E25 PCIE_CTX_GRX_N15 C53 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_N15
R9 EDP_COMP PEG_TX#[15]
+1.05VS_VCCP 1 2 24.9_0402_1% A18 eDP_COMPIO PCIE_CTX_C_GRX_P[0..15] <13>
A17 M28 PCIE_CTX_GRX_P0 C60 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P0
R33 eDP_ICOMPO PEG_TX[0] PCIE_CTX_GRX_P1 PCIE_CTX_C_GRX_P1
+1.05VS_VCCP 2 1 10K_0402_5% B16 M33 C72 1 2 DIS@ 0.22U_0402_10V6K
B eDP_HPD PEG_TX[1] PCIE_CTX_GRX_P2 C73 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P2 B
M30 1 2
PEG_TX[2] PCIE_CTX_GRX_P3 C74 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P3
L31 1 2
PEG_TX[3] PCIE_CTX_GRX_P4 C76 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P4
C15 L28 1 2
eDP_AUX PEG_TX[4] PCIE_CTX_GRX_P5 C75 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P5
D15 K30 1 2
eDP_AUX# PEG_TX[5]
eDP

K27 PCIE_CTX_GRX_P6 C78 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P6

PEG_TX[6] PCIE_CTX_GRX_P7 C77 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P7
J29 1 2
PEG_TX[7] PCIE_CTX_GRX_P8 C62 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P8
C17 eDP_TX[0] PEG_TX[8] J27 1 2
F16 H28 PCIE_CTX_GRX_P9 C61 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P9
eDP_TX[1] PEG_TX[9] PCIE_CTX_GRX_P10 C67 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P10
C16 G28 1 2
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_P11 C66 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P11
G15 E28 1 2
eDP_TX[3] PEG_TX[11] PCIE_CTX_GRX_P12 C69 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P12
PEG_TX[12] F28 1 2
C18 D27 PCIE_CTX_GRX_P13 C68 1 2 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P13
eDP_TX#[0] PEG_TX[13] PCIE_CTX_GRX_P14 C71 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P14
E16 E26 1 2
eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_P15 C70 DIS@ 0.22U_0402_10V6K PCIE_CTX_C_GRX_P15
D16 D25 1 2
eDP_TX#[2] PEG_TX[15]
F15 eDP_TX#[3]

Sandy Bridge_rPGA_Rev0p61 @
Close to CPU
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
FDI_INT 1 DIS@ 2
R689 1K_0402_5%
compatibility with future platforms having PCIE
FDI_FSYNC0 1 DIS@ 2 Gen3 (8GT/s)
R690 1K_0402_5%
FDI_FSYNC1 1 DIS@ 2
R695 1K_0402_5%
A
FDI_LSYNC0 1 DIS@ 2 A
R696 1K_0402_5%
FDI_LSYNC1 1 DIS@ 2
R697 1K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_DMI/PEG/FDI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS PHQAA LA-6831P M/B

www.vinafix.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 02, 2010 Sheet 6 of 58
5 4 3 2 1
 5 4 3 2 1

JCPUC JCPUD
<11> DDR_A_D[0..63]
<12> DDR_B_D[0..63]

AB6 DDRA_CLK0 AE2 DDRB_CLK0

SA_CLK[0] DDRA_CLK0# DDRA_CLK0 <11> SB_CLK[0] DDRB_CLK0# DDRB_CLK0 <12>
AA6 DDRA_CLK0# <11> AD2 DDRB_CLK0# <12>
DDR_A_D0 SA_CLK#[0] DDRA_CKE0 DDR_B_D0 SB_CLK#[0] DDRB_CKE0
C5 SA_DQ[0] SA_CKE[0] V9 DDRA_CKE0 <11> C9 SB_DQ[0] SB_CKE[0] R9 DDRB_CKE0 <12>
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 D10
DDR_A_D3 SA_DQ[2] DDR_B_D3 SB_DQ[2]
D2 C8
DDR_A_D4 SA_DQ[3] DDRA_CLK1 DDR_B_D4 SB_DQ[3] DDRB_CLK1
D6 SA_DQ[4] SA_CLK[1] AA5 DDRA_CLK1 <11> A9 SB_DQ[4] SB_CLK[1] AE1 DDRB_CLK1 <12>
D DDR_A_D5 DDRA_CLK1# DDR_B_D5 DDRB_CLK1# D
C6 AB5 DDRA_CLK1# <11> A8 AD1 DDRB_CLK1# <12>
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDRA_CKE1 DDR_B_D6 SB_DQ[5] SB_CLK#[1] DDRB_CKE1
C2 SA_DQ[6] SA_CKE[1] V10 DDRA_CKE1 <11> D9 SB_DQ[6] SB_CKE[1] R10 DDRB_CKE1 <12>
DDR_A_D7 C3 DDR_B_D7 D8
DDR_A_D8 SA_DQ[7] DDR_B_D8 SB_DQ[7]
F10 G4
DDR_A_D9 SA_DQ[8] DDR_B_D9 SB_DQ[8]
F8 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 SA_DQ[10] SA_CLK[2] AB4 F1 SB_DQ[10] SB_CLK[2] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] SA_CLK#[2] DDR_B_D12 SB_DQ[11] SB_CLK#[2]
F9 SA_DQ[12] SA_CKE[2] W9 G5 SB_DQ[12] SB_CKE[2] T9
DDR_A_D13 F7 DDR_B_D13 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 F2
DDR_A_D15 SA_DQ[14] DDR_B_D15 SB_DQ[14]
G7 SA_DQ[15] G2 SB_DQ[15]
DDR_A_D16 K4 AB3 DDR_B_D16 J7 AA1
DDR_A_D17 SA_DQ[16] SA_CLK[3] DDR_B_D17 SB_DQ[16] SB_CLK[3]
K5 SA_DQ[17] SA_CLK#[3] AA3 J8 SB_DQ[17] SB_CLK#[3] AB1
DDR_A_D18 K1 W10 DDR_B_D18 K10 T10
DDR_A_D19 SA_DQ[18] SA_CKE[3] DDR_B_D19 SB_DQ[18] SB_CKE[3]
J1 SA_DQ[19] K9 SB_DQ[19]
DDR_A_D20 J5 DDR_B_D20 J9
DDR_A_D21 SA_DQ[20] DDR_B_D21 SB_DQ[20]
J4 SA_DQ[21] J10 SB_DQ[21]
DDR_A_D22 J2 AK3 DDRA_SCS0# DDR_B_D22 K8 AD3 DDRB_SCS0#
DDR_A_D23 SA_DQ[22] SA_CS#[0] DDRA_SCS1# DDRA_SCS0# <11> DDR_B_D23 SB_DQ[22] SB_CS#[0] DDRB_SCS1# DDRB_SCS0# <12>
K2 SA_DQ[23] SA_CS#[1] AL3 DDRA_SCS1# <11> K7 SB_DQ[23] SB_CS#[1] AE3 DDRB_SCS1# <12>
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 SA_DQ[24] SA_CS#[2] DDR_B_D25 SB_DQ[24] SB_CS#[2]
N10 SA_DQ[25] SA_CS#[3] AH1 N4 SB_DQ[25] SB_CS#[3] AE6
DDR_A_D26 N8 DDR_B_D26 N2
DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
DDR_A_D29 SA_DQ[28] DDRA_ODT0 DDR_B_D29 SB_DQ[28] DDRB_ODT0
M9 AH3 DDRA_ODT0 <11> N5 AE4 DDRB_ODT0 <12>
SA_DQ[29] SA_ODT[0] SB_DQ[29] SB_ODT[0]

DDR SYSTEM MEMORY B

DDR_A_D30 N9 AG3 DDRA_ODT1 DDR_B_D30 M2 AD4 DDRB_ODT1

DDR SYSTEM MEMORY A

DDR_A_D31 SA_DQ[30] SA_ODT[1] DDRA_ODT1 <11> DDR_B_D31 SB_DQ[30] SB_ODT[1] DDRB_ODT1 <12>
M7 AG2 M1 AD5
DDR_A_D32 SA_DQ[31] SA_ODT[2] DDR_B_D32 SB_DQ[31] SB_ODT[2]
AG6 SA_DQ[32] SA_ODT[3] AH2 AM5 SB_DQ[32] SB_ODT[3] AE5
DDR_A_D33 AG5 DDR_B_D33 AM6
DDR_A_D34 SA_DQ[33] DDR_B_D34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
DDR_A_D35 AK5 DDR_B_D35 AP3
DDR_A_D36 SA_DQ[35] DDR_B_D36 SB_DQ[35]
AH5 SA_DQ[36] DDR_A_DQS#[0..7] <11> AN3 SB_DQ[36] DDR_B_DQS#[0..7] <12>
C DDR_A_D37 DDR_A_DQS#0 DDR_B_D37 DDR_B_DQS#0 C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 SA_DQ[39] SA_DQS#[2] J3 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D40 AJ8 M6 DDR_A_DQS#3 DDR_B_D40 AP5 N3 DDR_B_DQS#3
DDR_A_D41 SA_DQ[40] SA_DQS#[3] SB_DQ[40] SB_DQS#[3]
AK8 SA_DQ[41] SA_DQS#[4] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[41] SB_DQS#[4] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 AM8 DDR_A_DQS#5 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
DDR_A_D43 SA_DQ[42] SA_DQS#[5] SB_DQ[42] SB_DQS#[5]
AK9 SA_DQ[43] SA_DQS#[6] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[43] SB_DQS#[6] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 SA_DQ[45] AN8 SB_DQ[45]
DDR_A_D46 AL9 DDR_B_D46 AR6
DDR_A_D47 SA_DQ[46] DDR_B_D47 SB_DQ[46]
AL8 SA_DQ[47] AR5 SB_DQ[47]
DDR_A_D48 AP11 DDR_B_D48 AR9
SA_DQ[48] DDR_A_DQS[0..7] <11> SB_DQ[48] DDR_B_DQS[0..7] <12>
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 F6 AT8 G3
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AM12 SA_DQ[51] SA_DQS[2] K3 AT9 SB_DQ[51] SB_DQS[2] J6
DDR_A_D52 AM11 N6 DDR_A_DQS3 DDR_B_D52 AH11 M3 DDR_B_DQS3
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AL11 AL5 AR8 AN6
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D55 AH12 AK11 DDR_B_DQS6
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D57 AH14 DDR_B_D57 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 AR14
DDR_A_D59 SA_DQ[58] DDR_B_D59 SB_DQ[58]
AK15 DDR_A_MA[0..15] <11> AT14
DDR_A_D60 SA_DQ[59] DDR_B_D60 SB_DQ[59]
AL14 AT12 DDR_B_MA[0..15] <12>
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AK14 AD10 AN15 AA8
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 W1 AR15 T7
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
AH15 SA_DQ[63] SA_MA[2] W2 AT15 SB_DQ[63] SB_MA[2] R7
W7 DDR_A_MA3 T6 DDR_B_MA3
SA_MA[3] DDR_A_MA4 SB_MA[3] DDR_B_MA4
V3 T2
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
V2 T4
SA_MA[5] DDR_A_MA6 SB_MA[5] DDR_B_MA6
W3 T3
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS0 SB_MA[6] DDR_B_MA7
<11> DDR_A_BS0 AE10 W6 <12> DDR_B_BS0 AA9 R2
B DDR_A_BS1 SA_BS[0] SA_MA[7] DDR_A_MA8 DDR_B_BS1 SB_BS[0] SB_MA[7] DDR_B_MA8 B
<11> DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 <12> DDR_B_BS1 AA7 SB_BS[1] SB_MA[8] T5
DDR_A_BS2 V6 W5 DDR_A_MA9 DDR_B_BS2 R6 R3 DDR_B_MA9
<11> DDR_A_BS2 SA_BS[2] SA_MA[9] DDR_A_MA10 <12> DDR_B_BS2 SB_BS[2] SB_MA[9] DDR_B_MA10
SA_MA[10] AD8 SB_MA[10] AB7
V4 DDR_A_MA11 R1 DDR_B_MA11
SA_MA[11] DDR_A_MA12 SB_MA[11] DDR_B_MA12
W4 T1
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_CAS# SB_MA[12] DDR_B_MA13
<11> DDR_A_CAS# AE8 AF8 <12> DDR_B_CAS# AA10 AB10
DDR_A_RAS# SA_CAS# SA_MA[13] DDR_A_MA14 DDR_B_RAS# SB_CAS# SB_MA[13] DDR_B_MA14
<11> DDR_A_RAS# AD9 V5 <12> DDR_B_RAS# AB8 R5
DDR_A_WE# SA_RAS# SA_MA[14] DDR_A_MA15 DDR_B_WE# SB_RAS# SB_MA[14] DDR_B_MA15
<11> DDR_A_WE# AF9 V7 <12> DDR_B_WE# AB9 R4
SA_WE# SA_MA[15] SB_WE# SB_MA[15]

Sandy Bridge_rPGA_Rev0p61 @ Sandy Bridge_rPGA_Rev0p61 @

+1.5V

R466
1

0_0402_5%
1 2 R465
@ 1K_0402_5%

R467
2

Q14 1K_0402_5%
S

H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
<5> H_DRAMRST# SM_DRAMRST# <11,12>
2

BSS138_NL_SOT23-3
R464
G
2

4.99K_0402_1%
A A
1

<29> DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL

R463 0_0402_5%
1 Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
C140
0.047U_0402_25V6K Issued Date 200910/9 2010/01/23 Title
Deciphered Date
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_DDR3
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 7 of 58
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE

JCPUF POWER +1.05VS_VCCP Decoupling:

2X 330U (6m ohm), 12X 22U
94A (Quad Core 45W) +1.05VS_VCCP
53A (SV 35W) 8.5A TOP Socket Cavity x 7
D D

AG35
VCC1 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AG34 AH13
VCC2 VCCIO1
AG33 AH10 1 1 1 1 1 1 1 1 1 1
VCC3 VCCIO2 C146 C144 C143 C141 C137 C136 C135 C134 C133 C142
AG32 AG10
VCC4 VCCIO3
AG31
AG30
VCC5 VCCIO4
AC10
Y10
+CPU_CORE Decoupling:
VCC6 VCCIO5 2 2 2 2 2 2 2 2 2 2
AG29
VCC7 VCCIO6
U10 4X 470U (4m ohm), 16X 22U, 10X 10U
AG28 P10
VCC8 VCCIO7 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
22U_0805_6.3V6M
AF34
AF33
VCC12 VCCIO11
J12
J11 1 1 1 1 1 1 1 1 1
Bottom Socket Cavity
VCC13 VCCIO12 C147 C145 C163 C153 C160 C152 C139 C138 C132
AF32 H14
VCC14 VCCIO13 @ @ @ @ @ @ @
AF31 H12
VCC15 VCCIO14 +CPU_CORE
AF30 H11
VCC16 VCCIO15 2 2 2 2 2 2 2 2 2
AF29 G14
VCC17 VCCIO16
AF28 G13
PEG AND DDR

VCC18 VCCIO17 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
AF27 G12
VCC19 VCCIO18
AF26 F14
VCC20 VCCIO19
AD35 F13 1 1 1 1 1 1 1 1 1 1 1
VCC21 VCCIO20 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111
AD34 F12
VCC22 VCCIO21 330U_D2_2V_Y
AD33 F11
VCC23 VCCIO22 @
AD32 E14
VCC24 VCCIO23 ESR 9mohm 2 2 2 2 2 2 2 2 2 2 2
AD31 E12 1 1 1
VCC25 VCCIO24
AD30
AD29
VCC26
E11
Bottom Socket Cavity x 5 C10 + C11 + C12 + 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
VCC27 VCCIO25
AD28 D14
VCC28 VCCIO26 330U_D2_2V_Y @ 330U_D2_2V_Y
AD27 D13
VCC29 VCCIO27 2 2 2
AD26 D12
VCC30 VCCIO28
AC35 D11
C VCC31 VCCIO29 C
AC34 C14
VCC32 VCCIO30
AC33 C13
VCC33 VCCIO31
AC32 C12
VCC34 VCCIO32
AC31 C11
VCC35 VCCIO33
AC30 B14
VCC36 VCCIO34
AC29 B12
VCC37 VCCIO35
AC28
AC27
VCC38 VCCIO36
A14
A13
Top Socket Edge
VCC39 VCCIO37
AC26 A12
VCC40 VCCIO38 +CPU_CORE
AA35 A11
VCC41 VCCIO39
AA34
VCC42
AA33 J23
VCC43 VCCIO40 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AA32
VCC44
AA31
VCC45
AA30 1 1 1 1 1 1 1 1 1 1 1
VCC46 C159 C151 C130 C129 C124 C123 C122 C121 C131 C126 C125
AA29
VCC47
AA28
VCC48 @ @ @
AA27
VCC49 2 2 2 2 2 2 2 2 2 2 2
AA26
CORE SUPPLY

VCC50
Y35
VCC51 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
Y34
VCC52
Y33
VCC53 +1.05VS_VCCP +1.05VS_VCCP
Y32
VCC54
Y31
VCC55
Y30
VCC56
1

Y29
VCC57 R70 R68
Y28
VCC58 130_0402_5% 75_0402_5%
Y27
VCC59
Y26
V35
VCC60 Top Socket Cavity
SVID

VCC61 H_CPU_SVIDALRT#
V34 AJ29 1 2 VR_SVID_ALRT# <55>
VCC62 VIDALERT# H_CPU_SVIDCLK R67 1 +CPU_CORE
V33 AJ30 2 43_0402_1% VR_SVID_CLK <55>
VCC63 VIDSCLK H_CPU_SVIDDAT R63 1
B V32 AJ28 2 0_0402_5% VR_SVID_DAT <55>
B
VCC64 VIDSOUT R66 0_0402_5%
V31
VCC65 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
V30
VCC66 Pull high resistor on VR side
V29
VCC67
V28 1 1 1 1 1 1 1 1
VCC68 C158 C150 C128 C127 C120 C118 C119 C117
V27
VCC69
V26
VCC70
U35
VCC71 2 2 2 2 2 2 2 2
U34
VCC72
U33
VCC73 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78 +CPU_CORE
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82 Co-Lay with C2, C5, C7, C9 Bottom Socket Edge
2

R33
VCC83 R64
R32
VCC84 Close to CPU
R31 100_0402_1%
VCC85 +CPU_CORE +CPU_CORE
R30
VCC86
R29
1
SENSE LINES

VCC87 330U_D2_2VM_R6M 330U_D2_2V_Y

R28
VCC88
R27 AJ35 VCCSENSE_R R65 1 2 0_0402_5% VCCSENSE <55>
VCC89 VCC_SENSE
R26 AJ34 VSSSENSE_R R52 1 2 0_0402_5% VSSSENSE <55> 1 1 1 1 1 1
VCC90 VSS_SENSE @ @
P35
VCC91 + C890 + C891 C2 + C5 + C7 + C9 +
P34
VCC92
1

P33
VCC93 VCCIO_SENSE R62 330U_D2_2V_Y 330U_D2_2V_Y
P32 B10 VCCIO_SENSE <54>
VCC94 VCCIO_SENSE 100_0402_1% 2 3 2 3 2 2 2 2
P31 A10
VCC95 VSSIO_SENSE
P30
VCC96
VSS_SENSE_VCCIO
2

A A
P29 330U_D2_2VM_R6M 330U_D2_2V_Y
2

VCC97 R102 R105

P28
VCC98 100_0402_1%
P27 0_0402_5%
VCC99 @
P26
VCC100
1

+1.05VS_VCCP
Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Close to CPU Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_POWER-1
Sandy Bridge_rPGA_Rev0p61 @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 8 of 58
5 4 3 2 1
 5 4 3 2 1

+GFX_CORE

+GFX_CORE Decoupling: ESR 17mohm R121 R74

1 0_0402_5% 100_0402_1% +GFX_CORE
2X 470U (4m ohm), 12X 22U C873 +
UMA@ UMA@

330U_2.5V_M_R17 R251 R75

2
+GFX_CORE OPT@ 0_0402_5% 100_0402_1%
Bottom Socket Edge
Co-lay for Cost Down Plan
2

JCPUG
POWER UMA@ UMA@ R74
100_0402_1%
OPT@
Close to CPU

1
SENSE
LINES
330U_D2_2VM_R6M AT24 AK35 VCC_AXG_SENSE_R R121 1 OPT@ 2 0_0402_5%
VAXG1 VAXG_SENSE VCC_AXG_SENSE <55>
1 1 AT23 AK34 VSS_AXG_SENSE_R R251 1 OPT@ 2 0_0402_5%
D VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <55> D
AT21 VAXG3
2

C112 + C113 + ESR 6mohm AT20 VAXG4

1
R71 AT18 +1.5V_CPU
@ @ 330U_D2_2VM_R6M VAXG5 R75
0_0402_5%
2 2
AT17 VAXG6 33A +V_SM_VREF should
DIS@ AR24 100_0402_1%
VAXG7 have 20 mil trace width

1
AR23 OPT@
1

VAXG8 R111 R122

AR21

2
VAXG9 0_0402_5% 100_0402_1%
AR20 VAXG10

VREF
AR18 VAXG11 2 1
AR17

2
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VAXG12 +V_SM_VREF_CNT +V_SM_VREF
AP24 VAXG13 SM_VREF AL1 2 3
AP23 VAXG14

1
1 1 1 1 1 1 AP21 1 Q2
C266 C267 C271 C338 C341 C342 VAXG15 R486 C148 @ R252
AP20 VAXG16
AP18 @ AP2302GN-HF_SOT23-3 100_0402_1%
VAXG17 1

100K_0402_5%

0.1U_0402_16V4Z
OPT@ OPT@ OPT@ OPT@ OPT@ OPT@
2 2 2 2 2 2
AP17
AN24
VAXG18 2 +1.5V_CPU Decoupling:

2
VAXG19
Bottom Socket 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AN23 VAXG20
RUN_ON_CPU1.5VS3 1X 330U (6m ohm), 6X 10U
AN21 VAXG21
Cavity AN20 VAXG22
+1.5V_CPU

DDR3 -1.5V RAILS

Bottom Socket Edge AN18 VAXG23 +1.5V_CPU
AN17 VAXG24 5A

GRAPHICS
AM24 AF7 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
VAXG25 VDDQ1
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M AM23 VAXG26 VDDQ2 AF4 1 ESR 6mohm ESR 17mohm
AM21 VAXG27 VDDQ3 AF1 1 1 1 1 1 1 1
AM20 AC7 C114 C115 C116 C149 C154 C155 + C180
1 1 1 1 1 1 VAXG28 VDDQ4
C343 C344 C345 C346 C347 C348 AM18 AC4 @ C875 +
VAXG29 VDDQ5 330U_D2_2VM_R6M 330U_2.5V_M_R17
AM17 VAXG30 VDDQ6 AC1
OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ AL24 Y7 2 2 2 2 2 2 2
2 2 2 2 2 2 VAXG31 VDDQ7 2
AL23 VAXG32 VDDQ8 Y4
10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
C Top Socket 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AL21
AL20
VAXG33 VDDQ9 Y1
U7 Co-lay for Cost Down Plan C
VAXG34 VDDQ10
Cavity AL18 VAXG35 VDDQ11 U4
Top Socket Edge AL17
AK24
VAXG36 VDDQ12 U1
P7
VAXG37 VDDQ13
AK23 VAXG38 VDDQ14 P4
22U_0805_6.3V6M 22U_0805_6.3V6M AK21 P1
VAXG39 VDDQ15
AK20 VAXG40
1 1 1 1 AK18 VAXG41
C349 C350 C351 C391 AK17 VAXG42
@ @ @ @
AJ24
AJ23
VAXG43 +VCCSA Decoupling:
2 2 2 2 VAXG44
AJ21 VAXG45 1X 330U (6m ohm), 3X 10U
AJ20 VAXG46
22U_0805_6.3V6M 22U_0805_6.3V6M AJ18 VAXG47 +VCCSA
VCCSA_VID0 VCCSA_VID1 +VCCSA
AJ17 VAXG48 Bottom Socket Cavity Co-lay for Cost Down Plan
AH24 6A

SA RAIL
VAXG49
AH23 VAXG50 +VCCSA
0 0 0.90 V For Sandy Bridge
AH21 M27 10U_0805_10V6K 10U_0805_10V6K
VAXG51 VCCSA1 ESR 17mohm
AH20 VAXG52 VCCSA2 M26
AH18 VAXG53 VCCSA3 L26 1 2 VCCSA_SENSE 0 1 0.80 V
AH17 VAXG54 VCCSA4 J26 1 1 1 1 1 R253 0_0402_5% 1
J25 C100 C447 C476 C477
VCCSA5 + +
VCCSA6 J24 C485 1 0 0.75 V
H26 @ @
VCCSA7 2 2 2 2 330U_D2_2VM_R6M
VCCPLL Decoupling: VCCSA8 H25
2 C877 2 1 1 0.65 V
1.8V RAIL

+1.8VS
1X 330U (6m ohm), 1X 10U, 2x1U 10U_0805_10V6K 10U_0805_10V6K 330U_2.5V_M_R17

1.2A Bottom Socket Edge

R76
2 1 10U_0805_10V6K +1.8VS_VCCPLL B6 H23 VCCSA_SENSE
VCCPLL1 VCCSA_SENSE VCCSA_SENSE <53>
MISC

B 0_0805_5% A6 B
VCCPLL2
1 A2 VCCPLL3 1 R95 2
C185 1 1 1 VCCSA_VID0 0_0402_5% @
@+ C186 C206 C230 C22 VCCSA_VID0
FC_C22
VCCSA_VID1 C24 VCCSAP_VID1 <53>
1U_0402_6.3V6K
2

2
2 2 2 2
R114 R119
330U_B2_2.5VM_R15M 1U_0402_6.3V6K Sandy Bridge_rPGA_Rev0p61 @
10K_0402_5% 10K_0402_5%
+1.5V_CPU +1.5V
1

1
PJ30 @
2 2 1 1
+1.5V_CPU +1.5V
Follow CRB 1.0. JUMP_43X118

C213 1 2 0.1U_0402_16V4Z Q33

1 S D 8
C212 1 2 0.1U_0402_16V4Z 2 7
S D

2
C112 C267 C338 C271 1 3 6
330U_D2_2VM_R6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C211 1 S D
2 0.1U_0402_16V4Z R449 C179 4 G D 5
@ UMA@ UMA@ UMA@ 470_0805_5% 10U_0805_10V4K
C210 1 2 0.1U_0402_16V4Z FDS6676AS_SO8 R455
C347 C343 C345 C873 2 RUN_ON_CPU1.5VS3 1 2 +VSB

3 1
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 330U_2.5V_M_R17 220K_0402_5%
UMA@ UMA@ UMA@ UMA@

6
Q46B 1
C348 C344 C346 C472 R420 Q46A
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M SUSP 5 0.1U_0402_25V6 820K_0402_5%
UMA@ UMA@ UMA@ 2 SUSP
2 SUSP <5,47,54>
2N7002DW-T/R7_SOT363-6

2
A C266 C341 C342 2N7002DW-T/R7_SOT363-6 A

1
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
UMA@ UMA@ UMA@

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_POWER-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 9 of 58
5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

JCPUH JCPUI JCPUE (CFG[17:0] internal pull high to VCCIO)
AT35 AJ22
VSS1 VSS81
AT32 AJ19 L7
VSS2 VSS82 RSVD28 CFG2
AT29 AJ16 T35 F22 AG7
VSS3 VSS83 VSS161 VSS234 CFG0 RSVD29
AT27 AJ13 T34 F19 <5> CFG0 AK28 AE7
VSS4 VSS84 VSS162 VSS235 CFG[0] RSVD30

1
AT25 AJ10 T33 E30 T5 PAD CFG1 AK29 AK2
VSS5 VSS85 VSS163 VSS236 T6 PAD CFG2 CFG[1] RSVD31 R254
AT22 AJ7 T32 E27 AL26 W8
VSS6 VSS86 VSS164 VSS237 T7 PAD CFG3 CFG[2] RSVD32 1K_0402_1%
AT19 AJ4 T31 E24 AL27
VSS7 VSS87 VSS165 VSS238 T11 PAD CFG4 CFG[3] @
AT16 AJ3 T30 E21 AK26
VSS8 VSS88 VSS166 VSS239 T12 PAD CFG5 CFG[4]
AT13 AJ2 T29 E18 AL29 AT26

2
VSS9 VSS89 VSS167 VSS240 T15 PAD CFG6 CFG[5] RSVD33
AT10 AJ1 T28 E15 AL30 AM33
VSS10 VSS90 VSS168 VSS241 T18 PAD CFG7 CFG[6] RSVD34
D AT7 AH35 T27 E13 AM31 AJ27 D
VSS11 VSS91 VSS169 VSS242 T16 PAD CFG8 CFG[7] RSVD35
AT4 AH34 T26 E10 AM32
VSS12 VSS92 VSS170 VSS243 T19 PAD CFG9 CFG[8]
AT3 AH32 P9 E9 AM30
VSS13 VSS93 VSS171 VSS244 T21 PAD CFG10 CFG[9]
AR25 AH30 P8 E8 AM28
VSS14 VSS94 VSS172 VSS245 T20 PAD CFG11 CFG[10]
AR22 AH29 P6 E7 AM26
VSS15 VSS95 VSS173 VSS246 CFG[11]
AR19
VSS16 VSS96
AH28 P5
VSS174 VSS247
E6 <5> CFG12 CFG12 AN28
CFG[12]
PEG Static Lane Reversal - CFG2 is for the 16x
AR16 AH26 P3 E5 <5> CFG13 CFG13 AN31 T8
VSS17 VSS97 VSS175 VSS248 CFG14 CFG[13] RSVD37
AR13 AH25 P2 E4 <5> CFG14 AN26 J16
VSS18 VSS98 VSS176 VSS249 CFG15 CFG[14] RSVD38
AR10 AH22 N35 E3 AM27 H16 1: Normal Operation; Lane # definition matches
AR7
AR4
VSS19
VSS20
VSS21
VSS99
VSS100
VSS101
AH19
AH16
N34
N33
VSS177
VSS178
VSS179
VSS250
VSS251
VSS252
E2
E1
<5> CFG15
T26 PAD
T27 PAD
CFG16
CFG17
AK31
AN29
CFG[15]
CFG[16]
CFG[17]
RSVD39
RSVD40
G16
CFG2
* socket pin map definition
AR2 AH7 N32 D35
VSS22 VSS102 VSS180 VSS253
AP34
VSS23 VSS103
AH4 N31
VSS181 VSS254
D32 0:Lane Reversed
AP31 AG9 N30 D29
VSS24 VSS104 VSS182 VSS255
AP28 AG8 N29 D26 AR35
VSS25 VSS105 VSS183 VSS256 T22 PAD RSVD41 CFG4
AP25 AG4 N28 D20 AJ31 AT34
VSS26 VSS106 VSS184 VSS257 T24 PAD RSVD1 RSVD42
AP22 AF6 N27 D17 AH31 AT33
VSS27 VSS107 VSS185 VSS258 RSVD2 RSVD43

1
AP19 AF5 N26 C34 T25 PAD AJ33 AP35
VSS28 VSS108 VSS186 VSS259 T23 PAD RSVD3 RSVD44 R255
AP16 AF3 M34 C31 AH33 AR34
VSS29 VSS109 VSS187 VSS260 RSVD4 RSVD45 1K_0402_1%
AP13 AF2 L33 C28
VSS30 VSS110 VSS188 VSS261 @
AP10 AE35 L30 C27
VSS31 VSS111 VSS189 VSS262
AP7 AE34 L27 C25 AJ26

2
VSS32 VSS112 VSS190 VSS263 RSVD5

RESERVED
AP4 AE33 L9 C23
VSS33 VSS113 VSS191 VSS264
AP1 AE32 L8 C10
VSS34 VSS114 VSS192 VSS265
AN30
VSS35 VSS115
AE31 L6
VSS193 VSS266
C1 SA_DIMM_VREFDQ RSVD46
B34
AN27 AE30 L5 B22 CPU_RSVD6 B4 A33
VSS36 VSS116 VSS194 VSS267 CPU_RSVD7 RSVD6 RSVD47
AN25 AE29 L4 B19 D1 A34
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
RSVD7
SB_DIMM_VREFDQ RSVD48
RSVD49
RSVD50
B35
C35 Embedded Display Port Presence Strap

1
AN16 AE26 L1 B13
VSS40 VSS120 VSS198 VSS271
AN13 AE9 K35 B11 F25
VSS41 VSS121 VSS199 VSS272 R115 R116 RSVD8
AN10 AD7 K32 B9 F24 1 : Disabled; No Physical Display Port
C
AN7
AN4
VSS42
VSS43
VSS122
VSS123
AC9
AC8
K29
K26
VSS200
VSS201
VSS273
VSS274
B8
B7
1K_0402_1% 1K_0402_1% F23
D24
RSVD9
RSVD10
AJ32
* attached to Embedded Display Port
C

2
VSS44 VSS124 VSS202 VSS275 RSVD11 RSVD51
AM29
VSS45 VSS125
AC6 J34
VSS203 VSS276
B5 G25
RSVD12 RSVD52
AK32 CFG4
AM25
VSS46 VSS126
AC5 J31
VSS204 VSS277
B3 G24
RSVD13 0 : Enabled; An external Display Port device is
AM22 AC3 H33 B2 E23 connected to the Embedded Display Port
VSS47 VSS127 VSS205 VSS278 RSVD14
AM19 AC2 H30 A35 D23
VSS48 VSS128 VSS206 VSS279 RSVD15
AM16 AB35 H27 A32 C30 AH27
VSS49 VSS129 VSS207 VSS280 RSVD16 RSVD53 T28 PAD
AM13 AB34 H24 A29 A31
VSS50 VSS130 VSS208 VSS281 RSVD17
AM10 AB33 H21 A26 B30
VSS51 VSS131 VSS209 VSS282 RSVD18 CFG6
AM7 AB32 H18 A23 B29
VSS52 VSS132 VSS210 VSS283 RSVD19
AM4 AB31 H15 A20 D30 AN35 CLK_RES_ITP <29>
VSS53 VSS133 VSS211 VSS284 RSVD20 RSVD54 CFG5
AM3 AB30 H13 A3 B31 AM35 CLK_RES_ITP# <29>
VSS54 VSS134 VSS212 VSS285 RSVD21 RSVD55
AM2 AB29 H10 A30
VSS55 VSS135 VSS213 RSVD22

1
AM1 AB28 H9 C29
VSS56 VSS136 VSS214 RSVD23 R257 R256
AL34 AB27 H8
VSS57 VSS137 VSS215 1K_0402_1% 1K_0402_1%
AL31 AB26 H7
VSS58 VSS138 VSS216 @ @
AL28 Y9 H6 J20
VSS59 VSS139 VSS217 RSVD24
AL25 Y8 H5 B18 AT2

2
VSS60 VSS140 VSS218 RSVD25 RSVD56
AL22 Y6 H4 A19 AT1
VSS61 VSS141 VSS219 RSVD26 RSVD57
AL19
VSS62 VSS142
Y5 H3
VSS220
VCCIO_SEL RSVD58
AR1
AL16 Y3 H2
VSS63 VSS143 VSS221
AL13 Y2 H1 J15
VSS64 VSS144 VSS222 RSVD27
AL10 W35 G35
VSS65 VSS145 VSS223
AL7 W34 G32
VSS66 VSS146 VSS224
AL4 W33 G29 B1
VSS67 VSS147 VSS225 KEY
AL2 W32 G26
VSS68 VSS148 VSS226
AK33
VSS69 VSS149
W31 G23
VSS227 PCIE Port Bifurcation Straps
AK30 W30 G20
VSS70 VSS150 VSS228
AK27 W29 G17
VSS71 VSS151 VSS229
AK25 W28 G11 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
AK22
AK19
VSS72
VSS73
VSS74
VSS152
VSS153
VSS154
W27
W26
F34
F31
VSS230
VSS231
VSS232
Sandy Bridge_rPGA_Rev0p61 @ *10: x8, x8 - Device 1 function 1 enabled ; function 2 B
AK16 U9 F29 disabled
VSS75 VSS155 VSS233
AK13
VSS76 VSS156
U8 CFG[6:5]
AK10
VSS77 VSS157
U6 01: Reserved - (Device 1 function 1 disabled ; function
AK7 U5 2 enabled)
VSS78 VSS158
AK4 U3
VSS79 VSS159
AJ25
VSS80 VSS160
U2 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Sandy Bridge_rPGA_Rev0p61 @ Sandy Bridge_rPGA_Rev0p61 @ CFG7

1
R258
1K_0402_1%
@

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

de assertion
CFG7
0: PEG Wait for BIOS for training
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy Bridge_GND/RSVD/CFG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B

www.vinafix.vn
Date: Monday, August 02, 2010 Sheet 10 of 58
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V
JDDRL DDR3 SO-DIMM A
1 2
+VREF_DQA
DDR_A_D0
3
VREF_DQ
VSS
VSS
DQ4 4 DDR_A_D4
DDR_A_D5
Reverse Type DDR_A_DQS[0..7] <7>

5 DQ0 DQ5 6 DDR_A_DQS#[0..7] <7>

1 1 DDR_A_D1 7 8
C156 C157 DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10 DDR_A_D[0..63] <7>
11 12 DDR_A_DQS0
DM0 DQS0
0.1U_0402_16V4Z

2.2U_0603_6.3V4Z
13 VSS VSS 14 DDR_A_MA[0..15] <7>
2 2 DDR_A_D2 15 16 DDR_A_D6
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
D
23 DQ9 DQ13 24 D
25 VSS VSS 26
DDR_A_DQS#1 27 28
DDR_A_DQS1 DQS1# DM1 SM_DRAMRST#
Close to JDDRL.1 29 DQS1 RESET# 30 SM_DRAMRST# <7,12> +1.5V
31 VSS VSS 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36

1
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20 R79
DDR_A_D17 DQ16 DQ20 DDR_A_D21 1K_0402_1%
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_A_DQS#2 45 46

2
DDR_A_DQS2 DQS2# DM2 +VREF_DQA_DIMMA
47 DQS2 VSS 48 +VREF_DQA 2 1
49 50 DDR_A_D22 0_0402_5% R92
VSS DQ22

1
DDR_A_D18 51 52 DDR_A_D23
DDR_A_D19 DQ18 DQ23 R81
53 DQ19 VSS 54
55 56 DDR_A_D28 1K_0402_1%
DDR_A_D24 VSS DQ28 DDR_A_D29
57 DQ24 DQ29 58
DDR_A_D25 59 60

2
DQ25 VSS DDR_A_DQS#3
61 VSS DQS3# 62
63 64 DDR_A_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS VSS 72

DDRA_CKE0 73 74 DDRA_CKE1
<7> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <7>
75 VDD VDD 76
77 78 DDR_A_MA15
DDR_A_BS2 NC A15 DDR_A_MA14
C
<7> DDR_A_BS2 79 BA2 A14 80 C
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD VDD 100
DDRA_CLK0 101 102 DDRA_CLK1
<7> DDRA_CLK0 CK0 CK1 DDRA_CLK1 <7>
DDRA_CLK0# 103 104 DDRA_CLK1#
<7> DDRA_CLK0# CK0# CK1# DDRA_CLK1# <7>
105 VDD VDD 106
DDR_A_MA10 DDR_A_BS1 +1.5V
107 A10/AP BA1 108 DDR_A_BS1 <7>
DDR_A_BS0 109 110 DDR_A_RAS#
<7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
111 VDD VDD 112

1
DDR_A_WE# 113 114 DDRA_SCS0#
<7> DDR_A_WE# W E# S0# DDRA_SCS0# <7>
DDR_A_CAS# 115 116 DDRA_ODT0 R80
<7> DDR_A_CAS# CAS# ODT0 DDRA_ODT0 <7>
117 118 1K_0402_1%
DDR_A_MA13 VDD VDD DDRA_ODT1
119 A13 ODT1 120 DDRA_ODT1 <7>
DDRA_SCS1# 121 122

2
<7> DDRA_SCS1# S1# NC R89
123 VDD VDD 124
125 126 +VREF_CAA 1 2 +VREF_CAA_DIMMA
TEST VREF_CA 0_0402_5%
127 VSS VSS 128

1
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37 R82
131 DQ33 DQ37 132
133 134 1K_0402_1%
DDR_A_DQS#4 VSS VSS
135 DQS4# DM4 136
DDR_A_DQS4 137 138 1 1

2
B DQS4 VSS DDR_A_D38 C161 C162 B
139 VSS DQ38 140
DDR_A_D34 141 142 DDR_A_D39
DQ34 DQ39
2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

DDR_A_D35 143 144

DQ35 VSS DDR_A_D44 2 2
145 VSS DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_A_DQS#5 Layout Note: Layout Note: Place these 4 Caps near Layout Note:
VSS DQS5# DDR_A_DQS5
153 DM5 DQS5 154
155 VSS VSS 156 Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160 close to JDDRL.126
161 VSS VSS 162
+1.5V
Change C218 to OSCON at DVT
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53 +1.5V +0.75VS
165 DQ49 DQ53 166
167 168 C218 1 + 2 390U_2.5V_M_R10
DDR_A_DQS#6 VSS VSS
169 DQS6# DM6 170
DDR_A_DQS6 171 172 C164 1 2 0.1U_0402_16V4Z C165 1 2 10U_0805_6.3V6M
DQS6 VSS DDR_A_D54 C166 1
173 VSS DQ54 174 2 10U_0805_6.3V6M
DDR_A_D50 175 176 DDR_A_D55 C167 1 2 0.1U_0402_16V4Z
DDR_A_D51 DQ50 DQ55 C168 1
177 DQ51 VSS 178 2 10U_0805_6.3V6M C169 2 1 1U_0402_6.3V4Z
179 180 DDR_A_D60 C170 1 2 0.1U_0402_16V4Z
DDR_A_D56 VSS DQ60 DDR_A_D61 C171 1
181 DQ56 DQ61 182 2 10U_0805_6.3V6M C172 2 1 1U_0402_6.3V4Z
DDR_A_D57 183 184 C173 1 2 0.1U_0402_16V4Z
DQ57 VSS DDR_A_DQS#7 C174 1
185 VSS DQS7# 186 2 10U_0805_6.3V6M C175 2 1 1U_0402_6.3V4Z
187 188 DDR_A_DQS7
DM7 DQS7 C176 1
189 VSS VSS 190 2 10U_0805_6.3V6M C177 2 1 1U_0402_6.3V4Z
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63 C178 1
193 DQ59 DQ63 194 2 10U_0805_6.3V6M
R90 1 2 195 196
10K_0402_5% VSS VSS
A 197 SA0 EVENT# 198 A
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA <12,29,39>
PM_SMBCLK
0.1U_0402_16V4Z

201 202
2.2U_0603_6.3V4Z

SA1 SCL PM_SMBCLK <12,29,39>

1 1 +0.75VS 203 VTT VTT 204 +0.75VS
1

C182
C181 205 206
R91 GND1 BOSS1
207 208
2 2 10K_0402_5% GND2 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 200910/9 Deciphered Date 2010/01/23 Title
2

FOX_AS0A626-U2SN-7F_204P
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 11 of 58
5 4 3 2 1
 A B C D E

+1.5V +1.5V
JDDRH
1 2
+VREF_DQB
DDR_B_D0
3
VREF_DQ
VSS
VSS
DQ4 4 DDR_B_D4
DDR_B_D5
Reverse Type
5 6
DDR_B_D1 7
DQ0
DQ1
DQ5
VSS 8
DDR_B_DQS#0
DDR3 SO-DIMM B
9 VSS DQS0# 10
11 12 DDR_B_DQS0
DM0 DQS0
1 1 13 VSS VSS 14
C183 C184 DDR_B_D2 15 16 DDR_B_D6 DDR_B_DQS#[0..7] <7>
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
2.2U_0603_6.3V4Z

0.1U_0402_16V4Z
19 VSS VSS 20 DDR_B_DQS[0..7] <7>
2 2 DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
1
23 DQ9 DQ13 24 DDR_B_D[0..63] <7> 1
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_MA[0..15] <7>
DDR_B_DQS1 DQS1# DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# <7,11>
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
Close to JDDRH.1 35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 DDR_B_D20 +1.5V
39 DQ16 DQ20 40
DDR_B_D17 41 42 DDR_B_D21
DQ17 DQ21
43 VSS VSS 44

1
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS2# DM2 R83
47 DQS2 VSS 48
49 50 DDR_B_D22 1K_0402_1%
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54

2
DQ19 VSS DDR_B_D28 +VREF_DQB_DIMMB
55 VSS DQ28 56 +VREF_DQB 2 1
DDR_B_D24 57 58 DDR_B_D29 0_0402_5% R93
DQ24 DQ29

1
DDR_B_D25 59 60
DQ25 VSS DDR_B_DQS#3 R84
61 VSS DQS3# 62
63 64 DDR_B_DQS3 1K_0402_1%
DM3 DQS3
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30

2
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72

DDRB_CKE0 73 74 DDRB_CKE1
<7> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <7>
75 VDD VDD 76
77 78 DDR_B_MA15
DDR_B_BS2 NC A15 DDR_B_MA14
2
<7> DDR_B_BS2 79 BA2 A14 80 2
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
DDRB_CLK0 101 102 DDRB_CLK1
<7> DDRB_CLK0 CK0 CK1 DDRB_CLK1 <7>
DDRB_CLK0# 103 104 DDRB_CLK1#
<7> DDRB_CLK0# CK0# CK1# DDRB_CLK1# <7>
105 VDD VDD 106
DDR_B_MA10 DDR_B_BS1 +1.5V
107 A10/AP BA1 108 DDR_B_BS1 <7>
DDR_B_BS0 109 110 DDR_B_RAS#
<7> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7>
111 VDD VDD 112

1
DDR_B_WE# 113 114 DDRB_SCS0#
<7> DDR_B_WE# W E# S0# DDRB_SCS0# <7>
DDR_B_CAS# 115 116 DDRB_ODT0 R86
<7> DDR_B_CAS# CAS# ODT0 DDRB_ODT0 <7>
117 118 1K_0402_1%
DDR_B_MA13 VDD VDD DDRB_ODT1
119 A13 ODT1 120 DDRB_ODT1 <7>
DDRB_SCS1# 121 122

2
<7> DDRB_SCS1# S1# NC R97
123 VDD VDD 124
125 126 +VREF_CAB 1 2 +VREF_CAB_DIMMB
TEST VREF_CA 0_0402_5%
127 VSS VSS 128

1
DDR_B_D37 129 130 DDR_B_D32
DDR_B_D36 DQ32 DQ36 DDR_B_D33 R94
131 DQ33 DQ37 132
133 134 1K_0402_1%
DDR_B_DQS#4 VSS VSS
135 DQS4# DM4 136 1 1
DDR_B_DQS4 137 138 C187 C188

2
3 DQS4 VSS DDR_B_D38 3
139 VSS DQ38 140
2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

DDR_B_D34 141 142 DDR_B_D39

DDR_B_D35 DQ34 DQ39 2 2
143 DQ35 VSS 144
145 146 DDR_B_D44
DDR_B_D40 VSS DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
151 VSS DQS5# 152
153 154 DDR_B_DQS5
DM5 DQS5
DDR_B_D42
155 VSS VSS 156
DDR_B_D46
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DDR_B_D43
157 DQ42 DQ46 158
DDR_B_D47
Close to JDDRH.126 Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
159 DQ43 DQ47 160
161 VSS VSS 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53 +1.5V
165 DQ49 DQ53 166
167 168 @ +1.5V +0.75VS
DDR_B_DQS#6 VSS VSS C189 1 2 330U_B2_2.5VM_R15M
+
169 DQS6# DM6 170
DDR_B_DQS6 171 172
DQS6 VSS DDR_B_D50 C190 1
173 VSS DQ54 174 2 0.1U_0402_16V4Z C191 1 2 10U_0805_6.3V6M
DDR_B_D54 175 176 DDR_B_D51 C192 1 2 10U_0805_6.3V6M
DDR_B_D55 DQ50 DQ55 C193 1
177 DQ51 VSS 178 2 0.1U_0402_16V4Z
179 180 DDR_B_D60 C194 1 2 10U_0805_6.3V6M C195 2 1 1U_0402_6.3V4Z
DDR_B_D56 VSS DQ60 DDR_B_D61 C196 1
181 DQ56 DQ61 182 2 0.1U_0402_16V4Z
DDR_B_D57 183 184 C197 1 2 10U_0805_6.3V6M C198 2 1 1U_0402_6.3V4Z
DQ57 VSS DDR_B_DQS#7 C199 1
185 VSS DQS7# 186 2 0.1U_0402_16V4Z
187 188 DDR_B_DQS7 C200 1 2 10U_0805_6.3V6M C201 2 1 1U_0402_6.3V4Z
DM7 DQS7
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62 C202 1 2 10U_0805_6.3V6M C203 2 1 1U_0402_6.3V4Z
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
R98 1 2 195 196 C204 1 2 10U_0805_6.3V6M
10K_0402_5% VSS VSS
4 197 SA0 EVENT# 198 4
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA <11,29,39>
201 202 PM_SMBCLK
SA1 SCL PM_SMBCLK <11,29,39>
2.2U_0603_6.3V4Z
1 1 1 R99 2 +0.75VS 203 204 +0.75VS
10K_0402_5% VTT VTT
205 GND1 BOSS1 206
C207 C208 207 208
@ 2 2 @ GND2 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
0.1U_0402_16V4Z 200910/9 2010/01/23 Title
FOX_AS0A626-UASN-7F_204P
Issued Date Deciphered Date
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 12 of 58
A B C D E
 5 4 3 2 1

UV1A
Lane Reversal
PCIE_CTX_C_GRX_P15 AP17 Part 1 of 7 K1 PCIE_GTX_C_CRX_P[0..15]
+1.05VS_DGPU PEX_RX0 GPIO0 <6> PCIE_GTX_C_CRX_P[0..15]
150mA PCIE_CTX_C_GRX_N15 AN17 K2 HPD_C
LV2 N12PGS@ PCIE_CTX_C_GRX_P14 PEX_RX0_N GPIO1 VGA_BL_PWM
AN19 K3 VGA_BL_PWM <25>
0.1U_0402_16V4Z +PLLVDD PCIE_CTX_C_GRX_N14 PEX_RX1 GPIO2 VGA_ENVDD PCIE_GTX_C_CRX_N[0..15]
1 2 AP19 H3 VGA_ENVDD <25> <6> PCIE_GTX_C_CRX_N[0..15]
BLM18PG330SN1D_0603 PCIE_CTX_C_GRX_P13 PEX_RX1_N GPIO3 VGA_ENBKL
AR19 H2 VGA_ENBKL <25>
N12PGS@ PCIE_CTX_C_GRX_N13 PEX_RX2 GPIO4 GPU_VID0
2 1 1 1 1 1 AR20 H1 GPU_VID0 <56>
CV85 CV7 CV8 CV11 CV12 CV9 PCIE_CTX_C_GRX_P12 PEX_RX2_N GPIO5 GPU_VID1 PCIE_CTX_C_GRX_P[0..15]
AP20 H4 GPU_VID1 <56> <6> PCIE_CTX_C_GRX_P[0..15]
N12PGS@ N12PGS@ PCIE_CTX_C_GRX_N12 PEX_RX3 GPIO6
AN20 H5
N12PGS@ 22U_0805_6.3V6M 0.1U_0402_16V4Z PCIE_CTX_C_GRX_P11 PEX_RX3_N GPIO7
AN22 H6
1 2 2 2 2 2 PCIE_CTX_C_GRX_N11 PEX_RX4 GPIO8 THERM#_VGA PCIE_CTX_C_GRX_N[0..15]
AP22 J7 THERM#_VGA <14> <6> PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_P10 PEX_RX4_N GPIO9
AR22 K4
10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z PCIE_CTX_C_GRX_N10 PEX_RX5 GPIO10
AR23 K5
N12PGS@ N12PGS@ PCIE_CTX_C_GRX_P9 PEX_RX5_N GPIO11 ACIN_VGA
AP23 H7

GPIO
PCIE_CTX_C_GRX_N9 PEX_RX6 GPIO12 VGA_ENVDD
D AN23 J4 1 DIS@ 2 D
PCIE_CTX_C_GRX_P8 PEX_RX6_N GPIO13 RV1 10K_0402_5%
AN25 J6
PCIE_CTX_C_GRX_N8 PEX_RX7 GPIO14 HDMI_HPD_VGA VGA_ENBKL
45mA AP25 L1 2 DIS@ 1
LV13 N12MGE@ PCIE_CTX_C_GRX_P7 PEX_RX7_N GPIO15 RV125 RV2 10K_0402_5%
AR25 L2
4.7U_0603_6.3V6K PEX_RX8 GPIO16 EDP@
+1.05VS_DGPU 1 2 +SP_PLLVDD PCIE_CTX_C_GRX_N7 AR26 L4 VGA_BL_PWM 2 3D@ 1
BLM18PG330SN1D_0603 CV223 PCIE_CTX_C_GRX_P6 PEX_RX8_N GPIO17 0_0402_5% RV3 10K_0402_5%
AP26 M4
N12MGE@ PEX_RX9 GPIO18
1 1 1 PCIE_CTX_C_GRX_N6 AN26 L7 EDP_HPD_R 2 1 EDP_HPD <25>
HPD_C 1 DIS@ 2
CV222 CV224 PCIE_CTX_C_GRX_P5 PEX_RX9_N GPIO19 RV4 100K_0402_5%
AN28 L5
PEX_RX10 GPIO20
PCIE_CTX_C_GRX_N5 AP28 K6 HPD_F EDP_HPD_R 1 DIS@ 2
PCIE_CTX_C_GRX_P4 PEX_RX10_N GPIO21 RV5 100K_0402_5%
AR28 L6
2 2 2 PCIE_CTX_C_GRX_N4 PEX_RX11 GPIO22 HPD_F
AR29 M6 TV6 1 DIS@ 2
1U_0402_6.3V4Z PCIE_CTX_C_GRX_P3 PEX_RX11_N GPIO23 RV29 100K_0402_5%
AP29 M7
N12MGE@ 1U_0402_6.3V4Z PCIE_CTX_C_GRX_N3 PEX_RX12 GPIO24 HDMI_HPD
AN29 2 DHDMI@1
N12MGE@ PCIE_CTX_C_GRX_P2 PEX_RX12_N RV4 R1429 100K_0402_5%
AN31 N1
PEX_RX13 MIOA_D0_NC 100K_0402_5%
PCIE_CTX_C_GRX_N2 AP31 P4 HDMI_HPD_VGA 2 IHDMI@ 1
PCIE_CTX_C_GRX_P1 PEX_RX13_N MIOA_D1_NC OPT@ R1436 100K_0402_5%
AR31 P1
PCIE_CTX_C_GRX_N1 PEX_RX14 MIOA_D2_NC RV5
AR32 P2
PCIE_CTX_C_GRX_P0 PEX_RX14_N MIOA_D3_NC 100K_0402_5%
Lane Reversal PCIE_CTX_C_GRX_N0
AR34
AP34
PEX_RX15
PEX_RX15_N
MIOA_D4_NC
MIOA_D5_NC
P3
T3 OPT@
+3VS_DGPU
T2 RV29
MIOA_D6_NC 100K_0402_5%
T1
LV2 CV85 PCIE_GTX_C_CRX_P15 DIS@ CV5 0.22U_0402_10V6K PCIE_GTX_CRX_P15 MIOA_D7_NC OPT@
1 2 AL17 U4
BLM18PG330SN1D_0603 10U_0603_6.3V6M PCIE_GTX_C_CRX_N15 DIS@ CV6 0.22U_0402_10V6K PCIE_GTX_CRX_N15 PEX_TX0 MIOA_D8_NC VGA_EDID_CLK 1 DIS@

PCI EXPRESS
1 2 AM17 U1 2
N12PGE@ N12PGE@ PCIE_GTX_C_CRX_P14 DIS@ CV13 0.22U_0402_10V6K PCIE_GTX_CRX_P14 PEX_TX0_N MIOA_D9_NC RV6 2.2K_0402_5%
1 2 AM18 U2
DIS@ CV14 0.22U_0402_10V6K PEX_TX1 MIOA_D10_NC
PCIE_GTX_C_CRX_N14 1 2 PCIE_GTX_CRX_N14 AM19 U3 VGA_EDID_DATA 1 DIS@ 2
CV8 CV9 PCIE_GTX_C_CRX_P13 DIS@ CV15 0.22U_0402_10V6K PCIE_GTX_CRX_P13 PEX_TX1_N MIOA_D11_NC RV7 2.2K_0402_5%
1 2 AL19 R6
0.1U_0402_16V4Z 0.1U_0402_16V4Z PCIE_GTX_C_CRX_N13 DIS@ CV16 0.22U_0402_10V6K PCIE_GTX_CRX_N13 PEX_TX2 MIOA_D12_NC RV10 RV6
1 2 AK19 T6

DVO
N12PGE@ N12PGE@ PCIE_GTX_C_CRX_P12 DIS@ CV17 0.22U_0402_10V6K PCIE_GTX_CRX_P12 PEX_TX2_N MIOA_D13_NC 100K_0402_5% 2.2K_0402_5% SMB_CLK_GPU
1 2 AL20 N6 1 DIS@2
PCIE_GTX_C_CRX_N12 DIS@ CV18 0.22U_0402_10V6K PCIE_GTX_CRX_N12 PEX_TX3 MIOA_D14_NC OPT@ OPT@ RV8 2.2K_0402_5%
1 2 AM20
CV7 CV12 DIS@ CV19 0.22U_0402_10V6K PEX_TX3_N
PCIE_GTX_C_CRX_P11 1 2 PCIE_GTX_CRX_P11 AM21 Y1 SMB_DATA_GPU 1 DIS@2
22U_0805_6.3V6M 0.1U_0402_16V4Z PCIE_GTX_C_CRX_N11 DIS@ CV20 0.22U_0402_10V6K PCIE_GTX_CRX_N11 PEX_TX4 MIOB_D0_NC RV7 RV8 RV9 2.2K_0402_5%
1 2 AM22 Y2
N12PGE@ N12PGE@ DIS@ CV21 0.22U_0402_10V6K PEX_TX4_N MIOB_D1_NC 2.2K_0402_5% 2.2K_0402_5%
PCIE_GTX_C_CRX_P10 1 2 PCIE_GTX_CRX_P10 AL22 Y3 ACIN_VGA 1 DIS@ 2
PCIE_GTX_C_CRX_N10 DIS@ CV22 0.22U_0402_10V6K PCIE_GTX_CRX_N10 PEX_TX5 MIOB_D2_NC OPT@ OPT@ RV32 10K_0402_5%
1 2 AK22 AB3
CV11 DIS@ CV24 0.22U_0402_10V6K PEX_TX5_N MIOB_D3_NC
PCIE_GTX_C_CRX_P9 1 2 PCIE_GTX_CRX_P9 AL23 AB2 THERM#_VGA 1 DIS@ 2
C 0.1U_0402_16V4Z PCIE_GTX_C_CRX_N9 DIS@ CV23 0.22U_0402_10V6K PCIE_GTX_CRX_N9 PEX_TX6 MIOB_D4_NC RV9 RV11 RV10 100K_0402_5% C
1 2 AM23 AB1
N12PGE@ PCIE_GTX_C_CRX_P8 DIS@ CV26 0.22U_0402_10V6K PCIE_GTX_CRX_P8 PEX_TX6_N MIOB_D5_NC 2.2K_0402_5% 2.2K_0402_5%
1 2 AM24 AC4
PCIE_GTX_C_CRX_N8 DIS@ CV25 0.22U_0402_10V6K PCIE_GTX_CRX_N8 PEX_TX7 MIOB_D6_NC OPT@ OPT@
1 2 AM25 AC1
PCIE_GTX_C_CRX_P7 DIS@ CV27 0.22U_0402_10V6K PCIE_GTX_CRX_P7 PEX_TX7_N MIOB_D7_NC HDCP_SCL
1 2 AL25 AC2 1 DIS@ 2
PCIE_GTX_C_CRX_N7 DIS@ CV28 0.22U_0402_10V6K PCIE_GTX_CRX_N7 PEX_TX8 MIOB_D8_NC RV12 RV13 RV11 2.2K_0402_5%
1 2 AK25 AC3
DIS@ CV37 0.22U_0402_10V6K PEX_TX8_N MIOB_D9_NC 2.2K_0402_5% 2.2K_0402_5%
PCIE_GTX_C_CRX_P6 1 2 PCIE_GTX_CRX_P6 AL26 AE3 HDCP_SDA 1 DIS@ 2
PCIE_GTX_C_CRX_N6 DIS@ CV38 0.22U_0402_10V6K PCIE_GTX_CRX_N6 PEX_TX9 MIOBD_10_NC OPT@ OPT@ RV12 2.2K_0402_5%
1 2 AM26 AE2
PCIE_GTX_C_CRX_P5 DIS@ CV40 0.22U_0402_10V6K PCIE_GTX_CRX_P5 PEX_TX9_N MIOB_D11_NC
1 2 AM27 U6
CV5 CV6 PCIE_GTX_C_CRX_N5 DIS@ CV39 0.22U_0402_10V6K PCIE_GTX_CRX_N5 PEX_TX10 MIOB_D12_NC RV14 RV121
1 2 AM28 W6
0.22U_0402_10V6K 0.22U_0402_10V6K DIS@ CV42 0.22U_0402_10V6K PEX_TX10_N MIOB_D13_NC 2.2K_0402_5% 2.2K_0402_5%
PCIE_GTX_C_CRX_P4 1 2 PCIE_GTX_CRX_P4 AL28 Y6 VGA_CRT_DATA 1 DIS@ 2
OPT@ OPT@ PCIE_GTX_C_CRX_N4 DIS@ CV41 0.22U_0402_10V6K PCIE_GTX_CRX_N4 PEX_TX11 MIOB_D14_NC OPT@ OPT@ RV13 2.2K_0402_5%
1 2 AK28
CV13 CV14 PCIE_GTX_C_CRX_P3 DIS@ CV29 0.22U_0402_10V6K PCIE_GTX_CRX_P3 PEX_TX11_N VGA_CRT_CLK
1 2 AK29 N3 1 DIS@ 2
0.22U_0402_10V6K 0.22U_0402_10V6K PCIE_GTX_C_CRX_N3 DIS@ CV30 0.22U_0402_10V6K PCIE_GTX_CRX_N3 PEX_TX12 MIOA_HSYNC_NC RV122 RV32 RV14 2.2K_0402_5%
1 2 AL29 L3
OPT@ OPT@ PCIE_GTX_C_CRX_P2 DIS@ CV31 0.22U_0402_10V6K PCIE_GTX_CRX_P2 PEX_TX12_N MIOA_VSYNC_NC 2.2K_0402_5% 10K_0402_5%
1 2 AM29
CV15 CV16 PCIE_GTX_C_CRX_N2 DIS@ CV32 0.22U_0402_10V6K PCIE_GTX_CRX_N2 PEX_TX13 OPT@ OPT@
1 2 AM30 W1
0.22U_0402_10V6K 0.22U_0402_10V6K DIS@ CV34 0.22U_0402_10V6K PEX_TX13_N MIOB_HSYNC_NC
PCIE_GTX_C_CRX_P1 1 2 PCIE_GTX_CRX_P1 AM31 W2 I2CB_SCL 1 DIS@ 2
OPT@ OPT@ PCIE_GTX_C_CRX_N1 DIS@ CV33 0.22U_0402_10V6K PCIE_GTX_CRX_N1 PEX_TX14 MIOB_VSYNC_NC RV121 2.2K_0402_5%
1 2 AM32
CV17 CV18 DIS@ CV36 0.22U_0402_10V6K PEX_TX14_N
PCIE_GTX_C_CRX_P0 1 2 PCIE_GTX_CRX_P0 AN32 N2 I2CB_SDA 1 DIS@ 2
0.22U_0402_10V6K 0.22U_0402_10V6K PCIE_GTX_C_CRX_N0 DIS@ CV35 0.22U_0402_10V6K PCIE_GTX_CRX_N0 PEX_TX15 MIOA_DE_NC RV122 2.2K_0402_5%
1 2 AP32 P5
OPT@ OPT@ PEX_TX15_N MIOA_CTL3_NC
N5
CV19 CV20 MIOA_VREF_NC RV17 RV15
0.22U_0402_10V6K 0.22U_0402_10V6K Y5 10K_0402_5% 10K_0402_5% VGA_CRT_R 1 DIS@ 2
OPT@ OPT@ CLK_PCIE_VGA MIOB_DE_NC OPT@ OPT@ RV20 150_0402_1%
<29> CLK_PCIE_VGA AR16 W3
CV21 CV22 CLK_PCIE_VGA# PEX_REFCLK MIOB_CTL3_NC VGA_CRT_G
<29> CLK_PCIE_VGA# AR17 AF1 1 DIS@ 2
0.22U_0402_10V6K 0.22U_0402_10V6K CLK_REQ_GPU# PEX_REFCLK_N MIOB_VREF_NC RV21 150_0402_1%
AR13
OPT@ OPT@ PEX_CLKREQ_N
N4 1 DIS@ 2 VGA_CRT_B 1 DIS@ 2
CV23 CV24 @ PEX_TSTCLK_OUT MIOA_CLKIN_NC RV15 10K_0402_5% RV23 150_0402_1%
Differential signal 1 2 AJ17
PEX_TSTCLK_OUT MIOA_CLKOUT_NC
R4 Close to GPU
0.22U_0402_10V6K 0.22U_0402_10V6K RV16 200_0402_1% PEX_TSTCLK_OUT# AJ18
OPT@ OPT@ PEX_TSTCLK_OUT_N
AE1 1 DIS@ 2
CV25 CV26 MIOB_CLKIN_NC RV17 10K_0402_5%
V4
0.22U_0402_10V6K 0.22U_0402_10V6K MIOB_CLKOUT_NC
<32> PLTRST_VGA# 1 DIS@ 2 PLTRST_VGA_R# AM16 120mA
OPT@ OPT@ RV18 0_0402_5% PEX_RST_N LV3
AG21 T4
CV27 CV28 RV30 PEX_TERMP MIOA_CLKOUT_NC_N
1 DIS@ 2 W4 +DACA_VDD 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1 2 +3VS_DGPU
B 0.22U_0402_10V6K 0.22U_0402_10V6K 0_0402_5% RV19 2.49K_0402_1% MIOB_CLKOUT_NC_N MMZ1608D301BT_0603 B
OPT@ OPT@ N12PGE@ 60mA U5 1 1 1 1 1 1 DIS@ 1
CV37 CV38 +PLLVDD MIOACAL_PD_VDDQ_NC CV73 CV50 CV49
AE9 T5
0.22U_0402_10V6K 0.22U_0402_10V6K N12PGS@ PLLVDD MIOACAL_PU_GND_NC 0.1U_0402_16V4Z CV72 CV48 CV80 CV81 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K
OPT@ OPT@ RV18 RV19
45mA DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
1 2+SP_PLLVDD AF9 AA7
CV39 CV40 0_0402_5% 2.49K_0402_1% RV30 0_0402_5% SP_PLLVDD MIOBCAL_PD_VDDQ_NC 2 2 2 2 2 2 2
0.22U_0402_10V6K 0.22U_0402_10V6K OPT@ OPT@
45mA MIOBCAL_PU_GND_NC
AA6
AD9
OPT@ OPT@ VID_PLLVDD 0.1U_0402_16V4Z 0.1U_0402_16V4Z
CLK

CV41 CV42 RV26 RV25 XTALIN B1 LV3

0.22U_0402_10V6K 0.22U_0402_10V6K 10K_0402_5% 10K_0402_5% XTAL_OUT XTAL_IN VGA_CRT_R MMZ1608D301BT_0603
B2 AM15 VGA_CRT_R <26>
OPT@ OPT@ OPT@ OPT@ XTAL_OUT DACA_RED VGA_CRT_G OPT@
AM14 VGA_CRT_G <26>
CV29 CV30 RV26 2 DIS@ DACA_GREEN
1 10K_0402_5% XTALOUT D1 AL14 VGA_CRT_B
VGA_CRT_B <26>
0.22U_0402_10V6K 0.22U_0402_10V6K YV1 XTAL_OUTBUFF DACA_BLUE
2 DIS@ 1 XTALSSIN D2
OPT@ OPT@ 27MHZ_16PF_X5H027000FG1H RV25 10K_0402_5% XTAL_SSIN VGA_CRT_HSYNC
AM13 VGA_CRT_HSYNC <26>
CV31 CV32 OPT@ DACA_HSYNC VGA_CRT_VSYNC
AL13 VGA_CRT_VSYNC <26>
0.22U_0402_10V6K 0.22U_0402_10V6K DACA_VSYNC
Internal Thermal Sensor
OPT@ OPT@ CV45 CV138 <14> SMB_CLK_GPU SMB_CLK_GPU E2 AJ12 +DACA_VDD
CV33 CV34 18P_0402_50V8J 18P_0402_50V8J SMB_DATA_GPU I2CS_SCL DACA_VDD +DACA_VREF
<14> SMB_DATA_GPU E1 AK12
0.22U_0402_10V6K 0.22U_0402_10V6K OPT@ OPT@ I2CS_SDA DACA_VREF DACA_RSET
DACA_RSET
AK13 07/10/2010
OPT@ OPT@ VGA_EDID_CLK
LVDS <25> VGA_EDID_CLK E3 HDMI HPD for OPT DGPU output

1
I2CC_SCL
DACs

CV35 CV36 <25> VGA_EDID_DATA VGA_EDID_DATA E4 AK4 1 C879

0.22U_0402_10V6K 0.22U_0402_10V6K I2CC_SDA DACB_RED RV27 CV47 +3VS @
AL4
OPT@ OPT@ I2CB_SCL DACB_GREEN 124_0402_1% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
G3 AJ4
I2CB_SDA I2CB_SCL DACB_BLUE DIS@ DIS@ R1430
G2 1 2
I2C

I2CB_SDA 2 @
AM1

5
VGA_CRT_CLK DACB_HSYNC 0_0402_5% U55
CRT <26> VGA_CRT_CLK
VGA_CRT_DATA
G1
G4
I2CA_SCL DACB_VSYNC
AM2
2 1 1

P
+3VS_DGPU <26> VGA_CRT_DATA I2CA_SDA <32,33,47,56> VGA_PWROK IN1
<32,47,56> DGPU_PWR_EN AG7 +DACB_VDD 2 1 4 HDMI_HPD_VGA
HDCP_SCL DACB_VDD RV31 10K_0402_5% O
F6 AK6 <27,31,33> HDMI_HPD 2
I2CH_SCL DACB_VREF IN2

G
HDCP_SDA G6 AH7 DIS@
2

I2CH_SDA DACB_RSET SN74AHC1G08DCKR_SC70-5

3
RV124 @
2

10K_0402_5% @ N12P-GS1-A1_BGA_973P N12PGSR1@

A OPT@ RV118 1 2 RV31 A
10K_0402_5% RV28 10M_0402_5% 10K_0402_5% 1 2
2 1

OPT@ OPT@
YV1 0_0402_5%
G

QV2 OPT@ DIS@

<29> CLK_REQ_VGA# 1 3 CLK_REQ_GPU# XTALIN 1 2 XTAL_OUT R1431
D

27MHZ_16PF_X5H027000FG1H

www.vinafix.vn
2

2N7002_SOT23-3 DIS@
RV123
10K_0402_5%
1
CV45
18P_0402_50V8J
CV46
DIS@
1 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title
DIS@ @ DIS@ 18P_0402_50V8J
1 2 2 2 VGA_PCIE/DAC/GPIO
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RV110 0_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 13 of 58
5 4 3 2 1
 5 4 3 2 1

UV1D

Part 4 of 7
<25> VGA_TXCLK+ VGA_TXCLK+ AM11 A2
VGA_TXCLK- IFPA_TXC NC_0
<25> VGA_TXCLK- AM12 IFPA_TXC_N NC_1 A7
VGA_TXOUT0+ AM8 B7
<25> VGA_TXOUT0+
<25> VGA_TXOUT0- VGA_TXOUT0-
VGA_TXOUT1+
AL8
AM10
IFPA_TXD0
IFPA_TXD0_N
NC_2
NC_3 C5
C7
External VGA Thermal Sensor SMB_CLK_GPU <13>

<25> VGA_TXOUT1+ IFPA_TXD1 NC_4 SMB_DATA_GPU <13>

VGA_TXOUT1-
<25> VGA_TXOUT1-
VGA_TXOUT2+
AM9 IFPA_TXD1_N NC_5 D5 Address: 0x9A H
<25> VGA_TXOUT2+ AK10 IFPA_TXD2 NC_6 D6 Internal Thermal Sensor

1
<25> VGA_TXOUT2- VGA_TXOUT2- AL10 D7
IFPA_TXD2_N NC_7 RV33 RV34
AK11
AL11
IFPA_TXD3 NC_8 E5
E7 0_0402_5% 0_0402_5%
Address: 0x9E H
D IFPA_TXD3_N NC_9 @ @
D
NC_10 F4
G5

2
VGA_TZCLK+ NC_11 +3VS_DGPU
<25> VGA_TZCLK+ AP13 IFPB_TXC NC_12 H32
<25> VGA_TZCLK- VGA_TZCLK- AN13 J25 DIS@ UV2 DIS@
VGA_TZOUT0+ IFPB_TXC_N NC_13 VGA_SMB_CK2
<25> VGA_TZOUT0+ AN8 IFPB_TXD4 NC_14 J26 2 1 1 8
<25> VGA_TZOUT0- VGA_TZOUT0- AP8 P6 CV53 0.1U_0402_16V4Z VDD SCLK
VGA_TZOUT1+ IFPB_TXD4_N NC_15 THERM_D+ VGA_SMB_DA2
<25> VGA_TZOUT1+ AP10 IFPB_TXD5 NC_16 U7 2 D+ SDATA 7
<25> VGA_TZOUT1- VGA_TZOUT1- AN10 V6 CV54
VGA_TZOUT2+ IFPB_TXD5_N NC_17 THERM#_VGA
<25> VGA_TZOUT2+ AR11 IFPB_TXD6 NC_18 Y4 1 2 DIS@ 3 D- ALERT# 6 THERM#_VGA <13>
UV2
<25> VGA_TZOUT2- VGA_TZOUT2- AR10 AA4 ADM1032ARMZ-2REEL_MSOP8
IFPB_TXD6_N NC_19 THERM_D- 2200P_0402_50V7K OPT@
AN11 IFPB_TXD7 NC_20 AB4 4 THERM# GND 5
AP11 IFPB_TXD7_N NC_21 AB7
AC5 CV53 CV54
NC_22

NC
AD6 ADM1032ARMZ-2REEL_MSOP8 0.1U_0402_16V4Z 2200P_0402_50V7K
NC_23 OPT@ OPT@
AM7 IFPC_L0 NC_24 AF6
AM6 IFPC_L0_N NC_25 AG6
AL5 IFPC_L1 NC_26 AG20
AM5 IFPC_L1_N NC_27 AJ5
AM3 IFPC_L2 NC_28 AK15
AM4 IFPC_L2_N NC_29 AL7
AP1 +3VS_DGPU
IFPC_L3
AR2 IFPC_L3_N +3VS_DGPU

2
<25> VGA_EDP_TX0+ VGA_EDP_TX0+ AR8
VGA_EDP_TX0- IFPD_L0 RV22 RV24
<25> VGA_EDP_TX0- AR7 IFPD_L0_N
<25> VGA_EDP_TX1+ VGA_EDP_TX1+ AP7 2.2K_0402_5% 2.2K_0402_5%
VGA_EDP_TX1- IFPD_L1 OPT@ OPT@
eDP is supported <25> VGA_EDP_TX1- AN7 IFPD_L1_N

5
<25> VGA_EDP_TX2+ VGA_EDP_TX2+ AN5 OPT@

1
IFPD_L2
C only on IFPD <25> VGA_EDP_TX2- VGA_EDP_TX2- AP5 QV1B C

LVDS/TMDS
VGA_EDP_TX3+ IFPD_L2_N VGA_SMB_CK2
<25> VGA_EDP_TX3+ AR5 IFPD_L3 4 3 EC_SMB_CK2 <29,44,45,46>
<25> VGA_EDP_TX3- VGA_EDP_TX3- AR4 IFPD_L3_N

2
OPT@ 2N7002DW-T/R7_SOT363-6
QV1A
<27> VGA_HDMI_TX2+ VGA_HDMI_TX2+ AH6 VGA_SMB_DA2 1 6
VGA_HDMI_TX2- IFPE_L0 EC_SMB_DA2 <29,44,45,46>
<27> VGA_HDMI_TX2- AH5 IFPE_L0_N
<27> VGA_HDMI_TX1+ VGA_HDMI_TX1+ AH4 2N7002DW-T/R7_SOT363-6
VGA_HDMI_TX1- IFPE_L1
<27> VGA_HDMI_TX1- AG4 IFPE_L1_N
<27> VGA_HDMI_TX0+ VGA_HDMI_TX0+ AF4
VGA_HDMI_TX0- IFPE_L2 VGA_SMB_CK2 EC_SMB_CK2
<27> VGA_HDMI_TX0- AF5 IFPE_L2_N 1 DIS@ 2
<27> VGA_HDMI_CLK+ VGA_HDMI_CLK+ AE6 RV35 0_0402_5%
VGA_HDMI_CLK- IFPE_L3 VGA_SMB_DA2 EC_SMB_DA2
<27> VGA_HDMI_CLK- AE5 IFPE_L3_N 1 DIS@ 2
RV36 0_0402_5%
D35 VDD_SENSE
VDD_SENSE_0 VDD_SENSE <56>
AL2 IFPF_L0 VDD_SENSE_1 P7
AL3 IFPF_L0_N VDD_SENSE_2 AD20
AJ3 IFPF_L1
AJ2 IFPF_L1_N
AJ1 IFPF_L2
AH1 IFPF_L2_N GND_SENSE_0 AD19
AH2 IFPF_L3 GND_SENSE_1 E35
2 RV126 1 VGA_EDP_AUX AH3 R7
EDP@ 100K_0402_5% IFPF_L3_N GND_SENSE_2

2 RV127 1 VGA_EDP_AUX-
EDP@ 100K_0402_5% AP2 RV47
IFPC_AUX_I2CW _SCL 10K_0402_5%
AN3 IFPC_AUX_I2CW _SDA_N TEST OPT@
B B
VGA_EDP_AUX AP4 AP35 TESTMODE
+3VS_DGPU <25> VGA_eDP_AUX IFPD_AUX_I2CX_SCL TESTMODE
VGA_EDP_AUX-
eDP <25> VGA_eDP_AUX- AN4 IFPD_AUX_I2CX_SDA_N JTAG_TCK AP14 TV2

1
AN14 +3VS_DGPU
JTAG_TDI TV3
AN16 RV47
JTAG_TDO TV4 10K_0402_5%
1 DIS@ 2 VGA_HDMI_CLK VGA_HDMI_CLK ROM_CS# @
RV119 4.7K_0402_5% HDMI <27> VGA_HDMI_CLK
VGA_HDMI_DATA
AE4
AD4
IFPE_AUX_I2CY_SCL JTAG_TMS AR14
AP16 1 2
TV5
DIS@
2
RV44
1
10K_0402_5%
<27> VGA_HDMI_DATA IFPE_AUX_I2CY_SDA_N JTAG_TRST_N RV41 10K_0402_5%

2
1 DIS@ 2 VGA_HDMI_DATA
RV120 4.7K_0402_5% AF3 IFPF_AUX_I2CZ_SCL
AF2 IFPF_AUX_I2CZ_SDA_N SERIAL
C3 ROM_CS#
ROM_CS_N ROM_SI
ROM_SI D3 ROM_SI <24>
ROM_SO
RV119 RV120 ROM_SO C4
D4 ROM_SCLK
ROM_SO <24> for EMI
ROM_SCLK ROM_SCLK <24>
4.7K_0402_5% 4.7K_0402_5%
OPT@ OPT@ RV49 ROM_SCLK
10K_0402_5%
GENERAL

1
OPT@ A5
NC/SPDIF_NC R398
A4 BUFRST_N
MULTI_STRAP_REF0_GND N9 1 DIS@ 2 10_0402_5%
+3VS_DGPU 1 DIS@ 2 AB5 CEC
RV48 40.2K_0402_1% @
RV49 10K_0402_5% M9 1 DIS@ 2

2
STRAP0 MULTI_STRAP_REF1_GND RV50 40.2K_0402_1%
<24> STRAP0 W5 STRAP0 1
<24> STRAP1 STRAP1 W7 B5 THERM_D+ C87
STRAP2 STRAP1 THERMDP THERM_D- RV48 10P_0402_50V8J
<24> STRAP2 V7 STRAP2 THERMDN B4
40.2K_0402_1% @
OPT@ 2

A N12P-GS1-A1_BGA_973P N12PGSR1@ RV50 A

40.2K_0402_1%
OPT@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_LVDS/HDMI/THERM/eDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 14 of 58

www.vinafix.vn
5 4 3 2 1
 5 4 3 2 1

N12M-GE Performance Mode N12P-GS Performance Mode N12P-GE Performance Mode

Mode NVCLK (MHz) MCLK (MHz) +VGA_CORE Mode NVCLK (MHz) MCLK (MHz) +VGA_CORE Mode NVCLK (MHz) MCLK (MHz) +VGA_CORE

P0 606 790 1.00 V P0 TBD TBD TBD P0 TBD TBD TBD

P8 TBD TBD TBD P8 TBD TBD TBD P8 TBD TBD TBD

D D
P12 TBD TBD TBD P12 TBD TBD TBD P12 TBD TBD TBD

+VGA_CORE +VGA_CORE
UV1G CV225
22U_0603_6.3V6M
AB11 P21
32A for N11E-GE1-LP OPT@
VDD_0 Part 7 of 7 VDD_56
AB13
AB15
VDD_1 VDD_57 P23
P25
28A for N11P-GE1 +VGA_CORE +VGA_CORE CV226 CV227
VDD_2 VDD_58 22U_0603_6.3V6M 22U_0603_6.3V6M
AB17
AB19
VDD_3 VDD_59 R11
R12
16A for N11M-GE1 & N11M-OP1 330U_2.5V_M_R17 22U_0603_6.3V6M 22U_0603_6.3V6M OPT@ OPT@
VDD_4 VDD_60
AB21
AB23
VDD_5 VDD_61 R13
R14
14A for N11M-GE2 1 1
2 2 2 CV57 CV58
VDD_6 VDD_62 CV57 + + CV58 CV225 CV226 CV227 330U_2.5V_M_R17 330U_2.5V_M_R17
AB25 VDD_7 VDD_63 R15
AC11 R16 OPT@ OPT@
VDD_8 VDD_64 330U_2.5V_M_R17 DIS@ DIS@ DIS@
AC12 VDD_9 VDD_65 R17
AC13 R18 DIS@ 2 2 DIS@ 1 1 1 CV10 CV43
VDD_10 VDD_66 47U_0805_4V6 22U_0805_6.3V6M
AC14 VDD_11 VDD_67 R19
AC15 R20 22U_0603_6.3V6M OPT@ OPT@
VDD_12 VDD_68
AC16 VDD_13 VDD_69 R21
AC17 R22 CV60 CV61
VDD_14 VDD_70 10U_0603_6.3V6M 10U_0603_6.3V6M
AC18 VDD_15 VDD_71 R23
AC19 R24 +VGA_CORE OPT@ OPT@
VDD_16 VDD_72
AC20 VDD_17 VDD_73 R25
AC21 T12 10U_0603_6.3V6M 4.7U_0603_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K CV51 CV62
VDD_18 VDD_74 4.7U_0603_6.3V6K 1U_0402_6.3V4Z
C AC22 VDD_19 VDD_75 T14 C
AC23 T16 OPT@ OPT@
VDD_20 VDD_76

POWER
AC24 VDD_21 VDD_77 T18 1 1 2 2 1 1

1
AC25 T20 CV10 CV43 CV60 CV61 CV51 CV62 CV44 CV52 CV55 CV44 CV52
VDD_22 VDD_78 @ 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K
AD12 VDD_23 VDD_79 T22
AD14 T24 47U_0805_4V6 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ OPT@ OPT@

2
VDD_24 VDD_80 @ 2 2 1 1 2 2
AD16 VDD_25 VDD_81 V11
AD18 V13 CV55 CV59
VDD_26 VDD_82 0.22U_0402_6.3V6K 0.1U_0402_16V7K
AD22 VDD_27 VDD_83 V15
AD24 V17 22U_0805_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 0.22U_0402_6.3V6K OPT@ OPT@
VDD_28 VDD_84
L11 VDD_29 VDD_85 V19
L12 V21 CV63 CV64
VDD_30 VDD_86 0.1U_0402_16V7K 0.047U_0402_25V6K
L13 VDD_31 VDD_87 V23
L14 V25 OPT@ OPT@
VDD_32 VDD_88
L15 VDD_33 VDD_89 W11
L16 W12 +VGA_CORE CV65 CV66
VDD_34 VDD_90 0.047U_0402_25V6K 0.047U_0402_25V6K
L17 VDD_35 VDD_91 W13
L18 W14 0.1U_0402_16V7K 0.047U_0402_25V6K 0.022U_0402_25V7K 0.022U_0402_25V7K OPT@ OPT@
VDD_36 VDD_92
L19 VDD_37 VDD_93 W15
L20 W16 CV70 CV71
VDD_38 VDD_94 0.022U_0402_25V7K 0.022U_0402_25V7K
L21 VDD_39 VDD_95 W17 1 1 1 1 1 1 1 1
L22 W18 CV59 CV63 CV64 CV65 CV66 CV70 CV71 CV123 OPT@ OPT@
VDD_40 VDD_96
L23 VDD_41 VDD_97 W19
L24 W20 0.1U_0402_16V7K DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ CV123 CV74
VDD_42 VDD_98 DIS@ 2 2 2 2 2 2 2 2 0.022U_0402_25V7K 0.01U_0402_25V7K
L25 VDD_43 VDD_99 W21
M12 W22 OPT@ OPT@
VDD_44 VDD_100
M14 VDD_45 VDD_101 W23
B M16 W24 0.047U_0402_25V6K 0.047U_0402_25V6K 0.022U_0402_25V7K CV75 CV76 B
VDD_46 VDD_102 0.01U_0402_25V7K 0.01U_0402_25V7K
M18 VDD_47 VDD_103 W25
M20 Y12 OPT@ OPT@
VDD_48 VDD_104
M22 VDD_49 VDD_105 Y14
M24 Y16 CV77 CV78
VDD_50 VDD_106 +VGA_CORE 0.01U_0402_25V7K 0.01U_0402_25V7K
P11 VDD_51 VDD_107 Y18
P13 Y20 OPT@ OPT@
VDD_52 VDD_108 0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K
P15 VDD_53 VDD_109 Y22
P17 Y24 CV79 CV124
VDD_54 VDD_110 0.01U_0402_25V7K 0.01U_0402_25V7K
P19 VDD_55
1 1 1 1 1 1 1 1 OPT@ OPT@
CV74 CV75 CV76 CV77 CV78 CV79 CV124 CV125
CV125
0.01U_0402_25V7K DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0.01U_0402_25V7K
N12P-GS1-A1_BGA_973P N12PGSR1@ DIS@ 2 2 2 2 2 2 2 2 OPT@

0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_VGA CORE
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 15 of 58
5 4 3 2 1
 5 4 3 2 1

UV1E
3.5A Part 5 of 7 2200mA
+VRAM_1.5VS 4.7U_0603_6.3V6K 1U_0402_6.3V4Z J23
1600mA AG11 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M +1.05VS_DGPU
FBVDDQ_0 PEX_IOVDDQ_0
J24 AG12
FBVDDQ_1 PEX_IOVDDQ_1
1 1 1 1 1 J29 FBVDDQ_2 PEX_IOVDDQ_2 AG13 1 1 1 1 1 1 1
CV82 CV83 CV67 CV68 CV86 AA27 AG15 CV3
FBVDDQ_3 PEX_IOVDDQ_3 CV87 CV88 CV89 CV90 CV91 CV92 22U_0805_6.3V6M
AA29 FBVDDQ_4 PEX_IOVDDQ_4 AG16
4.7U_0603_6.3V6K DIS@ DIS@ DIS@ DIS@ AA31 AG17 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ 2 2 2 2 2 0.1U_0402_16V4Z FBVDDQ_5 PEX_IOVDDQ_5 2 2 2 2 2 2 2
AB27 FBVDDQ_6 PEX_IOVDDQ_6 AG18
AB29 FBVDDQ_7 PEX_IOVDDQ_7 AG22
1U_0402_6.3V4Z AC27 AG23 0.1U_0402_16V4Z 1U_0402_6.3V4Z 4.7U_0603_6.3V6K
FBVDDQ_8 PEX_IOVDDQ_8
AD27 FBVDDQ_9 PEX_IOVDDQ_9 AG24
D AE27 FBVDDQ_10 PEX_IOVDDQ_10 AG25 D
AJ28 AG26 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M +1.05VS_DGPU
FBVDDQ_11 PEX_IOVDDQ_11
B18 AJ14
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z FBVDDQ_12 PEX_IOVDDQ_12
+VRAM_1.5VS E21 AJ15 1 1 1 1 1 1 1
FBVDDQ_13 PEX_IOVDDQ_13 CV4
G17 AJ19
FBVDDQ_14 PEX_IOVDDQ_14 CV93 CV94 CV95 CV96 CV97 CV98 22U_0805_6.3V6M
1 1 1 1 1 1 1 G18 FBVDDQ_15 PEX_IOVDDQ_15 AJ21
CV99 CV100 CV101 CV102 CV103 CV104 CV126 G22 AJ22 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
FBVDDQ_16 PEX_IOVDDQ_16 2 2 DIS@ 2 2 2 2 2
G8 FBVDDQ_17 PEX_IOVDDQ_17 AJ24
0.1U_0402_16V4Z DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ G9 AJ25
DIS@ 2 2 2 2 2 2 2 FBVDDQ_18 PEX_IOVDDQ_18 0.1U_0402_16V4Z 1U_0402_6.3V4Z 4.7U_0603_6.3V6K
H29 FBVDDQ_19 PEX_IOVDDQ_19 AJ27

POWER
J14 FBVDDQ_20 PEX_IOVDDQ_20 AK18
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z J15 AK20 LV4
FBVDDQ_21 PEX_IOVDDQ_21 BLM18PG121SN1D_0603
J16 AK23
FBVDDQ_22 PEX_IOVDDQ_22 OPT@
J17 FBVDDQ_23 PEX_IOVDDQ_23 AK26
J20 AL16
FBVDDQ_24 PEX_IOVDDQ_24 LV4 CV108
J21 FBVDDQ_25
CV82 CV83 CV67 CV68 J22 1U_0402_6.3V4Z 2 1 +1.05VS_DGPU 4.7U_0603_6.3V6K
4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z FBVDDQ_26 BLM18PG121SN1D_0603 OPT@
OPT@ OPT@ OPT@ OPT@
N27
P27
FBVDDQ_27 600mA AK16 1 1 1 DIS@ 1
FBVDDQ_28 PEX_IOVDD_0 CV109 CV109
R27 FBVDDQ_29 PEX_IOVDD_1 AK17
CV86 CV99 CV100 CV101 T27 AK21 CV105 CV107 CV108 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z FBVDDQ_30 PEX_IOVDD_2 DIS@ DIS@ 4.7U_0603_6.3V6K DIS@ OPT@
U27 FBVDDQ_31 PEX_IOVDD_3 AK24
OPT@ OPT@ OPT@ OPT@ U29 AK27 2 2 2 DIS@ 2
FBVDDQ_32 PEX_IOVDD_4 CV107
CV102 CV103 CV104 CV126
V27
V29
FBVDDQ_33 120mA 0.1U_0402_16V4Z 1U_0402_6.3V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z FBVDDQ_34 OPT@
OPT@ OPT@ OPT@ OPT@
V34
W27
FBVDDQ_35 120mA AG14 +PEX_PLLVDD
FBVDDQ_36 PEX_PLLVDD CV105
Y27 FBVDDQ_37 +3VS_DGPU 0.1U_0402_16V4Z
OPT@
+IFPAB_PLLVDD AK9 AG19
120mA
C @ IFPAB_PLLVDD PEX_SVDD_3V3 C
1 2 AJ11 IFPAB_RSET PEX_SVDD_3V3_NC F7
RV96 1K_0402_1% 1 1 DIS@ CV111 CV110
+3VS_DGPU CV110 CV111 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
+IFPAB_IOVDD 0.1U_0402_16V4Z 4.7U_0603_6.3V6K OPT@ OPT@
AG9
AG10
IFPA_IOVDD
J10
120mA 0.1U_0402_16V4Z 1U_0402_6.3V4Z DIS@
IFPB_IOVDD VDD33_0 2 2
J11
VDD33_1 CV3 CV4 CV93
VDD33_2 J12 1 1 1 1 1
+IFPD_PLLVDD AJ9 J13 CV114 22U_0805_6.3V6M 22U_0805_6.3V6M 0.1U_0402_16V4Z
@ IFPC_PLLVDD VDD33_3 CV217 CV216 CV112 CV113 4.7U_0603_6.3V6K OPT@ OPT@ OPT@
1 2 AK7 IFPC_RSET VDD33_4 J9
RV51 1K_0402_1% DIS@ DIS@ DIS@ DIS@ DIS@
+IFPD_IOVDD AJ8 2 2 2 2 2 CV92 CV98 CV94
IFPC_IOVDD 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z
P9
240mA 0.1U_0402_16V4Z 0.1U_0402_16V4Z OPT@ OPT@ OPT@
+IFPD_PLLVDD MIOA_VDDQ_NC_0
AC6 IFPD_PLLVDD MIOA_VDDQ_NC_1 R9
1 EDP@ 2 AB6 IFPD_RSET MIOA_VDDQ_NC_2 T9 CV91 CV97 CV87
RV52 1K_0402_1% U9 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
+IFPD_IOVDD MIOA_VDDQ_NC_3 OPT@ OPT@ OPT@
AK8
IFPD_IOVDD
AA9 CV89 CV90 CV88
+IFPEF_PLLVDD MIOB_VDDQ_NC_0 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z
AJ6 IFPEF_PLLVDD MIOB_VDDQ_NC_1 AB9
1DHDMI@ 2 AL1 IFPEF_RSET MIOB_VDDQ_NC_2 W9 N12MGE@ OPT@ OPT@ OPT@
RV53 1K_0402_1% Y9 +MIO_VDDQ 2 1 +3VS_DGPU
+IFPE_IOVDD MIOB_VDDQ_NC_3 R196 0_0603_5% CV95 CV96
AE7 1 1
IFPE_IOVDD CV115 CV116 1U_0402_6.3V4Z 1U_0402_6.3V4Z
AD7 IFPF_IOVDD 0.1U_0402_16V4Z 0.1U_0402_16V4Z OPT@ OPT@
N12MGE@ N12MGE@
2 2
N12P-GS1-A1_BGA_973P N12PGSR1@ CV115 CV115 CV114 CV113 CV112
10K_0402_5% 10K_0402_5% 4.7U_0603_6.3V6K 1U_0402_6.3V4Z 0.1U_0402_16V4Z
CV120 N12PGE@ N12PGS@ OPT@ OPT@ OPT@
10K_0402_5%
B OPT@ CV216 CV217 B
+1.05VS_DGPU 0.1U_0402_16V4Z 0.1U_0402_16V4Z
LV5 220mA +3VS_DGPU OPT@ OPT@
2 1 1U_0402_6.3V4Z +IFPAB_PLLVDD LV7 220mA
BLM18PG121SN1D_0603 2 1 1U_0402_6.3V4Z 0.1U_0402_16V4Z +IFPEF_PLLVDD
DIS@ BLM18PG181SN1D_0603
DHDMI@ +3VS_DGPU
1 1 1 1 LV11
CV117 1 1 1 1 1 1 2 1 1U_0402_6.3V4Z 0.1U_0402_16V4Z +IFPD_PLLVDD
4.7U_0603_6.3V6K CV118 CV119 CV120 CV127 CV215 BLM18PG181SN1D_0603
DIS@ DIS@ DIS@ DIS@ 4.7U_0603_6.3V6K CV128 CV129 CV130 CV131 0.1U_0402_16V4Z CV131 EDP@
2 2 2 2 DHDMI@ DHDMI@ DHDMI@ DHDMI@ DHDMI@ DHDMI@ 10K_0402_5%
2 2 2 2 2 2 IHDMI@ CV221
1 1 1 1 1 1
CV140 CV218 10K_0402_5%
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 4.7U_0603_6.3V6K CV220 CV139 CV214 CV221 0.1U_0402_16V4Z NOEDP@
4.7U_0603_6.3V6K 0.1U_0402_16V4Z EDP@ EDP@ EDP@ EDP@ EDP@ EDP@
2 2 2 2 2 2
CV221
10K_0402_5%
+1.05VS_DGPU 4.7U_0603_6.3V6K 0.1U_0402_16V4Z NOEDP@
+1.8VS LV10 285mA
LV8 220mA 2 1 4.7U_0603_6.3V6K 0.1U_0402_16V4Z +IFPE_IOVDD
2 1 4.7U_0603_6.3V6K 0.1U_0402_16V4Z +IFPAB_IOVDD BLM18PG181SN1D_0603 CV212
BLM18PG181SN1D_0603 DHDMI@ +1.05VS_DGPU 10K_0402_5%
1 1 1 1 1
1 DIS@ 1 1 1 1 CV141 CV145 LV12 NOEDP@
CV132 CV213 4.7U_0603_6.3V6K CV142 CV143 CV144 0.1U_0402_16V4Z CV143 2 1 4.7U_0603_6.3V6K 0.1U_0402_16V4Z +IFPD_IOVDD
4.7U_0603_6.3V6K CV133 CV134 CV135 0.1U_0402_16V4Z DHDMI@ DHDMI@ DHDMI@ DHDMI@ DHDMI@ 10K_0402_5% BLM18PG181SN1D_0603
DIS@ DIS@ DIS@ DIS@ DIS@ 2 2 2 2 2 IHDMI@ EDP@ CV212
2 2 2 2 2 1 1 1 1 1
CV219 CV212 10K_0402_5%
1U_0402_6.3V4Z 4.7U_0603_6.3V6K CV147 CV148 CV197 0.1U_0402_16V4Z NOEDP@
1U_0402_6.3V4Z EDP@ EDP@ EDP@ EDP@ EDP@
A 2 2 2 2 2 A

CV213
10K_0402_5% 1U_0402_6.3V4Z
OPT@

www.vinafix.vn
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 16 of 58
5 4 3 2 1
 5 4 3 2 1

UV1F

B3 Part 6 of 7
GND_0
B6 GND_1 GND_97 V18
B9 GND_2 GND_98 V20
B12 GND_3 GND_99 V22
B15 GND_4 GND_100 V24
B21 GND_5 GND_101 V31
B24 GND_6 GND_102 Y11
B27 GND_7 GND_103 Y13
B30 GND_8 GND_104 Y15
B33 GND_9 GND_105 Y17
D
C2 GND_10 GND_106 Y19 D
C34 GND_11 GND_107 Y21
E6 GND_12 GND_108 Y23
E9 GND_13 GND_109 Y25
E12 GND_14 GND_110 AA2
E15 GND_15 GND_111 AA5
E18 GND_16 GND_112 AA11
E24 GND_17 GND_113 AA12
E27 GND_18 GND_114 AA13
E30 GND_19 GND_115 AA14
F2 GND_20 GND_116 AA15
F31 GND_21 GND_117 AA16
F34 GND_22 GND_118 AA17
F5 GND_23 GND_119 AA18
J2 GND_24 GND_120 AA19
J5 GND_25 GND_121 AA20
J31 GND_26 GND_122 AA21
J34 GND_27 GND_123 AA22
K9 GND_28 GND_124 AA23
L9 GND_29 GND_125 AA24
M2 GND_30 GND_126 AA25
M5 GND_31 GND_127 AA34
M11 GND_32 GND_128 AB12
M13 GND_33 GND_129 AB14
M15 GND_34 GND_130 AB16
M17 GND_35 GND_131 AB18
M19 GND_36 GND_132 AB20
M21 GND_37 GND_133 AB22
M23 GND_38 GND_134 AB24
M25 GND_39 GND_135 AC9
C M31 GND_40 GND_136 AD2 C
M34 GND_41 GND_137 AD5

GND
N11 GND_42 GND_138 AD11
N12 GND_43 GND_139 AD13
N13 GND_44 GND_140 AD15
N14 GND_45 GND_141 AD17
N15 GND_46 GND_142 AD21
N16 GND_47 GND_143 AD23
N17 GND_48 GND_144 AD25
N18 GND_49 GND_145 AD31
N19 GND_50 GND_146 AD34
N20 GND_51 GND_147 AE11
N21 GND_52 GND_148 AE12
N22 GND_53 GND_149 AE13
N23 GND_54 GND_150 AE14
N24 GND_55 GND_151 AE15
N25 GND_56 GND_152 AE16
P12 GND_57 GND_153 AE17
P14 GND_58 GND_154 AE18
P16 GND_59 GND_155 AE19
P18 GND_60 GND_156 AE20
P20 GND_61 GND_157 AE21
P22 GND_62 GND_158 AE22
P24 GND_63 GND_159 AE23
R2 GND_64 GND_160 AE24
R5 GND_65 GND_161 AE25
R31 GND_66 GND_162 AG2
R34 GND_67 GND_163 AG5
T11 GND_68 GND_164 AG31
B
T13 GND_69 GND_165 AG34 B
T15 GND_70 GND_166 AK2
T17 GND_71 GND_167 AK5
T19 GND_72 GND_168 AK14
T21 GND_73 GND_169 AK31
T23 GND_74 GND_170 AK34
T25 GND_75 GND_171 AL6
U11 GND_76 GND_172 AL9
U12 GND_77 GND_173 AL12
U13 GND_78 GND_174 AL15
U14 GND_79 GND_175 AL18
U15 GND_80 GND_176 AL21
U16 GND_81 GND_177 AL24
U17 GND_82 GND_178 AL27
U18 GND_83 GND_179 AL30
U19 GND_84 GND_180 AN2
U20 GND_85 GND_181 AN34
U21 GND_86 GND_182 AP3
U22 GND_87 GND_183 AP6
U23 GND_88 GND_184 AP9
U24 GND_89 GND_185 AP12
U25 GND_90 GND_186 AP15
V2 GND_91 GND_187 AP18
V5 GND_92 GND_188 AP21
V9 GND_93 GND_189 AP24
V12 GND_94 GND_190 AP27
V14 GND_95 GND_191 AP30
V16 GND_96 GND_192 AP33

A A
N12P-GS1-A1_BGA_973P N12PGSR1@

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 17 of 58
5 4 3 2 1
 5 4 3 2 1

UV1B

Part 2 of 7 CMDA0
D <20,21> MDA[0..63]
MDA[0..63] MDA0 L32 FBA_D0
FBA_CMD0
FBA_CMD1
U30
V30
CMDA0 <20> GB2-128 D
MDA1 CMDA2
MDA2
N33
L33
FBA_D1
FBA_D2
FBA_CMD2
FBA_CMD3
U31
V32 CMDA3
CMDA2
CMDA3
<20>
<20>
Mode E - Mirror Mode Mapping
MDA3 N34 T35 CMDA4
FBA_D3 FBA_CMD4 CMDA4 <20,21>
MDA4 N35 U33 CMDA5 DATA Bus
FBA_D4 FBA_CMD5 CMDA5 <20,21>
MDA5 P35 W 32 CMDA6
FBA_D5 FBA_CMD6 CMDA6 <20,21>
MDA6 P33 W 33 CMDA7
CMDA7 <20,21> Address 0..31 32..63
MDA7 FBA_D6 FBA_CMD7 CMDA8
P34 FBA_D7 FBA_CMD8 W 31 CMDA8 <20,21>
MDA8 K35 W 34 CMDA9 CMD3 CKE_L
FBA_D8 FBA_CMD9 CMDA9 <20,21>
MDA9 K33 U34 CMDA10
FBA_D9 FBA_CMD10 CMDA10 <20,21>
MDA10 K34 U35 CMDA11 CMD8 A8 A8
FBA_D10 FBA_CMD11 CMDA11 <20,21>
MDA11 H33 U32 CMDA12
FBA_D11 FBA_CMD12 CMDA12 <20,21>
MDA12 G34 T34 CMDA13 CMD2 CS0#_L
FBA_D12 FBA_CMD13 CMDA13 <20,21>
MDA13 G33 T33 CMDA14
FBA_D13 FBA_CMD14 CMDA14 <20,21>
MDA14 E34 W 30 CMDA15 CMD21 A7 A6
FBA_D14 FBA_CMD15 CMDA15 <20,21>
MDA15 E33 AB30 CMDA16
FBA_D15 FBA_CMD16 CMDA16 <21>
MDA16 G31 AA30 CMD24 A2 A1
MDA17 FBA_D16 FBA_CMD17 CMDA18
F30 FBA_D17 FBA_CMD18 AB31 CMDA18 <21>
MDA18 G30 AA32 CMDA19 CMD23 A11 A9
FBA_D18 FBA_CMD19 CMDA19 <21>
MDA19 G32 AB33 CMDA20
FBA_D19 FBA_CMD20 CMDA20 <20,21>
MDA20 K30 Y32 CMDA21 CMD26 A5 A4
FBA_D20 FBA_CMD21 CMDA21 <20,21>
MDA21 K32 Y33 CMDA22
FBA_D21 FBA_CMD22 CMDA22 <20,21>
MDA22 H30 AB34 CMDA23 CMD7 A0 A12
FBA_D22 FBA_CMD23 CMDA23 <20,21>
MDA23 K31 AB35 CMDA24
FBA_D23 FBA_CMD24 CMDA24 <20,21>
MDA24 L31 Y35 CMDA25 CMD15 CAS# CAS#
FBA_D24 FBA_CMD25 CMDA25 <20,21>
MDA25 L30 W 35 CMDA26
FBA_D25 FBA_CMD26 CMDA26 <20,21>
MDA26 M32 Y34 CMDA27 CMD13 BA1 A3

MEMORY INTERFACE
FBA_D26 FBA_CMD27 CMDA27 <20,21>
MDA27 N30 Y31 CMDA28
FBA_D27 FBA_CMD28 CMDA28 <20,21>
MDA28 M30 Y30 CMDA29 CMD4 A9 A11
FBA_D28 FBA_CMD29 CMDA29 <20,21>
MDA29 P31 W 29 CMDA30
FBA_D29 FBA_CMD30 CMDA30 <20,21>
C MDA30 R32 Y29 CMD18 CS0#_H C
MDA31 FBA_D30 FBA_CMD31
R30 FBA_D31
MDA32 AG30 P32 DQMA0 CMD29 BA0 BA0
MDA33 FBA_D32 FBA_DQM0 DQMA1
AG32 FBA_D33 FBA_DQM1 H34
MDA34 AH31 J30 DQMA2 CMD27 BA2 A15
MDA35 FBA_D34 FBA_DQM2 DQMA3
AF31 FBA_D35 FBA_DQM3 P30 DQMA[7..0] <20,21>
MDA36 AF30 AF32 DQMA4 CMD6 A3 BA1
MDA37 FBA_D36 FBA_DQM4 DQMA5
AE30 FBA_D37 FBA_DQM5 AL32
MDA38 AC32 AL34 DQMA6 CMD17 CS1#_H
MDA39 FBA_D38 FBA_DQM6 DQMA7
AD30 FBA_D39 FBA_DQM7 AF35
+VRAM_1.5VS MDA40 AN33 FBA_D40 CMD19 ODT_H
MDA41 AL31 L35 DQSA#0
FBA_D41 FBA_DQS_RN0

A
MDA42 AM33 G35 DQSA#1 CMD22 A4 A5
FBA_D42 FBA_DQS_RN1
1

MDA43 AL33 H31 DQSA#2

RV55 MDA44 FBA_D43 FBA_DQS_RN2 DQSA#3
AK30 FBA_D44 FBA_DQS_RN3 N32 DQSA#[7..0] <20,21> CMD12 A13 A14
1.1K_0402_1% MDA45 AK32 AD32 DQSA#4
@ MDA46 FBA_D45 FBA_DQS_RN4 DQSA#5
AJ30 FBA_D46 FBA_DQS_RN5 AJ31 CMD28 WE# A10
12mil MDA47 AH30 AJ35 DQSA#6
2

+FB_VREF MDA48 FBA_D47 FBA_DQS_RN6 DQSA#7

AH33 FBA_D48 FBA_DQS_RN7 AC34 CMD10 A1 A2
MDA49 AH35 FBA_D49
1

1 MDA50 AH34 L34 DQSA0 CMD25 A10 WE#

RV56 CV146 MDA51 FBA_D50 FBA_DQS_W P0 DQSA1
AH32 FBA_D51 FBA_DQS_W P1 H35
1.1K_0402_1% 0.01U_0402_25V7K MDA52 AJ33 J32 DQSA2 CMD9 A12 A0
@ @ MDA53 FBA_D52 FBA_DQS_W P2 DQSA3
AL35 FBA_D53 FBA_DQS_W P3 N31 DQSA[7..0] <20,21>
2 MDA54 DQSA4
AM34 AE31 CMD1 CS1#_L
2

MDA55 FBA_D54 FBA_DQS_W P4 DQSA5

AM35 FBA_D55 FBA_DQS_W P5 AJ32
MDA56 AF33 AJ34 DQSA6 CMD11 RAS# RAS#
MDA57 FBA_D56 FBA_DQS_W P6 DQSA7
AE32 FBA_D57 FBA_DQS_W P7 AC33
MDA58 AF34 CMD0 ODT_L
MDA59 FBA_D58
B
AE35 FBA_D59 FBA_W CK0 P29 B
MDA60 AE34 R29 CMD5 A6 A7
MDA61 FBA_D60 FBA_W CK0_N
AE33 FBA_D61 FBA_W CK1 L29
+1.05VS_DGPU MDA62 CMD16
AB32 FBA_D62 FBA_W CK1_N M29 CKE_H
MDA63 AC35 AG29
LV6 FBA_D63 FBA_W CK2
100mA FBA_W CK2_N AH29 CMD20 RST RST
1 2 1U_0402_6.3V4Z +FB_AVDD0 AG27 AD29
BLM18PG330SN1D_0603 FB_DLLAVDD_0 FBA_W CK3
AF27 FB_PLLAVDD_0 FBA_W CK3_N AE29 CMD14 A14 A13
2 DIS@ 2 1 1
CV106 CV69 CV149 CV84 +FB_AVDD1 J19 CMD30 A15 BA2
10U_0603_6.3V6M FB_DLLAVDD_1 CLKA0
J18 FB_PLLAVDD_1 FBA_CLK0 T32 CLKA0 <20>
DIS@ DIS@ DIS@ DIS@ 0.1U_0402_16V4Z T31 CLKA0#
1 1 2 2 FBA_CLK0_N CLKA0# <20>
+FB_VREF J27
RV101 FB_VREF_NC
+VRAM_1.5VS 2 DIS@ 1 60.4_0402_1%T30 FBA_DEBUG0 FBA_CLK1 AC31 CLKA1
CLKA1 <21>
10U_0603_6.3V6M 2 1 T29 AC30 CLKA1#
FBA_DEBUG1 FBA_CLK1_N CLKA1# <21>
RV57 10K_0402_5%
N12PGS@
N12P-GS1-A1_BGA_973P N12PGSR1@
+1.05VS_DGPU

LV9
100mA RV57
1 2 1U_0402_6.3V4Z +FB_AVDD1 10K_0402_5% LV6
BLM18PG330SN1D_0603 N12PGE@ BLM18PG330SN1D_0603
2 N12PGS@ 2 1 1 OPT@
CV137 CV121 CV150 CV136
10U_0603_6.3V6M CV106 CV69
N12PGS@ N12PGS@ N12PGS@ N12PGS@ 0.1U_0402_16V4Z 10U_0603_6.3V6M 10U_0603_6.3V6M
1 1 2 2 OPT@ OPT@

10U_0603_6.3V6M CV149 CV84

A RV101 1U_0402_6.3V4Z 0.1U_0402_16V4Z A
60.4_0402_1% OPT@ OPT@
CV137 LV9 OPT@
10U_0603_6.3V6M BLM18PG330SN1D_0603
N12PGE@ N12PGE@

CV121 CV136
10U_0603_6.3V6M 0.1U_0402_16V4Z Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
N12PGE@ N12PGE@ 2009/01/01 2010/01/01 Title
Issued Date Deciphered Date
CV150
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_MEM Interface A
1U_0402_6.3V4Z AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
N12PGE@ 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 18 of 58
5 4 3 2 1
 5 4 3 2 1

UV1C

Part 3 of 7 F18 CMDB0

MDB[0..63] FBC_CMD0 CMDB0 <22>
MDB0 B13 E19
<22,23> MDB[0..63] FBC_D0 FBC_CMD1
MDB1 D13 D18 CMDB2
FBC_D1 FBC_CMD2 CMDB2 <22>
MDB2 A13 C17 CMDB3
FBC_D2 FBC_CMD3 CMDB3 <22>
MDB3 A14 F19 CMDB4
FBC_D3 FBC_CMD4 CMDB4 <22,23>
MDB4 C16 C19 CMDB5
FBC_D4 FBC_CMD5 CMDB5 <22,23>
MDB5 CMDB6
D
MDB6
B16
A17
FBC_D5
FBC_D6
FBC_CMD6
FBC_CMD7
B17
E20 CMDB7
CMDB6
CMDB7
<22,23>
<22,23>
GB2-128 D

MDB7 CMDB8
MDB8
D16
C13
FBC_D7
FBC_D8
FBC_CMD8
FBC_CMD9
B19
D20 CMDB9
CMDB8
CMDB9
<22,23>
<22,23>
Mode E - Mirror Mode Mapping
MDB9 B11 A19 CMDB10
FBC_D9 FBC_CMD10 CMDB10 <22,23>
MDB10 C11 D19 CMDB11
FBC_D10 FBC_CMD11 CMDB11 <22,23>
MDB11 A11 C20 CMDB12 DATA Bus
FBC_D11 FBC_CMD12 CMDB12 <22,23>
MDB12 C10 F20 CMDB13
FBC_D12 FBC_CMD13 CMDB13 <22,23>
MDB13 C8 B20 CMDB14
CMDB14 <22,23> Address 0..31 32..63
MDB14 FBC_D13 FBC_CMD14 CMDB15
B8 FBC_D14 FBC_CMD15 G21 CMDB15 <22,23>
MDB15 A8 F22 CMDB16 CMD3 CKE_L
FBC_D15 FBC_CMD16 CMDB16 <23>
MDB16 E8 F24
MDB17 FBC_D16 FBC_CMD17 CMDB18
F8 FBC_D17 FBC_CMD18 F23 CMDB18 <23> CMD8 A8 A8
MDB18 F10 C25 CMDB19
FBC_D18 FBC_CMD19 CMDB19 <23>
MDB19 F9 C23 CMDB20 CMD2 CS0#_L
FBC_D19 FBC_CMD20 CMDB20 <22,23>
MDB20 F12 F21 CMDB21
FBC_D20 FBC_CMD21 CMDB21 <22,23>
MDB21 D8 E22 CMDB22 CMD21 A7 A6
FBC_D21 FBC_CMD22 CMDB22 <22,23>
MDB22 D11 D21 CMDB23
FBC_D22 FBC_CMD23 CMDB23 <22,23>
MDB23 E11 A23 CMDB24 CMD24 A2 A1
FBC_D23 FBC_CMD24 CMDB24 <22,23>
MDB24 D12 D22 CMDB25
FBC_D24 FBC_CMD25 CMDB25 <22,23>
MDB25 E13 B23 CMDB26 CMD23 A11 A9
FBC_D25 FBC_CMD26 CMDB26 <22,23>
MDB26 F13 C22 CMDB27

MEMORY INTERFACE C
FBC_D26 FBC_CMD27 CMDB27 <22,23>
MDB27 F14 B22 CMDB28 CMD26 A5 A4
FBC_D27 FBC_CMD28 CMDB28 <22,23>
MDB28 F15 A22 CMDB29
FBC_D28 FBC_CMD29 CMDB29 <22,23>
MDB29 E16 A20 CMDB30 CMD7 A0 A12
FBC_D29 FBC_CMD30 CMDB30 <22,23>
MDB30 F16 G20
MDB31 FBC_D30 FBC_CMD31
F17 FBC_D31 CMD15 CAS# CAS#
C MDB32 D29 A16 DQMB0 C
MDB33 FBC_D32 FBC_DQM0 DQMB1
F27 FBC_D33 FBC_DQM1 D10 CMD13 BA1 A3
MDB34 F28 F11 DQMB2
MDB35 FBC_D34 FBC_DQM2 DQMB3
E28 FBC_D35 FBC_DQM3 D15 DQMB[7..0] <22,23> CMD4 A9 A11
MDB36 D26 D27 DQMB4
MDB37 FBC_D36 FBC_DQM4 DQMB5
F25 FBC_D37 FBC_DQM5 D34 CMD18 CS0#_H
MDB38 D24 A34 DQMB6
MDB39 FBC_D38 FBC_DQM6 DQMB7
E25 FBC_D39 FBC_DQM7 D28 CMD29 BA0 BA0
MDB40 E32
MDB41 FBC_D40 DQSB#0
F32 FBC_D41 FBC_DQS_RN0 B14 CMD27 BA2 A15
MDB42 D33 B10 DQSB#1
MDB43 FBC_D42 FBC_DQS_RN1 DQSB#2
E31 FBC_D43 FBC_DQS_RN2 D9 CMD6 A3 BA1
MDB44 C33 E14 DQSB#3
FBC_D44 FBC_DQS_RN3 DQSB#[7..0] <22,23>
MDB45 F29 F26 DQSB#4 CMD17 CS1#_H
MDB46 FBC_D45 FBC_DQS_RN4 DQSB#5
D30 FBC_D46 FBC_DQS_RN5 D31
MDB47 E29 A31 DQSB#6 CMD19 ODT_H
MDB48 FBC_D47 FBC_DQS_RN6 DQSB#7
B29 FBC_D48 FBC_DQS_RN7 A26
MDB49 C31 CMD22 A4 A5
MDB50 FBC_D49 DQSB0
C29 FBC_D50 FBC_DQS_WP0 C14
RV58 MDB51 B31 A10 DQSB1 CMD12 A13 A14
40.2_0402_1% MDB52 FBC_D51 FBC_DQS_WP1 DQSB2
C32 FBC_D52 FBC_DQS_WP2 E10
OPT@ MDB53 B32 D14 DQSB3 CMD28 WE# A10
FBC_D53 FBC_DQS_WP3 DQSB[7..0] <22,23>
MDB54 B35 E26 DQSB4
RV59 MDB55 FBC_D54 FBC_DQS_WP4 DQSB5
B34 FBC_D55 FBC_DQS_WP5 D32 CMD10 A1 A2
40.2_0402_1% MDB56 A29 A32 DQSB6
OPT@ MDB57 FBC_D56 FBC_DQS_WP6 DQSB7
B28 FBC_D57 FBC_DQS_WP7 B26 CMD25 A10 WE#
MDB58 A28
RV60 MDB59 FBC_D58
B C28 FBC_D59 FBC_WCK0 G14 CMD9 A12 A0 B
60.4_0402_1% MDB60 C26 G15
OPT@ MDB61 FBC_D60 FBC_WCK0_N
D25 FBC_D61 FBC_WCK1 G11 CMD1 CS1#_L
MDB62 B25 G12
MDB63 FBC_D62 FBC_WCK1_N
A25 FBC_D63 FBC_WCK2 G27 CMD11 RAS# RAS#
FBC_WCK2_N G28
FBC_WCK3 G24 CMD0 ODT_L
+VRAM_1.5VS 1 DIS@ 2 K27 FBCAL_PD_VDDQ FBC_WCK3_N G25
RV58 40.2_0402_1% CMD5 A6 A7
1 DIS@ 2 L27 FBCAL_PU_GND
RV59 40.2_0402_1% E17 CLKB0 CMD16 CKE_H
FBC_CLK0 CLKB0 <22>
1 DIS@ 2 M27 FBCAL_TERM_GND FBC_CLK0_N D17 CLKB0#
CLKB0# <22>
RV60 60.4_0402_1% CMD20 RST RST
+VRAM_1.5VS RV105 2 N12PGS@ 1 60.4_0402_1%G19 FBC_DEBUG0 FBC_CLK1 D23 CLKB1
CLKB1 <23>
2 1 G16 E23 CLKB1# CMD14 A14 A13
FBB_DEBUG1 FBC_CLK1_N CLKB1# <23>
RV61 10K_0402_5%
N12PGS@ CMD30 A15 BA2
N12P-GS1-A1_BGA_973P N12PGSR1@

RV61
10K_0402_5%
N12PGE@

RV105
60.4_0402_1%
A N12PGE@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_MEM Interface C
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 19 of 58
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits MDA[0..63]

CMDA[30..0]
<18,21>

<18,21>

DQMA[7..0] <18,21>
UV5 UV6
DQSA[7..0] <18,21>
+VRAM_1.5VS +FBA_VREF0 M8 E3 MDA3 +FBA_VREF0 M8 E3 MDA19
VREFCA DQL0 VREFCA DQL0 DQSA#[7..0] <18,21>
H1 F7 MDA6 H1 F7 MDA17
VREFDQ DQL1 MDA1 VREFDQ DQL1 MDA18
DQL2 F2 DQL2 F2
1

D CMDA7 N3 F8 MDA4 CMDA7 N3 F8 MDA16 Group2 D

RV62 CMDA10 A0 DQL3 MDA2 CMDA10 A0 DQL3 MDA20
P7 A1 DQL4 H3 Group0 P7 A1 DQL4 H3
1.1K_0402_1% CMDA24 P3 H8 MDA7 CMDA24 P3 H8 MDA22
DIS@ CMDA6 A2 DQL5 MDA0 CMDA6 A2 DQL5 MDA21
N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDA22 P8 H7 MDA5 CMDA22 P8 H7 MDA23
2

+FBA_VREF0 CMDA26 A4 DQL7 CMDA26 A4 DQL7

CMDA5
P2
R8
A5
A6
CMDA5
P2
R8
A5
A6
GB2-128
1

CMDA21 MDA29 CMDA21 MDA14

RV63
1
CV151 CMDA8
R2
T8
A7
A8
DQU0
DQU1
D7
C3 MDA26 CMDA8
R2
T8
A7
A8
DQU0
DQU1
D7
C3 MDA9 Mode E - Mirror Mode Mapping
1.1K_0402_1% 0.01U_0402_25V7K CMDA4 R3 C8 MDA30 CMDA4 R3 C8 MDA12
DIS@ DIS@ CMDA25 A9 DQU2 MDA24 CMDA25 A9 DQU2 MDA11
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
2 CMDA23 MDA27 CMDA23 MDA13
R7 A7 Group3 R7 A7 Group1 DATA Bus
2

CMDA9 A11 DQU4 MDA25 CMDA9 A11 DQU4 MDA8

N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDA12 T3 B8 MDA31 CMDA12 T3 B8 MDA15 Address 0..31 32..63
CMDA14 A13 DQU6 MDA28 CMDA14 A13 DQU6 MDA10
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDA30 M7 CMDA30 M7 CMD3 CKE_L
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD8 A8 A8
CMDA29 M2 B2 CMDA29 M2 B2
CMDA13 BA0 VDD CMDA13 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD2 CS0#_L
CLKA0 CMDA27 M3 G7 CMDA27 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD21 A7 A6
VDD K8 VDD K8
2

VDD N1 VDD N1 CMD24 A2 A1

RV64 CLKA0 J7 N9 CLKA0 J7 N9
<18> CLKA0 CK VDD CK VDD
243_0402_1% CLKA0# K7 R1 CLKA0# K7 R1 CMD23 A11 A9
<18> CLKA0# CK VDD CK VDD
N12MGE@ CMDA3 K9 R9 CMDA3 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
C CMD26 A5 A4 C
1

CLKA0# CMDA0 K1 A1 CMDA0 K1 A1 CMD7 A0 A12

CMDA2 ODT/ODT0 VDDQ CMDA2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDA11 J3 C1 CMDA11 J3 C1 CMD15 CAS# CAS#
CMDA15 RAS VDDQ CMDA15 RAS VDDQ CMDA0
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDA28 L3 D2 CMDA28 L3 D2 CMD13 BA1 A3
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
RV62 RV63 F1 F1 CMDA3 CMD4 A9 A11
1.1K_0402_1% 1.1K_0402_1% DQSA0 VDDQ DQSA2 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
OPT@ OPT@ DQSA3 C7 H9 DQSA1 C7 H9 CMD18 CS0#_H
DQSU VDDQ DQSU VDDQ

2
CV151 RV64 RV98 RV102 CMD29 BA0 BA0
0.01U_0402_25V7K 160_0402_1% DQMA0 E7 A9 DQMA2 E7 A9 10K_0402_5% 10K_0402_5%
OPT@ N12PGE@ DQMA3 DML VSS DQMA1 DML VSS DIS@ DIS@
D3 DMU VSS B3 D3 DMU VSS B3 CMD27 BA2 A15
E1 E1

1
RV64 VSS VSS
VSS G8 VSS G8 CMD6 A3 BA1
160_0402_1% DQSA#0 G3 J2 DQSA#2 G3 J2
N12PGS@ DQSA#3 DQSL VSS DQSA#1 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD17 CS1#_H
VSS M1 VSS M1
VSS M9 VSS M9 CMD19 ODT_H
VSS P1 VSS P1
CMDA20 T2 P9 CMDA20 T2 P9 CMD22 A4 A5
RESET VSS RESET VSS
VSS T1 VSS T1
L8 T9 RV67 L8 T9 CMD12 A13 A14
ZQ/ZQ0 VSS 243_0402_1% ZQ/ZQ0 VSS
RV65 OPT@ CMD28 WE# A10
1

1
B
10K_0402_5% J1 B1 J1 B1 RV98 RV102 B
OPT@ RV65 RV66 NC/ODT1 VSSQ RV67 NC/ODT1 VSSQ 10K_0402_5% 10K_0402_5%
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 CMD10 A1 A2
10K_0402_5% 243_0402_1% J9 D1 243_0402_1% J9 D1 OPT@ OPT@
RV66 DIS@ DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 CMD25 A10 WE#
243_0402_1% E2 E2
2

2
OPT@ VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD9 A12 A0
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD1 CS1#_L
VSSQ G9 VSSQ G9
CMD11 RAS# RAS#
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD0 ODT_L
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
@ @ CMD5 A6 A7
CV152 CV153
1U_0402_6.3V4Z 1U_0402_6.3V4Z CMD16 CKE_H
OPT@ OPT@ +VRAM_1.5VS +VRAM_1.5VS
CV159 CV160 CMD20 RST RST
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
OPT@ OPT@ CMD14 A14 A13
CV154 CV155 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z CV152 CV153 CV154 CV155 CV156 CV157 CV158 CV159 CV160 CV161 CV162 CV163 CV164 CV165 CMD30 A15 BA2
OPT@ OPT@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
CV156 CV157 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2
OPT@ OPT@ 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
CV158 CV161
A 0.1U_0402_16V4Z 0.1U_0402_16V4Z A
OPT@ OPT@
CV162 CV163
0.1U_0402_16V4Z 0.1U_0402_16V4Z
OPT@ OPT@
CV164 CV165
0.1U_0402_16V4Z
OPT@
0.1U_0402_16V4Z
OPT@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_VRAM_A Lower
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 20 of 58
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits

MDA[0..63] <18,20>

CMDA[30..0] <18,20>
UV8 UV7
+VRAM_1.5VS
DQMA[7..0] <18,20>
+FBA_VREF1 M8 E3 MDA38 +FBA_VREF1 M8 E3 MDA58
VREFCA DQL0 MDA33 VREFCA DQL0 MDA59
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQSA[7..0] <18,20>
1
F2 MDA39 F2 MDA57
RV68 CMDA9 DQL2 MDA35 CMDA9 DQL2 MDA61
D N3 A0 DQL3 F8 N3 A0 DQL3 F8 DQSA#[7..0] <18,20> D
1.1K_0402_1% CMDA24 P7 H3 MDA36 Group4 CMDA24 P7 H3 MDA60 Group7
DIS@ CMDA10 A1 DQL4 MDA34 CMDA10 A1 DQL4 MDA62
P3 A2 DQL5 H8 P3 A2 DQL5 H8
CMDA13 N2 G2 MDA37 CMDA13 N2 G2 MDA56
2

+FBA_VREF1 CMDA26 A3 DQL6 MDA32 CMDA26 A3 DQL6 MDA63

P8 A4 DQL7 H7 P8 A4 DQL7 H7
CMDA22 CMDA22
P2 A5 P2 A5 GB2-128
1

1 CMDA21 R8 CMDA21 R8
RV69 CV166 CMDA5 A6 MDA42 CMDA5 A6 MDA51
1.1K_0402_1% 0.01U_0402_25V7K CMDA8
R2
T8
A7
A8
DQU0
DQU1
D7
C3 MDA45 CMDA8
R2
T8
A7
A8
DQU0
DQU1
D7
C3 MDA52 Mode E - Mirror Mode Mapping
DIS@ DIS@ CMDA23 R3 C8 MDA40 CMDA23 R3 C8 MDA48
2 CMDA28 A9 DQU2 MDA46 CMDA28 A9 DQU2 MDA53
L7 C2 L7 C2
2

CMDA4 A10/AP DQU3 MDA41 CMDA4 A10/AP DQU3 MDA49

R7 A11 DQU4 A7 Group5 R7 A11 DQU4 A7 Group6 DATA Bus
CMDA7 N7 A2 MDA47 CMDA7 N7 A2 MDA54
CMDA14 A12 DQU5 MDA43 CMDA14 A12 DQU5 MDA50 Address
T3 A13 DQU6 B8 T3 A13 DQU6 B8 0..31 32..63
CMDA12 T7 A3 MDA44 CMDA12 T7 A3 MDA55
CMDA27 A14 DQU7 CMDA27 A14 DQU7
M7 A15/BA3 +VRAM_1.5VS
M7 A15/BA3 +VRAM_1.5VS
CMD3 CKE_L
CMD8 A8 A8
CMDA29 M2 B2 CMDA29 M2 B2
CMDA6 BA0 VDD CMDA6 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD2 CS0#_L
CLKA1 CMDA30 M3 G7 CMDA30 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD21 A7 A6
VDD K8 VDD K8
2

VDD N1 VDD N1 CMD24 A2 A1

RV70 CLKA1 J7 N9 CLKA1 J7 N9
<18> CLKA1 CK VDD CK VDD
243_0402_1% CLKA1# K7 R1 CLKA1# K7 R1 CMD23 A11 A9
<18> CLKA1# CK VDD CK VDD
N12MGE@ CMDA16 K9 R9 CMDA16 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
C CMD26 A5 A4 C
1

CLKA1# CMDA19 K1 A1 CMDA19 K1 A1 CMD7 A0 A12

CMDA18 ODT/ODT0 VDDQ CMDA18 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDA11 J3 C1 CMDA11 J3 C1 CMD15 CAS# CAS#
CMDA15 RAS VDDQ CMDA15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDA25 L3 D2 CMDA25 L3 D2 CMD13 BA1 A3
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD4 A9 A11
DQSA4 F3 H2 DQSA7 F3 H2
RV68 RV69 DQSA5 DQSL VDDQ DQSA6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD18 CS0#_H
1.1K_0402_1% 1.1K_0402_1%
OPT@ OPT@ CMDA19 CMD29 BA0 BA0
DQMA4 E7 A9 DQMA7 E7 A9
CV166 RV70 DQMA5 DML VSS DQMA6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD27 BA2 A15
0.01U_0402_25V7K 160_0402_1% E1 E1 CMDA16
OPT@ N12PGE@ VSS VSS
VSS G8 VSS G8 CMD6 A3 BA1
DQSA#4 G3 J2 DQSA#7 G3 J2
RV70 DQSA#5 DQSL VSS DQSA#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD17 CS1#_H

2
160_0402_1% M1 M1
N12PGS@ VSS VSS RV100 RV104
VSS M9 VSS M9 CMD19 ODT_H
P1 P1 10K_0402_5% 10K_0402_5%
CMDA20 VSS CMDA20 VSS DIS@ DIS@
T2 RESET VSS P9 T2 RESET VSS P9 CMD22 A4 A5
T1 T1

1
VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD12 A13 A14
CMD28 WE# A10
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 B
RV71 L1 B9 RV72 L1 B9 CMD10 A1 A2
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
DIS@ L9 D8 DIS@ L9 D8 CMD25 A10 WE#
RV71 NCZQ1 VSSQ RV72 NCZQ1 VSSQ
E2 E2
2

2
243_0402_1% VSSQ 243_0402_1% VSSQ
VSSQ E8 VSSQ E8 CMD9 A12 A0
OPT@ F9 OPT@ F9
VSSQ VSSQ RV100 RV104
VSSQ G1 VSSQ G1 CMD1 CS1#_L
G9 G9 10K_0402_5% 10K_0402_5%
VSSQ VSSQ OPT@ OPT@ CMD11 RAS# RAS#
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD0 ODT_L
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
@ @ CMD5 A6 A7
CV167 CV168 +VRAM_1.5VS +VRAM_1.5VS CMD16 CKE_H
1U_0402_6.3V4Z 1U_0402_6.3V4Z
OPT@ OPT@ 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CMD20 RST RST
CV174 CV175
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CMD14 A14 A13
OPT@ OPT@ CV167 CV168 CV169 CV170 CV171 CV172 CV173 CV174 CV175 CV176 CV177 CV178 CV179 CV180
CV169 CV170 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ CMD30 A15 BA2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
OPT@ OPT@ 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV171 CV172 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
OPT@ OPT@
A CV173 CV176 A
0.1U_0402_16V4Z 0.1U_0402_16V4Z
OPT@ OPT@
CV177 CV178
0.1U_0402_16V4Z 0.1U_0402_16V4Z
OPT@ OPT@
CV179
0.1U_0402_16V4Z
CV180
0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title
OPT@ OPT@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_VRAM_A Upper
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 21 of 58
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits MDB[0..63]

CMDB[30..0]
<19,23>

<19,23>

DQMB[7..0] <19,23>

DQSB[7..0] <19,23>
+VRAM_1.5VS UV9 UV10
DQSB#[7..0] <19,23>
+FBB_VREF0 M8 E3 MDB3 +FBB_VREF0 M8 E3 MDB16
VREFCA DQL0 VREFCA DQL0
1
D H1 F7 MDB5 H1 F7 MDB17 D
RV73 VREFDQ DQL1 MDB2 VREFDQ DQL1 MDB19
DQL2 F2 DQL2 F2
1.1K_0402_1% CMDB7 MDB4 Group0 CMDB7 MDB18
8PCS@ CMDB10
N3
P7
A0
A1
DQL3
DQL4
F8
H3 MDB1 CMDB10
N3
P7
A0
A1
DQL3
DQL4
F8
H3 MDB23 Group2 GB2-128
CMDB24 MDB6 CMDB24 MDB21
P3 H8 P3 H8
Mode E - Mirror Mode Mapping
2

+FBB_VREF0 CMDB6 A2 DQL5 MDB0 CMDB6 A2 DQL5 MDB22

N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDB22 P8 H7 MDB7 CMDB22 P8 H7 MDB20
A4 DQL7 A4 DQL7
1

1 CMDB26 P2 CMDB26 P2 DATA Bus

RV74 CV181 CMDB5 A5 CMDB5 A5
R8 A6 R8 A6
1.1K_0402_1% 0.01U_0402_25V7K CMDB21 R2 D7 MDB31 CMDB21 R2 D7 MDB13 Address 0..31 32..63
8PCS@ 8PCS@ CMDB8 A7 DQU0 MDB25 CMDB8 A7 DQU0 MDB9
T8 A8 DQU1 C3 T8 A8 DQU1 C3
2 CMDB4 MDB29 CMDB4 MDB14
R3 C8 R3 C8 CMD3 CKE_L
2

CMDB25 A9 DQU2 MDB24 CMDB25 A9 DQU2 MDB11

L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
CMDB23 R7 A7 MDB28 Group3 CMDB23 R7 A7 MDB12 Group1 CMD8 A8 A8
CMDB9 A11 DQU4 MDB26 CMDB9 A11 DQU4 MDB8
N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDB12 T3 B8 MDB30 CMDB12 T3 B8 MDB15 CMD2 CS0#_L
CMDB14 A13 DQU6 MDB27 CMDB14 A13 DQU6 MDB10
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDB30 M7 CMDB30 M7 CMD21 A7 A6
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD24 A2 A1
CMDB29 M2 B2 CMDB29 M2 B2
CMDB13 BA0 VDD CMDB13 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD23 A11 A9
CLKB0 CMDB27 M3 G7 CMDB27 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD26 A5 A4
VDD K8 VDD K8
2

VDD N1 VDD N1 CMD7 A0 A12

RV75 CLKB0 J7 N9 CLKB0 J7 N9
<19> CLKB0 CK VDD CK VDD
C 160_0402_1% CLKB0# K7 R1 CLKB0# K7 R1 CMD15 CAS# CAS# C
<19> CLKB0# CK VDD CK VDD
8PCS@ CMDB3 K9 R9 CMDB3 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
CMD13 BA1 A3
1

CLKB0# CMDB0 K1 A1 CMDB0 K1 A1 CMD4 A9 A11

CMDB2 ODT/ODT0 VDDQ CMDB2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDB11 J3 C1 CMDB11 J3 C1 CMD18 CS0#_H
CMDB15 RAS VDDQ CMDB15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDB28 L3 D2 CMDB28 L3 D2 CMD29 BA0 BA0
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD27 BA2 A15
DQSB0 F3 H2 DQSB2 F3 H2 CMDB0
DQSB3 DQSL VDDQ DQSB1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD6 A3 BA1
CMDB3 CMD17 CS1#_H
DQMB0 E7 A9 DQMB2 E7 A9
DQMB3 DML VSS DQMB1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD19 ODT_H
VSS E1 VSS E1

2
VSS G8 VSS G8 CMD22 A4 A5
DQSB#0 G3 J2 DQSB#2 G3 J2 RV111
DQSB#3 DQSL VSS DQSB#1 DQSL VSS RV106 10K_0402_5%
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD12 A13 A14
M1 M1 10K_0402_5% 8PCS@
VSS VSS 8PCS@
M9 M9 CMD28 WE# A10

1
VSS VSS
VSS P1 VSS P1
CMDB20 T2 P9 CMDB20 T2 P9 CMD10 A1 A2
RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD25 A10 WE#
B B
CMD9 A12 A0
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV76 RV77 L1 B9 RV78 L1 B9 CMD1 CS1#_L
10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
8PCS@ 8PCS@ L9 D8 8PCS@ L9 D8 CMD11 RAS# RAS#
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD0 ODT_L
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD5 A6 A7
VSSQ G9 VSSQ G9
CMD16 CKE_H
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD20 RST RST
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
@ @ CMD14 A14 A13
CMD30 A15 BA2
+VRAM_1.5VS +VRAM_1.5VS

1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV182 CV183 CV184 CV185 CV186 CV187 CV188 CV189 CV190 CV191 CV192 CV193 CV194 CV195
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z
8PCS@ 8PCS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2
A 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_VRAM_C Lower
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 22 of 58
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits MDB[0..63] <19,22>

CMDB[30..0] <19,22>
UV11 UV12

+VRAM_1.5VS DQMB[7..0] <19,22>

+FBB_VREF1 M8 E3 MDB37 +FBB_VREF1 M8 E3 MDB56
VREFCA DQL0 MDB35 VREFCA DQL0 MDB63
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQSB[7..0] <19,22>
D F2 MDB36 F2 MDB57 D
DQL2 DQL2
1
CMDB9 N3 F8 MDB34 CMDB9 N3 F8 MDB62
A0 DQL3 A0 DQL3 DQSB#[7..0] <19,22>
RV79 CMDB24 P7 H3 MDB38 Group4 CMDB24 P7 H3 MDB58 Group7
1.1K_0402_1% CMDB10 A1 DQL4 MDB32 CMDB10 A1 DQL4 MDB60
P3 A2 DQL5 H8 P3 A2 DQL5 H8
8PCS@ CMDB13 N2 G2 MDB39 CMDB13 N2 G2 MDB59
CMDB26 A3 DQL6 MDB33 CMDB26 A3 DQL6 MDB61
P8 H7 P8 H7
2

+FBB_VREF1 CMDB22 A4 DQL7 CMDB22 A4 DQL7

P2 A5 P2 A5
CMDB21 CMDB21
R8 A6 R8 A6 GB2-128
1

1 CMDB5 R2 D7 MDB41 CMDB5 R2 D7 MDB49

RV80 CV196 CMDB8 A7 DQU0 MDB46 CMDB8 A7 DQU0 MDB55
1.1K_0402_1% 0.01U_0402_25V7K CMDB23
T8
R3
A8
A9
DQU1
DQU2
C3
C8 MDB42 CMDB23
T8
R3
A8
A9
DQU1
DQU2
C3
C8 MDB48 Mode E - Mirror Mode Mapping
8PCS@ 8PCS@ CMDB28 L7 C2 MDB47 CMDB28 L7 C2 MDB53
2 CMDB4 A10/AP DQU3 MDB44 CMDB4 A10/AP DQU3 MDB51
R7 A7 Group5 R7 A7 Group6 DATA Bus
2

CMDB7 A11 DQU4 MDB45 CMDB7 A11 DQU4 MDB52

N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDB14 T3 B8 MDB40 CMDB14 T3 B8 MDB50 Address 0..31 32..63
CMDB12 A13 DQU6 MDB43 CMDB12 A13 DQU6 MDB54
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDB27 M7 CMDB27 M7 CMD3 CKE_L
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD8 A8 A8
CMDB29 M2 B2 CMDB29 M2 B2
CMDB6 BA0 VDD CMDB6 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD2 CS0#_L
CMDB30 M3 G7 CMDB30 M3 G7
CLKB1 BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD21 A7 A6
VDD K8 VDD K8
VDD N1 VDD N1 CMD24 A2 A1
2

CLKB1 J7 N9 CLKB1 J7 N9
<19> CLKB1 CK VDD CK VDD
RV81 CLKB1# K7 R1 CLKB1# K7 R1 CMD23 A11 A9
<19> CLKB1# CK VDD CK VDD
C 160_0402_1% CMDB16 K9 R9 CMDB16 K9 R9 C
CKE/CKE0 VDD CKE/CKE0 VDD
8PCS@ CMD26 A5 A4
1

CMDB19 K1 A1 CMDB19 K1 A1 CMD7 A0 A12

CLKB1# CMDB18 ODT/ODT0 VDDQ CMDB18 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDB11 J3 C1 CMDB11 J3 C1 CMD15 CAS# CAS#
CMDB15 RAS VDDQ CMDB15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDB25 L3 D2 CMDB25 L3 D2 CMD13 BA1 A3
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD4 A9 A11
DQSB4 F3 H2 DQSB7 F3 H2
DQSB5 DQSL VDDQ DQSB6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD18 CS0#_H
CMD29 BA0 BA0
DQMB4 E7 A9 DQMB7 E7 A9
DQMB5 DML VSS DQMB6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD27 BA2 A15
VSS E1 VSS E1
G8 G8 CMDB19 CMD6 A3 BA1
DQSB#4 VSS DQSB#7 VSS
G3 DQSL VSS J2 G3 DQSL VSS J2
DQSB#5 B7 J8 DQSB#6 B7 J8 CMD17 CS1#_H
DQSU VSS DQSU VSS CMDB16
VSS M1 VSS M1
VSS M9 VSS M9 CMD19 ODT_H
VSS P1 VSS P1

2
CMDB20 T2 P9 CMDB20 T2 P9 CMD22 A4 A5
RESET VSS RESET VSS RV108 RV112
VSS T1 VSS T1
L8 T9 L8 T9 10K_0402_5% 10K_0402_5% CMD12 A13 A14
ZQ/ZQ0 VSS ZQ/ZQ0 VSS 8PCS@ 8PCS@
B CMD28 WE# A10 B

1
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV82 L1 B9 RV83 L1 B9 CMD10 A1 A2
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
L9 D8 8PCS@ L9 D8 CMD25 A10 WE#
8PCS@ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD9 A12 A0
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD1 CS1#_L
VSSQ G9 VSSQ G9
CMD11 RAS# RAS#
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD0 ODT_L
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
@ @ CMD5 A6 A7
+VRAM_1.5VS CMD16 CKE_H
+VRAM_1.5VS +VRAM_1.5VS
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CMD20 RST RST
1 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+
1 1 1 1 1 1 1 CMD14 A14 A13
CV122 1 1 1 1 1 1 1 CV205 CV206 CV207 CV208 CV209 CV210 CV211
390U_2.5V_M_R10 CV198 CV199 CV200 CV201 CV202 CV203 CV204 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z CMD30 A15 BA2
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z 8PCS@
2 8PCS@ 2 2 2 2 2 2 2
2 2 2 2 2 2 2 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_VRAM_C Upper
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 23 of 58
5 4 3 2 1
 5 4 3 2 1

Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
+3VS_DGPU
ROM_SO +3VS_DGPU XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
ROM_SCLK +3VS_DGPU PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLLEN_TERM
ROM_SI +3VS_DGPU RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]

2
RV87 RV85 RV86 RV87 STRAP2 +3VS_DGPU PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
45.3K_0402_1% 34.8K_0402_1% 15K_0402_1% 45.3K_0402_1%
DIS@ @ N12MGE@ OPT@ STRAP1 +3VS_DGPU 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
D D

1
STRAP0 +3VS_DGPU USER[3] USER[2] USER[1] USER[0]
<14> STRAP0 STRAP0 RV88
<14> STRAP1 STRAP1 34.8K_0402_1%
<14> STRAP2 STRAP2 OPT@

Resistor Values Pull-up to +3VS Pull-down to Gnd

2
RV84 RV88 RV89 RV89 5K 1000 0000
45.3K_0402_1% 34.8K_0402_1% 24.9K_0402_1% 30K_0402_1%
@ DIS@ N12PGS@ N12PGE@ 10K 1001 0001
1

1
15K 1010 0010
20K 1011 0011
25K 1100 0100
30K 1101 0101

+3VS_DGPU
35K 1110 0110
45K 1111 0111

RV92
2

2
C 15K_0402_1% C
RV90 RV91 RV92 N12PGE@
4.99K_0402_1% 4.99K_0402_1% 15K_0402_1%
@ @ N12PGS@
1

1
RV92
15K_0402_1%
N12MGE@
<14> ROM_SI ROM_SI
<14> ROM_SO ROM_SO
ROM_SCLK
<14> ROM_SCLK
RV94 SUB_VENDOR XCLK_417
10K_0402_1%
2

OPT@ 0 No VBIOS ROM (Default) 0 277MHz (Default)

2

RV93
X76 15K_0402_1% RV94 RV95
@ 10K_0402_1% 15K_0402_1% 1 BIOS ROM is present 1 Reserved
DIS@ @
1

GPU DeviceID ROM_SCLK STRAP2

1

N12M-GE 0x0A7A Pull up 15K Pull up 15K

FB_0_BAR_SIZE USER Straps
0 256MB (Default) User[3:0]
N12P-GS 0x0DF4 Pull up 15K Pull down 25K
1 Reserved 1000-1100 Customer defined
B N12P-GE 0x0DF5 Pull up 15K Pull down 30K B

3GIO_PADCFG PEX_PLL_EN_TERM
3GIO_PADCFG[3:0] 0 Disable (Default)

0110 Notebook Default 1 Enable

512M 0010 PD 15K SLOT_CLOCK_CFG

Hynix H5TQ1G63BFR-12C
SD034150280 0 GPU and MCH don't share a common reference clock
SA000032400 1G 0010 PD 15K
1 GPU and MCH share a common reference clock (Default)
512M 0011 PD 20K
Samsung K4W1G1646E-HC12
SD034200280 SMBUS_ALT_ADDR VGA_DEVICE
SA000035700 1G 0011 PD 20K 0 0x9E (Default) 0 3D Device
A A

1 0x9C (Multi-GPU usage) 1 VGA Device (Default)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title
VGA_MSIC

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 24 of 58
5 4 3 2 1
 A B C D E F G H

R107 R109 C233

OPTIMUS 150_0603_5% 47K_0402_5% 0.1U_0402_16V4Z
+LCD_VDD +3VS +5VS EDP@ EDP@ EDP@
R262 R263 C229 Q1
1 OPT@ 2 LVDS_TXOUT0+ 0_0402_5% 0_0402_5% 0.01U_0402_25V7K 2N7002DW-T/R7_SOT363-6
<31> LCD_TXOUT0+

1
R262 0_0402_5% UMA@ UMA@ EDP@ EDP@

1
<31> LCD_TXOUT0- 1 OPT@ 2 LVDS_TXOUT0- R264 R265 R107
R263 0_0402_5% 0_0402_5% 0_0402_5% 150_0603_5% R108 R120
1 OPT@ 2 LVDS_TXOUT1+ UMA@ UMA@ OPT@ 100K_0402_5% 100K_0402_5% +3VS +5VS
<31> LCD_TXOUT1+
R265 0_0402_5% R298 R277 OPT@ EDP@

2
<31> LCD_TXOUT1- 1 OPT@ 2 LVDS_TXOUT1- 0_0402_5% 0_0402_5%

2
R264 0_0402_5% UMA@ UMA@

6
1 OPT@ 2 LVDS_TXOUT2+ R297 R296
<31> LCD_TXOUT2+
R298 0_0402_5% 0_0402_5% 0_0402_5% OPT@ 2 W=80mils EDP@ 2 W=80mils
1 1
1 OPT@ 2 LVDS_TXOUT2- UMA@ UMA@ Q1A C228 C251
<31> LCD_TXOUT2-
R277 0_0402_5% R300 R299 2N7002DW-T/R7_SOT363-6 2 0.1U_0402_16V7K 0.1U_0402_16V7K

3
S S
<31> LCD_TXCLK+ 1 OPT@ 2 LVDS_TXCLK+ 0_0402_5% 0_0402_5% Reserve for EMI request OPT@ OPT@ EDP@
R297 0_0402_5% UMA@ UMA@ 1 1 2
R109 2 LCDPWR_GATE
G
Q17 LCDPWR_GATE 12G
Q23

1
1 OPT@ 2 LVDS_TXCLK- R332 R350 47K_0402_5% 1 AO3413_SOT23 AO3413_SOT23
<31> LCD_TXCLK-

3
R296 0_0402_5% 0_0402_5% 0_0402_5% 1 CAM@ 2 OPT@ D D

1
1 OPT@ 2 LVDS_EDID_CLK UMA@ UMA@ R78 0_0402_5% C229 +LCD_VDD
<31> LCD_EDID_CLK
R300 0_0402_5% R357 L55 @ 0.01U_0402_25V7K +LCD_VDD
W=80mils
1 OPT@ 2 LVDS_EDID_DATA 0_0402_5% 1 1 USB20_N11_R LCD_ENVDD OPT@ 2
<31> LCD_EDID_DATA
R299 0_0402_5% UMA@
<32> USB20_N11 2 2 5
Q1B 1
1 OPT@ 2 LED_PWM 2N7002DW-T/R7_SOT363-6 C233 W=80mils
<31> PCH_PWM

4
R332 0_0402_5% <32> USB20_P11 4 3 USB20_P11_R OPT@ 0.1U_0402_16V4Z
4 3

2
1 OPT@ 2 LCD_ENVDD OPT@
<31> UMA_ENVDD 2
R350 0_0402_5% WCM-2012-900T_0805 R112 R112
1 OPT@ 2 EC_ENBKL 100K_0402_5% 100K_0402_5%
<31> UMA_ENBKL EC_ENBKL <44>
R357 0_0402_5% 1 CAM@ 2 UMA@ OPT@
R96 0_0402_5%

1
Close to LVDS Connector
DISCRETE LCD/PANEL BD. Conn. R107 R108 R109 C228
150_0603_5% 100K_0402_5% 47K_0402_5% 0.1U_0402_16V7K
1 DIS@ 2 LVDS_TXOUT0+ W=20mils CAM@ D84 @ UMA@ UMA@ UMA@ UMA@
<14> VGA_TXOUT0+
R331 0_0402_5% 0.1U_0402_16V4Z 2
1 DIS@ 2 LVDS_TXOUT0- +3VS 1 CAM@ 2 +3VS_LVDS_CAM 1 2 1 Q1 C229 C233
<14> VGA_TXOUT0-
R309 0_0402_5% R388 0_0603_5% C225 3 2N7002DW-T/R7_SOT363-6 0.01U_0402_25V7K 0.1U_0402_16V4Z
1 DIS@ 2 LVDS_TXOUT1+ JLVDS @ UMA@ UMA@ UMA@
<14> VGA_TXOUT1+
R317 0_0402_5% 1 1 LVDS_EDID_CLK PACDN042Y3R_SOT23-3
LVDS_TXOUT1- USB20_P11_R 2 2 LVDS_EDID_DATA
2
<14> VGA_TXOUT1- 1 DIS@ 2 3 3 4 4 Q17 2
R315 0_0402_5% USB20_N11_R 5 5 INT_MIC_CLK AO3413_SOT23
LVDS_TXOUT2+ 6 6 INT_MIC_DATA
INT_MIC_CLK <43>
<14> VGA_TXOUT2+ 1 DIS@ 2 7 7 8 8 INT_MIC_DATA <43>
UMA@
R308 0_0402_5% LVDS_TXOUT0+ 9 9 LED_PWM R387 2 NO3D@ 1 0_0402_5%
LVDS_TXOUT2- LVDS_TXOUT0- 10 10 BKOFF#_R
INVT_PWM <44>
<14> VGA_TXOUT2- 1 DIS@ 2 11 11 12 12 2 1 BKOFF# <44>
R302 0_0402_5% LVDS_TXOUT1+ 13 13 14 R103 33_0402_5% 1 R143 2 EDP@
LVDS_TXCLK+ LVDS_TXOUT1- 14 LCD_ENVDD EDP_HPD <13>
<14> VGA_TXCLK+ 1 DIS@ 2 15 15 16 16 1 2 0_0402_5%
R305 0_0402_5% LVDS_TXOUT2+ 17 17 R113 10K_0402_5%
LVDS_TXCLK- +3VS LVDS_TXOUT2- 18 18 +3VS_LVDSDDC
<14> VGA_TXCLK- 1 DIS@ 2 19 19 20 20 2 R1440 1 NOEDP@ +3VS
R304 0_0402_5% LVDS_TXCLK+ 21 21 3A 0_0603_5%
LVDS_EDID_CLK LVDS_TXCLK- 22 22
<13> VGA_EDID_CLK 1 DIS@ 2 23 23 24 24 +LCD_VDD
R314 0_0402_5% 2 R1434 1 LVDS_EDID_DATA 25 25 26 26 1 1 For EMI
1 DIS@ 2 LVDS_EDID_DATA EDP@ 100K_0402_5% 27 27
<13> VGA_EDID_DATA
R310 0_0402_5% 28 28 +LCD_INV
C226 C227 @
1 1
29 29 30 30
1 3D@ 2 LED_PWM 2 R1435 1 LVDS_EDID_CLK 0.1U_0402_16V4Z 4.7U_0805_10V4Z C231 C232
<13> VGA_BL_PWM 2 2
R349 0_0402_5% EDP@ 100K_0402_5% 31 GND1 680P_0402_50V7K 0.1U_0402_16V4Z
1 DIS@ 2 LCD_ENVDD 32 GND2 2 2
<13> VGA_ENVDD
R356 0_0402_5%
1 DIS@ 2 EC_ENBKL ACES_87242-3001-09
<13> VGA_ENBKL
R358 0_0402_5%

Close to LVDS Connector

+LCD_INV B+
L2
DISCRETE for Full-HD and 3D LVDS Panel 2 1 R107 R108 R109 C228
1 1 FBMA-L11-201209-221LMA30T_0805 150_0603_5% 100K_0402_5% 47K_0402_5% 0.1U_0402_16V7K
NO3D@ NO3D@ NO3D@ NO3D@
<14> VGA_TZOUT0+ 1 3D@ 2 LVDS_TZOUT0+ For 3D Panel C234 C235
R500 0_0402_5% 68P_0402_50V8J 0.1U_0402_25V6 Q1 C229 C233
3 2 2 3
1 3D@ 2 LVDS_TZOUT0- 2N7002DW-T/R7_SOT363-6 0.01U_0402_25V7K 0.1U_0402_16V4Z
<14> VGA_TZOUT0-
R501 0_0402_5% NO3D@ NO3D@ NO3D@
1 3D@ 2 LVDS_TZOUT1+ JLVDS1
<14> VGA_TZOUT1+
R502 0_0402_5% LVDS_TZOUT0+ 1 Q17
LVDS_TZOUT1- LVDS_TZOUT0- 1
<14> VGA_TZOUT1- 1 3D@ 2 2 2
AO3413_SOT23
R503 0_0402_5% LVDS_TZOUT1+ 3 NO3D@
LVDS_TZOUT2+ LVDS_TZOUT1- 3
<14> VGA_TZOUT2+ 1 3D@ 2 4 4
R504 0_0402_5% LVDS_TZOUT2+ 5 B+
LVDS_TZOUT2- LVDS_TZOUT2- 5
<14> VGA_TZOUT2- 1 3D@ 2 6 6 For EMI
R505 0_0402_5% LVDS_TZCLK+ 7
LVDS_TZCLK+ LVDS_TZCLK- 7
<14> VGA_TZCLK+ 1 3D@ 2 8 8
R507 0_0402_5% +5VALW 9
LVDS_TZCLK- 9
<14> VGA_TZCLK- 1 3D@ 2 10 10 1 1 1 1

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
R508 0_0402_5%
C236 C268 C489 C490
@
2 2 2 2
Close to LVDS1 Connector 11
12
GND1
GND2
ACES_87213-1000N
DISCRETE for Full-HD and 3D eDP Panel @
EDP@
C880 1 20.1U_0402_16V7K LVDS_TZOUT0+
<14> VGA_EDP_TX0+
EDP@
C881 1 20.1U_0402_16V7K LVDS_TZOUT0-
<14> VGA_EDP_TX0-
EDP@
C882 1 20.1U_0402_16V7K LVDS_TZOUT1+
<14> VGA_EDP_TX1+
EDP@
C883 1 20.1U_0402_16V7K LVDS_TZOUT1-
<14> VGA_EDP_TX1-
4 EDP@ 4
C884 1 20.1U_0402_16V7K LVDS_TZOUT2+
<14> VGA_EDP_TX2+
EDP@
C885 1 20.1U_0402_16V7K LVDS_TZOUT2-
<14> VGA_EDP_TX2-
EDP@
C886 1 20.1U_0402_16V7K LVDS_TZCLK+
<14> VGA_EDP_TX3+
EDP@
C887 20.1U_0402_16V7K LVDS_TZCLK- Security Classification Compal Secret Data Compal Electronics, Inc.
<14> VGA_EDP_TX3- 1
Close to LVDS1 Connector Issued Date 200910/9 Deciphered Date 2010/01/23 Title
EDP@
<14> VGA_EDP_AUX
C888 1 20.1U_0402_16V7K LVDS_EDID_CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/eDP
EDP@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C889 1 20.1U_0402_16V7K LVDS_EDID_DATA Custom 0.1
<14> VGA_EDP_AUX- DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
PHQAA LA-6831P M/B
Close to LVDS Connector MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 02, 2010 Sheet 25 of 58

www.vinafix.vn
A B C D E F G H
 A B C D E

CRT CONNECTOR

1
D3 @ D4 @ D5 @
+3VS
If=1A
+5VS +CRT_VCC_R +CRT_VCC
D6
OPTIMUS DAN217_SC59 DAN217_SC59 DAN217_SC59 2 F1 40 mils

3
1 1 2
1 3 RB491D_SOT23-3 1 1
<31> UMA_CRT_R 1 OPT@ 2 CRT_R 1.1A_6V_MINISMDC110F-2
R200 0_0402_5% C237
<31> UMA_CRT_G 1 OPT@ 2 CRT_G 0.1U_0402_16V4Z
R204 0_0402_5% CRT_R L3 2
1 2 NBQ100505T-800Y_0402 CRT_R_L @
<31> UMA_CRT_B 1 OPT@ 2 CRT_B
R211 0_0402_5% CRT_G L4 1 2 NBQ100505T-800Y_0402 CRT_G_L
<31> UMA_CRT_HSYNC 1 OPT@ 2 CRT_HSYNC
R213 0_0402_5% CRT_B L5 1 2 NBQ100505T-800Y_0402 CRT_B_L
<31> UMA_CRT_VSYNC 1 OPT@ 2 CRT_VSYNC
R235 0_0402_5% JCRT @
<31> UMA_CRT_CLK 1 OPT@ 2 CRT_CLK 6 6
R236 0_0402_5% 11 11
1 OPT@ 2 CRT_DATA R138 R139 R140 CRT_R_L 1

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
<31> UMA_CRT_DATA 1
R261 0_0402_5%

150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1 7 7

1
CRT_DDC_DAT 12
C238 C239 C240 C241 C242 C243 CRT_G_L 12
2 2
Close to CRT Connector 2 2 2 2 2 2 HSYNC
8
13
8
13
CRT_B_L 3

2
3
+CRT_VCC 9 9
VSYNC 14 16
R200 R204 R211 14 G
4 4 G 17
0_0402_5% 0_0402_5% 0_0402_5% 10
UMA@ UMA@ UMA@ CRT_DDC_CLK 10
15 15
5 5
R213 R235 R236
0_0402_5% 0_0402_5% 0_0402_5% ALLTO_C10532-11505-L_15P-T
UMA@ UMA@ UMA@
2 2
R261 +CRT_VCC
0_0402_5%
UMA@
1 2
C244 0.1U_0402_16V4Z 2 1
R141 10K_0402_5%

5
1
DISCRETE

OE#
P
CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC
A Y L6 10_0402_5%
+CRT_VCC

G
<13> VGA_CRT_R 1 DIS@ 2 CRT_R U6
R178 0_0402_5% SN74AHCT1G125GW _SOT353-5

5
1
<13> VGA_CRT_G 1 DIS@ 2 CRT_G
R181 0_0402_5%

OE#
P
<13> VGA_CRT_B 1 DIS@ 2 CRT_B CRT_VSYNC 2 A Y 4 D_CRT_VSYNC 1 2 VSYNC
R167 0_0402_5% L7 10_0402_5%

10P_0402_50V8J

10P_0402_50V8J
1 1

G
<13> VGA_CRT_HSYNC 1 DIS@ 2 CRT_HSYNC U7
R177 0_0402_5% SN74AHCT1G125GW _SOT353-5 C245 C246

3
<13> VGA_CRT_VSYNC 1 DIS@ 2 CRT_VSYNC @ @
R179 0_0402_5% 2 2
<13> VGA_CRT_CLK 1 DIS@ 2 CRT_CLK
R193 0_0402_5%
<13> VGA_CRT_DATA 1 DIS@ 2 CRT_DATA
R194 0_0402_5%

Close to CRT Connector

3 3

+CRT_VCC

+3VS

2
R153 R159
4.7K_0402_5% 4.7K_0402_5%

1
2
Q205A
CRT_CLK 5 1 6 CRT_DDC_CLK

2N7002DW -T/R7_SOT363-6
Q205B
CRT_DATA 4 3 CRT_DDC_DAT
1 1
1 1 2N7002DW -T/R7_SOT363-6
C284 C283
C282 C285 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 26 of 58
A B C D E
 5 4 3 2 1

HDMI CEC Controller Address: 0011010X U16

CEC_INT#
<44,49> EC_SMB_CK1 1 11 CEC_INT# <44> +3VL
+3VL +3VL P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01

+3VL 2 12 CEC_TEST 1 CEC@ 2

P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# R168 4.7K_0402_5%

2
+3VL +3VL
R162 D9 2 CEC@ 1CEC_RST# 3 13 CEC_FSHUPD1 CEC@ 2
R169 4.7K_0402_5% RESET# P1_4/TXD0 R170 4.7K_0402_5%
10K_0402_5% CH751H-40PT_SOD323-2
CEC@ CEC@ CEC_FSHUPD (Pin13)

1
2 CEC@ 1CEC_XOUT 4 14 Low= Force to update flash.

1 1
HDMI_CECIN R171 47K_0402_5% XOUT/P4_7 P1_3/KI3#/AN11/TZOUT R166 R164
+3VL 4.7K_0402_5% 4.7K_0402_5% Q47

2
R581 5 15 CEC@ CEC@ CEC@ BSH111_SOT23-3
D VSS/AVSS P1_2/KI2#/AN10/CMP0_2 D

G
27K_0402_5% 1 2 CEC@

2
1
D CEC@ C848 1U_0402_6.3V4Z
Q49 2 2 CEC@ 1CEC_XIN 6 16 1 2 HDMI_CLK 3 1 HDMI_SCLK

2
XIN/P4_6 P4_2/VREF

2
2N7002_SOT23-3 G HDMI_CEC R174 47K_0402_5% C263 0.1U_0402_16V4Z

D
CEC@ S CEC@
3

7 17 HDMI_CLK
VCC/AVCC P1_1/KI1#/AN9/CMP0_1 HDMI_DATA HDMI_SDATA
3 1

1
D

D
HDMI_CECOUT 1 R163 2 2 Q50 2 CEC@ 1 8 18 HDMI_DATA Q48
27K_0402_5% 2N7002_SOT23-3 R176 4.7K_0402_5% MODE P1_0/KI0#/AN8/CMP0_0 BSH111_SOT23-3
G
CEC@ S CEC@ C262 1 CEC@
3
1

0.1U_0402_16V4Z HDMI_CECIN 9 19 HDMI_HPD_R

R165 CEC@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
100K_0402_5%
CEC@ 2 HDMI_CECOUT 10 20 EC_SMB_DA1 <44,49>
P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1
2

R5F211A4C33SP-W4_LSSOP20 CEC@

+3VS +3VS_DGPU
+HDMI_5V_OUT
+5VL HDMI@
R145

2
HDMI_HPD_U 1 2 HDMI_HPD_C
R453 R452 2 1K_0402_5%
0_0402_5% 0_0402_5% C264 2

2
0.1U_0402_16V4Z R186 C265
For DISCRETE IHDMI@ DHDMI@

1
HDMI@ U9 100K_0402_5% 0.1U_0402_16V4Z

1
C 1 C
IHDMI@ HDMI@ HDMI@

OE#
1

1
HDMI_HPD_R 1
<31> UMA_HDMI_CLK 2 1 2 4
CV296 A Y
<14> VGA_HDMI_CLK+ 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXC+ R435 0_0402_5% R184 R185

1
G
2.2K_0402_5% 2.2K_0402_5% 74AHCT1G125GW_SOT353-5
CV293 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXC- DHDMI@ HDMI@ HDMI@ HDMI@
<14> VGA_HDMI_CLK-

3
2
<14> VGA_HDMI_CLK 2 1

2
G
CV294 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD0+ R391 0_0402_5%
<14> VGA_HDMI_TX0+
CV297 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD0- 3 1 HDMI_SCLK
<14> VGA_HDMI_TX0-

2
G

D
CV299 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD1+ Q18
<14> VGA_HDMI_TX1+
DHDMI@ BSH111_SOT23-3
CV298 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD1- <14> VGA_HDMI_DATA 2 1 3 1 HDMI@ HDMI_SDATA HDMI@ HDMI@
<14> VGA_HDMI_TX1-
R401 0_0402_5% +3VL 2 1 2 1 +3VS

D
CV295 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD2+ R570 R571
<14> VGA_HDMI_TX2+
IHDMI@ Q19 100K_0402_5% 2.2K_0402_5%
CV300 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD2- 2 1 BSH111_SOT23-3 D55
<14> VGA_HDMI_TX2- <31> UMA_HDMI_DATA
R438 0_0402_5% HDMI@ HDMI_HPD_R 1 2 HDMI_HPD <13,31,33>
CH751H-40PT_SOD323-2
HDMI@

VGA_DVI_TXC- 1 @ 2 HDMI_R_CK- HDMI_R_CK+ 1 DHDMI@2

R157 0_0402_5% R195 499_0402_1%
L8 HDMI@ HDMI_R_CK- 1 DHDMI@2
R197 499_0402_1% HDMI@
For Optimus 1
1 2
2
HDMI_R_D1- 1 DHDMI@2 D53 F2
R198 499_0402_1% +5VS 2 1 +HDMI_5V_OUT_F 2 1 +HDMI_5V_OUT
4 3 HDMI_R_D1+ 1 DHDMI@2 1.1A_6V_MINISMDC110F-21
CV308 4 3
<31> UMA_HDMI_TXC+ 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXC+ R202 499_0402_1% PMEG2010AEH_SOD123 HDMI@ C259
OCE2012120YZF HDMI_R_D0+ 1 DHDMI@2 HDMI@
CV304 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXC- VGA_DVI_TXC+ 1 @ 2 HDMI_R_CK+ R201 499_0402_1% D54 0.1U_0402_16V4Z
<31> UMA_HDMI_TXC- 2
B R173 0_0402_5% HDMI_R_D0- 1 DHDMI@2 +5VL 2 1 B
CV306 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD0+ R203 499_0402_1%
<31> UMA_HDMI_TX0+
HDMI_R_D2- 1 DHDMI@2 PMEG2010AEH_SOD123
CV302 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD0- VGA_DVI_TXD0+ 1 @ 2 HDMI_R_D0+ R205 499_0402_1% CEC@
<31> UMA_HDMI_TX0-
R175 0_0402_5% HDMI_R_D2+ 1 DHDMI@2
CV303 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD1+ L9 HDMI@ R206 499_0402_1%
<31> UMA_HDMI_TX1+

1
D
1 2
CV301 1 2
<31> UMA_HDMI_TX1- 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD1- +5VS 2 Q24
G 2N7002_SOT23-3
CV307 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD2+ 4 3 S HDMI@
<31> UMA_HDMI_TX2+

3
4 3 @
1 2
CV305 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD2- OCE2012120YZF R207 100K_0402_5%
<31> UMA_HDMI_TX2-
VGA_DVI_TXD0- 1 @ 2 HDMI_R_D0-
R180 0_0402_5%
HDMI Connector
VGA_DVI_TXD1- 1 @ 2 HDMI_R_D1- JHDMI @
R182 0_0402_5% HDMI_HPD_C 19
L10 HDMI@ HP_DET
+HDMI_5V_OUT 18
+5V
1 2 17
1 2 R195 R197 HDMI_SDATA DDC/CEC_GND
16
680_0402_5% 680_0402_5% HDMI_SCLK SDA
15
IHDMI@ IHDMI@ SCL
4 3 14
4 3 HDMI_CEC Reserved
13
OCE2012120YZF R198 R202 HDMI_R_CK- CEC
12 20
VGA_DVI_TXD1+ @ HDMI_R_D1+ 680_0402_5% 680_0402_5% CK- GND
1 2 11 21
R183 0_0402_5% IHDMI@ IHDMI@ HDMI_R_CK+ CK_shield GND
10 22
HDMI_R_D0- CK+ GND
9 23
R201 R203 D0- GND
8
VGA_DVI_TXD2+ @ HDMI_R_D2+ 680_0402_5% 680_0402_5% HDMI_R_D0+ D0_shield
1 2 7
R187 0_0402_5% IHDMI@ IHDMI@ HDMI_R_D1- D0+
6
L11 HDMI@ D1-
5
R205 R206 HDMI_R_D1+ D1_shield
1 2 4
A 1 2 680_0402_5% 680_0402_5% HDMI_R_D2- D1+ A
3
IHDMI@ IHDMI@ D2-
2
HDMI_R_D2+ D2_shield
4 3 1
4 3 D2+
07/10/2010
OCE2012120YZF TYCO_1939864-1_19P
VGA_DVI_TXD2- 1 @ 2 HDMI_R_D2-
Intel DG P.132
R188 0_0402_5%

www.vinafix.vn
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn./CEC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 27 of 58
5 4 3 2 1
 5 4 3 2 1

U2A
CMOS Setting, near DDR Door JCOMS @ PCH_RTCX1 LPC_AD0
2 1 A20 C38 LPC_AD0 <44,45>
R292 1 PCH_RTCRST# C216 15P_0402_50V8J RTCX1 FWH0 / LAD0 LPC_AD1
+RTCVCC 2 1 2 A38

LPC
FWH1 / LAD1 LPC_AD1 <44,45>
20K_0402_5% Y3 PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 <44,45>

1
10M_0402_5%
C247 1 2 2 1 C37 LPC_AD3
NC OSC FWH3 / LAD3 LPC_AD3 <44,45>
1U_0402_6.3V4Z PCH_RTCRST# D20
RTCRST#

R291
3 4 D36 LPC_FRAME#
NC OSC FWH4 / LFRAME# LPC_FRAME# <44,45>
PCH_SRTCRST# G22
32.768KHZ_12.5PF_Q13MC14610002 SRTCRST# +3VS
iME Setting. E36

RTC
2
JME @ SM_INTRUDER# LDRQ0# FELICA_PWR
2 1 K22 K36 FELICA_PWR <38>
R293 1 INTRUDER# LDRQ1# / GPIO23
2PCH_SRTCRST# 1 2 C205 15P_0402_50V8J
20K_0402_5% PCH_INTVRMEN C17 V5 SERIRQ SERIRQ 2 1
INTVRMEN SERIRQ SERIRQ <44,45>
C248 1 2 R136 10K_0402_5%
1U_0402_6.3V4Z
AM3 SATA_PRX_C_DTX_N0
SATA0RXN SATA_PRX_C_DTX_N0 <37>
D R286 1 2 33_0402_5% AZ_BITCLK N34 AM1 SATA_PRX_C_DTX_P0 D
<43> AZ_BITCLK_HD HDA_BCLK SATA0RXP SATA_PRX_C_DTX_P0 <37>

SATA 6G
SATA_PTX_DRX_N0 +3VS
Integrated SUS 1.05V VRM Enable AZ_SYNC L34
SATA0TXN
AP7
AP5 SATA_PTX_DRX_P0
SATA_PTX_DRX_N0 <37> HDD
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 <37>

High - Enable Internal VRs <43> PCH_SPKR

PCH_SPKR T10
SPKR SATA1RXN
AM10
PCH_INTVRMEN (must be always pulled high) AM8 SATA_LED# R336 2 1 10K_0402_5%
R142 1 SATA1RXP
<43> AZ_RST_HD# 2 33_0402_5% AZ_RST# K34 AP11
HDA_RST# SATA1TXN
AP10
SATA1TXP CR_WAKE# R334 2 1 10K_0402_5%
+RTCVCC AZ_SDIN0_HD E34 AD7 SATA_PRX_C_DTX_N2
<43> AZ_SDIN0_HD HDA_SDIN0 SATA2RXN SATA_PRX_C_DTX_N2 <37>
AD5 SATA_PRX_C_DTX_P2
SATA2RXP SATA_PRX_C_DTX_P2 <37>
R117 1 SM_INTRUDER# SATA_PTX_DRX_N2 PCH_GPIO19 R335 1 2 10K_0402_5%
2
1M_0402_5%
G34
HDA_SDIN1 SATA2TXN
AH5
AH4 SATA_PTX_DRX_P2
SATA_PTX_DRX_N2 <37> ODD
SATA2TXP SATA_PTX_DRX_P2 <37>
R118 1 2 PCH_INTVRMEN C34

IHDA
330K_0402_5% HDA_SDIN2
AB8
+3VS @ SATA3RXN
+3VALW_PCH 2 1 A34 AB10
@ R273 1K_0402_5% HDA_SDIN3 SATA3RXP
AF3
PCH_SPKR SATA3TXN
1 2 AF1 +RTCBATT
R276 1K_0402_5% R289 1 SATA3TXP
<43> AZ_SDOUT_HD 2 33_0402_5% AZ_SDOUT A36

SATA
HDA_SDO

1
High = Enabled (No Reboot) SATA4RXN
Y7
* Low = Disabled (Default)
<44> PWRME_CTRL#
PWRME_CTRL# C36
HDA_DOCK_EN# / GPIO33
SATA4RXP
SATA4TXN
Y5
AD3 D13
AD1 +RTCVCC BAS40-04_SOT23-3
+3VALW_PCH CR_CPPE# SATA4TXP
<41> CR_CPPE# N32
HDA_DOCK_RST# / GPIO13
Y3

2
CR_CPPE# SATA5RXN
1
R560
2
10K_0402_5% HDA_SDO SATA5RXP
Y1
AB3 1
+3VL
PWRME_CTRL# PCH_JTAG_TCK SATA5TXN C486
1 2 ME debug mode, J3
JTAG_TCK SATA5TXP
AB1
R274 @ 1K_0402_5%
this signal has a weak internal pull down T37 PAD PCH_JTAG_TMS H7 Y11 0.1U_0402_16V4Z

JTAG
JTAG_TMS SATAICOMPO 2
*Low = Disable (default)
High = Enable (flash descriptor security overide) T38 PAD PCH_JTAG_TDI K5
JTAG_TDI SATAICOMPI
Y10 SATAICOMP 1 2 +1.05VS_VCC_SATA
R279 37.4_0402_1%
T39 PAD PCH_JTAG_TDO H1
JTAG_TDO
AB12
C SATA3RCOMPO C

SATA3_COMP
HDA_SYNC SATA3COMPI
AB13 1
R280
2
49.9_0402_1%
+1.05VS_SATA3

*This signal has a weak internal pull

H=>On Die PLL is supplied by 1.5V
down
PCH_SPICLK T3
SPI_CLK SATA3RBIAS
AH1 RBIAS_SATA3 1 2
R281 750_0402_1%
L=>On Die PLL is supplied by 1.8V PCH_SPICS# Y14
SPI_CS0#
Need to pull high for Huron River platform T1

SPI
AZ_SYNC +3V_SPI SPI_CS1# SATA_LED#
+3VALW_PCH 2 1 P3 SATA_LED# <46>
R284 1K_0402_5% SATALED#
PCH_SPIDI CR_WAKE#
+5VS 8M Byte V4
SPI_MOSI SATA0GP / GPIO21
V14 CR_WAKE# <41>

1 PCH_SPIDO U3 P1 PCH_GPIO19
SPI_MISO SATA1GP / GPIO19 PCH_GPIO19 <32>
2
G

U13
Q21 C494 BOOT BIOS Strap Bit 0
1 2 AZ_SYNC_R 3 1 0.1U_0402_16V4Z
8
VCC VSS
4 for EMI COUGARPOINT_FCBGA989~D Q65R1@
<43> AZ_SYNC_HD 2
R156 33_0402_5%
S

3
W CLK
BSS138_NL_SOT23-3 7
HOLD

1
1 @ 2
R285 0_0402_5% CS# 1 R397
S
10_0402_5%
CLK 6 @
C

2
DI 5 2 DO 1
D Q C86
PCH_SPIDI R572 1 2 @ 0_0402_5% DI W25Q64BVSSIG_SO8 10P_0402_50V8J
PCH_SPICLK R573 1 2 @ 0_0402_5% CLK 45@ @
PCH_SPICS# R574 @ 0_0402_5% CS# 2
PCH_SPIDO R575
1
1
2
2 @ 0_0402_5% DO Socket: SP07000F500/SP07000H900
R569 2 1 @ 0_0603_5%
+3VS +3V_SPI Please close to U2 PCH
B +5VALW B

For MP phase +5VALW

C249
2 1 2 R418
SPI@ SPI@
8

U51 0.1U_0402_16V4Z 10K_0402_5%

1 3
P

<44,45> KSO6
1

1OE# +
4 1
2OE# O
1

10 EC_ON 2 1
3OE# -
G

13 R217 SPI@ C483 +3VALW

4OE# SPI@ LM393DG_SO8 SPI@
4

PCH_SPIDI 2 3 DI 100K_0402_5% U56A 0.1U_0402_16V4Z

PCH_SPICLK 1A 1B CLK 2
5 6
2

PCH_SPICS# 2A 2B CS#
9 8 D43
PCH_SPIDO 3A 3B DO
12 11
4A 4B

1
D
3
14 7 +5VALW 1 2 Q37
+3VS VCC GND
1 2 G SPI@
C455 SN74CBT3125PWRG4_TSSOP14 +5VALW S AO3416_SOT23-3

3
2

1
SPI@ SPI@ SPI@ RB715FGT106_UMD3
0.1U_0402_16V4Z R432 R226 +3VALW_PCH +3VALW_PCH +3VALW_PCH
2 SPI@ SPI@
8

U56B 10K_0402_5% 100K_0402_5%

2
5
P

<39,44,47,52,54,56> SUSP# +3V_SPI

1

2
+ R278
7 R363 R330
O 200_0402_5%
6 200_0402_5% 200_0402_5%
-
G

U53 SPI@ 1
EC_ON 1 LM393DG_SO8 C482
<44,46,51> EC_ON
4

1
1OE# SPI@ PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI
4
2OE# 0.1U_0402_16V4Z
10
3OE#

2
2
13
4OE# R301
R306 R295
2 3 DI 100_0402_1% 100_0402_1% 100_0402_1%
<44,45,46> KSI6 1A 1B
SPIDI 5 6 CLK
A <44,45> KSI5 2A 2B A
SPICLK 9 8 CS#
<44,45> KSI4

1
SPICS# 3A 3B DO
<44,45> KSI7 12 11
SPIDO 4A 4B

+3V_SPI 14 7
VCC GND PCH_JTAG_TCK
1 1 2
C456 SN74CBT3125PWRG4_TSSOP14 R355 51_0402_1%
SPI@ SPI@

www.vinafix.vn
0.1U_0402_16V4Z
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Please close to U2 PCH,and between U2 & U13 Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_HDA/JTAG/SATA/SPI/LPC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 28 of 58
5 4 3 2 1
 5 4 3 2 1

U2B +3VALW_PCH 2 R232 1 2.2K_0402_5% +3VS

PCIE_PRX_C_LANTX_N1 BG34 2 R260 1 2.2K_0402_5% R400 4.7K_0402_5%
<40> PCIE_PRX_C_LANTX_N1 PERN1

5
PCIE_PRX_C_LANTX_P1 BJ34 E12 EC_LID_OUT# Q3B R386 4.7K_0402_5%
<40> PCIE_PRX_C_LANTX_P1 PERP1 SMBALERT# / GPIO11 EC_LID_OUT# <44>
LAN <40> PCIE_PTX_C_LANRX_N1 C498 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_N1 AV32
C497 2 PCIE_PTX_LANRX_P1 PETN1 PCH_SMBCLK PCH_SMBDATA
<40> PCIE_PTX_C_LANRX_P1 1 0.1U_0402_16V7K AU32 PETP1 SMBCLK H14 3 4 PM_SMBDATA <11,12,39>

2
PCIE_PRX_WLANTX_N2 BE34 C9 PCH_SMBDATA Q3A 2N7002DW-T/R7_SOT363-6
<39> PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PERN2 SMBDATA
<39> PCIE_PRX_WLANTX_P2 BF34 PERP2
WLAN <39> PCIE_PTX_C_WLANRX_N2 C501 2 1 0.1U_0402_16V7K PCIE_PTX_WLANRX_N2 BB32 PCH_SMBCLK 6 1
PCIE_PTX_WLANRX_P2 PETN2 PM_SMBCLK <11,12,39>
C502 2 1 0.1U_0402_16V7K AY32

SMBUS
<39> PCIE_PTX_C_WLANRX_P2 PETP2
A12 DRAMRST_CNTRL_PCH 2N7002DW-T/R7_SOT363-6
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7>
<39> PCIE_PRX_JETTX_N3 PCIE_PRX_JETTX_N3 BG36
PCIE_PRX_JETTX_P3 PERN3 PCH_SMLCLK0
D <39> PCIE_PRX_JETTX_P3 BJ36 PERP3 SML0CLK C8 D
JET C505 1 2 0.1U_0402_16V7K PCIE_PTX_JETRX_N3 AV34
<39> PCIE_PTX_C_JETRX_N3 PETN3
C503 1 2 0.1U_0402_16V7K PCIE_PTX_JETRX_P3 AU34 G12 PCH_SMLDATA0 +3VALW_PCH 2 R364 1 2.2K_0402_5% +3VS
<39> PCIE_PTX_C_JETRX_P3 PETP3 SML0DATA
PCIE_PRX_C_CRTX_N4 BF36 2 R385 1 2.2K_0402_5%
<41> PCIE_PRX_C_CRTX_N4 PERN4

5
PCIE_PRX_C_CRTX_P4 BE36 Q4B
<41> PCIE_PRX_C_CRTX_P4 PERP4
Card Reader C504 1 2 0.1U_0402_16V7K PCIE_PTX_CRRX_N4 AY34 C13 PCH_GPIO74
<41> PCIE_PTX_C_CRRX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74
C868 1 2 0.1U_0402_16V7K PCIE_PTX_CRRX_P4 BB34 PCH_SMLDATA1 3 4
<41> PCIE_PTX_C_CRRX_P4 PETP4 EC_SMB_DA2 <14,44,45,46>
E14 PCH_SMLCLK1

PCI-E*
SML1CLK / GPIO58

2
PCIE_PRX_NEWTX_N5 BG37 Q4A 2N7002DW-T/R7_SOT363-6
<39> PCIE_PRX_NEWTX_N5 PERN5
NEW@ PCIE_PRX_NEWTX_P5 BH37 M16 PCH_SMLDATA1
<39> PCIE_PRX_NEWTX_P5 PERP5 SML1DATA / GPIO75
NewCard C499 2 1 0.1U_0402_16V7K PCIE_PTX_NEWRX_N5 AY36 PCH_SMLCLK1 6 1
<39> PCIE_PTX_C_NEWRX_N5 PETN5 EC_SMB_CK2 <14,44,45,46>
<39> PCIE_PTX_C_NEWRX_P5 C500 2 1 0.1U_0402_16V7K PCIE_PTX_NEWRX_P5 BB36 PETP5 2N7002DW-T/R7_SOT363-6
NEW@ PCIE_PRX_C_USBTX_N6 BJ38
<42> PCIE_PRX_C_USBTX_N6 PERN6
<42> PCIE_PRX_C_USBTX_P6 PCIE_PRX_C_USBTX_P6 BG38

Controller
C519 1 PCIE_PTX_USBRX_N6 PERP6
USB30 <42> PCIE_PTX_C_USBRX_N6 2 0.1U_0402_16V7K AU36 PETN6 CL_CLK1 M7
C869 1 2 0.1U_0402_16V7K PCIE_PTX_USBRX_P6 AV36
<42> PCIE_PTX_C_USBRX_P6 PETP6
Control Link only for support Intel IAMT.

Link
BG40 PERN7 CL_DATA1 T11
BJ40 PERP7
AY40 +3VALW_PCH
+3VS PETN7
BB40 PETP7 CL_RST1# P10

R287 1 2 10K_0402_5% CLKREQ_JET# BE38 PERN8

EC_LID_OUT# R123 1 2 10K_0402_5%
BC38 PERP8
R338 1 2 10K_0402_5% CLKREQ_WLAN# AW 38 PETN8
DRAMRST_CNTRL_PCH R228 1 2 10K_0402_5%
AY38 PETP8 PCH_GPIO74 R234 1 2 10K_0402_5%
M10 CLK_REQ_VGA# CLK_REQ_VGA# <13>
CLK_LAN# PEG_A_CLKRQ# / GPIO47 PCH_SMLCLK0 R238 1
<40> CLK_LAN# Y40 CLKOUT_PCIE0N 2 10K_0402_5%
C
LAN CLK_LAN Y39 C
<40> CLK_LAN CLKOUT_PCIE0P CLK_PCIE_VGA# PCH_SMLDATA0
AB37 R239 1 2 10K_0402_5%
CLK_PCIE_VGA# <13>

CLOCKS
CLKREQ_LAN# CLKOUT_PEG_A_N CLK_PCIE_VGA
<40> CLKREQ_LAN# J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 CLK_PCIE_VGA <13> VGA

CLK_WLAN# AB49 AV22 CLK_CPU_DMI# +3VALW_PCH

<39> CLK_WLAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <5>
WLAN CLK_WLAN AB47 AU22 CLK_CPU_DMI @
<39> CLK_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <5>
2 1 CLK_REQ_VGA# 2 1
CLKREQ_WLAN# M1 R303 10K_0402_5% R275 10K_0402_5%
<39> CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
AM12 CLK_DPLL#
CLKOUT_DP_N / CLKOUT_BCLK1_N T13 PAD
AM13 CLK_DPLL 120 MHz for eDP
CLKOUT_DP_P / CLKOUT_BCLK1_P T14 PAD
CLK_JET# AA48
<39> CLK_JET# CLKOUT_PCIE2N
JET CLK_JET AA47
<39> CLK_JET CLKOUT_PCIE2P
BF18 PCH_CLK_DMI# PCH_CLK_DMI# R242 1 2 10K_0402_5%
CLKREQ_JET# CLKIN_DMI_N PCH_CLK_DMI PCH_CLK_DMI R243 1
<39> CLKREQ_JET# V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 2 10K_0402_5%

CLKIN_GND1# R244 1 2 10K_0402_5%

CLK_CR# Y37 CLKIN_GND1_N CLKIN_DMI2_N BJ30 CLKIN_GND1# CLKIN_GND1 R245 1 2 10K_0402_5%
<41> CLK_CR# CLKOUT_PCIE3N
Card Reader CLK_CR Y36 CLKIN_GND1_P CLKIN_DMI2_P BG30 CLKIN_GND1
<41> CLK_CR CLKOUT_PCIE3P CLK_DOT# R246 1 2 10K_0402_5%
CLKREQ_CR# A8 CLK_DOT R247 1 2 10K_0402_5%
PCIECLKRQ3# / GPIO25 CLK_DOT#
G24
CLKIN_DOT_96N
E24 CLK_DOT From Clock Gen. CLK_SATA# R248 1 2 10K_0402_5%
CLK_NEW# CLKIN_DOT_96P CLK_SATA R249 1
<39> CLK_NEW# Y43 CLKOUT_PCIE4N 2 10K_0402_5%
NewCard CLK_NEW Y45
<39> CLK_NEW CLKOUT_PCIE4P
AK7 CLK_SATA# CLK_14M_PCH R250 1 2 10K_0402_5%
CLKREQ_NEW# CLKIN_SATA_N / CKSSCD_N CLK_SATA
<39> CLKREQ_NEW# L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P AK5

CLK_USB30# V45 K45 CLK_14M_PCH

<42> CLK_USB30# CLKOUT_PCIE5N REFCLK14IN
USB30 CLK_USB30 V46
B <42> CLK_USB30 CLKOUT_PCIE5P B
+3VALW_PCH CLKREQ_USB30# L14 H45 CLK_PCILOOP
For EMI
<42> CLKREQ_USB30# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCILOOP <32>
@
R343 1 210K_0402_5% CLKREQ_LAN# AB42 V47 PCH_X1 CLK_PCILOOP 2 @ 1 2 1
CLKOUT_PEG_B_N XTAL25_IN PCH_X2 R417 10_0402_5% C474 22P_0402_50V8J
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49
R344 1 210K_0402_5% CLKREQ_NEW#
PCH_GPIO56 E6
R345 1 CLKREQ_CR# PEG_B_CLKRQ# / GPIO56
210K_0402_5%
Y47 XCLK_RCOMP 1 2
XCLK_RCOMP +1.05VS_VCCDIFFCLKN
R346 1 210K_0402_5% CLKREQ_USB30# V40 CLKOUT_PCIE6N
R354 90.9_0402_1%
V42 CLKOUT_PCIE6P
R348 1 210K_0402_5% PCH_GPIO46
LVDS_SEL T13
R351 1 PCH_GPIO56 PCIECLKRQ6# / GPIO45
210K_0402_5%
V38 K43 CLK_FLEX0
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 T29 PAD
V37
FLEX CLOCKS

R233 @ CLKOUT_PCIE7P PCH_48MCLK 1 @ R576 2

<10> CLK_RES_ITP# 2 1 0_0402_5% CLKOUTFLEX1 / GPIO65 F47 48MCLK_USB30 <42>
R282 2 @ 1 0_0402_5% PCH_GPIO46 K12 22_0402_5% R365 2 1 1M_0402_5%
<10> CLK_RES_ITP PCIECLKRQ7# / GPIO46
H47 CLK_FLEX2
CLKOUTFLEX2 / GPIO66 T31 PAD
R352 2 1 0_0402_5% CLK_BCLK_ITP# AK14 Y2
<5> CLK_CPU_ITP# CLKOUT_BCLK0_N / CLKOUT_PCIE8N
R353 2 1 0_0402_5% CLK_BCLK_ITP AK13 K49 CLK_FLEX3 T33 PAD PCH_X1 1 2 PCH_X2
<5> CLK_CPU_ITP CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67
1 25MHZ_20PF_7A25000012 1
COUGARPOINT_FCBGA989~D Q65R1@ C506 C507

27P_0402_50V8J 27P_0402_50V8J
2 2

+3VALW_PCH LVDS_SEL
A A

R347 1 2 10K_0402_5% LVDS_SEL LVDS_SEL H L

@ Single
R564 1 2 10K_0402_5% Channel (Default) Dual
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title
PCH_PCI-E/SMBUS/CLK

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 29 of 58
5 4 3 2 1
 5 4 3 2 1

U2C

<6> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
<6> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <6>
<6> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <6>
<6> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
+3VALW_PCH DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <6>
BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 <6>
D <6> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 D
DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <6>
<6> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <6>
2 1 DRAMPWROK <6> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <6>
R316 200_0402_5% <6> DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20
PCH_SUSPWRDN_R DMI3RXP FDI_CTX_PRX_P0
2 1 BG14 FDI_CTX_PRX_P0 <6>
R218 10K_0402_5% DMI_PTX_CRX_N0 FDI_RXP0 FDI_CTX_PRX_P1
<6> DMI_PTX_CRX_N0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_CTX_PRX_P1 <6>
2 1 RI# DMI_PTX_CRX_N1 AW20 BF14 FDI_CTX_PRX_P2
<6> DMI_PTX_CRX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <6>
R220 10K_0402_5% DMI_PTX_CRX_N2 BB18 BG13 FDI_CTX_PRX_P3
<6> DMI_PTX_CRX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <6>
2 1 PCH_LOW_BAT# DMI_PTX_CRX_N3 AV18 BE12 FDI_CTX_PRX_P4

DMI
FDI
<6> DMI_PTX_CRX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <6>
R221 10K_0402_5% BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <6>
DMI_PTX_CRX_P0 AY24 BJ10 FDI_CTX_PRX_P6
<6> DMI_PTX_CRX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <6>
DMI_PTX_CRX_P1 AY20 BH9 FDI_CTX_PRX_P7
<6> DMI_PTX_CRX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6>
DMI_PTX_CRX_P2 AY18
<6> DMI_PTX_CRX_P2 DMI2TXP
DMI_PTX_CRX_P3 AU18
<6> DMI_PTX_CRX_P3 DMI3TXP
2 1 PCH_RSMRST# AW16 FDI_INT
FDI_INT FDI_INT <6>
R127 10K_0402_5% PCH_DPWROK 1 2 PCH_RSMRST#
2 1 PM_PWROK +1.05VS_PCH 1 2 DMI_COMP BJ24 AV12 FDI_FSYNC0 R222 0_0402_5%
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6>
R128 10K_0402_5% R130 49.9_0402_1%
2 1 SYS_PWROK BG25 BC10 FDI_FSYNC1 Stuff R222 if do not support DeepSX state
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <6>
R129 10K_0402_5%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <6>
R160 750_0402_1%
BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 <6>

A18 DSWVREN +RTCVCC

DSWVRMEN

System Power Management

C +3VS PAD T34 SUSACK# C12 E22 PCH_DPWROK DSWVREN R224 2 1 330K_0402_5% C
0.1U_0402_16V4Z SUSACK# DPWROK
1 2 R225 2 @ 1 330K_0402_5%
C250 <5> XDP_DBRESET# XDP_DBRESET# K3 B9 EC_SWI#
SYS_RESET# WAKE# EC_SWI# <39,40,42>
5

U12
1
P

<5,44,55> VGATE IN1

4 SYS_PWROK P12 N3 PM_CLKRUN# DSWVREN must be always pulled high to +RTCVCC
PM_PWROK O SYS_PWROK CLKRUN# / GPIO32
<5,44> PM_PWROK 2 IN2
G

DSWVREN - Internal Deep Sleep 1.05V regulator

SN74AHC1G08DCKR_SC70-5 PM_PWROK PM_PWROK_R SUS_STAT# T17 PAD
1 2 L22 G8
* H Enable
3

R216 0_0402_5% PWROK SUS_STAT# / GPIO61

32.768 KHz L Disable
L10 N14 SUSCLK 1 @ 2
APWROK SUSCLK / GPIO62 CLK_EC <44>
R566 0_0402_5%

DRAMPWROK B13 D10 PM_SLP_S5#

<5> DRAMPWROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <44>
SUSACK# 2 @ 1 PCH_SUSPWRDN_R +3VS
R137 0_0402_5% PCH_RSMRST# C21 H4 PM_SLP_S4#
<44> PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <44>
PM_CLKRUN# R313 1 2 8.2K_0402_5%
Stuff R137 if EC does not want to <44> PCH_SUSPWRDN 1 2 PCH_SUSPWRDN_R K16 SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# F4 PM_SLP_S3#
PM_SLP_S3# <44>
R320 0_0402_5%
involve in the handshake mechanism
for the DeepSX state entry and exit <5,44> PBTN_OUT# PBTN_OUT# E20 PWRBTN# SLP_A# G10 PM_SLP_A# T35 PAD

1 2 PCH_ACIN H20 G16 PM_SLP_SUS# T58 PAD +3VALW_PCH

+3VALW_PCH ACPRESENT / GPIO31 SLP_SUS#
R469 330K_0402_5%
B B
D12 PCH_LOW_BAT# E10 AP14 H_PM_SYNC EC_SWI# R319 1 2 10K_0402_5%
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <5>
1 2
<44,46,50> ACIN
CH751H-40PT_SOD323-2 RI# A10 K14 PCH_GPIO29 PCH_GPIO29 R563 1 @ 2 10K_0402_5%
RI# SLP_LAN# / GPIO29

COUGARPOINT_FCBGA989~D Q65R1@

D16
PM_PWROK 2 1 PCH_RSMRST#

CH751H-40PT_SOD323-2

D14
<49,51> POK 1 2

CH751H-40PT_SOD323-2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_DMI/FDI/PM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
PHQAA LA-6831P M/B

www.vinafix.vn
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, August 02, 2010 Sheet 30 of 58
5 4 3 2 1
 5 4 3 2 1

U2D
UMA_ENBKL J47 AP43
<25> UMA_ENBKL L_BKLTEN SDVO_TVCLKINN +3VS
UMA_ENVDD M45 AP45
<25> UMA_ENVDD L_VDD_EN SDVO_TVCLKINP
PCH_PW M P45 AM42
<25> PCH_PW M L_BKLTCTL SDVO_STALLN
SDVO_STALLP AM40

1
<25> LCD_EDID_CLK LCD_EDID_CLK T40
R230 LCD_EDID_DATA L_DDC_CLK R214 R215
<25> LCD_EDID_DATA K47 L_DDC_DATA SDVO_INTN AP39
100K_0402_5% AP40 2.2K_0402_5% 2.2K_0402_5%
UMA@ LCTL_CLK SDVO_INTP IHDMI@ IHDMI@
D T45 L_CTRL_CLK D
LCTL_DATA P39

2
R219 OPT@ L_CTRL_DATA
2.37K_0402_1% 1 2 LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK UMA_HDMI_CLK <27>
OPT@ UMA@ R219 2.37K_0402_1% AF36 M39
LVD_VBG SDVO_CTRLDATA UMA_HDMI_DATA <27>
1 2 UMA_ENBKL T40 PAD
R230 100K_0402_5% AE48 R1432
LVD_VREFH IHDMI@
AE47 LVD_VREFL DDPB_AUXN AT49
AT47 0_0402_5%
DDPB_AUXP HDMI_HPD_UMA HDMI_HPD HDMI_HPD_UMA 2
DDPB_HPD AT40 2 1 HDMI_HPD <13,27,33> 1
LCD_TXCLK- AK39 100K_0402_5%

LVDS
<25> LCD_TXCLK- LVDSA_CLK#
LCD_TXCLK+ AK40 AV42 UMA_HDMI_TX2- R1433
<25> LCD_TXCLK+ LVDSA_CLK DDPB_0N UMA_HDMI_TX2- <27>
AV40 UMA_HDMI_TX2+
+3VS DDPB_0P UMA_HDMI_TX2+ <27>
LCD_TXOUT0- AN48 AV45 UMA_HDMI_TX1-
<25> LCD_TXOUT0- LVDSA_DATA#0 DDPB_1N UMA_HDMI_TX1- <27>
LCD_TXOUT1- UMA_HDMI_TX1+
AM47 AV46
HDMI

Digital Display Interface

<25> LCD_TXOUT1- LVDSA_DATA#1 DDPB_1P UMA_HDMI_TX1+ <27>
LCD_TXOUT2- AK47 AU48 UMA_HDMI_TX0-
<25> LCD_TXOUT2- LVDSA_DATA#2 DDPB_2N UMA_HDMI_TX0- <27>
2 1 LCTL_CLK AJ48 AU47 UMA_HDMI_TX0+
LVDSA_DATA#3 DDPB_2P UMA_HDMI_TX0+ <27>
R471 2.2K_0402_5% AV47 UMA_HDMI_TXC-
DDPB_3N UMA_HDMI_TXC- <27>
LCD_TXOUT0+ AN47 AV49 UMA_HDMI_TXC+
<25> LCD_TXOUT0+ LVDSA_DATA0 DDPB_3P UMA_HDMI_TXC+ <27>
2 1 LCTL_DATA LCD_TXOUT1+ AM49
<25> LCD_TXOUT1+ LVDSA_DATA1
R472 2.2K_0402_5% LCD_TXOUT2+ AK49
<25> LCD_TXOUT2+ LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
2 1 LCD_EDID_CLK P42
R223 2.2K_0402_5% DDPC_CTRLDATA
AF40 LVDSB_CLK#
2 1 LCD_EDID_DATA AF39 AP47
R229 2.2K_0402_5% LVDSB_CLK DDPC_AUXN
DDPC_AUXP AP49
AH45 AT38 R473 2 1 100K_0402_5%
UMA_CRT_CLK LVDSB_DATA#0 DDPC_HPD
2 1 AH47 LVDSB_DATA#1
C R237 2.2K_0402_5% AF49 AY47 C
LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 DDPC_0P AY49
2 1 UMA_CRT_DATA AY43
R231 2.2K_0402_5% DDPC_1N
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49

OPT@ UMA_CRT_B N48 M43

<26> UMA_CRT_B CRT_BLUE DDPD_CTRLCLK
1 2 UMA_CRT_B UMA_CRT_G P49 M36
<26> UMA_CRT_G CRT_GREEN DDPD_CTRLDATA
R240 150_0402_1% UMA_CRT_R T49
<26> UMA_CRT_R CRT_RED
OPT@
1 2 UMA_CRT_G AT45

CRT
R241 150_0402_1% UMA_CRT_CLK DDPD_AUXN
<26> UMA_CRT_CLK T39 CRT_DDC_CLK DDPD_AUXP AT43
OPT@ <26> UMA_CRT_DATA UMA_CRT_DATA M40 BH41 R524 2 1 100K_0402_5%
UMA_CRT_R CRT_DDC_DATA DDPD_HPD
1 2
R318 150_0402_1% BB43
UMA_CRT_HSYNC DDPD_0N
<26> UMA_CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
UMA_CRT_VSYNC M49 BF44
<26> UMA_CRT_VSYNC CRT_VSYNC DDPD_1N
DDPD_1P BE44
OPT@ BF42
CRT_IREF DDPD_2N
2 1 T43 DAC_IREF DDPD_2P BE42
R240 R311 1K_0402_0.5% T42 BJ42
150_0402_1% CRT_IRTN DDPD_3N
DDPD_3P BG42
UMA@
COUGARPOINT_FCBGA989~D Q65R1@
R241
B 150_0402_1% B
UMA@ R311
1K_0402_5%
R318 DIS@
150_0402_1%
UMA@ R311
1K_0402_0.5%
UMA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_CRT/LVDS/HDMI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 31 of 58
5 4 3 2 1
 5 4 3 2 1

PLT_RST#

U2E
NV_CE#0 AY7

1
NV_CE#1 AV7
BG26 AU3 R533 +3VS
TP1 NV_CE#2 OPT@
BJ26 TP2 NV_CE#3 BG4 0_0402_5%
BH25 TP3 OPT@ 1 2
BJ16 AT10 C508 0.1U_0402_16V4Z

2
TP4 NV_DQS0

5
BG16 BC8 @ U20
TP5 NV_DQS1 OPT@
AH38 2 1 1

P
D TP6 <13,33,47,56> VGA_PW ROK IN1 D
AH37 AU2 R531 0_0402_5%
TP7 NV_DQ0 / NV_IO0 DGPU_RST# O 4 R5282 1
0_0402_5%
PLTRST_VGA# <13>
AK43 TP8 NV_DQ1 / NV_IO1 AT4 2 IN2

G
AK45 TP9 NV_DQ2 / NV_IO2 AT3

1
C18 AT1 SN74AHC1G08DCKR_SC70-5

3
TP10 NV_DQ3 / NV_IO3

2
N30 AY3 OPT@
TP11 NV_DQ4 / NV_IO4 R532 R530
H3 TP12 NV_DQ5 / NV_IO5 AT5
AH12 AV3 1K_0402_5% 100K_0402_5%
TP13 NV_DQ6 / NV_IO6

NVRAM
AM4 AV1 OPT@ OPT@

2
TP14 NV_DQ7 / NV_IO7
AM5 BB1

1
+3VS TP15 NV_DQ8 / NV_IO8
Y13 TP16 NV_DQ9 / NV_IO9 BA3
K24 TP17 NV_DQ10 / NV_IO10 BB5
RP1 L24 BB3
PCH_GPIO4 TP18 NV_DQ11 / NV_IO11
8 1 AB46 TP19 NV_DQ12 / NV_IO12 BB7
7 2 PCI_PIRQC# AB45 BE8 DIS@

RSVD
PCI_PIRQA# TP20 NV_DQ13 / NV_IO13 PLT_RST# PLTRST_VGA#
6 3 NV_DQ14 / NV_IO14 BD4 2 1
5 4 PCH_GPIO2 BF6 R529 0_0402_5%
NV_DQ15 / NV_IO15

2
8.2K_0804_8P4R_5% B21 AV5
TP21 NV_ALE NV_CLE R534
M20 TP22 AY1
RP2 AY16 TP23
DF_TVS NV_CLE 100K_0402_5%
8 1 PCH_GPIO52 BG46 AV10
PCH_GPIO53 TP24 NV_RCOMP
7 2

1
6 3 NV_RB# AT8
5 4 RF_OFF#
BE28 TP25 NV_RE#_WRB0 AY5
8.2K_0804_8P4R_5% BC30 BA2
TP26 NV_RE#_WRB1
BE32 TP27
RP3
8 1
BJ32
BC28
TP28
TP29
NV_WE#_CK0
NV_WE#_CK1
AT12
BF3 For Optimus
7 2 PCI_PIRQB# BE30
ODD_DA# TP30
6 3 BF32 TP31
C W L_OFF# USB20_N0 C
5 4 BG32 TP32 USBP0N C24 USB20_N0 <37>
AV26 A24 USB20_P0 USB-RIGHT1
TP33 USBP0P USB20_P0 <37>
8.2K_0804_8P4R_5% BB26 C25 USB20_N1
TP34 USBP1N USB20_N1 <37>
AU28 B25 USB20_P1 USB-RIGHT2
TP35 USBP1P USB20_P1 <37>
1 2 PCH_GPIO5 AY30 C26 USB20_N2
TP36 USBP2N USB20_N2 <37>
R321 8.2K_0402_5% AU26 A26 USB20_P2 USB-Left1
TP37 USBP2P USB20_P2 <37>
1 2 PCI_PIRQD# R578 AY26 K28 USB20_N3
TP38 USBP3N USB20_N3 <42>
R322 8.2K_0402_5% 10K_0402_5% AV28 H28 USB20_P3 USB-Left2
TP39 USBP3P USB20_P3 <42>
1 DIS@ 2 DGPU_RST# UMA@ AW30 EHCI 1 E28 USB20_N4 DMI & FDI Termination Voltage
TP40 USBP4N USB20_N4 <39>
R578 10K_0402_5% D28 USB20_P4 NewCard
USBP4P USB20_P4 <39>
1 DIS@ 2 DGPU_PW R_EN C28 USB20_N5
USBP5N USB20_N5 <38>
R544 10K_0402_5% R544 A28 USB20_P5 IR Emitter Set to VCC when HIGH
USBP5P USB20_P5 <38>
10K_0402_5% C29 NV_CLE
DGPU_PW R_EN USBP6N
1 OPT@ 2 UMA@ Set to VSS when LOW
R399 1K_0402_5% PCI_PIRQA# K40
USBP6P B29
N28
USB port6 and port7 are disabled on HM65
PCI_PIRQB# PIRQA# USBP7N
K38 M28

PCI
PCI_PIRQC# PIRQB# USBP7P USB20_N8
H38 PIRQC# USBP8N L30 USB20_N8 <38>
PCI_PIRQD# USB20_P8 +1.8VS
G38 PIRQD# USBP8P K30
USB20_N9
USB20_P8 <38> Finger Printer
USBP9N G30 USB20_N9 <39>
DGPU_RST# C46 E30 USB20_P9 WiMax

USB
REQ1# / GPIO50 USBP9P USB20_P9 <39>

1
PCH_GPIO52 C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 <39>
DGPU_PW R_EN USB20_P10 R324
For Optimus <13,47,56> DGPU_PW R_EN E40 REQ3# / GPIO54 EHCI 2 USBP10P A30
L32 USB20_N11
USB20_P10 <39> TV Tuner #1 1K_0402_5%
USBP11N USB20_N11 <25>
<39> RF_OFF# RF_OFF# D47 K32 USB20_P11 Int. Camera
GNT1# / GPIO51 USBP11P USB20_P11 <25>
PCH_GPIO53 E42 G32 USB20_N12
USB20_N12 <39>

2
W L_OFF# GNT2# / GPIO53 USBP12N USB20_P12 NV_CLE
<39> W L_OFF# F46 GNT3# / GPIO55 USBP12P E32
USB20_N13
USB20_P12 <39> 3G/ TV tuner #2 2
R323
1
1K_0402_5%
H_SNB_IVB# <5>
USBP13N C32 USB20_N13 <38>
A32 USB20_P13 Felica
USBP13P USB20_P13 <38>
PCH_GPIO2 G42
ODD_DA# PIRQE# / GPIO2
<37> ODD_DA# G40 PIRQF# / GPIO3
PCH_GPIO4 C42 C33 USBBIAS 1 2
B PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# R535 22.6_0402_1% B
D44 PIRQH# / GPIO5
Within 500 mils
USBRBIAS B33
T32 PAD PCI_PME# K10 PME#
PLT_RST# C6 A14 USB_OC#0 USB-Right
<5,39,40,41,42,44,45> PLT_RST# PLTRST# OC0# / GPIO59 USB_OC#0 <37,44>
K20 USB_OC#1 USB-Left & eSATA
OC1# / GPIO40 USB_OC#1 <42,44> +3VALW _PCH
B17 USB_OC#2
22_0402_5% 1 CLK_EC_R OC2# / GPIO41 USB_OC#3
<44> CLK_PCI_EC 2 R525 H49 CLKOUT_PCI0 OC3# / GPIO42 C16
22_0402_5% 1 2 R526 CLK_PCH H43 L16 USB_OC#4
<29> CLK_PCILOOP CLKOUT_PCI1 OC4# / GPIO43
22_0402_5% 1 2 R527 CLK_SIO J48 A16 SLP_CHG_M3 RP4
<45> CLK_PCI_DDR CLKOUT_PCI2 OC5# / GPIO9 SLP_CHG_M3 <42>
K42 D14 SLP_CHG_M4 USB_OC#0 4 5
CLKOUT_PCI3 OC6# / GPIO10 SLP_CHG_M4 <42>
H40 C14 EXP_CPPE# SLP_CHG_M3 3 6
CLKOUT_PCI4 OC7# / GPIO14 EXP_CPPE# <39>
SLP_CHG_M4 2 7
USB_OC#4 1 8
COUGARPOINT_FCBGA989~D Q65R1@
10K_0804_8P4R_5%

RP5
USB_OC#1 4 5
USB_OC#2 3 6
Boot BIOS Strap USB_OC#3 2 7
EXP_CPPE# 1 8
RF_OFF# PCH_GPIO19 Boot BIOS Loaction
10K_0804_8P4R_5%
1K_0402_5% @ 1 R537 RF_OFF#
2 0 0 LPC
1K_0402_5% @ 1 R538 PCH_GPIO19
2 PCH_GPIO19 <28> 0 1 Reserved
1 0 PCI
A 1 1 SPI * A

A16 Swap Override Strap

www.vinafix.vn
1K_0402_5% 2 @ 1 R536 W L_OFF#
Low= A16 swap override Enable
Security Classification Compal Secret Data Compal Electronics, Inc.
WL_OFF# 200910/9 2010/01/23
* High= A16 swap override Disable Issued Date Deciphered Date Title
PCH_PCI/USB/NAND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 32 of 58
5 4 3 2 1
 5 4 3 2 1

@
1 R100 2 +3VS
+3VALW _PCH 100K_0402_5% U2F
ODD_EN# 1 2
HDMI_HPD T7 C40 ODD_EN# R106 10K_0402_5%
<13,27,31> HDMI_HPD BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# <47>
2 1 USB30_SMI# GATEA20 1 2
R390 1K_0402_5% PCH_GPIO1 A42 B41 PCH_W L_BT_LED R548 10K_0402_5%
EC_SMI# TACH1 / GPIO1 TACH5 / GPIO69 KB_RST#
1 2 1 2
R558 10K_0402_5% PCH_GPIO6 H36 C41 LOGO_LED R559 10K_0402_5%
TACH2 / GPIO6 TACH6 / GPIO70 LOGO_LED <46>
1 2 PCH_GPIO12 LOGO_LED 1 2
R556 10K_0402_5% <44> EC_SCI# EC_SCI# E38 A40 PCH_GPIO71 PAD T73 R436 10K_0402_5%
PCH_GPIO28 TACH3 / GPIO7 TACH7 / GPIO71 PCH_W L_BT_LED
D 1 2 1 2 D
R557 10K_0402_5% <44> EC_SMI# EC_SMI# C10 R110 10K_0402_5%
PCH_GPIO57 GPIO8
1 2
R549 10K_0402_5% PCH_GPIO12 C4 LAN_PHY_PWR_CTRL / GPIO12
+3VS USB30_SMI# G2 P4 GATEA20
<42> USB30_SMI# GPIO15 A20GATE GATEA20 <44>
<46> W L_BT_LED#
AU16 PCH_PECI_R 1 @ 2 H_PECI <5,44>

CPU/MISC
BT_ON# PCH_GPIO16 PECI R212 0_0402_5%
1 2 U2 SATA4GP / GPIO16

3
R567 10K_0402_5% KB_RST#
1 @ 2 HDMI_HPD
For Optimus RCIN# P5 KB_RST# <44>
Q53B

GPIO
R539 10K_0402_5% VGA_PW ROK D40 AY11 H_PW RGOOD
<13,32,47,56> VGA_PW ROK TACH0 / GPIO17 PROCPWRGD H_PW RGOOD <5>
1 2 PCH_GPIO1 PCH_W L_BT_LED 5
R540 10K_0402_5% PCH_GPIO22 T5 AY10 PCH_THRMTRIP# 1 2
SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP# <5>
1 2 PCH_GPIO22 R416 390_0402_5% 2N7002DW -T/R7_SOT363-6

4
R542 10K_0402_5% E8 T14
GPIO24 / MEM_LED INIT3_3V#
1 UMA@ 2 VGA_PW ROK
R579 10K_0402_5% PCH_GPIO27 E16 GPIO27
1 2 ODD_DETECT# This signal has weak internal
R545 200K_0402_5% PCH_GPIO28 P8
1 2 PCH_GPIO6 GPIO28
AH8
pull-up, can't be pulled low
R546 10K_0402_5% BT_ON# NC_1
<39> BT_ON# K1 STP_PCI# / GPIO34
1 2 PCH_GPIO16 AK11
R577 10K_0402_5% PCH_GPIO35 NC_2
T74 PAD K4 GPIO35
1 2 EC_SCI# AH10
R550 10K_0402_5% ODD_DETECT# NC_3
<37> ODD_DETECT# V8 SATA2GP / GPIO36
1 2 CIR_EN# AK10
R551 100K_0402_5% PCH_GPIO37 NC_4
M5 SATA3GP / GPIO37
1 @ 2 ISDBT_DET P37
C R552 10K_0402_5% OPTIMUS_EN# NC_5 C
N2 SLOAD / GPIO38
1 2 PCH_GPIO49
R553 10K_0402_5% R555 CIR_EN# M3 SDATAOUT0 / GPIO39
1 DIS@ 2 OPTIMUS_EN# 10K_0402_5%
R555 10K_0402_5% UMA@ <39> ISDBT_DET ISDBT_DET V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
PCH_GPIO49 V3 BG48
SATA5GP / GPIO49 VSS_NCTF_16
PCH_GPIO57 D6 BH3
GPIO57 VSS_NCTF_17

VSS_NCTF_18 BH47
2 1 PCH_GPIO37
R547 100K_0402_5% A4 BJ4
PCH_GPIO27 VSS_NCTF_1 VSS_NCTF_19
2 1
R402 10K_0402_5% A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
2 CIR@ 1 CIR_EN#
R405 10K_0402_5% A45 BJ45
ISDBT_DET VSS_NCTF_3 VSS_NCTF_21
1 2

NCTF
R328 47K_0402_5% A46 BJ46
VSS_NCTF_4 VSS_NCTF_22
2 OPT@ 1 OPTIMUS_EN#
R415 10K_0402_5% A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
A6 VSS_NCTF_6 VSS_NCTF_24 BJ6

B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47 VSS_NCTF_8 VSS_NCTF_26 C48

BD1 VSS_NCTF_9 VSS_NCTF_27 D1

B B
GPIO28
BD49 VSS_NCTF_10 VSS_NCTF_28 D49
On-Die PLL Voltage Regulator
* H: Enable BE1 VSS_NCTF_11 VSS_NCTF_29 E1

L: Disable BE49 VSS_NCTF_12 VSS_NCTF_30 E49

BF1 VSS_NCTF_13 VSS_NCTF_31 F1

R325 1 @ 2 1K_0402_5% PCH_GPIO28
BF49 VSS_NCTF_14 VSS_NCTF_32 F49

COUGARPOINT_FCBGA989~D Q65R1@

GPIO8
Integrated Clock Chip Enable (Removed) OPTIMUS_EN#
H: Disable
L: Enable OPTIMUS_EN# H L
*
R326 1 @ 2 1K_0402_5% EC_SMI#
SKU Discrete Optimus
A A
Integrated clock enable functionality
is achieved by soft-strap
The current default is clock enable
Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_CPU/GPIO
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 33 of 58
5 4 3 2 1
 5 4 3 2 1

+1.05VS_VCCP U2G POWER +3VS

PCH Power Rail Table
PJ31 @ 1300mA L12
2 1 1U_0402_6.3V6K +1.05VS_PCH AA23 U48 +VCCA_DAC 0.1U_0402_10V7K 2 1 S0 Iccmax
2 1
AC23
VCCCORE[1] 1mA VCCADAC BLM18PG181SN1D_0603 Voltage Rail Voltage
VCCCORE[2] 1 1 Current (A)

CRT
JUMP_43X118 1 1 1 1 AD21 C512 C288 C286
C274 C269 C275 C289 VCCCORE[3] 0.01U_0402_25V7K 10U_0603_6.3V6M
AD23 VCCCORE[4] VSSADAC U47
D D

VCC CORE
AF21
VCCCORE[5]
V_PROC_IO 1.05 0.001
10U_0603_6.3V6M AF23 2 2
2 2 2 2 VCCCORE[6] +3VS
AG21
VCCCORE[7]
AG23
VCCCORE[8]
R541 V5REF 5 0.001
1U_0402_6.3V6K 1U_0402_6.3V6K AG24 1mA AK36 +VCCA_LVDS 1 OPT@ 2 0_0603_5%
VCCCORE[9] VCCALVDS R541 0_0603_5% UMA@
AG26 VCCCORE[10]
AG27
VCCCORE[11] VSSALVDS
AK37 V5REF_SUS 5 0.001
AG29 R424 1 DIS@ 2 0_0402_5%
VCCCORE[12]
AJ23

LVDS
VCCCORE[13] +1.8VS
AJ26
VCCCORE[14] VCCTX_LVDS[1]
AM37 VCC3_3 3.3 0.266
AJ27 L1 OPT@
VCCCORE[15] +VCCTX_LVDS 0.01U_0402_25V7K
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 1 2
AJ31 VCCCORE[17] 1 0.1UH_MLF1608DR10KT_10%_1608 VCCADAC 3.3 0.001
+1.05VS_PCH 60mA VCCTX_LVDS[3] AP36 C256
This pin can be left as NC if C514 C513 22U_0805_6.3V6M
AP37 0.01U_0402_25V7K OPT@ OPT@ VCCADPLLA 1.05 0.08
On-Die VR is enabled (Default) AN19
VCCTX_LVDS[4] OPT@ 2 C513
+1.05VS_PCH VCCIO[28] 0_0402_5%
@ L22 DIS@ VCCADPLLB 1.05 0.08
1 2 +VCCAPLLEXP BJ22 +3VS
1UH_LB2012T1R0M_20% VCCAPLLEXP
1 V33 VCCCORE 1.05 1.3

HVCMOS
C509 VCC3_3[6]
AN16 VCCIO[15]
10U_0603_6.3V6M 1
@ AN17
VCCIO[16]
C272 VCCDMI 1.05 0.042
2 V34 0.1U_0402_10V7K
VCC3_3[7]
AN21 2 VCCIO 1.05 2.925
VCCIO[17] +VCCAFDI_VRM +1.5VS
AN26 R474
VCCIO[18] 0_0603_5% VCCASW 1.05 1.01
+VCCAFDI_VRM
C
AN27 VCCIO[19] 2925mA VCCVRM[3] AT16 1 2
C
+1.05VS_PCH AP21 +VCCP_VCCDMI R480 +1.05VS_VCCP VCCSPI 3.3 0.02
VCCIO[20] 0_0805_5%
1U_0402_6.3V6K AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO[21] VCCDMI[1]
1 VCCDSW 3.3 0.002

DMI
AP24 R477 +1.05VS_PCH
1 1 1 1 1

VCCIO
C277 C273 C279 C510 C511 VCCIO[22] 0_0805_5% C276
AP26 AB36 +1.05VS_VCC_DMI 1 2 1U_0402_6.3V6K VCCDFTERM 1.8 0.19
10U_0603_6.3V6M 1U_0402_6.3V6K VCCIO[23] 20mA VCCIO[1] 2
2 2 2 2 2 1
AT24
VCCIO[24] C270 VCCRTC 3.3 6 uA
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2
AN33 VCCIO[25]
VCCDFTERM VCCSUS3_3 3.3 0.97
AN34 AG16 +1.8VS
+3VS VCCIO[26] VCCPNAND[1]
VCCSusHDA 3.3 / 1.5 0.01

NAND / SPI
BH29 AG17 L1
VCC3_3[3] VCCPNAND[2] 0.1UH_MLF1608DR10KT_10%_1608
1 1
C290 190mA UMA@ VCCVRM 1.5 0.16
This pin can be left as NC if 0.1U_0402_10V7K AJ16 C278
VCCPNAND[3] 0.1U_0402_10V7K C256
On-Die VR is enabled (Default) 2 +VCCAFDI_VRM AP16
2 22U_0805_6.3V6M VCCCLKDMI 1.05 0.02
+1.05VS_PCH VCCVRM[2] UMA@
AJ17
@ VCCPNAND[4]
R483 2 1 0_0603_5% +1.05VS_VCCAPLL_FDI BG6 C513 VCCSSC 1.05 0.095
VCCFDIPLL +3VS 0.01U_0402_25V7K
1 UMA@
+1.05VS_PCH AP17
VCCIO[27]
VCCDIFFCLKN 1.05 0.055
FDI

C280 V1 C514
1U_0402_6.3V6K 20mA VCCSPI 0.01U_0402_25V7K
@ 2 UMA@ VCCALVDS 3.3 0.001
+VCCP_VCCDMI AU20 1
B VCCDMI[2] B
C281
COUGARPOINT_FCBGA989~D Q65R1@ 1U_0402_6.3V6K VCCTX_LVDS 1.8 0.06
2

+3VALW

Vgs=-4.5V,Id=3A,Rds<97mohm
2

PJ32
2

JUMP_43X79
@
1

+3VALW_PCH
1

1 1
C687 C688
A 4.7U_0805_10V4Z 1U_0402_6.3V4Z A
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_POWER-1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 34 of 58
5 4 3 2 1
 5 4 3 2 1

This pin can be left as NC if

+3VS On-Die VR is enabled (Default)
+1.05VS_PCH @
L18 R498
1 2 +3VS_VCC_CLKF33 2 1 +VCCACLK
10UH_LB2012T100MR_20% 1 1
0_0603_5%
C301 C310
10U_0603_6.3V6M 1U_0402_6.3V6K +3VALW_PCH +5VALW JUMP_43X39 +5VALW_PCH
2 2 U2J POWER +1.05VS_PCH @ PJ334
2 1
2 1
1 AD49 N26
C324 VCCACLK VCCIO[29]
1 1
D 0.1U_0402_10V7K P26 C291 D
VCCIO[30] C328
T16
@ 2 VCCDSW3_3 3mA 1U_0402_6.3V6K 0.1U_0402_10V7K
"@" Avoid leakage C305 VCCIO[31]
P28
2 2
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
This pin can be left as NC if 0.1U_0402_10V7K T29
On-Die VR is enabled (Default) +3VS_VCC_CLKF33 VCCIO[33] +3VALW_PCH
T38
+1.05VS_PCH VCC3_3[5]
L20 @ T23
+VCCAPLL_CPY_PCH VCCSUS3_3[7]
1 2 BH23 1
10UH_LB2012T100MR_20% VCCAPLLDMI2 C321 +3VALW_PCH
119mA VCCSUS3_3[8]
T24
+5VALW_PCH +3VALW_PCH
1 +1.05VS_PCH AL29 0.1U_0402_10V7K
C302 VCCIO[14]
V23

USB
10U_0603_6.3V6M VCCSUS3_3[9] 2
1

2
@ +VCCSUS AL24 V24
2 DCPSUS[3] VCCSUS3_3[10] C332 R512 D8
1
C300 P24 0.1U_0402_10V7K 100_0402_5%
1U_0402_6.3V6K VCCSUS3_3[6] 2 CH751H-40PT_SOD323-2
@ AA19

1
+1.05VS_PCH 2 VCCASW[1] +PCH_V5REF_SUS
T26 +1.05VS_PCH
VCCIO[34]
AA21
VCCASW[2] 1010mA 1

AA24 1mA M26 +PCH_V5REF_SUS C326

VCCASW[3] V5REF_SUS 0.1U_0603_25V7K
AA26 @ 2

Clock and Miscellaneous

1 1 VCCASW[4]
C311 C312 AN23 +VCCA_USBSUS C335 1 2 1U_0402_6.3V6K
DCPSUS[4]
AA27
22U_0805_6.3V6M VCCASW[5]
AN24 +3VALW_PCH
2 2 VCCSUS3_3[1]
AA29
22U_0805_6.3V6M VCCASW[6]
+5VS +3VS
AA31
VCCASW[7]
C C
1U_0402_6.3V6K AC26 P34 +PCH_V5REF_RUN
VCCASW[8] 1mA V5REF

2
+3VALW_PCH
1 1 1
C323 C294 C308 AC27 R490 D7
VCCASW[9] 100_0402_5%
N20

PCI/GPIO/LPC
1U_0402_6.3V6K 1U_0402_6.3V6K VCCSUS3_3[2] CH751H-40PT_SOD323-2
AC29 1
2 2 2 VCCASW[10] C293
N22

1
+1.05VS_PCH VCCSUS3_3[3] 1U_0402_6.3V4Z +PCH_V5REF_RUN
AC31
L21 VCCASW[11]
P20 1
10UH_LB2012T100MR_20% VCCSUS3_3[4] 2
AD29
+1.05VS_VCCADPLLA VCCASW[12] C304
1 2 P22
VCCSUS3_3[5] +3VS 1U_0603_10V6K
AD31
L19 VCCASW[13] 2
1 2 +1.05VS_VCCADPLLB W21 AA16
10UH_LB2012T100MR_20% VCCASW[14] VCC3_3[1]
+3VS 1
1 1 W23 W16 C313
VCCASW[15] VCC3_3[8] 0.1U_0402_10V7K
1 1
C333 + C295 C515 + C298 W24 T34
220U_B2_2.5VM_R15 1U_0402_6.3V6K VCCASW[16] VCC3_3[4] 2
1U_0402_6.3V6K W26 1 2
2 2 2 2 VCCASW[17] C306
220U_B2_2.5VM_R15 W29 0.1U_0402_10V7K +3VS
VCCASW[18]
W31 AJ2
+1.05VS_PCH VCCASW[19] VCC3_3[2] +1.05VS_SATA3 +1.05VS_PCH
1
R522 W33 R516
+VCCDIFFCLK VCCASW[20] C297
2 1 AF13 2 1
VCCIO[5] 0.1U_0402_10V7K
0_0603_5% +VCCRTCEXT N16 2 0_0805_5%
1 DCPRTC 1
C337 1 AH13 C329
1U_0402_6.3V6K C334 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM +1.05VS_SATA3
This pin can be left as NC if
Y49 AH14
2 VCCVRM[4] VCCIO[13] 2 On-Die VR is enabled (Default)
B 2 B
AF14 +1.05VS_PCH
+1.05VS_PCH +1.05VS_VCCDIFFCLKN +1.05VS_VCCADPLLA VCCIO[6] L17 @
BD47

SATA
R485 VCCADPLLA 80mA +VCCSATAPLL
AK1 1 2
+1.05VS_VCCDIFFCLKN +1.05VS_VCCADPLLB VCCAPLLSATA +VCCAFDI_VRM 10UH_LB2012T100MR_20%
2 1 BF47
1
VCCADPLLB 80mA 1
0_0603_5% C320 AF11 +VCCAFDI_VRM C296
1U_0402_6.3V6K +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA +1.05VS_PCH 10U_0603_6.3V6M
AF17
VCCIO[7] R491 @
AF33
2 VCCIO[8] +1.05VS_VCC_SATA 2
VCCIO[9] 55mA
AF34 AC16 2 1
+1.05VS_VCCDIFFCLKN VCCIO[2] 0_0805_5%
AG34
+1.05VS_PCH VCCIO[11]
AC17 1
VCCIO[3] C331
AG33 AD17 1U_0402_6.3V6K
VCCIO[10] 95mA VCCIO[4]
1 2
C318
1U_0402_6.3V6K +VCCSST V16 +1.05VS_PCH
DCPSST
2 1
0.1U_0402_10V7K
+1.05VM_VCCSUS T17 T21 +VCCME_22 R509 2 1 0_0603_5%
C299 DCPSUS[1] VCCASW[22]
V19
MISC

2 DCPSUS[2]
+1.05VS_VCCP V21 +VCCME_23 R517 2 1 0_0603_5%
R511 VCCASW[23]
1mA
CPU

+1.05VS_PCH 1 2 0.1U_0402_10V7K +V_CPU_IO BJ8

R521 @ V_PROC_IO +VCCME_21 R520 2
T19 1 0_0603_5%
+1.05VM_VCCSUS 0_0603_5% VCCASW[21]
2 1 1 1 1
C322 C303 +RTCVCC
0_0603_5% C325 +3VALW_PCH
1
RTC

C316 4.7U_0603_6.3V6K 0.1U_0402_10V7K 0.1U_0402_10V7K A22 10mA P32

HDA

2 2 2 VCCRTC VCCSUSHDA
1U_0402_6.3V6K
2 1 1 1 1
C327 C330 C336 COUGARPOINT_FCBGA989~D Q65R1@ C307
A A
0.1U_0402_16V4Z
1U_0402_6.3V6K 0.1U_0402_10V7K
2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_POWER-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 35 of 58
5 4 3 2 1
 5 4 3 2 1

U2I

AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
U2H B15 K7
VSS[164] VSS[264]
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38 B27 VSS[167] VSS[267] L20
AA2 VSS[2] VSS[81] AK4 B31 VSS[168] VSS[268] L26
AA3 VSS[3] VSS[82] AK42 B35 VSS[169] VSS[269] L28
D AA33 VSS[4] VSS[83] AK46 B39 VSS[170] VSS[270] L36 D
AA34 VSS[5] VSS[84] AK8 B7 VSS[171] VSS[271] L48
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 BB24 VSS[177] VSS[277] M30
AB7 VSS[12] VSS[91] AL26 BB28 VSS[178] VSS[278] M32
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
C C
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 VSS[37] VSS[116] AP42 BF22 VSS[203] VSS[303] T47
AD45 VSS[38] VSS[117] AP46 BF24 VSS[204] VSS[304] T8
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13 BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18 BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22 BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26 BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34 BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39 BH11 VSS[217] VSS[317] W2
AF29 VSS[52] VSS[131] AT42 BH15 VSS[218] VSS[318] W27
AF31 VSS[53] VSS[132] AT46 BH17 VSS[219] VSS[319] W48
AF38 VSS[54] VSS[133] AT7 BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16 BH31 VSS[223] VSS[323] Y42
AF5 VSS[58] VSS[137] AV20 BH33 VSS[224] VSS[324] Y46
AF7 VSS[59] VSS[138] AV24 BH35 VSS[225] VSS[325] Y8
AF8 VSS[60] VSS[139] AV30 BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18 D18 VSS[232] VSS[335] BG41
B AH36 AW2 D22 G14 B
VSS[67] VSS[146] VSS[233] VSS[337]
AH39 VSS[68] VSS[147] AW22 D24 VSS[234] VSS[338] H16
AH40 VSS[69] VSS[148] AW26 D26 VSS[235] VSS[340] T36
AH42 VSS[70] VSS[149] AW28 D30 VSS[236] VSS[342] BG22
AH46 VSS[71] VSS[150] AW32 D32 VSS[237] VSS[343] BG24
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12 E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22 G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28 G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
COUGARPOINT_FCBGA989~D Q65R1@ G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]

COUGARPOINT_FCBGA989~D Q65R1@

A A

www.vinafix.vn
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 36 of 58
5 4 3 2 1
 5 4 3 2 1

SATA HDD SATA ODD Conn

Conn. +5VS
Place closely JHDD SATA CONN.
1.2A SW5
SMT1-05-A_4P
1 1 1 1 JODD @
Close to JODD ODD_DA#_R 1 3
C356 C357 C358 C359
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 4
GND SATA_PTX_C_DRX_P2 C378 1
A+ 2 2 0.01U_0402_25V7K SATA_PTX_DRX_P2 <28>
2 2 2 2 3 SATA_PTX_C_DRX_N2 C377 1 2 0.01U_0402_25V7K SATA_PTX_DRX_N2 <28>

6
5
A-
GND 4
5 SATA_PRX_DTX_N2 C376 1 2 0.01U_0402_25V7K
B- SATA_PRX_C_DTX_N2 <28>
6 SATA_PRX_DTX_P2 C375 1 2 0.01U_0402_25V7K
D B+ SATA_PRX_C_DTX_P2 <28> D
SSD HDD need 400mA for 3V(PHISON) GND 7
+3VS
+3VS rail reserve for SSD ODD_DETECT#_R
DP 8 1 2 ODD_DETECT# <33>
1 1 1 1 +5V 9 +5VS_ODD R561 0_0402_5%
+5VS_ODD
C363 C364 C365 C366
+5V 10 Place components closely ODD CONN.
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 11 ODD_DA#_R 1 2 1.1A
MD ODD_DA# <32>
@ @ @ @ 15 12 R562 0_0402_5%
2 2 2 2 GND GND
14 GND GND 13 1 1 1 1 1
C352 C353 C354
@ C355 C360
SANTA_206401-1_RV 10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2

JHDD
Close to JHDD
GND 1
2 SATA_PTX_C_DRX_P0 C369 1 2 0.01U_0402_25V7K
A+ SATA_PTX_DRX_P0 <28>
3 SATA_PTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K
A- SATA_PTX_DRX_N0 <28>
4 R73 0_0402_5% W=60mils
GND
B-
B+
5
6
7
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
C368 1
C370 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_C_DTX_N0 <28>
SATA_PRX_C_DTX_P0 <28>
USB Board@ Right Side 1

L53
@ 2
+USB_VCCA 22
21
JPIO
22
@

GND USB20_N0_R 21
<32> USB20_N0 1 1 2 2 20 20
+5VL 1 2 19 19
8 R149 0_0402_5% 18
V33 +3VS USB20_P0_R 18
V33 9 <32> USB20_P0 4 4 3 3 17 17
10 +5VALW 1 @ 2 +5V_IO 16
V33 WCM-2012-900T_0805 R148 0_0402_5% USB20_N1_R 16
GND 11 15 15
12 W=60mils USB20_P1_R 14
GND @ 14
C GND
V5
13
14 +5VS
+5VALW 2.5A +USB_VCCA For EMI
1
R87
2
0_0402_5%
13
12
13
12
C
15 U14 USB20_N0_R 11
V5 R77 0_0402_5% USB20_P0_R 11
V5 16 1 GND VOUT 8 2 1 10 10
17 2 7 C361 1000P_0402_50V7K 1 @ 2 9
GND VIN VOUT 9
Reserved 18 3 VIN VOUT 6 8 8
19 USB_EN# 4 5 USB_OC#0 <32,44> L54 7
GND EN FLG <43> HP_R 7
20 1 <32> USB20_N1 1 2 USB20_N1_R 6
V12 1 2 <43> HP_L 6
24 21 RT9715BGS_SO8 5
GND V12 C362 5
23 GND V12 22 <43> MIC1_L 4 4
4.7U_0805_10V4Z <32> USB20_P1 4 3 USB20_P1_R 3
2 @ 4 3 <43> MIC1_R 3
<43> NBA_PLUG 2 2
SANTA_191201-1 WCM-2012-900T_0805 1
<43> BACK_SENSE 1
1 @ 2 ACES_85201-2005N
R88 0_0402_5%

USB Board@ Left Side

Q8

S
+USB_VCCC 3 +USB_VCCB
AO3413_SOT23
1 2

G
+5VALW

2
R568 100K_0402_5%

<44> USB_EN# USB_EN#

B B

+USB_VCCC

C426 1 2 220U_6.3V_M_R15

+
W=60mils

C428 1 2 1000P_0402_50V7K

2 @ 1 C389 1 2 0.1U_0402_16V4Z
R190 0_0402_5%

L15 JUSB @
<32> USB20_N2 3 3 4 4 1 VCC GND 5
USB20_N2_R 2 6
USB20_P2_R D- GND
3 D+ GND 7
<32> USB20_P2 2 2 1 1 4 GND GND 8

WCM-2012-900T_0805 ALLTOP C107L8-10405-L

2 @ 1
R189 0_0402_5%

D23 @
USB20_N2_R 2
1
A USB20_P2_R 3 A

PJDLC05C_SOT23-3

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA-HDD/ODD/USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 37 of 58
5 4 3 2 1
 5 4 3 2 1

IR Emitter Connector 3D@

R150 1 2 0_0402_5%

L57 @
4 3 USB20_P5_R
<32> USB20_P5 4 3

1 2 USB20_N5_R
<32> USB20_N5 1 2
D W CM-2012-900T_0805 D

3D@
R144 1 2 0_0402_5%

JIR @
+5VS 2 3D@ 1 +IR_VCC 1 1
R151 0_0603_5% USB20_P5_R 2
USB20_N5_R 2
3 3 GND 5
For ESD 3D@ 4 4 GND 6
C399
0.1U_0402_16V4Z ACES_87213-0400G
D10 @
USB20_P5_R 3
1
USB20_N5_R 2

PESD5V0U2BT_SOT23-3

C
Felica C

B-CAS Circuit
+3VS

+5VALW +5VS +3VS

JFEL @
+FLICA_VCC 1 1
1

1 TV@ Inrush current = 0A 1 <32> USB20_N13

USB20_N13 2 2

2
TV@RB2
TV@RB2 CB1 2 FELICA@ USB20_P13 3
<32> USB20_P13 3
0.1U_0402_16V7K R419 FELICA@ C414 C758 FELICA_GND 4
100K_0402_5% 100K_0402_5% C479 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4
5 5
3

RB5 2 S
QB1 FELICA@ 0.1U_0402_16V7K FELICA@ 2
6
2

3
G
AO3413_SOT23 FELICA@ 1 S
2 1 2 7

1
G1

1
G
TV@ 1 2 2 Q20 8 G2
3

47K_0402_5% 1
D R403 47K_0402_5% 2 AO3413_SOT23 R132
1

2N7002DW -T/R7_SOT363-6 TV@ +5VS_BCAS +5VS_L_BCAS C403 D FELICA@ 0_0603_5% ACES_87151-06051

1
D

1
QB2B TV@ LB1 TV@ 0.01U_0402_25V7K FELICA@
BCPW ON 5 TV@ CB2 1 2 2 FELICA@
<39> BCPW ON <28> FELICA_PW R

2
2
0.01U_0402_25V7K 1
+5VS_L_BCAS 1 1 FBMA-L11-201209-221LMA30T_0805 G
+FLICA_VCC
1

CB4 Q34 S 2N7002_SOT23-3

4

3
1

1 TV@ CB5 TV@ FELICA@

TV@ RB7 0.1U_0402_16V4Z 1U_0402_6.3V4Z
10K_0402_5% TV@ RB8 CB3 TV@ 2 2
2.2K_0402_5% 4.7U_0603_6.3V6K
2

2
2

B +5VS_L_BCAS B
5

UB1 TV@
1 Finger printer
P

IN1 B_R_BCRST 1 TV@ B_BCRST

O 4 2 B_BCRST <39>
BCRSTM 2 RB9 100_0402_5%
<39> BCRSTM IN2
G

SN74AHC1G08DCKR_SC70-5
3

JFP @
5

UB2 TV@ +3VS 1 R134 2 +3VS_FP 1

0_0603_5% 1 USB20_N8 1
1 2
P

IN1 <32> USB20_N8 2

4 B_R_XBCCLK1 TV@ 2 B_XBCCLK FP@ C480 USB20_P8 3
O B_XBCCLK <39> <32> USB20_P8 3
XBCLKM 2 RB11 100_0402_5% 0.1U_0402_16V4Z FP_GND 4
<39> XBCLKM IN2 4
G

FP@ 5 GND

1
SN74AHC1G08DCKR_SC70-5 2
6
3

R133 GND
0_0603_5% P-TW O_161011-04021
D82 FP@ FP@
4 2

2
VIN IO1
3 IO2 GND 1
+5VS_L_BCAS
CM1293A-02SR SOT143-4
A 1 2 For ESD A
RB12 TV@
3

RB1 TV@ E 10K_0402_5%

+5VS_L_BCAS 1 2 2 1 2 QB4 TV@ BCIO
B BCIO <39>
RB13 TV@ 2SB1197K_SOT23-3
10K_0402_5% 10K_0402_5% C
1
6

1 2
QB2A RB14 TV@ Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
TV@ 1.5K_0402_5% 200910/9 2010/01/23 Title
Issued Date Deciphered Date
CPLGP1
<39> CPLGP1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IR/FP/B-CAS/Felica
2N7002DW -T/R7_SOT363-6 Size Document Number Rev
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 38 of 58
5 4 3 2 1
 +3VS
120 mils For SED
Slot 2 Full PCIe Mini Card- 3G/ TV Tuner
WLAN&BT Combo module circuits 0.1U_0402_16V4Z
Slot 1 Half PCIe Mini Card-WLAN/ WiMax Half PCIe Mini Card- JET 1 1 1

1
BT BT CM4 CM5 CM6 C255
on module on module 47P_0402_50V8J
+1.5VS +3VS 0.01U_0402_25V7K @

2
J3G @ 2 2 2
Enable Disable PCIE--JET B-CAS
+3VALW 2 1 +3V_WLAN 1 2 2.75A 4.7U_0805_10V4Z
2 1 1 2
<38> XBCLKM 3 4
PJ27@ JUMP_43X79 BCCDET 3 4
BT_CRTL H L 5
5 6
6
+3VS 2 1 <29> CLKREQ_JET# 7 8 +UIM_PWR
2 1 7 8 UIM_DATA
9 10
PJ26@ JUMP_43X79 9 10
BT_ON# L H <29> CLK_JET# 11
11 12
12 UIM_CLK
<29> CLK_JET 13 14 UIM_RESET RM3 0_0402_5%
13 14 COMMON
Short PJ27 for Wimax 15 16 1 3G@ 2 UIM_VPP
15 16
**If +3V_WLAN is +3VS, please <38> BCRSTM 17
17 18
18 ISDBT_DET
ISDBT_DET <33>
COMMON
RF_OFF# 1 TV@ BCIO
Short PJ26 for WLAN remove D24 <38> BCPWON 19
21
19 20
20
22 PLT_RST#
RF_OFF# <32>
USB--TV#2 RM7
2
0_0402_5%
BCIO <38>
21 22 USB20_P10_TV 1 R126
<29> PCIE_PRX_JETTX_N3 23 24 2 TV@ 0_0402_5% USB20_P10 <32>
D24 23 24 USB20_N10_TV 1
<29> PCIE_PRX_JETTX_P3 25 26 2 TV@ 0_0402_5% USB20_N10 <32>
SUSP# BT_CTRL 25 26 R135
1 2 27 28
27 28 R72 1 3G@ 2 0_0402_5% PM_SMBCLK
40 mils CH751H-40PT_SOD323-2
<29> PCIE_PTX_C_JETRX_N3
29
31
29
31
30
32
30
32 R85 1 3G@ 2 0_0402_5% PM_SMBDATA Close to J3G

1
+3V_WLAN +1.5VS D
For SED For SED <29> PCIE_PTX_C_JETRX_P3 33
33 34
34
2 Q36 35 36 USB20_N12 <32> +5VS_BCAS 1 TV@ 2 +VCC_SIM
<33> BT_ON# 35 36
0.1U_0402_16V4Z 0.1U_0402_16V4Z G 37 38 USB20_P12 <32> USB--3G/TV#1 RM4 0_0603_5%
37 38
1 1 1 1 1 1 S 2N7002_SOT23-3 +3VS 39 40 +UIM_PWR 1 3G@ 2

3
39 40
1

1
41 42 LED_WIMAX# RM1 0_0603_5%
CM1 CM2 CM3 C253 CM7 CM8 CM9 C254 41 42 CPLGP1
43 44 CPLGP1 <38>
47P_0402_50V8J 47P_0402_50V8J 43 44
45 46 TMPTU1_SXP <44>
2

2
2 2 2 @ 2 2 2 @ 45 46
<44> TMPTU2_SXP 47 48 UIM_RESET 1 3G@ 2 SIM_RESET
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z 47 48 RM5 0_0402_5%
49
49 50
50 B-CAS
51 52 <38> B_BCRST
B_BCRST 1 TV@ 2
51 52 RM8 0_0402_5%
53 54
GND1 GND2
+1.5VS +3V_WLAN UIM_CLK 1 3G@ 2 SIM_CLK
JWLAN @ FOX_AS0B226-S40N-7F RM9 0_0402_5%
1 2 BT_CTRL 1 R327 2 E51_RXD_R Add BCCDET pull down <38> B_XBCCLK
B_XBCCLK 1 TV@ 2
1 2 1K_0402_5% RM10 0_0402_5%
3 4
BT_CTRL 3 4
5 6
5 6 BCCDET
<29> CLKREQ_WLAN# 7 8 For isolate Intel Rainbow Peak and 1 TV@ 2
7 8 R307 470_0402_5% +UIM_PWR
9 10 Compal Debug Card. UIM_DATA 1 3G@ 2 SIM_DATA
9 10 RM11 0_0402_5%
<29> CLK_WLAN# 11 12
11 12 BCIO
<29> CLK_WLAN 13 14 1 TV@ 2
13 14 RM12 0_0402_5%
15 16

1
15 16
17 18
17 18 RM2
19 20 WL_OFF# <32>
19 20 PLT_RST# J3GSIM @ 4.7K_0402_5%
21 22 PLT_RST# <5,32,40,41,42,44,45>
21 22 +VCC_SIM @
<29> PCIE_PRX_WLANTX_N2 23 24 1 4
23 24 SIM_RESET VCC GND UIM_VPP
<29> PCIE_PRX_WLANTX_P2 25 26 2 5

2
25 26 SIM_CLK RST VPP SIM_DATA
27 28 3 6
27 28 CLK I/O
29 30 PM_SMBCLK <11,12,29> 1
29 30

1
31 32 PM_SMBDATA <11,12,29> 1 7 8 CM14
<29> PCIE_PTX_C_WLANRX_N2 31 32 NC NC
33 34 CM13 DM1 1 1 22P_0402_50V8J
<29> PCIE_PTX_C_WLANRX_P2 33 34
35 36 USB20_N9 <32> 0.1U_0402_16V4Z RLZ20A_LL34 MOLEX_47273-0001~D @
35 36 3G@ CM15 CM16 2
WLAN/ WiFi 37
37 38
38 USB20_P9 <32> WiMax 2 3G@
10P_0402_50V8J 10P_0402_50V8J
+3V_WLAN 39 40

2
39 40 LED_WIMAX# 3G@ 2 2 3G@
41 42 LED_WIMAX# <46>
41 42
43 44
43 44
45 46 1 2 +3VS
R16 45 46 RM6 100K_0402_5%
47 48
47 48
<44> E51_TXD 10_0402_5%2 49 50 WIMAX@
E51_RXD_R 49 50
<44> E51_RXD 1 2 51 52
0_0402_5% 51 52
R17 53 54
GND1 GND2
Debug card using
FOX_AS0B226-S40N-7F

+3VALW_CARD +3VS_CARD +1.5VS_CARD

Imax = 0.275A Imax = 1.35A Imax = 0.75A JEXP @
1 1 1 1 1 1 1
CN1 CN2 CN3 CN4 CN5 CN6 USB20_N4_R GND
2
+3VALW 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z USB20_P4_R USB_D-
3
NEW@ NEW@ NEW@ NEW@ NEW@ NEW@ NEW@ CP_USB# USB_D+
4
2 2 2 2 2 2 CPUSB#
1 2 CP_USB# 5
RN4 100K_0402_5% RSV
6
PM_SMBCLK RSV
7
UN1 NEW@ SMB_CLK
40mils PM_SMBDATA 8
SMB_DATA
+1.5VS 12 11 +1.5VS_CARD +1.5VS_CARD 9
1.5Vin 1.5Vout +1.5V
14 13 10
1.5Vin 1.5Vout +1.5V
<30,40,42> EC_SWI# 11
WAKE#
60mils +3VALW_CARD 12
+3.3VAUX
+3VS 2 3 +3VS_CARD PERST# 13
3.3Vin 3.3Vout PERST#
4 5 +3VS_CARD 14
3.3Vin 3.3Vout +3.3V
20mils 15
+3.3V
+3VALW 17 15 +3VALW_CARD CLKREQ# 16
AUX_IN AUX_OUT EXP_CPPE# CLKREQ#
<32> EXP_CPPE# 17
PLT_RST# CPPE#
6 19 <29> CLK_NEW# 18
SYSRST# OC# REFCLK-
Reserve for EMI request <29> CLK_NEW 19
REFCLK+
SYSON 20 8 PERST# 20
<42,44,52> SYSON SHDN# PERST# GND
+3VS +3VS 21
<29> PCIE_PRX_NEWTX_N5 PERn0
<28,44,47,52,54,56> SUSP#
SUSP# 1 16 1 NEW@ 2 <29> PCIE_PRX_NEWTX_P5 22
+3VS STBY# NC R125 0_0402_5% PERp0
23
1

RN6 EXP_CPPE# GND

1 10 7 <29> PCIE_PTX_C_NEWRX_N5 24
10K_0402_5% CN7 CPPE# GND L56 @ PETn0
<29> PCIE_PTX_C_NEWRX_P5 25
1

@ 0.1U_0402_16V4Z CP_USB# USB20_P4_R PETp0

9 21 <32> USB20_P4 1 2 26
RN7 UN2 @ CPUSB# Thermal_Pad 1 2 GND
5

10K_0402_5% @ 2 RCLKEN 18
2

@ CLKREQ# RCLKEN USB20_N4_R

2 <32> USB20_N4 4 3 27 29
G Vcc

B CLKREQ_NEW# TPS2231MRGPR-2 QFN 4 3 GND GND

4 CLKREQ_NEW# <29> 28 30
2

Y WCM-2012-900T_0805 GND GND

1
A SANTA_130801-5_NR
NC7SZ32P5X_NL_SC70-5
3
1

D
1 NEW@ 2
RCLKEN 2 Q27 R124 0_0402_5%
G 2N7002_SOT23-3
S @
3

NEW@ Security Classification Compal Secret Data Compal Electronics, Inc.

CLKREQ# 1 2 CLKREQ_NEW# 200910/9 2010/01/23 Title
RN8 0_0402_5%
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-WLAN/JET/3G/TV/NewCard
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 39 of 58

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 A B C D E

UL1
+3V_LAN CL3 to CL6 close to Pin 27,39,47,48
CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 22 31 +LAN_VDD10 CL7 to CL8 close to Pin 12,42
<29> PCIE_PRX_C_LANTX_P1 HSOP LED3/EEDO
37
LED1/EESK
<29> PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 23 HSON LED0 40 LL1
8111E@ 1 2
+LAN_REGOUT 1 2 CL3 0.1U_0402_16V4Z
PCIE_PTX_C_LANRX_P1 17 30 RL2 2 1 10K_0402_5% 2.2UH +-5% NLC252018T-2R2J-N 1 2
<29> PCIE_PTX_C_LANRX_P1 PCIE_PTX_C_LANRX_N1 18 HSIP EECS/SCL
32 RL1 2 1 10K_0402_5% 1 1 CL4 0.1U_0402_16V4Z
<29> PCIE_PTX_C_LANRX_N1 HSIN EEDI/SDA Layout Note: LL1 must be 1 2
within 200mil to Pin36, CL13 CL9 CL5 0.1U_0402_16V4Z
CLKREQ_LAN# 2 1 16 1 LAN_MDI0+ CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 1 2
<29> CLKREQ_LAN# CLKREQB MDIP0
RL19 0_0402_5% 2 LAN_MDI0- 200mil to LL1 8111E@ 2 2 8111E@ CL6 0.1U_0402_16V4Z
PLT_RST# MDIN0 LAN_MDI1+
<5,32,39,41,42,44,45> PLT_RST# 25 4 1 2
PERSTB MDIP1 LAN_MDI1- 8111E@ CL7 0.1U_0402_16V4Z
MDIN1 5
1 +3V_LAN CLK_LAN 19 7 LAN_MDI2+ LL1 CL13 CL9 1 2 1
<29> CLK_LAN CLK_LAN# REFCLK_P NC/MDIP2 LAN_MDI2-
20 8 2.2UH +-5% NLC252018T-2R2J-N 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 8111E@ CL8 0.1U_0402_16V4Z
<29> CLK_LAN# REFCLK_N NC/MDIN2 LAN_MDI3+
10 8105E-SWR@ 8105E-SWR@ 8105E-SWR@
RL24 2 @ CLKREQ_LAN# NC/MDIP3 LAN_MDI3-
1 10K_0402_5% 11
LAN_X1 NC/MDIN3
43
RL25 2 @ EC_SWI# CKXTAL1
1 10K_0402_5%
LAN_X2 44 13 +LAN_VDD10 +LAN_EVDD10
CKXTAL2 DVDD10 +LAN_VDD10 +LAN_VDD10
29 CL19, CL20,CL21 close to pin 13,29,45, respectively
DVDD10
RTL8105E RTL8111E DVDD10 41 1 2 CL22 close to pin 3, respectively
EC_SWI# 28 LL2 0_0603_5% CL23,CL24,CL25 close to pin 6,9,41, respectively
<30,39,42> EC_SWI# LANWAKEB
Pin14 NC NC 1 1
+3VS ISOLATE# 26 27 1 2
ISOLATEB DVDD33 +3V_LAN CL17
Pin15 NC 10K ohm PD DVDD33 39 CL18 CL19 0.1U_0402_16V4Z
1U_0402_6.3V4Z 0.1U_0402_16V4Z 1 2
Pin38 1K ohm Pull-high 2 2 CL20 0.1U_0402_16V4Z
14 NC/SMBCLK AVDD33 12 +3V_LAN
1

RL21 2 8111E@ 1 10K_0402_5% 15 42 1 2

RL22 1 NC/SMBDATA AVDD33
+3V_LAN 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 CL21 0.1U_0402_16V4Z
1K_0402_5%
AVDD33
48 Close to Pin 21 1 2
RL6 8111E@ CL22 0.1U_0402_16V4Z
@ ENSWREG 33 1 2
2

ENSWREG 8111E@ CL23 0.1U_0402_16V4Z

EVDD10 21 +LAN_EVDD10
ISOLATE# 1 2 WOL_EN 34 +3V_LAN +LAN_VDDREG 1 2
+LAN_VDDREG VDDREG
RL433 0_0402_5% 35 3 +LAN_VDD10 8111E@ CL24 0.1U_0402_16V4Z
VDDREG AVDD10
AVDD10 6 1 2 1 2
9 8111E@ LL3 0_0603_5% 1 1 8111E@ CL25 0.1U_0402_16V4Z
AVDD10
1 2 46 RSET AVDD10 45
RL7 Sx Enable Sx Disable S0 RL5 2.49K_0402_1% CL28 CL29
15K_0402_5% Wake up Wake up 24 36 +LAN_REGOUT 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
GND REGOUT 8111E@ 2 2 8111E@
49 PGND 60 mils
WOL_EN LOW HIGH HIGH
RTL8111E-GR_QFN48_6X6
2 8111E@ LL3 CL28 CL29 2
0_0603_5% 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
8105E-SWR@ 8105E-SWR@ 8105E-SWR@

+3VALW TO +3V_LAN
YL1 RTL8105E-VC RTL8105E-VC
LAN_X1 1 2 LAN_X2 +3V_LAN
+3VALW
RTL8111E-VB
25MHZ_20PF_7A25000012 PWM Mode LDO Mode

1
+3VALW RL4 0 ohm NC
1 1
CL26 CL27 RL4 (Pull High)
27P_0402_50V8J 27P_0402_50V8J 0_0402_5%
1

2 8111E@ NC 0 ohm
RL147 CL483 Vgs=-4.5V,Id=3A,Rds<97mohm 2 2 RL23 (Pull Down)

2
100K_0402_5% @ ENSWREG
@ 0.1U_0402_16V7K
2

1
1
2

S
@ RL432 @ QL51 PJ29 RL23 RL4
2

G
1 2 2 JUMP_43X79 0_0402_5% 0_0402_5%
<44> WOL_EN
@ 8105E-LDO@ 8105E-SWR@
+3V_LAN
1

47K_0402_5% 2 AO3413_SOT23 D
1

2
@
1

CL482 +3V_LAN
0.01U_0402_25V7K
1
1

CL681
1
CL682
1U_0402_6.3V4Z
1 LAN Conn.
2 @ 1
4.7U_0805_10V4Z CL683 + CL684
@ 2 220U_6.3V_M_R16 10U_0805_10V6K JLAN
3 @ @ 3
2 2 RJ45_MIDI3- 8 PR4-
RJ45_MIDI3+
+3V_LAN rising time (10%~90%) need > 1ms and <100ms. 7 PR4+
RJ45_MIDI1- 6
PR2-
FOR EMI ISN TEST DEMAND.
RJ45_MIDI2- 5
PR3-
RJ45_MIDI2+ 4 PR3+
UL4 RJ45_MIDI1+ 3
CL39 1000P_0402_50V7K PR2+
For P/N and footprint 1 24 2 1 1 8111E@ 2 RJ45_MIDI0- 2
LAN_MDI3- TCT1 MCT1 8111E@ RL11 75_0402_1% RJ45_MIDI3- PR1-
Please place them to ISPD page 2 TD1+ MX1+ 23
LAN_MDI3+ 3 22 RJ45_MIDI3+ RJ45_MIDI0+ 1
UL1 UL1 TD1- MX1- CL40 1000P_0402_50V7K PR1+
4 21 2 1 1 8111E@ 2 9
LAN_MDI2- TCT2 MCT2 8111E@ RL12 75_0402_1% RJ45_MIDI2- SHLD1
5 20
LAN_MDI2+ TD2+ MX2+ RJ45_MIDI2+
6 TD2- MX2- 19 SHLD2 10
CL41 1000P_0402_50V7K
7 TCT3 MCT3 18 2 1 1 2
8105E-VC 10/100M 8105E-VC 10/100M LAN_MDI1- 8 17 RL13 75_0402_1% RJ45_MIDI1- SANTA_130451-D
8105E-LDO@ 8105E-SWR@ LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+ @
9 TD3- MX3- 16
CL42 1000P_0402_50V7K
UL4 UL4 10 15 2 1 1 2
LAN_MDI0- TCT4 MCT4 RL15 75_0402_1% RJ45_MIDI0-
11 TD4+ MX4+ 14
LAN_MDI0+ 12 13 RJ45_MIDI0+
TD4- MX4-
1 RJ45_GND 1 2 LANGND
RJ45_GND CL36 1000P_1808_3KV7K 1 1
10/100M transformer 10/100M transformer Place CL34 colse CL34 SUPERWORLD_SWG150401 CL37 CL38
4 8105E-LDO@ 8105E-SWR@ 0.1U_0402_25V4K 8111E@ 4
to LAN chip
2 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-LAN-RTL8105E/8111E
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 40 of 58
A B C D E
 5 4 3 2 1

+1.8VS_OUT CC3 close to pin 5

CC2 close to CC3
20mil CC1 is near CC3

D3E mode

1000P_0402_50V7K
10U_0805_10V4Z

0.1U_0402_16V4Z
0.22U_0402_6.3V4K
1 1 1 1
CC1 CC2 CC3 CC4
CC4 close to pin 10
2 2 2 2 RC31 0_0402_5%
CC16 close to pin43 <28> CR_CPPE# 1 2 CPPE#

D
For internal LDO in SD3.0
JMB389C RC6 0_0402_5%
SD_CD#
D
<28> CR_W AKE# 1 2
+3VS
UC1 +3VS
place near pin 19,20 and 44
CLK_CR# 3 5 1 2
<29> CLK_CR# CLK_CR APCLKN APVDD CC5 0.1U_0402_16V4Z
<29> CLK_CR 4 APCLKP APV18 10 40mil 2
NC/TAV33 36 1 2
PCIE_PTX_C_CRRX_N4 9 CC6 0.1U_0402_16V4Z CC12
<29> PCIE_PTX_C_CRRX_N4 PCIE_PTX_C_CRRX_P4 APRXN
<29> PCIE_PTX_C_CRRX_P4 8 APRXP DV33 19 1 2 0.1U_0402_16V4Z
CC7 0.1U_0402_16V4Z 1
DV33 20
<29> PCIE_PRX_C_CRTX_N4 CC8 1 2 0.1U_0402_16V7K PCIE_PRX_CRTX_N4 11 44
CC9 0.1U_0402_16V7K PCIE_PRX_CRTX_P4 APTXN DV33 +1.8VS_OUT
<29> PCIE_PRX_C_CRTX_P4 1 2 12 APTXP DV18 18 20mil CC12 close to pin 36
DV18 37 Power On Strapping setting
2 1 APREXT 7 APREXT XD_SD_MS_D0
RC3 12K_0402_1% 12mil
MDIO0 48 2 1 Description
47 XD_SD_MS_D1 CC10 CC11 10U_0805_10V4Z Pin name
+SDV33_18 MDIO1 XD_SD_MS_D2
2 1 43 SDDV/MDIO4 MDIO2 46 High low
CC16 2.2U_0603_6.3V6K 39 45 XD_SD_MS_D3 CC11 close to pin18
TXIN/NC MDIO3 SDCMD_MSBS_XDW E# 1 2
MDIO6/4 41 For intenal LDO's usage
42 SDCLK_MSCLK_XDCE# 0.22U_0402_6.3V4K MDIO7 on-board add-in card
MDIO5 XDW P#_SDW P#
JMB389 G/MDIO6
MDIO7
24
40 XD_CLE
29 XD_SD_D4 CC10 close to pin37 CR_LED CR_LED
MDIO8 XD_SD_D5
<5,32,39,40,42,44,45> PLT_RST#
RC4 1 2 100_0402_5% 1 XRSTN MDIO9 28 MDIO14 high active low active
1 2 27 XD_SD_D6
CC13 XTEST MDIO10 XD_SD_D7
MDIO11 26
0.1U_0402_16V4Z 25 XD_RE#
CPPE# MDIO12 XD_RB# +3VS
13 CPPE_N MDIO13 23
2 XD_CD# XD_ALE
14 CR1_CD2N MDIO14 22

30 XD_CLE 1 2
C MS_CD# NC/SPI_SCK RC28 @ 10K_0402_5% C
15 CR1_CD1N NC/SPI_CSN 33 MDIO7
SD_CD# 16 34
CR1_CD0N NC/SPI_SO
NC/SPI_SI 35
40 mils
+VCC_OUT 17 XD_ALE 1 2
+VCC_OUT CR1_PCTLN RC26 @ 1K_0402_5%
APGND 6 MDIO14
NC/GND 31
CR_LED 21 32 1 2
XDW P#_SDW P# CR1_LEDN NC/GND RC25 @ 200K_0402_5%
2 1 NC/GND 38
RC7 10K_0402_5%
1 2 XD_RB#
RC9 1K_0402_5% Vendor review to set @
JMB389-LGAZ0A_LQFP48_7X7

Add RC24 and RC17 close to UC1 for xD issue

SDCMD_MSBS_XDW E# 2 1 XDW E#
RC24 22_0402_5%

2 1 SDCMD_MSBS
RC17 22_0402_5%

5 in 1 Card Reader
B SD_CD# XD_CD# JREAD @ B
+VCC_OUT
40 mils MS-VCC 14 +VCC_OUT
1 1 33 15 MS_CLK SDCLK_MSCLK_XDCE# RC11 1 2 22_0402_5% SD_CLK
CC22 CC23 XD_CD# XD-VCC MS-SCLK MS_CD#
34 XD-CD-SW MS-INS 17
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 XD_RB# 1 21 SDCMD_MSBS RC12 1 2 22_0402_5% MS_CLK
@ @ CC17 CC18 XD_RE# XD-R/B MS-BS XD_SD_MS_D0
2 XD-RE MS-DATA0 19
2 2 XD_CE# XD_SD_MS_D1 RC13 1 XD_CE#
3 XD-CE MS-DATA1 20 2 22_0402_5%
10U_0805_10V4Z 0.1U_0402_16V4Z XD_CLE 4 18 XD_SD_MS_D2
2 2 XD_ALE XD-CLE MS-DATA2 XD_SD_MS_D3
5 XD-ALE MS-DATA3 16
XDW E# 6 Reserved for EMI,close to UC1.42
XDW P#_SDW P# XD-WE
7 XD-WP SD-VCC 23 +VCC_OUT
24 SD_CLK
XD_SD_MS_D0 SD-CLK SDCMD_MSBS
8 XD-D0 SD-CMD 12
XD_SD_MS_D1 9 25 XD_SD_MS_D0
XD_SD_MS_D2 XD-D1 SD-DAT0 XD_SD_MS_D1
26 XD-D2 SD-DAT1 29
XD_SD_MS_D3 27 10 XD_SD_MS_D2 @ @
XD_SD_D4 XD-D3 SD-DAT2 XD_SD_MS_D3 RC14 CC19
28 XD-D4 SD-DAT3 11
XD_SD_D5 30 35 XDW P#_SDW P# SD_CLK 1 2 1 2
XD_SD_D6 XD-D5 SD-WP-SW SD_CD#
31 XD-D6 SD-CD-SW 36
XD_SD_D7 32 100_0402_5% 100P_0402_50V8J
XD-D7 @ @
CR_LEDCON# CR_LEDCON# <46> 13 RC15 CC20
4in1-GND MS_CLK
4in1-GND 22 1 2 1 2
4in1-GND 37
38 100_0402_5% 100P_0402_50V8J
4in1-GND @ @
RC16 CC21
2 1 XD_CE# 1 2 1 2
RC8 0_0402_5% TAITW _R015-211-LM-A_NR
100_0402_5% 100P_0402_50V8J
1

D
A A
QC1 2 CR_LED
2N7002_SOT23-3 G Reserved for EMI,close to JREAD
2

@ S Confirm sinking 16mA

3

RC10
4.7K_0402_5%
@

www.vinafix.vn
Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-CardReader JMB389
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 41 of 58
5 4 3 2 1
 5 4 3 2 1

+1.5V to +1.05V Transfer Close to U102.D7 Close to U102.P13

+5VALW +1.5V +5VALW +1.5V +1.05V +3VA +3VA DT1 @
1U_0603_10V6K~N

10U_0603_6.3V6M
UT2 1A 2 USB20_DN1_L
CT1

CT2
1 1 5 3 1
VIN VOUT USB20_DP1_L
9 4 3
VIN VOUT
6
VCNTL

0.1U_0402_16V7K~N

0.01U_0402_16V7K~N

0.1U_0402_16V7K~N

0.01U_0402_16V7K~N
USB30_POK 7 2 2 1 PJDLC05C_SOT23-3
2 2 POK FB

8P_0402_50V8K

8P_0402_50V8K
RT2 1 2 1 1 2 1

10U_0603_6.3V6M

CT4

CT5

CT6

CT7

CT8

CT9
8 1 10K_0402_1%
EN GND +USB_VCCB

CT3
1 U3RXDP1_R USB30@ 1 2 RT4 U3RXDP1_R_L U3TXDP1 USB30@ 1 2 RT5 U3TXDP1_L
SYSON APL5930KAI-TRG_SO8 RT3 0_0402_5% 0_0402_5%
<39,44,52> SYSON 2 1 2 2 1 2 WCM-2012-121T_0805 WCM-2012-121T_0805
32.4K_0402_1% DT2
Vout=0.8(1+10K/32.4K) 4 3 4 3 U3RXDN1_R_L 1 8

2
2 4 3 4 3 U3RXDP1_R_L R- VCC
1.042 ~ 1.0469 ~ 1.0519V 2 7
D
U3TXDN1_L R+ GND USB20_DN1_L D
3 6
Spec: 0.9975 ~ 1.05 ~ 1.1025 @ @ U3TXDP1_L T- D- USB20_DP1_L
1 2 1 2 4 5
1 2 1 2 T+ D+
LT1 @ LT2 @ LXES4XBAA6-027_MSOP8
U3RXDN1_R 1 2 RT6 U3RXDN1_R_L U3TXDN1 1 2 RT7 U3TXDN1_L @
USB30@ 0_0402_5% USB30@ 0_0402_5%
+1.05V
+3VALW +1.05VR +3VALW +3VA Follow Vendor recommend.

2
CT10

CT11

CT12

CT13

CT14

CT15

CT16

CT17

CT18

CT19

CT20

CT21

CT22

CT23

CT24
LT3 RT8
1 2 +3VALW 0_0805_5% +USB_VCCB
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+1.05VR +3VA

10U_0805_6.3V6M
BLM18AG601SN1D_2P RT9 0_0402_5% W=80mils
1 1 2

1
0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

CT25
USB30@ 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 LT4 1
USB20_DN1_R 1 2 USB20_DN1_L 1 1 1
2 1 2 CT26 + CT27 CT28
CT31
USB20_DP1_R 4 3 USB20_DP1_L
4 3 2 2 2 2
<BOM Structure> @ WCM-2012-900T_0805

D10

H11
E11
E12

K11
K12

P13
F13
F14

L10

L13
L14
G3
G4

N4
N5
N6

C4
C5
C6
C7
D5

C8
C9
D8
D9

H3
H4

D7
UT1 220U_6.3V_M_R15 1000P_0402_50V7K

P3

E3
E4
F3
1 2

L9

L5

L8
RT10 USB30@ 0_0402_5%

VDD33
VDD33
VDD33

VDD33
VDD33
VDD33

VDD33
VDD33

VDD33
VDD33

VDD33
VDD33
VDD33
VDD33

VDD10
VDD10
VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

VDD10
VDD10

VDD10
VDD10

VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

U3AVDO33

U2AVDD10
+USB_VCCB
<29> CLK_USB30 B2
PECLKP
<29> CLK_USB30# B1
USB30@ PECLKN @
CT29 2
+3V:200mA U3TXDP2
B6
<29> PCIE_PRX_C_USBTX_P6 1 0.1U_0402_16V7K PCIE_PRX_USBTX_P6 D2 USB30PWRON RT11 10_0402_5% 2 USB_CHG_EN JUSB20 @
CT30 2 PCIE_PRX_USBTX_N6 PETXP OCL1# USB_OC#1
<29> PCIE_PRX_C_USBTX_N6 1 0.1U_0402_16V7K D1 +1.05V:800mA A6 RT19 10_0402_5% 2 1 5
USB30@ PETXN U3TXDN2 USB30@ USB20_DN1_L VCC GND

USB20_GND
N8 2 6
U2DM2 USB20_DP1_L D- GND
<29> PCIE_PTX_C_USBRX_P6 F2 3 7
PERXP D+ GND
<29> PCIE_PTX_C_USBRX_N6 F1 P8 4 8
PERXN U2DP2 GND GND
C B8 C
U3RXDP2 P-TWO_CU304G-A0G1G-P
A8
+3VALW U3RXDN2

2
<5,32,39,40,41,44,45> PLT_RST# H2
USB30@ RT12 10_0402_5% 2 USB30_WAKE# PERSTB OCI2#
<30,39,40> EC_SWI# K1 G14 1 RT13 2 10K_0402_5% +3VALW RT14
PEWAKEB OCI2B OCL1#
<29> CLKREQ_USB30# K2 H13 0_0805_5%
PECREQB OCI1B
1

+3VALW RT15 1 2 10K_0402_5% USB20@

RT1 RT16 @1
@ 2 100_0402_1% J2

1
4.7K_0402_5% RT17 10K_0402_5% AUXDET JUSB30
+3VALW 1 2 J1 H14
PSEL PPON2 USB30PWRON U3TXDP1_L
H1 J14 USB30PWRON <44> 9
USB30@ RT18 10_0402_5% 2 USB30_SMI#_R SMI PPON1 SSTX+
<33> USB30_SMI# P4 +USB_VCCB 1
2

SMIB U3TXDN1_L VBUS

8
USB30_POK USB30_POK USB20_DP1_L SSTX-
P5 3
PONRSTB U3TX_C_DP1 CT32 U3TXDP1 D+
B10 2 1 0.1U_0402_16V4Z 7
U3TXDP1 USB30@ USB20_DN1_L GND
2
SPI_CLK_USB U3TX_C_DN1 CT33 U3TXDN1 U3RXDP1_R_L D-
M2 A10 2 1 0.1U_0402_16V4Z 6
SPI_CS_USB# SPISCK U3TXDN1 U2D_DN1_R USB30@ SSRX+
N2 N10 4 10
SPI_SI_USB SPISCB U2DM1 U3RXDN1_R_L GND GND USB30_GND
N1 5 11
SPI_SO_USB SPISI U2D_DP1_R SSRX- GND 0.01U_0402_16V7K
M1 P10
SPISO U2DP1

2
B12 U3RXDP1_R SANTA_371394-1 2 2
U3RXDP1 @ RT21 CT35 CT36
K13 A12 U3RXDN1_R 1M_0402_5% USB30@ USB30@
GND U3RXDN1 USB30@
K14
GND 1 1
J13

1
GND
0.1U_0402_16V4Z
P12 RT22 1 21.6K_0402_1%
RREF
N12
U2AVSS
C14
GND
N11
U2PVSS USB20@
D6 <32> USB20_N3 10_0402_5% 2 RT23 U2D_DN1
U3AVSS USB20@
N14
CLK_48M_USB XT1 U2D_DP1
M14 <32> USB20_P3 10_0402_5% 2 RT24
XT2
U2D_DN1_R 10_0402_5% 2 RT25
2
100_0402_5%
RT26

USB30@
B B
U2D_DP1_R 10_0402_5% 2 RT27
P6
CSEL CSEL=0 24MHz XTAL USB30@

YT1
CSEL=1 48MHz Clock P14
1

GND
A1 P11
GND GND
2

2 1 A2 P9
0_0402_5%

0_0402_5%

GND GND
A3 P7
24MHZ 12PF +-20PPM X5H024000DC1H GND GND
A4 P2
GND GND +5VALW +USB_VCCB
A5 P1 OCP: 2A
GND GND
USB Sleep & Charge
2

A7 N13 W=80mils
0_0402_5%

1 1
RT281

RT291

GND GND
2
12P_0402_50V8J
CT37

12P_0402_50V8J
CT38

@ A9 N9 U4
GND GND
0_0402_5%

2 2
@
RT31
A11
A13
A14
GND
GND
GND
GND
N7
N3
M13
Auto-Mode 1
USB_OC#1
1

13
IN OUT
12

9
<32,44> USB_OC#1
RT301

@ GND GND FAULT# NC

B3 M12
1

+3VALW GND GND C390 0.1U_0402_16V4Z U2D_DN1 USB20_DN1_R

B4 M11 2 11
GND GND 2 U2D_DP1 DM_OUT DM_IN USB20_DP1_R
B5 M10 3 10
GND GND DP_OUT DP_IN
B7 M9
GND GND R101
B9 M8 4 15
GND GND USB_CHG_EN ILIM_SEL ILIM1
B11 M7 <44> USB_CHG_EN 5 16 1 2
<29> 48MCLK_USB30 GND GND DSC ILIM0
B13
GND GND
M6 07/08/2010
B14 M5 SLP_CHG_M4 6 24K_0402_1%
GND GND Need EC to set these signals to high active <32> SLP_CHG_M4
SLP_CHG_M3 CTL1
Place as close as possibile to C1
C2
GND
GND
GND
GND
M4
M3 SLP_CHG, USB_CHG_EN <32> SLP_CHG_M3
<44> SLP_CHG SLP_CHG
7
8
CTL2
CTL3
GND
GPAD
14
17
C3 L12
UU102.N14 and UU102.M14 C10
GND
GND
GND
GND
L11 TPS2541RTER_QFN16_3X3
C11 L7
GND GND
L6
GND
SLP_CHG_M4 SLP_CHG_M3 SLP_CHG Mode
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

0 0 X(1) Dedicated Charging Port, Auto-detect

C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

+3VALW 0 1 X(1) Dedicated Charging Port, BC Specification 1.1 Only (Mode 3)

A A
1 0 X(1) Dedicated Charging Port, Apple Only (Mode 4)
1

UPD720200AF1-XXX-A_FBGA176
1K_0402_5%

10K_0402_5%
RT32

SPI_CLK_USB 1 RT34 2 1 1 0 Standard Downstream Port, USB 2.0 Mode

RT33

0_0402_5%
@ 1
2

0.1U_0402_16V7K~N
CT40

35mA 1 1 1 Charging Downstream Port, BC Specification 1.1

UT4 CT39 Close to UU37.6

www.vinafix.vn
SPI_CS_USB# 1 8 2 10.1U_0402_16V7K~N @
SPI_SO_USB CS# VCC 2
2 7 1 RT35 210K_0402_5%
3
SO
WP#
HOLD#
SCLK
6 1 RT36 20_0402_5% SPI_CLK_USB
SPI_SI_USB
Security Classification Compal Secret Data Compal Electronics, Inc.
4
GND SI
5 Issued Date 200910/9 Deciphered Date 2010/01/23 Title

MX25L5121EMC-20G SOP 8P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-USB3.0 UPD720200A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 42 of 58
5 4 3 2 1
 5 4 3 2 1

RA2
Speaker Connector
+PVDD1 600 mA0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z +5VALW placement near Audio Codec
1 1 0_0603_5% 1 1
CA57 CA44 RA13
CA56 CA43 SPKL+ 2 1 SPK_L1

2
0_0603_5% 1
RA20 JA1 2 2 2 2

2
+3VS 2 1 0.1U_0402_16V4Z +DVDD_IO JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z CA19 DA7 @
FBMH1608HM601-T @ @ 10U_0805_10V4Z 2 2
2

1
1 1 place close to chip CA24 1
CA2 CA1 1 1U_0402_6.3V4Z 3

1
@
+3VS_DVDD 1
D place close to chip 10U_0805_10V4Z
2 2
RA11 CA20 PESD5V0U2BT_SOT23-3 D
+PVDD2 2 1 0.1U_0402_16V4Z +5VALW RA14 @ 10U_0805_10V4Z JSPK
0_0603_5% SPKL- 2 SPK_L2 SPK_L1
1 1 1 1 2 1 1 1
RA1 0.1U_0402_16V4Z 0.1U_0402_16V4Z CA60 @ CA59 CA58 0_0603_5% SPK_L2 2 2
+3VS 2 1 35 mA CA61 @ @ @ RA15 SPK_R1 3 3
FBMH1608HM601-T +AVDD SPKR+ 2 1 SPK_R1 SPK_R2 4
1 1 2 2 2 2 4
0_0603_5% 1
CA8 CA7 10U_0805_10V4Z 10U_0805_10V4Z DA6 @ ACES_85204-0400N
10U_0805_10V4Z RA3 CA25 2 @
2 2 68 mA 10U_0805_10V4Z 0.1U_0402_16V4Z 2 @ 10U_0805_10V4Z
1 +5VALW 2 1
0_0603_5% 2 CA27 3
RA36 RA35 1 1U_0402_6.3V4Z
MIC1_LINE1_R_L @ PESD5V0U2BT_SOT23-3

39

46

25

38
1 1 1 1

9
UA1 CA3 CA4 CA5 CA6 CA26 1
0_0402_5% 0_0402_5% RA30 RA16 @ 10U_0805_10V4Z

PVDD1

PVDD2

AVDD1

AVDD2
DVDD_IO
DVDD
SPKR- 2 SPK_R2
Ext. Mic/LINE IN 0_0402_5%
2 2 2 2
2 1
@ place close to chip 0_0603_5%
10U_0805_10V4Z 0.1U_0402_16V4Z
1U_0402_6.3V4Z CA9
1 2 23 40 SPKL+
RA39 RA38 24
LINE1_L SPK_OUT_L+
41 SPKL- Beep sound
MIC1_LINE1_R_R CA10 1 2
LINE1_R SPK_OUT_L- EC Beep RA7
14 45 SPKR+ 1 2
LINE2_L SPK_OUT_R+ <44> EC_BEEP#
0_0402_5% 0_0402_5% 1U_0402_6.3V4Z 15 44 SPKR- 47K_0402_5%
RA37 4.7U_0805_10V4Z CA21 LINE2_R SPK_OUT_R-
0_0402_5% MIC1_LINE1_R_L 2 1 21 MIC1_L HP_OUT_L 32 RA4 75_0402_1%
HP_L <37>
@ 22 33
MIC1_LINE1_R_R 2 1
MIC1_R HP_OUT_R RA5 75_0402_1%
HP_R <37>
PCI Beep RA8
CA13
16 1 2 1 2 MONO_IN
C 4.7U_0805_10V4Z CA22 MIC2_L <28> PCH_SPKR C
17 MIC2_R 47K_0402_5%
10 AZ_SYNC_HD 0.1U_0402_16V4Z
SYNC AZ_SYNC_HD <28>
INT_MIC_DATA 2 6 AZ_BITCLK_HD
<25> INT_MIC_DATA GPIO0/DMIC_DATA BCLK AZ_BITCLK_HD <28>
INT_MIC_CLK_R 3 GPIO1/DMIC_CLK

1
5 AZ_SDOUT_HD AZ_SDOUT_HD <28> 1
SDATA_OUT
EC_MUTE# 4 8 AZ_SDIN0_HD_R 2 1 RA12 CA18
<44> EC_MUTE# PD# SDATA_IN AZ_SDIN0_HD <28>
RA6 33_0402_5% 10K_0402_5% 0.1U_0402_16V4Z
2
For EMI Change to AGND for

2
<28> AZ_RST_HD#
AZ_RST_HD# 11 RESET# EAPD 47 For EMI high frequency noise issue
SPDIFO 48
RA44 CA11 1 2 MONO_IN 12 @ CA29
100K_0402_5% 0.01U_0402_25V7K CA12 100P_0402_50V8J PCBEEP AZ_BITCLK_HD 2
MONO_OUT 20 1 1 2 @
@ @ 10_0402_5% RA17
SENSE_A 13 SENSE A
29
10P_0402_50V8J Ext.MIC/LINE IN JACK
MIC2_VREFO
For EMI 18 SENSE B
30 +MIC1_VREFO_R CA23 10U_0805_10V4Z RA33 2 RA31 1 +MIC1_VREFO_R
RA41 MIC1_VREFO_R 1K_0402_5% 2.2K_0402_5%
1 2 36 CBP LDO_CAP 28 1 2
INT_MIC_CLK_R CA15 MIC1_LINE1_R_R 2 1
<25> INT_MIC_CLK MIC1_R <37>
FBMA-10-100505-301T 2.2U_0603_6.3V4Z 35 27 AC_VREF
CAM@ CBN VREF
1 +MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1% MIC1_LINE1_R_L 2 1
MIC1_VREFO_L JDREF MIC1_L <37>
CA28 1 1 1K_0402_5%
CA47 1 2 0.1U_0603_50V7K 27P_0402_50V8J 43 34 CPVEE 1 2 RA32 2 RA29 1 +MIC1_VREFO_L
@ PVSS2 CPVEE CA14 2.2U_0603_6.3V4Z CA17 CA16 2.2K_0402_5%
42 PVSS1
B CA48 1 2 B
2 0.1U_0603_50V7K 49 DVSS2 AVSS1 26 2.2U_0603_6.3V6K
2 2 @
7 DVSS1 AVSS2 37
CA49 1 2 0.1U_0603_50V7K 0.1U_0402_16V4Z
+5VALW ALC269Q-VB5-GR _QFN48_7X7
CA50 1 2 0.1U_0603_50V7K place close to chip MIC_SENSE
DGND AGND

6
2 1
RA18 10_0603_5% RA42 QA1A
100K_0402_5% RA28 100K_0402_5%
@ 2N7002DW -T/R7_SOT363-6 2

EC_MUTE# RA22 2 1 4.7K_0402_5%

1
RA43 100K_0402_5%
Sense Pin Impedance Codec Signals Function +3VL
place close to chip RA34 @ 100K_0402_5%
+3VALW
39.2K PORT-I (PIN 32, 33) Headphone out
<44> SM_SENSE#
MIC_SENSE 2 1 SENSE_A

3
20K PORT-B (PIN 21, 22) Ext. MIC RA10 20K_0402_1%
SENSE A QA1B

10K PORT-C (PIN 23, 24) 2N7002DW -T/R7_SOT363-6

5 BACK_SENSE <37>

<37> NBA_PLUG

4
A A
5.1K (PIN 48) RA21 39.2K_0402_1%

39.2K PORT-E (PIN 14, 15)

SENSE B 20K PORT-F (PIN 16, 17)

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

10K PORT-H (PIN 20) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDA-ALC269/HP/MIC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 43 of 58
5 4 3 2 1
 5 4 3 2 1

+3VL R737
+3VL 0_0402_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1 H_PROCHOT# <5>
<55> VR_HOT#
1 1 1 1 2 2 C442
C436 1 2

1
C437 C438 C439 C440 C441 D
For EMI 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z H_PROCHOT#_EC 2 Q41 C518
2 2 2 2 1 1 G 47P_0402_50V8J

2
111
125
0.1U_0402_16V4Z 1000P_0402_50V7K S 2N7002_SOT23

22
33
96

67

3
9
CLK_PCI_EC U19

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1
R377
10_0402_5% BATT_TEMPA 1 2
@ GATEA20 1 21 KB_LED C445 100P_0402_50V8J
<33> GATEA20 GATEA20/GPIO00 PWM0/GPIO0F KB_LED <45>
KB_RST# 2 23 EC_BEEP# ACIN_D 1 2
<33> KB_RST# EC_BEEP# <43>
2
D KBRST#/GPIO01 BEEP#/PWM1/GPIO10 D
1 SERIRQ 3 PWM Output 26 SM_SENSE# C446 100P_0402_50V8J
<28,45> SERIRQ SERIRQ# FANPWM0/GPIO12 SM_SENSE# <43>
C443 LPC_FRAME# 4 27 ACOFF
<28,45> LPC_FRAME# LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13 ACOFF <48,50>
22P_0402_50V8J LPC_AD3 5
<28,45> LPC_AD3 LPC_AD3/LAD3
@ LPC_AD2 7
2 <28,45> LPC_AD2 LPC_AD2/LAD2
LPC_AD1 8 63 BATT_TEMPA
<28,45> LPC_AD1 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38 BATT_TEMPA <49>
LPC_AD0 10 64 TMPTU1_SXP
<28,45> LPC_AD0 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39 TMPTU1_SXP <39> +3VS
LPC & MISC 65 ADP_I TV tuner
ADP_I/AD2/GPI3A ADP_I <50>
CLK_PCI_EC 12 66 ADP_V
<32> CLK_PCI_EC
PLT_RST# 13
CLK_PCI_EC/PCICLK
AD Input
AD3/GPI3B
75 TMPTU2_SXP
ADP_V <50> temperature
<5,32,39,40,41,42,45> PLT_RST# PCIRST#/GPIO05 AD4/GPI42 TMPTU2_SXP <39>
ECRST# 37 76 HDPACT R754 10K_0402_5%
+3VL R378 EC_SCI# EC_RST#/ECRST# AD5/GPI43 HDPACT <45> TMPTU1_SXP
<33> EC_SCI# 20 1 2
47K_0402_5% HDPLOCK EC_SCI#/GPIO0E
<45> HDPLOCK 38
ECRST# CLKRUN#/GPIO1D R757 10K_0402_5%
2 1 68
DAC_BRIG/DA0/GPO3C EN_DFAN1 TMPTU2_SXP
70 EN_DFAN1 <5> 1 2
EN_DFAN1/DA1/GPO3D IREF
2 1 DA Output IREF/DA2/GPO3E
71 IREF <50>
C444 0.1U_0402_16V4Z KSI0 55 72 CHGVADJ R758 10K_0402_5%
KSI0/GPIO30 DA3/GPO3F CHGVADJ <50>
KSI1 56 H_PROCHOT#_EC 1 2
KSI2 KSI1/GPIO31 @
57
KSI3 KSI2/GPIO32 EC_MUTE#
58 83 EC_MUTE# <43>
KSI4 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A USB_EN# +3VL
59 84 USB_EN# <37>
+3VL KSI5 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B CAP_INT#
60 85 CAP_INT# <46>
KSI6 KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C H_PROCHOT#_EC CEC_INT#
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86 2 1
1 2 KSO1 KSI7 62 87 TP_CLK R53 100K_0402_5%
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <46>
R380 47K_0402_5% KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <46>
1 2 KSO2 KSO1 40 CAP_INT# 1 2
R382 47K_0402_5% KSO2 KSO1/GPIO21 R172 4.7K_0402_5%
41
KSO3 KSO2/GPIO22 VGATE
42 97 VGATE <5,30,55>
KSO3/GPIO23 SDICS#/GPXIOA00 +5VS
to avoid EC entry ENE test mode KSO4 43
KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01
98 WOL_EN
WOL_EN <40>
KSO5 PWRME_CTRL#
KSO5/GPIO25 Int. K/B
44 99 PWRME_CTRL# <28>
KSO6 ME_EN/SDIMOSI/GPXIOA02 LID_SW#
45 109
KSO7 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00 LID_SW# <45>
TP_CLK
46
KSO7/GPIO27 SPI Device I/F 1 2
KSO8 47 R379 4.7K_0402_5%
KSO9 KSO8/GPIO28 EC_SI_SPI_SO TP_DATA
48 119 EC_SI_SPI_SO <45> 1 2
C KSI[0..7] KSO10 KSO9/GPIO29 SPIDI/MISO EC_SO_SPI_SI R381 4.7K_0402_5% C
<28,45,46> KSI[0..7] 49 120 EC_SO_SPI_SI <45>
KSO11 KSO10/GPIO2A SPIDO/MOSI SPI_CLK
50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126 SPI_CLK <45>
KSO[0..17] KSO12 51 128 SPI_CS#
<28,45,46> KSO[0..17] KSO12/GPIO2C SPICS# SPI_CS# <45> +3VALW
KSO13 52
KSO14 KSO13/GPIO2D
53
KSO15 KSO14/GPIO2E CIR_IN LID_SW#
54 73 2 1
RP7 KSO16 KSO15/GPIO2F GPIO40 EC_PECI R461 1
81 74 2 43_0402_1% H_PECI <5,33>
47K_0402_5% R383
EC_SMB_CK1 KSO17 KSO16/GPIO48 H_PECI/GPIO41 FSTCHG
+3VL 1 8 82
KSO17/GPIO49 GPIO FSTCHG/GPIO50
89 FSTCHG <50>
2 7 EC_SMB_DA1 90 BATT_FULL_LED#
BATT_CHG_LED#/GPIO52 BATT_FULL_LED# <46>
+3VS 3 6 EC_SMB_CK2 91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <45>
4 5 EC_SMB_DA2 EC_SMB_CK1 77 92 BATT_CHG_LOW_LED#
<27,49> EC_SMB_CK1 EC_SMB_CK1/SCL0/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# <46>
EC_SMB_DA1 78 93 PWR_ON_LED# SYSON 1 2
<27,49> EC_SMB_DA1 EC_SMB_DA1/SDA0/GPIO45 PWR_LED#/GPIO55 PWR_ON_LED# <46>
2.2K_0804_8P4R_5% EC_SMB_CK2 79 95 SYSON R5 4.7K_0402_5%
<14,29,45,46> EC_SMB_CK2 EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 SYSON <39,42,52>
EC_SMB_DA2 80 121 VR_ON
<14,29,45,46> EC_SMB_DA2 EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <55>
127 ACIN_D
AC_IN/GPIO59
SM Bus
PM_SLP_S3# 6 100 PCH_RSMRST#
<30> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PCH_RSMRST# <30>
SLP_S5# 14 101 EC_LID_OUT# R341 330K_0402_5%
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <29>
EC_SMI# 15 102 EC_ON +3VL 1 2
<33> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXIOA05 EC_ON <28,46,51>
USB_CHG_EN 16 103 TP_LED
<42> USB_CHG_EN GPIO0A EC_SWI#/GPXIOA06 TP_LED <46>
ESB_CK 17 104 PM_PWROK D21
<46> ESB_CK GPIO0B ICH_PWROK/GPXIOA07 PM_PWROK <5,30>
ESB_DAT 18 GPIO 105 BKOFF# ACIN_D 2 1
<46> ESB_DAT GPIO0C BKOFF#/GPXIOA08 BKOFF# <25> ACIN <30,46,50>
PCH_SUSPWRDN 19 GPO RF_OFF#/GPXIOA09 106 HDPINT
<30> PCH_SUSPWRDN SUS_PWR_DN_ACK/GPIO0D HDPINT <45>
INVT_PWM 25 107 CAP_RST# CH751H-40PT_SOD323-2
<25> INVT_PWM INVT_PWM/PWM2/GPIO11 GPXIOA10 CAP_RST# <46>
@ FAN_SPEED1 28 108 SA_PGOOD
<5> FAN_SPEED1 FAN_SPEED1/FANFB0/GPIO14 GPXIOA11 SA_PGOOD <53>
1 2 PLT_RST# USB30PWRON 29
<42> USB30PWRON FANFB1/GPIO15
C819 1U_0402_6.3V6K E51_TXD 30
<39> E51_TXD EC_TX/GPIO16
E51_RXD 31 110 CEC_INT#
<39> E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 CEC_INT# <27> +3VALW
@ ON/OFFBTN# 32 112 EC_ENBKL
<46> ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXIOD02 EC_ENBKL <25>
1 2 SUSP# PWR_SUSP_LED# 34 114 USB_OC#1
<46> PWR_SUSP_LED# SUSP_LED#/GPIO19 EAPD/GPXIOD03 USB_OC#1 <32,42>
C820 180P_0402_50V8J NUM_LED# 36 GPI EC_THERM#/GPXIOD04 115 SLP_CHG
<45> NUM_LED# NUM_LED#/GPIO1A SLP_CHG <42>
116 SUSP# SLP_CHG 2 @ 1
SUSP#/GPXIOD05 SUSP# <28,39,47,52,54,56>
B 117 PBTN_OUT# R1428 10K_0402_5% B
PBTN_OUT#/GPXIOD06 PBTN_OUT# <5,30>
118 USB_OC#0
EC_PME#/GPXIOD07 USB_OC#0 <32,37>
CRY1 122
@ XCLK1
<30> CLK_EC 1 2 CRY2 123 124 +EC_V18R
R565 0_0402_5% XCLK0 V18R R439 2
Close to EC SLP_CHG 1 10K_0402_5%
AGND
GND
GND
GND
GND
GND

C448 SUSP# R423 2 1 10K_0402_5%

4.7U_0805_10V4Z
KB930QF-A1_LQFP128_14X14 VR_ON R462 2 1 10K_0402_5%
11
24
35
94
113

69

+3VALW

2
C818
1
CIR
+5VL
5

U44 0.1U_0402_16V4Z
1
P

<30> PM_SLP_S5# IN1

2
4 SLP_S5#
O R748
<30> PM_SLP_S4# 2
IN2
G

10K_0402_5%
SN74AHC1G08DCKR_SC70-5 R389
3

CRY1 1 2 CRY2

1
U45
10M_0402_5% CIR_IN 1
@ Vout
+5VL 1 CIR@ 2 +5VL_CIR 2
R750 100_0805_5% VCC
1 1 3
@ @ C783 GND
1

A C449 C450 4.7U_0805_10V4Z 4 A

Y4 CIR@ GND
18P_0402_50V8J

18P_0402_50V8J
OSC

OSC

2 2 IRM-V538/TR1
@ CIR@
1 2 E51_TXD
NC

NC

R342 100K_0402_5%

1 2 USB30PWRON
2

www.vinafix.vn
R492 100K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title
32.768KHZ_12.5PF_Q13MC14610002
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPC-EC-KB930
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 44 of 58
5 4 3 2 1
 Place the PAD under DDR DIMM.
SPI Flash (256KB) Lid SW LPC Debug Port
+3VS H7 @
+3VL
6 5

1 20mils
C451 U22 1 2 7 4
<28,44> SERIRQ PLT_RST# <5,32,39,40,41,42,44>
8 4 R392 0_0402_5%
0.1U_0402_16V4Z VCC VSS +3VALW
2
3 W <28,44> LPC_AD3 8 3 LPC_AD2 <28,44>
U21
7 APX9132ATI-TRL_SOT23-3
HOLD
<28,44> LPC_AD1 9 2 LPC_AD0 <28,44>
SPI_CS# 1 2 3

GND
<44> SPI_CS# S VDD VOUT LID_SW # <44>
SPI_CLK 6 10 1
<44> SPI_CLK C <28,44> LPC_FRAME# CLK_PCI_DDR <32>
1 1

1
EC_SO_SPI_SI 5 2 EC_SI_SPI_SO
<44> EC_SO_SPI_SI D Q EC_SI_SPI_SO <44>

2
C453 C452
MX25L2005CMI-12G SO8 0.1U_0402_16V4Z 10P_0402_50V8J DEBUG_PAD R393
2 2 22_0402_5%
@

1
2
SPI_CLK 1 R394 2 1 2
10_0402_5% C454 10P_0402_50V8J C457
@ @ 22P_0402_50V8J
1 @
For EMI
For EMI

UG1 GSENSOR@ GSENSOR@

Keyboard LED JBLG G-Sensor +3VS_HDP 2
12
Vdd1
Vdd2
Voutx
Vouty
3
5
VOUTXCG1
VOUTYCG2
1
1
2
2
0.033U_0402_16V7K
0.033U_0402_16V7K
1 +5VS_LED 7 VOUTZCG3 1 2GSENSOR@
0.033U_0402_16V7K
1 Voutz GSENSOR@
Q38 2 2
KBL@ 3 RG2 @ SELF_TEST 4 10
+5VS AO3413_SOT23-3 3 ST NC1
4 4 +3VS 2 1 +3VS_HDP 6 PD NC2 11
GND 5 8 FS NC3 14 Reserve for 2nd Source
S

3 1 +5VS_LED 6 0_0603_5% 15
GND NC4
1 NC5 16
1

ACES_85201-0405N
R587 C836 @ +5VS GSENSOR@ +3VS_HDP 9 1 +3VS_HDP
G

+3VS_HDP
2

10K_0402_5% 0.1U_0402_16V4Z DG1 CH751H-40PT_SOD323-2 Rev GND1 CG9 0.1U_0402_16V4Z UG4 @

GND2 13
KBL@ 2 KBL@ @
1 2 2 1VOUTX2 6
2 2 TSH35TR_LGA16 CG10 0.1U_0402_16V4Z XOUT VDD
2

For EMI CG12 UG3 GSENSOR@ @ 2 1VOUTY3

1U_0402_6.3V4Z CG13 CG11 0.1U_0402_16V4ZYOUT 1
NC
D Close to JKB GSENSOR@ 1 VIN VOUT 5
1U_0402_6.3V4Z
Place UG1 and UG4 @ 2 1VOUTZ4 ZOUT NC 8
1

1 1 GSENSOR@
NC 11
<44> KB_LED 2
G
Q52
2N7002_SOT23-3
KSO16 1
C401
2
100P_0402_50V8J
2 GND CG14
on TOP Layer 9 0G-DET NC 12
NC 14
S KBL@ KSO17 1 2 3 4 2 1 +3VS_HDP 7
3

C402 100P_0402_50V8J SHDN# BP SLEEP#

10 G-SELECT
KSO2 1 2 @ SELF_TEST 13 5
C404 100P_0402_50V8J G9191-330T1U_SOT23-5 0.22U_0402_10V4Z ST VSS
KSO1 1 2 MMA7360LR2_LGA14
C405 100P_0402_50V8J
KSO0 1 2
C406 100P_0402_50V8J
KSO4 1 2
KEYBOARD CONN. KSO3
C407
1
100P_0402_50V8J
2
UG5

C408 100P_0402_50V8J 1 11 HDPACT <44>

<14,29,44,46> EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01
KSO5 1 2

2
KSI[0..7] C409 100P_0402_50V8J
KSI[0..7] <28,44,46>
KSO14 1 2 SELF_TEST 2 12 RG9
KSO[0..17] C410 100P_0402_50V8J P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 47K_0402_5%
KSO[0..17] <28,44,46>
KSO6 1 2 GSENSOR@
C411 100P_0402_50V8J +3VS_HDP RG3 2 1 3 13

1
KSO7 GSENSOR@ 4.7K_0402_5% RESET# P1_4/TXD0
1 2
JKB C412 100P_0402_50V8J
JKB34 1 2 +3VS KSO13 1 2 RG4 2 1GXOUT 4 14 HDPLOCK <44>
34 KSO16 R372 300_0402_5% C413 100P_0402_50V8J GSENSOR@ 4.7K_0402_5% XOUT/P4_7 P1_3/KI3#/AN11/TZOUT
33 KSO8 RG10 47K_0402_5%
32 1 2
KSO17 C415 100P_0402_50V8J 5 15 VOUTZ 2 1
31 KSO9 VSS/AVSS P1_2/KI2#/AN10/CMP0_2 GSENSOR@
30 1 2
C416 100P_0402_50V8J
29 KSO2 KSO10 RG5 2
28 1 2 1GXIN 6 XIN/P4_6 P4_2/VREF 16 +3VS_HDP
KSO1 C417 100P_0402_50V8J GSENSOR@ 4.7K_0402_5%
27 KSO0 KSO11
26 1 2 1
KSO4 C418 100P_0402_50V8J 7 17 VOUTX CG6
25 KSO3 KSO12 VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_16V4Z
24 1 2
KSO5 C419 100P_0402_50V8J GSENSOR@
23 KSO14 KSO15 RG6 2
22 1 2 2 1 4.7K_0402_5% 8 MODE P1_0/KI0#/AN8/CMP0_0 18 VOUTY
KSO6 C420 100P_0402_50V8J GSENSOR@
21 KSO7 KSI7
20 1 2
KSO13 C421 100P_0402_50V8J HDPINT RG7 2 1 1K_0402_5% 9 19
19 KSO8 KSI2 <44> HDPINT GSENSOR@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
18 1 2
KSO9 C422 100P_0402_50V8J
17 KSO10 KSI3
16 1 2 1 1 10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA2 <14,29,44,46>
KSO11 C423 100P_0402_50V8J CG8
15 KSO12 KSI4 CG7 GSENSOR@
14 1 2
KSO15 C424 100P_0402_50V8J 0.1U_0402_16V4Z 0.1U_0402_16V4Z R5F211B4D34SP GSENSOR@
13 KSI7 KSI0 GSENSOR@ 2 2
12 1 2
KSI2 C425 100P_0402_50V8J
11 KSI3 KSI5
10 1 2
KSI4 C427 100P_0402_50V8J
9 KSI0 KSI6
8 1 2
KSI5 C429 100P_0402_50V8J
7 KSI6 KSI1
6 1 2
KSI1 C431 100P_0402_50V8J
5
4
JKB4 2 1 +3VS CAPS_LED# 1 2
Security Classification Compal Secret Data Compal Electronics, Inc.
CAPS_LED# R376 300_0402_5% C433 100P_0402_50V8J 200910/9 2010/01/23 Title
CAPS_LED# <44> Issued Date Deciphered Date

www.vinafix.vn
3 NUM_LED#
2 NUM_LED#
NUM_LED# <44>
1
C435
2
100P_0402_50V8J SPI ROM/LID/Debug/KB/G-Sen
1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ACES_88170-3400 0.1
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 45 of 58
 5 4 3 2 1

+3VL
Power Button Caps Sensor/Light Sensor Conn. Touchpad & Light Pipe Connector

2
For debug R395 JCS @
+5VALW 1 SW1
100K_0402_5% 1 SW_L
51_ON# <48> +3VL 2 1 3
FBMA-11-100505-301T_0402 +3VS 2
3

1
ON/OFFBTN# L13 1 ESB_DAZ 3
ON/OFFBTN# <44> <44> ESB_DAT 2 4 2 4
4

6
TOP side L14 1 2 ESB_CKZ 5
<44> ESB_CK 5
1 Q7A FBMA-11-100505-301T_0402 CAP_INT# 6 SMT1-05_4P
<44> CAP_INT#

6
5
C458 2N7002DW-T/R7_SOT363-6 CAP_RST# 6
<44> CAP_RST# 7
0.1U_0402_25V6 7
2 <14,29,44,45> EC_SMB_CK2 8
@ <28,44,51> EC_ON 8
<14,29,44,45> EC_SMB_DA2 9
9

2
2
10

1
SW3 R396 10
11
GND JTPL @
1 3 10K_0402_5% 12
D GND D
1
+5VS 1
BTM side 2 4 For EMI request P-TWO_161021-10021
<44> TP_CLK 2

1
2
<44> TP_DATA 3
SMT1-05-A_4P SW_L 3
4
6
5

SW_R 4 SW4
5
5 SW_R
6 1 3
JPOWER TP_LED# 6
For EMI 7
7
1 PWR_ON_LED# KSI6 8 2 4
1 <28,44,45> KSI6 8
2 1 2 KSO0 9
2 +5VALW <44,45> KSO0 9
3 ON/OFFBTN# R22 390_0402_5% @ R428 C260 @ 10 SMT1-05_4P

6
5
3 10

3
4 ESB_DAZ 1 2 1 2 11
4 GND
5 12
G1 100_0402_5% 100P_0402_50V8J Q7B GND
6
G2 P-TWO_161021-10021
5
ACES_85201-0405N D83 @ R427 C261 @ <44> TP_LED
@ ON/OFFBTN# 2 ESB_CKZ 1 2 1 2 2N7002DW-T/R7_SOT363-6

4
1
PWR_ON_LED# 3 100_0402_5% 100P_0402_50V8J

PJSOT05C_SOT23-3

Screw Hole
H5 H6 H8 H9 H10 H11 H12 H13 H14
DC-IN LED ACIN <30,44,50> WiMAX LED H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
R506 @ @ @ @ @ @ @ @ @
WIMAX_LED_GND# 1 2 LED_WIMAX# <39>

1
2

Q32 0_0402_5%
G

2
@
DC_IN 1 3 R819
2 1 6 1
D

+5VS
10K_0402_5% H1 H26

5
C 2N7002_SOT23-3 WIMAX@ Q156A H_2P7x3P2N H_2P7N C
2N7002DW-T/R7_SOT363-6 @ @
WIMAX_LED_GND# 3 4 WIMAX@

1
Q156B 2N7002DW-T/R7_SOT363-6
WIMAX@ VGA
H2 H3 H4
H_2P9 H_2P9x3P9 H_2P9x3P9
@ @ @

1
MINI CARD -- 3G
HDD LED SATA_LED# <28>
Logo LED
2

LOGO_LED <33> CPU H15 H16 H17

+5VS 2 R404 1 6 1 H_3P3 H_3P3 H_3P3

5
10K_0402_5% D22 H20 H21 H22 H23 @ @ @
5

Q9A HT-SV116BP_WHITE H_4P2 H_4P2x4P7 H_4P2x4P7 H_4P7

1
2N7002DW-T/R7_SOT363-6 1 2 2 1 LOGO_LED# 3 4 @ @ @ @
+5VS
HDD_LED# 3 4 R774 120_0402_5%

1
2N7002DW-T/R7_SOT363-6
Q9B 2N7002DW-T/R7_SOT363-6 Q6B
1 @ 2
R50 0_0402_5% 1 2 2 1
R776 120_0402_5% MINI CARD -- WLAN
HT-SV116BP_WHITE
D20 H18 H19
H_3P3 H_3P3
@ @

1
B
PCB Fedical Mark PAD B

FD1 FD2 FD3 FD4

@ @ @ @

LED/B Connector

1
JLED @
ISPD
+5VALW 1
1
+5VS 2
WIMAX_LED_GND# 2 UV1 N12PGSR3@ UV1 N12MGER1@ U2 Q65R3@ ZZZ
3
WL_BT_LED# 3
<33> WL_BT_LED# 4
DC_IN 4
5
PWR_ON_LED# 5
<44> PWR_ON_LED# 6
PWR_SUSP_LED# 6
<44> PWR_SUSP_LED# 7
HDD_LED# 7
8
CR_LEDCON# 8 N12P-GS-A1 N12M-GE-B-B1 PCH PCB LA-6831P
<41> CR_LEDCON# 9
BATT_FULL_LED# 9
<44> BATT_FULL_LED# 10
BATT_CHG_LOW_LED# 10
<44> BATT_CHG_LOW_LED# 11 13
11 GND UV1 N12PGER1@ UV1 N12MGER3@ U2 Q67R1@ PJP1 45@
12 14
12 GND

ACES_85201-1205N

N12P-GE-A1 N12M-GE-B-B1 PCH PJP1

UV1 N12PGER3@ U2 Q67R3@

A A

N12P-GE-A1 PCH

www.vinafix.vn
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR/Cap./TP/LED/LP/LS/Screw
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 46 of 58
5 4 3 2 1
 A B C D E

+3VALW TO +3VS +5VALW TO +5VS +1.5V to +1.5VS

Vgs=10V,Id=9A,Rds=18.5mohm +1.8VS
+3VALW +3VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW +5VS +1.5V +1.5VS
4.7U_0805_10V4Z

2
4.7U_0805_10V4Z +5VS Vgs=10V,Id=14.5A,Rds=6mohm
1 1 1 1 1 1 R470
Q29 C459 C460 4.7U_0805_10V4Z Q30 C461 C462 Q31 C463 C464 470_0805_5%

470_0805_5%

470_0805_5%

470_0805_5%
8
D S
1 8
D S
1 For EMI 8
D S
1

2
7 2 7 2 1U_0402_6.3V4Z 7 2

1
D S 2 2 D S 2 2 D S 2 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
6 3 R406 6 3 R407 6 3 R408
D S D S D S
5 4 5 4 2 2 5 4
D G 1U_0402_6.3V4Z D G C822 C821 D G 1U_0402_6.3V4Z

1
1 SI4800BDY_SO8 D 1
1 R409 2 +VSB SI4800BDY_SO8 1 R410 2 +VSB FDS6676AS_SO8 1 R411 2 +VSB Q190

3 1

3 1

3 1
0.022U_0402_25V7K

0.01U_0402_25V7K
4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 47K_0402_5% 1 1 47K_0402_5% @ @ 1 1 220K_0402_5% 2 SUSP

6
1 1

0.1U_0402_25V6
C466 G

C470
C465 R412 Q10A C467 C468 R413 Q11A C469 R414 Q12A S 2N7002_SOT23-3

3
330K_0402_5% Q10B 200K_0402_5% Q11B 820K_0402_5% Q12B
2 2 SUSP 2 2 @ SUSP 2 2 SUSP
2 5 2 5 2 5
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
2

2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

4
Q43 C473
+1.5V to +VRAM_1.5VS FDS6676AS_SO8
OPT@
4.7U_0805_10V4Z
OPT@
+3VALW

C481 C478 For S3 CPU Power Saving

0.1U_0402_25V6 1U_0402_6.3V4Z

2
OPT@ OPT@ +5VALW +0.75VS +1.05VS_VCCP
+1.5V +VRAM_1.5VS R430 C475 R425
820K_0402_5% 4.7U_0805_10V4Z 100K_0402_5%

2
Vgs=10V,Id=14.5A,Rds=6mohm OPT@ OPT@
R431 R146 R422 R421 R468

1
1 1 220K_0402_5% 100K_0402_5% 100K_0402_5% 22_0805_5% 470_0805_5%
0.75VR_EN# <54>
Q43 DIS@ C478 C475 OPT@ OPT@

3
8 1 DIS@ 4.7U_0805_10V4Z 470_0805_5% R429 Q188

1
D S
2

7 2 DIS@ 470_0805_5% 2N7002_SOT23-3 SUSP

D S 2 2 <5,9,54> SUSP
6 3 R429 OPT@ OPT@ Q44B
D S

6
5 4 DIS@ Q13 <53,54> VCCPPWRGD 1 2 0.75VR_EN 5 2N7002DW-T/R7_SOT363-6
D G

1
2 1U_0402_6.3V4Z DIS@ 2N7002DW-T/R7_SOT363-6 R158 100K_0402_5% Q6A D Q189 D Q60 2
FDS6676AS_SO8 1 R431 2 +VSB OPT@ 2 SUSP 2 2N7002_SOT23-3
3 1

4
6
4.7U_0805_10V4Z

1 1 220K_0402_5% Q44A 2 G G
<28,39,44,52,54,56> SUSP#
1

6
0.1U_0402_25V6

2N7002DW-T/R7_SOT363-6 S 2N7002_SOT23-3 S

3
C473 C481 R430 Q13A 2N7002DW-T/R7_SOT363-6

1
DIS@ DIS@ 820K_0402_5% DIS@ Q13B SUSP 2
2 2 DIS@ 2 VGA_PWROK# 5 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6 DIS@
2

1
1

+5VALW

R146
1 DIS@ 2

100K_0402_5%
+3VS to +3VS_DGPU
1

D
2 Q188
<13,32,33,56> VGA_PWROK
G 2N7002_SOT23-3 +5VS_ODD
S DIS@
3

+3VS
+3VALW +5VS TO +5VS_ODD

2
R457
470_0805_5%

2
2
R433 C491 Vgs=-4.5V,Id=3A,Rds<97mohm

6 1
100K_0402_5% 0.1U_0402_16V7K
OPT@ OPT@

1
1 Q53A
+1.05VS_VCCP to +1.05VS_DGPU 1

3
S
R426 Q54
G R104
DGPU_PWR_EN# 1 2 2 0_0805_5% 2 ODD_EN#
3 DIS@ 3
47K_0402_5% AO3413_SOT23 D +3VS_DGPU 2N7002DW-T/R7_SOT363-6
2

1
6

OPT@ OPT@ +5VS

Q206A C492
OPT@ OPT@ 0.01U_0402_25V7K
2 1 +3VS +5VS
<13,32,56> DGPU_PWR_EN 1
2N7002DW-T/R7_SOT363-6
Short PJ33 for Discrete SKUs C683
1
C684 2
1

2
4.7U_0805_10V4Z 1U_0402_6.3V4Z C471 Vgs=-4.5V,Id=3A,Rds<97mohm
@ 2 OPT@ R441 0.1U_0402_16V7K
+1.05VS_VCCP +5VALW 2 10K_0402_5%

2
1

3
S
+1.05VS_DGPU R440 Q45 PJ28

2
1
2

G
Vgs=4.5V,Id=3A,Rds<22mohm <33> ODD_EN# 3 1 1 2 2 JUMP_43X79
R434

D
@
2

+5VS_ODD

1
47K_0402_5% 47K_0402_5% 2
D

1
1

Q56 OPT@ R460 2N7002_SOT23-3 AO3413_SOT23

1
1

PJ33 D 470_0805_5% +3VS_DGPU +VGA_CORE C217

Q51
1

JUMP_43X118 2 OPT@ 0.01U_0402_25V7K

@ G 1
1
1

2
2

S 2 1
3

AO3416_SOT23-3 C493 R458 R459 C680

2

OPT@ 0.01U_0402_25V7K 470_0805_5% 470_0805_5% C679 1U_0402_6.3V4Z

OPT@ Q207A OPT@ OPT@ 4.7U_0805_10V4Z 2
1 Q207B @ 2
3 1

2 DGPU_PWR_EN# 5
+1.05VS_DGPU 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
OPT@ OPT@
1

Q206B D Q55
1 1
C685 C686 2N7002DW-T/R7_SOT363-6 5 DGPU_PWR_EN# 2 2N7002_SOT23-3
4.7U_0603_6.3V6K 1U_0402_6.3V4Z OPT@ G OPT@
@ OPT@ S
4

4 2 2 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-DC INTERFACE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 47 of 58

www.vinafix.vn
A B C D E
 A B C D

PreCHG PQ1
VIN TP0610K-T1-E3_SOT23-3
PL1 PD1
PR1
PF1 SMB3025500YA_2P
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2
VIN 1 2 2 1 3 1 B+
1K_1206_5%
@ PJP1 LL4148_LL34-2
10A_125V_451010MRL PR2
+ 1 1 2

1000P_0402_50V7K

1000P_0402_50V7K

100P_0402_50V8J
100P_0402_50V8J
1K_1206_5%

1
+ 2

1
PR5

PC4
PR4

PC1

PC2
PR3

2
PC3
1 1

- 3 1 2
100K_0402_5% 100K_0402_5%
1K_1206_5%

2
4

2
-
PR6
SINGA_2DW -0005-B03 1 2

1
1K_1206_5%
PR7
100K_0402_5%

1 2
1
VIN PD2
<44,50> ACOFF 2
1 2 2

2
<51> +5VALW P 3
PD3
RB715F_SOT323-3 PQ2 PQ3
RLS4148_LL34-2

3
DTC115EUA_SC70-3 DTC115EUA_SC70-3

1
1

1
PR8 PR9
PQ4 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3

2
PD4
2 1 N1 3 1
2
BATT+ VS 2

RLS4148_LL34-2
1

PR10 PC6

1
100K_0402_1% 0.22U_0603_25V7K PC5
RTC Battery
2

0.1U_0603_25V7K
2

2
PR11
<46> 51_ON# 1 2
22K_0402_1%
- @ PBJ1
+ PR12 PR13
2 1 1 2 1 2 +RTCBATT
560_0603_5% 560_0603_5%

@ PJ152 MAXEL_ML1220T10
@ PJ332 @ PJ76 2 2 1 1
+3VALW P 2 2 1 1 +3VALW +0.75VSP 2 2 1 1 +0.75VS JUMP_43X118
JUMP_43X118 JUMP_43X79
@ PJ153 SP093MX0000
(5A,200mils ,Via NO.= 10) (1A,40mils ,Via NO.= 2)
+1.5VP 2 1 1 +1.5V
OCP=8.6A 2
JUMP_43X118
@ PJ352 @ PJ452 (16A,640mils ,Via NO.= 32)
+5VALW P 2 2 1 1 +5VALW +VCCSAP 2 2 1 1 +VCCSA

JUMP_43X118 JUMP_43X118

3
(5A,200mils ,Via NO.= 10) (6A,240mils ,Via NO.= 12) @ PJ402
3

OCP=7.9A 2 2 1 1

JUMP_43X118
@ PJ182 @ PJ333 @ PJ403
+1.8VSP 2 2 1 1 +1.8VS +3VLP 2 2 1 1 +3VL +1.05VS_VCCPP 2 2 1 1 +1.05VS_VCCP
JUMP_43X118 JUMP_43X39 JUMP_43X118
(1.65A,70mils ,Via NO.= 4) (100mA,40mils ,Via NO.= 2) (17A,680mils ,Via NO.=34)
OCP=4.2A

@ PJ2 @ PJ502
+VSBP 2 2 1 1 +VSB 2 2 1 1
JUMP_43X39 JUMP_43X118
(120mA,40mils ,Via NO.= 1) @ PJ503
+GFX_COREP 2 2 1 1 +GFX_CORE
JUMP_43X118
(33A,1320mils ,Via NO.=66)
@ PJ602 OCP=40A
2 2 1 1
JUMP_43X118 ACIN
@ PJ603 Precharge detector
Min. typ. Max.
4 4
+VGA_COREP 2 2 1 1 +VGA_CORE
JUMP_43X118
(30A,1200mils ,Via NO.=60)
H-->L 14.42V 14.74V 15.23V
L-->H 15.39V 15.88V 16.39V

www.vinafix.vn
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2009/04/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/VIN DECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. NHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 48 of 58
A B C D
 A B C D

1
VMB 1

PL2
PH1 under CPU botten side :
@ PJP2 PF2 SMB3025500YA_2P
1 BATT_S1 1 2 1 2
CPU thermal protection at 95 degree C
1 BATT+
2 2
3 BATT_P3 15A_65V_451015MRL
Recovery at 56 degree C
3 BATT_P4
+3VLP
4 4
5 BATT_P5
5

1
10 6 EC_SMDA PC8
GND 6 PC7

1
11 7 EC_SMCA
GND 7 PR14 1000P_0402_50V7K 0.01U_0402_25V7K
12 8

2
GND 8 1K_0402_1%
13 GND 9 9

SUYIN_200045MR009G171ZR

2
@ PD6
VL
1

PJSOT24C_SOT23-3

1
@ PD5 2
PJSOT24C_SOT23-3 1 PR15
3

1
PR16 19.6K_0402_1%
6.49K_0402_1% PC9
2

2
2 1 0.1U_0603_25V7K

2
+3VLP

2
PR18
1

8.66K_0402_1%
PR19 PU1

1
2 2
1 8

1
1K_0402_1% VCC TMSNS1
PH1
2 7
2

GND RHYST1
2

100K_0402_1%_NCP15W F104F03RC
PR20 PR21 BATT_TEMPA <44> 3 6

2
OT1 TMSNS2
100_0402_1% 100_0402_1%
4 OT2 RHYST2 5
<51> VS_ON
1

G718TM1U_SOT23-8
EC_SMB_DA1 <27,44>

EC_SMB_CK1 <27,44>

PQ5
TP0610K-T1-E3_SOT23-3

B+ 3 1 +VSBP
3 3
0.22U_0603_25V7K
100K_0402_1%
1

PC10
1

1
PR23

PC11 @
VL @ 0.1U_0603_25V7K
2

2
2

PR24
2

1 2
PR25 22K_0402_1%
100K_0402_1%
1

D
PR26
1 2 2 PQ6
<30,51> POK
G SSM3K7002FU_SC70-3
0_0402_5%
S
3
1

@ PC12
.1U_0402_16V7K
2

4 4

www.vinafix.vn
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/11/13 Deciphered Date 2009/04/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 49 of 58
A B C D
 A B C D

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
@ @ @ PQ208 AO4407A_SO8
1 8

1
PC207

PC208

PC209
2 7
3 6
CHG_B+ 5
B+

2
PQ203 P2 PQ204 P3 PR215
AO4407A_SO8 AO4407A_SO8 0.015_1206_1% PJ201

4
VIN 8 1 1 8 1 4 2 2 1 1
7 2 2 7 PQ207 AO4407A_SO8
6 3 3 6 2 3 @ JUMP_43X118 CSIN 1 8
5 5 2 7
3 6

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
CSIP 5

1
1 1

PC231

PC232

PC233
VIN PreCHG

2
PR236

4
PC211
1 2
VIN

2
1

5600P_0402_25V7K
47K_0402_1%

1
1

2
0.1U_0603_25V7K

6251VDD
PR210
200K_0402_1% PR212 PR226 PR237

2
ACSETIN

PC210
200K_0402_1% 191K_0402_1% 10K_0402_1%
2

2.2U_0603_6.3V6K
PD201

1 1
PQ210 RB751V-40_SOD323-2 ACSETIN

1000P_0402_25V8J
1
PC212
DTA144EUA_SC70-3

1 1
3

1
1
PC217
2
PR228
PR227 14.3K_0402_1% PQ215
2 2

2
PR216 10_1206_5% DTC115EUA_SC70-3

2
10K_0402_1%

2
<44> FSTCHG 2 1 PU200
1

1
PC218 PC222

3
1 24 DCIN 2 1 PR238 2200P_0402_25V7K
1

VDD DCIN
1

2
0.1U_0603_25V7K 100K_0402_1%
PR213 PR217
BATT_ON 2 2 23 ACPRN <51>

2
PQ211 150K_0402_1% 100K_0402_1% ACSET ACPRN
DTC115EUA_SC70-3 PR229 20_0402_5%
2

2
6251_EN 3 22 1 2 CSON BATT_ON
6

D EN CSON

1
D
PC219
3

5
6
7
8
2 0.047U_0402_16V7K ACPRN 2
G 4 21 1 2 CSOP G

1
CELLS CSOP
PR230 20_0402_5% PQ201 PQ216 S

3
S PQ212A PC213
AO4466_SO8
1

2
DMN66D0LDW -7_SOT363-6 1 2 5 20 PR2312 1 20_0402_5% 2N7002W -T/R7_SOT323-3 2

ICOMP CSIN

2
PC220 4
PQ212B PC214 PR218 6800P_0402_25V7K
0.1U_0603_25V7K
DMN66D0LDW -7_SOT363-6 1 2 1 2 6 19 1 2

1
VCOMP CSIP PL202
3

D
10K_0402_1% PR232 2_0402_5% PR235
5 0.01U_0402_25V7K PR219 10UH_MSCDRI-104A-100M-E_4.6A_20% BATT+

3
2
1
G 1 2 7 18 LX_CHG 1 2 CHG 1 4
<44> ADP_I ICM PHASE
47K_0402_1%

1
5
6
7
8
S PC215 2 3
4

PR211 1 2 6251VREF 8 17 DH_CHG PQ202

47K_0402_5% PR220 VREF UGATE @ PR206
AO4466_SO8 0.02_1206_1%
PACIN 154K_0402_1% PC205 4.7_1206_5%

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
1 2 .1U_0402_16V7K PR205
<44> IREF 2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1 @

2
CHLIM BOOT

1
0_0603_5% 4
1

1
0.01U_0402_25V7K

0.1U_0603_25V7K

PC202

PC203

PC204
PR222 PD202
1

1
6251VREF
1 2 6251aclim 10 15 6251VDDP
ACLIM VDDP
1

PQ213 RB751V-40_SOD323-2 @ PC206

PC216

2
PR221 75K_0402_1%
DTC115EUA_SC70-3 1 2 6251VDD 680P_0603_50V7K

2
3
2
1
ACOFF 2 120K_0402_1% 11 14 DL_CHG PR233 4.7_0603_5%
<44,48> ACOFF
2

VADJ LGATE
1

2
2

PC221
PR223 12 13 4.7U_0603_6.3V6M

1
GND PGND
20K_0402_1%
3

G5209S31U_SSOP24

PR224
<44> CHGVADJ 1 2
3
15.4K_0402_1% 3
2

PR225
31.6K_0402_1%

VIN
1

6251VDD

1
PR241
1

10K_0402_1% PR246
PR240 1 2 ACIN <30,44,46>
PR242 309K_0402_1%
47K_0402_1%
10K_0402_1% PR247

2
10K_0402_1%
2

PACIN 1 2 ADP_V <44>

1

1
PQ214

1
DTC115EUA_SC70-3 PR248 PC223
1

ACPRN 47K_0402_1% .1U_0402_16V7K

2 PR243

2
14.3K_0402_1%

2
CC=0.25A~3A
2

CP mode Vin Detector

3

IREF=1.016*Icharge
Iada=0~3.42A(65W) CP= 92%*Iada; CP=3.147A
IREF=0.254V~3.048V
4
Vaclim=1.08V(65W) PR68=75k PR45=0.02 High 18.089V 4

VCHLIM need over 95mV

Iada=0~3.947A(75W) CP= 92%*Iada; CP=3.63A - Low 17.44V
Vaclim=0.736V(75W) PR68=24k PR70=20k PR49=0.02
CHGVADJ=(Vcell-4)*9.445
Iada=0~4.737A(90W) CP= 92%*Iada; CP=4.36A

www.vinafix.vn
Vaclim=0.736V(90W) PR68=53.6k PR70=20k PR49=0.015
Vcell CHGVADJ Security Classification Compal Secret Data Compal Electronics, Inc.
4V 0V Issued Date 2010/01/25 Deciphered Date 2009/04/28 Title
Iada=0~6.316A(120W) CP= 92%*Iada; CP=5.81A CHARGER
4.2V 1.882V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Vaclim=0.736V(120W) PR68=8.25k PR70=26.7k PR49=0.015 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
4.35V 3.2935V Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 50 of 58
A B C D
 5 4 3 2 1

2VREF_8205

D D

1
PC363
1U_0603_10V6K

2
PR362 PR364
13K_0402_1% 30K_0402_1%
1 2 1 2

PR363 PR365
RT8205_B+ 20K_0402_1% 19.1K_0402_1%
1 2 1 2 RT8205_B+
PJ331
@ JUMP_43X118

ENTRIP1
ENTRIP2
B+ 2 2 1 1 +3VLP PR337 PR357
150K_0402_1% 150K_0402_1%
1 2 1 2

1
PC366
1

PC360 10U_1206_25V6M

4.7U_0805_10V6K
8
7
6
5

5
6
7
8
PU330
10U_1206_25V6M

2
1
PQ331 PQ351

PC361

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
2

C AO4466L_SO8 C
25

2
P PAD
4 4
7 VO2 VO1 24 POK <30,49>

PC335 8 VREG3 PGOOD 23 PC355

PR335 PR355 AO4466L_SO8
1
2
3

3
2
1
0.1U_0603_25V7K
1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2 0.1U_0603_25V7K
PL332 0_0603_5% 0_0603_5% PL352
UG_3V 10 21 UG_5V
4.7UH_SIL1045R-4R7PF_6.3A_30% UGATE2 UGATE1 4.7UH_SIL1045R-4R7PF_6.3A_30%
LX_3V LX_5V
+5VALWP
+3VALWP 1 2 11 PHASE2 PHASE1 20 1 2
8
7
6
5

5
6
7
8
1

1
PQ332 LG_3V 12 19 LG_5V
LGATE2 LGATE1

SKIPSEL
@ PR336 PR356 @

220U_6.3V_M
VREG5
4.7_1206_5% 4.7_1206_5%
1 1

GND

VIN

NC
EN
4 4
2

2
+ +

PC352
PC332
PR360 S IC UP6182CQAG VQFN 24P PW M PQ352

13

14

15

16

17

18
220U_6.3V_M
1

1
@ PC336 499K_0402_1%
2 PC356 @ 2
680P_0603_50V7K AO4712L_SO8 1 2 AO4712L_SO8
B+
1
2
3

3
2
1
680P_0603_50V7K
2

2
Ipeak=6.97A

1
100K_0402_5%
Imax=4.88A
1
VL

PR361
PC362
F=375KHz

1
1U_0402_6.3V6K
PC364
2
B Total Capacitor ??uF, 4.7U_0805_10V6K
B

2
ESR ??mohm ENTRIP1 ENTRIP2 RT8205_B+ Ipeak=3.98A

2
Imax=2.8A
D D F=300KHz
6

2 5 Total Capacitor ??uF,

PQ360A G G PQ360B
ESR ??mohm

1
DMN66D0LDW -7_SOT363-6 DMN66D0LDW -7_SOT363-6 PC365
S S
2VREF_8205
1

0.1U_0603_25V7K

2
PR370
VL 2 1
100K_0402_1%
1

<49> VS_ON

PR371
VS 1 2 2
100K_0402_1%
2.2U_0603_10V6K
42.2K_0402_1%
<BOM Structure>

PQ361
1

2N7002W -T/R7_SOT323-3 DTC115EUA_SC70-3

PR372

PC370

PQ362 D
1

PR373
2

<50> ACPRN 1 2 2
2

G
A 200K_0402_1% A
S
3
1

<28,44,46> EC_ON 2 Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
PQ363 Issued Date 2009/11/13 Deciphered Date 2009/04/28 Title

DTC115EUA_SC70-3 3VALWP/5VALWP
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 51 of 58
5 4 3 2 1
 A B C D

PJ151
@ JUMP_43X118
1.5_B+ 2 2
1
1 1 B+ 1

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC163
@ PC165

PC164
5
680P_0402_50V7K

TPCA8030-H_SOP-ADV8-5

2
PR164

PQ151
255K_0402_1%
4
1 2
PR160
<39,42,44> SYSON 1 2 PR155
BST_1.5V 1 2
0_0402_5%

3
2
1
0_0603_5%
1
PL152

15

14
PC160 @

1
PU150 PC155 1.8UH_SIL104R-1R8PF_9.5A_30%
.1U_0402_16V7K BST_1.5V-1 1 2 2 1 +1.5VP

EN_SKIP

TP

BST
2

2 13 DH_1.5V 0.1U_0603_25V7K

SI7170DP-T1-GE3_POWERPAK8-5
TON DH
3 12 LX_1.5V Ipeak=19.6A
OUT LX

1
5
PR161 PR157
1 2 4 11 1 2 @ PR156 1 Imax=13.72A
+5VALW VCC
VFB=0.75V ILIM +5VALW 4.7_1206_5%
100_0603_5% 10K_0402_1%
+ PC152 F=294KHz
5 FB VDD 10
Total Capacitor ??uF,

PQ152
220U_6.3V_M

2
1

PC161 6 9 DL_1.5V
PGOOD DL 4 ESR ??mohm

AGND

PGND
2
4.7U_0603_6.3V6K

2
2

1
PC162 @ PC156
G5603RU1U_TQFN14_3P5X3P5 4.7U_0805_10V6K 680P_0603_50V7K

3
2
1
2 2

2
PR162
1 2
10K_0402_1%
1

PR163
10K_0402_1%
2

PU180
SY8033BDBC_DFN10_3X3 PL182
4

@ PJ181 1UH_FMJ-0630T-1R0 HF_11A_20%

Ipeak=1.308A
3 3

+5VALW 2 1 10 2 LX_1.8V 1 2 +1.8VSP

PG

2 1 PVIN LX
JUMP_43X39
ILIM = 4A

68P_0402_50V8J
9 PVIN LX 3

1
F=1MHz
1

1
4.7_1206_5%

PC187
PC184 8 SVIN Total Capacitor ??uF,

PR186
22U_0805_6.3VAM PR183
6 FB=0.6Volt 20K_0402_1% ESR ??mohm

22U_0805_6.3VAM

22U_0805_6.3VAM
2

2
FB
5

2
EN

1
NC

NC
TP

PC183
PC182
2
FB_1.8V
11

2
PR181

680P_0603_50V7K
<28,39,44,47,54,56> SUSP# 1 2 EN_1.8V

1
PC186
0_0402_5%
PR184
1

2
10K_0402_1%
1

@ PR182 PC185@

2
499K_0402_1% 0.1U_0402_10V7K
2
2

4 4

www.vinafix.vn
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/25 Deciphered Date 2009/04/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VP/+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 52 of 58
A B C D
 5 4 3 2 1

D D
PJ451
@ JUMP_43X118
VCCSAP_B+ 2 1
B+
2 1

0.1U_0402_25V6
4.7U_0805_25V6-K

4.7U_0805_25V6-K

2200P_0402_50V7K
1

1
PC463

PC464

PC466
PC465
5
6
7
8

2
1
PR462
2
Ipeak=6A
255K_0402_1%
4
Imax=4.2A
PQ451 F=276K
<47,54> VCCPPWRGD 1
PR460
2 BST_VCCSAP 1
PR455
2
AO4466_SO8
Toatal Capacitor ??u

3
2
1
0_0402_5% 2.2_0603_5%
BST_VCCSAP-1
ESR=??mohm
1

@ PC460 PL452

15

14
1
.1U_0402_16V7K PU450 PC455 1.8U_D104C-919AS-1R8N_9.5A_30%
1 2 1 2 +VCCSAP

BST
EN_SKIP

TP
2

DH_VCCSAP 0.1U_0603_25V7K
2 13
TON DH

1
<BOM Structure>
PR461 VOUT 3 12 LX_VCCSAP @ PR456 1
OUT LX

5
6
7
8
100_0402_1% PR457
1 2 4 11 1 2 +5VALW 4.7_1206_5% + PC452
+5VALW VCC ILIM
390U_2.5V_M
10K_0402_1%

2
FB 5 10 1 2
FB VDD 2
PR471

1
1 2 6 9 PC462 4 @ PC456
+3VS PGOOD DL
1

AGND

PGND
PC461 10K_0402_1% 4.7U_0805_10V6K
DL_VCCSAP 680P_0603_50V7K PR463
4.7U_0805_10V6K

2
PQ452 0_0603_5%
2

C G5603RU1U_TQFN14_3P5X3P5 AO4712_SO8 C
7

3
2
1

2
2

<44> SA_PGOOD
@ PR472
10K_0402_1%
PR464
10_0402_5%
1

2 1 VCCSA_SENSE <9>

1
PR465
680_0402_1%

2
+3VS

1
PR466 PR467
5.1K_0402_1%

1
9.09K_0402_1%
2

2
PR468
10K_0402_1%
PR469

2
1
D 10K_0402_1%
2 1 2 PMBT2222A_SOT23-3
G
S PQ454 PR473

1
.1U_0402_16V7K
PQ453 0_0402_5%

100K_0402_1%
1

@ PR470
2 1 2 VCCSAP_VID1 <9>

PC470
SSM3K7002FU_SC70-3

3
1
B B

VID1 +VCCSAP

1 0.8V

0 0.9V

A A

www.vinafix.vn
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/25 Deciphered Date 2009/04/28 Title

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCCSAP/+1.0VSDGPUP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 53 of 58
5 4 3 2 1
 5 4 3 2 1

+1.5V

1
@ PJ75

1
JUMP_43X79

22
D PU75 D
1 VIN VCNTL 6 +3VALW
PC261 2 5
GND NC

1
4.7U_0805_6.3V6K

1
3 7 PC264
@ PR282 PR280 VREF NC

2
0_0402_5% 1K_0402_1% 4 8 1U_0603_10V6K
VOUT NC
1 2
<5,9,47> SUSP 9

2
TP
UP7711U8 PSOP 8P

PR279

.1U_0402_16V7K
D +0.75VSP

1
0_0402_5%

SSM3K7002FU_SC70-3
PQ260

PC263
1K_0402_1%
1 2 2
<47> 0.75VR_EN#

1
G

2
S PR281 PC262

3
1
10U_0805_6.3V6M

2
PC260
.1U_0402_16V7K

2
For shortage changed

TPCA8030-H_SOP-ADV8-5
PL401
HCB4532KF-800T90_1812
C 1.05VS_B+ 1 2 C
B+

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC413

PC414

PC415
PR414

5
PQ401
255K_0402_1%

2
1 2

PR410 4
0_0402_5%
<28,39,44,47,52,56> SUSP# 1 2
1

PC410 PR405 PC405 PL402

15

14

3
2
1
1

@ PU400 0_0603_5% 0.1U_0603_25V7K 1UH_FDUE1040D-1R0M-P3_21.3A_20%

.1U_0402_16V7K BST_1.05VS_VCCP
1 2 1 2 2 1 +1.05VS_VCCPP
EN_SKIP

TP

BST
2

2 13 DH_1.05VS_VCCP
TON DH

1
5
3 12 LX_1.05VS_VCCP @ PR406
OUT LX PR407 4.7_1206_5% 1
4 VCC ILIM 11 1 2 +5VALW + PC402

1 2

2
VFB=0.75V 13.7K_0402_1% 390U_2.5V_M

0_0603_5%
5 10 1 2

680P_0603_50V7K
FB VDD

PR420
4
PR411 PC412 2

@ PC406
6 PGOOD DL 9
AGND

PGND

100_0603_1% 4.7U_0805_10V6K

2
SI7170DP-T1-GE3_POWERPAK8-5
1 2 DL_1.05VS_VCCP
+5VALW

1
3
2
1
B B

PQ402
G5603RU1U_TQFN14_3P5X3P5
7

8
1

PC411
4.7U_0603_6.3V6K
2

PR415
1 2
<47,53> VCCPPW RGD +3VALW
10K_0402_1%
2

@ PR416
10K_0402_1%
1

PR412 PR421
4.02K_0402_1% 10_0402_5%
1 2 2 1 VCCIO_SENSE <8>
1

PR413
10K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 2010/01/25 Deciphered Date 2009/04/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VS_VCCP/+0.75VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 54 of 58
5 4 3 2 1
 5 4 3 2 1

2 1 @ PC555 470P_0402_50V7K NTCG CPU_B+ 1 2 B+

1000P_0402_50V7K
8.06K_0402_1%

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PL501

GFX@ PR530

GFX@ PC530

GFX@ PC563

GFX@ PC564

GFX@ PC565
HCB4532KF-800T90_1812

TPCA8030-H_SOP-ADV8-5
@ PR563 @ PH501 470KB_0402_5%_ERTJ0EV474J

1
2 1 2 1
3.83K_0402_1%

GFX@ PQ501
@ PR564 27.4K_0402_1%

2
1 2
UGATEG 4
GFX@ PC556

1
330P_0402_50V7K

330P_0402_50V7K
@ PR531 1 2

GFX@ PC557
499K_0402_1% GFX@ PC531 GFX@ PL502
VCC_AXG_SENSE <9> +GFX_COREP

3
2
1
1
39P_0402_50V7K 0.36UH_PCMC104T-R36MN1R17_30A_20%
2 1 2 1 2 1 PHASEG 4 1
2 2 1 VSS_AXG_SENSE <9>
GFX@ PC505

390U_2.5V_M
GFX@ PC502
D GFX@ PR532 GFX@ PC532 0.22U_0603_10V7K 3 2 1 D

10K_0402_1%
GFX@ PR570

GFX@ PR571
422_0402_1% 680P_0402_50V7K GFX@ PC558 BOOTG 2 1 2 1

1_0402_5%
4.7_1206_5%
+

SI7170DP-T1-GE3_POWERPAK8-5
2 1 2 1 2 1 1000P_0402_50V7K

PR506
PR505
GFX@ PC533 GFX@ PR533 GFX@ PR534 +5VALW 0_0603_5%
2

GFX@ PQ502
150P_0402_50V8J 475K_0402_1% 2.55K_0402_1%

1U_0603_10V6K
0.047U_0603_16V7K
@ PR567 @

2
2
18.2K_0402_1%
PR539

GFX@ PC534
16.5K_0402_1% LGATEG 4
1

1
0_0603_5%

0_0603_5%
+1.05VS_VCCPP

PC559
1 GFX@ PH504 10K_0402_1%_ERTJ0EG103FA

680P_0603_50V7K
UGATEG

PR568

PR577
PHASEG

LGATEG
NTCG
1 2 1 2 1 2

BOOTG
ISNG
ISPG

@ PC506
GFX@ PR572

1
130_0402_1%

54.9_0402_1%
.1U_0402_16V7K
7.5K_0402_1% GFX@ PC570
2

3
2
1
2

1
PC560
PU501 1 2 .1U_0402_16V7K
2

1
PR538
BOOT3 GFX@ PR573

PR537
5 1

2
VSS_AXG_SENSE VCC BOOT 11K_0402_1%
1 6
FCCM UGATE
8 UGATE3 1 2 1 2

470P_0402_50V7K
@ PR574

49

48

47

46

45

44

43

42

41

40

39

38

37
2

2
2 7 PHASE3 GFX@ PC571 100_0402_1%
PWM PHASE

590_0402_1%
GFX@ PR575

@ PC572
.1U_0402_16V7K

GND

COMPG

FBG

VSENG

RTNG

ISPG

ISNG

NTCG

PROG2

BOOTG

UGG

PHG

LGG
<8> VR_SVID_DAT

1
3 4 LGATE3
GND LGATE

2
0_0603_5%
1 36 BOOT2
<8> VR_SVID_ALRT# VWG BOOT2

PR569
9

2
UGATE2 PGND
2 35 1 2

2
<8> VR_SVID_CLK IMONG UG2 ISL6208ACRZ-T_QFN8_3X3
3 34 PHASE2 @ PC573

1
PGOODG PH2 0.01U_0402_16V7K

ISNG
ISPG
SVID_SDA 4 33 1 2
SDA VSSP2
Connect to +5V can disable 1 2 +5VALW
SVID_ALERT# 5 32 LGATE2 @ PR561 @ PR576 0_0402_5%
ALERT# LG2 0_0402_5% PWM3
VSSSENSE SVID_SCLK 6 31 VDDP+ 1 2 Connect to +5V can disable
SCLK ISL95831CRZ-T_TQFN48_6X6 VDDP +5VALW
PR540 GFX portion

2.2U_0603_10V6K
<44> VR_ON 1 2 7 30 PR562
VR_ON PWM3 0_0603_5%

1
0_0402_5%
19.1K_0402_1%

0.033U_0603_16V7

PC554
8 29 LGATE1
PR541 PGOOD LG1
1

C C
+3VS 1 2
1
PR542

PC561

9 28 CPU_B+
1.91K_0402_1%

2
IMON VSSP1

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
TPCA8030-H_SOP-ADV8-5
<5,30,44> VGATE 10 27 PHASE1
2

VR_HOT# PH1

PC588

PC587

PC586
2

PQ507
11 26 UGATE1

ISEN3/ FB2
NTC UG1

1
12 25 BOOT1

PROG1
ISUMN

ISUMP
VW BOOT1
COMP

ISEN2

ISEN1

VSEN
<44> VR_HOT# UGATE3 4

VDD
RTN

2
VIN
FB

@ PC538 470P_0402_50V7K
43P_0402_50V8J

2 1
PU500
13

14

15

16

17

18

19

20

21

22

23

24
1
PC537

@ PR544 @ PH502 470KB_0402_5%_ERTJ0EV474J PL505

3
2
1
1 2 1 2 0.36UH_PCMC104T-R36MN1R17_30A_20%
+1.05VS_VCCPP

VDD+
2

3.83K_0402_1% PHASE3
1 2 4 1
@ PR543 +CPU_CORE
499_0402_1% 2 1 PR559 PC535 3 2

1
@ PR545 1 2 0.22U_0603_10V7K
CPU_B+

680P_0603_50V7K 4.7_1206_5%
SI7170DP-T1-GE3_POWERPAK8-5

SI7170DP-T1-GE3_POWERPAK8-5
27.4K_0402_1% DC@ PR560 BOOT3 2 1 2 1
0_0603_5%

PR536
7.87K_0402_1% PR535
1000P_0402_50V7K

PR586 PR587
8.06K_0402_1%

0_0603_5%
1

PQ512

PQ514
For Turbo mode , PH502 must be PR558 ISEN3 2 1 2 1 ISEN1

2
1
PC539

changed 470K (b value = 4700) 2 1 @

PR546

+5VALW

2
10K_0402_1% 10K_0402_1%
1U_0603_10V6K
LGATE3
ISEN3

ISEN2

ISEN1

4 4
1_0603_5%
2

@ PC540 1
PC548
2

1
PR589

@ PC536
2 1 PC549 PR585
0.22U_0603_10V7K VSUM+ 2 1 2 1 ISEN2
2

3
2
1

3
2
1
22P_0402_50V8J

2
VSUM+ 3.65K_0402_1% 10K_0402_1%

2.61K_0402_1%
PR584

1
2 1 VSUM- 2 1

0.022U_0402_16V7K

PR557
PC541 1_0402_5%
0.33U_0402_10V6K

B PC567 0.22U_0402_6.3V6K B
@ PR547 33P_0402_50V8J PC542 VSUM-
PR548 2 1
1

1
@ PC550

@ PC551

1 2 2 1 2 1 2 1

11K_0402_1%

1 2
499K_0402_1%
PC562 0.22U_0402_6.3V6K 1
499_0402_1% 470P_0402_50V7K
PR556

2 1
2

2
330P_0402_50V7K

PC543 PR549 PR551 PH503

2 1 2 1 2 1 PC544 0.22U_0402_6.3V6K 10K_0402_1%_ERTJ0EG103FA
3.83K_0402_1% PR554
2

150P_0402_50V8J 316K_0402_1% 698_0402_1% CPU_B+

2

2 1 VSUM-

TPCA8030-H_SOP-ADV8-5
.1U_0402_16V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PC545 330P_0402_50V7K
1

PQ505
PC553

PC580

PC581

PC582
2 1 @ PC552 @ PR555
<8> VCCSENSE
330P_0402_50V7K 100_0402_1%

1
PC547

PC546 1000P_0402_50V7K 2 1 2 1
<8> VSSSENSE
2

2 1 UGATE2 4

2
PL503

3
2
1
0.36UH_PCMC104T-R36MN1R17_30A_20%
CPU_B+
TPCA8030-H_SOP-ADV8-5

PHASE2 4 1 +CPU_CORE
5

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

68U_25V_M_R0.36

68U_25V_M_R0.36

68U_25V_M_R0.36
PC583

PC584

PC585

1 1 1 1 PC515 3 2
100U_25V_M
PQ503

0.22U_0603_10V7K
1

680P_0603_50V7K 4.7_1206_5%
+ + + +
PC568

PC566

PC569

@ PC574

SI7170DP-T1-GE3_POWERPAK8-5

SI7170DP-T1-GE3_POWERPAK8-5
BOOT2 2 1 2 1

PR516
PR515
UGATE1 4 0_0603_5% PR580 PR581
2

2 2 2 2

PQ508

PQ510
ISEN2 2 1 2 1 ISEN1
@

2
LGATE2 10K_0402_1% 10K_0402_1%
4 4
PL504
3
2
1

0.36UH_PCMC104T-R36MN1R17_30A_20%

1
PR588

@ PC516
PHASE1 4 1
A +CPU_CORE PR582 A
SI7170DP-T1-GE3_POWERPAK8-5

SI7170DP-T1-GE3_POWERPAK8-5

3 VSUM+ 2 1 2 1 ISEN3
2
1

3
2
1
5

680P_0603_50V7K 4.7_1206_5%

PC525 3 2

2
3.65K_0402_1% 10K_0402_1%
PR526

0.22U_0603_10V7K PR591 PR594

BOOT1 2 1 2 1 ISEN1 2 1 2 1 ISEN3 PR583
PQ506

PR525 VSUM- 2 1
0_0603_5% @ 10K_0402_1% 10K_0402_1%
2

LGATE1 1_0402_5%
4 4

www.vinafix.vn
PR592 PR590
1
@ PC526

VSUM+ ISEN2
PQ504
2 1 2 1 Security Classification Compal Secret Data Compal Electronics, Inc.
3.65K_0402_1% 10K_0402_1%
Issued Date 2010/01/25 Deciphered Date 2009/04/28 Title
3
2
1

3
2
1

VSUM- 2
PR593
1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE/GFX
Size Document Number Rev
1_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 55 of 58
5 4 3 2 1
 5 4 3 2 1

B+ 1 2 B+_core

PL601 LX_VCORE
HCB4532KF-800T90_1812
6268_VCC

10U_1206_25VAK

4.7U_0805_25V6-K
DH_VCORE

10U_1206_25VAK

1
PR605 2.2_0603_1%

PC622
PR620

PC620

PC621
1 2 1 2
1.5K_0402_1% BST_VCORE

2
PC605
0.1U_0603_25V7K

2
<13,32,33,47> VGA_PW ROK
D 1 2 D
+5VALW
PR621 3K_0402_1%

TPCA8030-H_SOP-ADV8-5
5
PR626
0_0603_5%
Ipeak=24A

PQ601
Imax=16.8A
26268_VCC

16

15
1
F=231.5kHZ

2
8

1
PU600
PR627 4 Total capacitor

UG
GND

PGOOD

PHASE

BOOT
4.7_0603_5%
1050u
3 14 1 2 PC628
6268_VCC VIN PVCC ESR=3.1m ohm

3
2
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K

PL602
PC623

4 13 DL_VCORE +VGA_COREP
VCC LG
1

0.56U_PCMC104T-R56MN_25A_20%
1 2
APW 7138NITRL_SSOP16
2

1
PGND 12

TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
@PR606
@ PR606

390U_2.5V_M
4.7_1206_5%

10U_1206_25VAK

10U_1206_25VAK
1

CE@ PQ604
AM@ PR622 20K_0402_1%

PC602

1
1 2 5 11 ISEN_VCORE 1 2 +

1 2
EN ISEN

2
8,39,44,47,52,54> SUSP#

PQ602

PC630

@ PC631
4 4

FSET
CE@ PR607 3.9K_0402_1%

0_0402_5%
680P_0603_50V7K

2
1

VO
NC

@ PC606

PR630
FB
.1U_0402_16V7K
PC624

2
C APOP@ PR623 68K_0402_1% C
2

10

3
2
1

3
2
1

1
1 2
,32,47> DGPU_PW R_EN

PR631
10_0402_5%
VDD_SENSE <14>
1 2

57.6K_0402_1%
1

1
1

1
@ PR624

2
@ PC625 49.9K_0402_1% @PC627
@ PC627

PR625
22P_0402_50V8J 0.01U_0402_25V7K

1000P_0402_50V7K
2

2
PR632

2
4.75K_0402_1%
1

1
@ PC632
1
@ PC626
2200P_0402_25V7K
2

2
FSW=1/(75E-12*57.6K)=231.48KHz

+3VS_DGPU
N11M-GE1/GE2 N11P-GE1/GE2 N11E-GE1_LP

2
PR633

1
56.2K_0402_1%

AP2OP@ PR640
Imax=16.09A Imax=16.8A Imax=16.8A

40.2K_0402_1%
2
Ipeak=18.19A Ipeak=24A Ipeak=24A

1
PR641
Iocp=20.72A Iocp=29.17A Iocp=32.14A PR634

1
14K_0402_1% 100K_0402_1%

2
B B

1
PR255=5.36K PR255=7.15K PR255=7.15K PQ605 PR635

2
D SSM3K7002FU_SC70-3

1
3K_0402_1%
PQ50=unpop PQ50=unpop 2 1 2
G GPU_VID0 <13>
S

3
VFB(0.6)=Vout*Rbottom/(Rtop+Rbottom)

22K_0402_1%
.1U_0402_16V7K
PC633

@ PR636
GPU_VID0 GPU_VID1 N11M-GE1 N11M-GE2 N11P-GE1 N11P-GE2 N11E-GE1-LP

2
+3VS_DGPU

1
0 0 0.80V 0.80V 0.80V

1
PR642
1 0 0.85V 0.85V 0.85V 0.85V 0.85V 100K_0402_1%

SSM3K7002FU_SC70-3
PR643

2
D

1
0 1 3K_0402_1%

PQ606
2 1 2
G GPU_VID1 <13>
1 1 1.03V 1V 0.95V 0.925V 0.9V S

2
PC634

22K_0402_1%
.1U_0402_16V7K

@ PR644
PR260=4.75K PR260=4.75K PR260=4.75K PR260=4.75K PR260=4.75K

2
PR262=14K PR262=14K PR262=14K PR262=14K PR262=14K

1
A
PR261=56.2K PR261=56.2K PR261=56.2K PR261=56.2K PR261=56.2K A
PR263=16.2K PR263=19.6K PR263=29.4K PR263=40.2K PR263=63.4K

Security Classification Compal Secret Data Compal Electronics, Inc.

www.vinafix.vn
Issued Date 2010/01/23 Title
2009/01/23 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VGA_COREP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 56 of 58
5 4 3 2 1
 5 4 3 2 1

HW PIR (Product Improve Record)

NWQAA LA-6062P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
GERBER-OUT DATE: 2009/12/30
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------------------------

D D

C C

B B

A A

www.vinafix.vn
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 57 of 57
5 4 3 2 1
1 2010/04/20 P36-P45 Release

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/11/13 Deciphered Date 2009/04/28 Title

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NHQAA LA-6831P M/B
Date: Monday, August 02, 2010 Sheet 57 of 58