Final Notes Combined PDF

EC-3003 :: MICROPROCESSORS AND MICROCONTROLLERS
(Credit - 4)
Unit One: Introduction
School of Electronics Engineering

Kalinga Institute of Industrial Technology
Deemed to be University
1 Review of Digital Electronics
1.1 Gate Types and Truth Tables
The basic logic gates are AND, OR, NAND, NOR, XOR, INV, and BUF. The last two
are not standard terms; they stand for “inverter” and “buffer”, respectively.
Truth Tables are an easy way to represent a combinational logic output by tabulat-
ing all possible inputs. The symbols for these gates and their corresponding Boolean
expressions and truth tables are given below.
Logic Logic Truth Boolean

function symbol table expression
Buffer A-l>-Y ffffi Y=A
Inverter
(NOT gate) A --{>- Y
ffrn
A B y
Y=A
2-input
AND gate :=O-v 0 0
0 1
1 0
1 1
0
0
0
1
A B y
2-input 0 0 1
NANO 0 1 1
gate 1 0 1
1 1 0
A B y
0 0 0
2-input 0 1 1 Y=A+B
OR gate 1 0 1
1 1 1
A B y
2-input
0 0 1
NOR gate
0 1 0
1 0 0
1 1 0
A B y
0 0 0
2-input 0 1 1 Y = AE)B
EX-OR 1 0 1
gate 1 1 0
A B y
2-input 0 0 1
EX-NOR 0 1 0
gate 1 0 0
1 1 1
Figure 1: Basic Logic gates
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1.2 Boolean Algebra and K-Maps
Boolean algebra can be used to formalize the combinations of binary logic states. Using
the definition of Boolean addition, multiplication and inversion, we can define all the logic
gates algebraically.
For designing any combinational circuit, we use Boolean algebra. However, for any
arbitrary circuit the boolean expression might be lengthy and cumbersome which might
lead to inefficient implementation. Thus, the need of logic minimization. One method is
through the use of Karnaugh Maps or K-Maps.
For a boolean function of n variables, x1 , x2 , . . . xn , a product term in which each
of the n variables appears once (in either its complemented or uncomplemented form) is
called a minterm. The addition or “OR”-ing of minterms give the Sum of Products.
For a boolean function of n variables, x1 , x2 , . . . xn , a sum term in which each of the
n variables appears once (in either its complemented or uncomplemented form) is called
a maxterm. The multiplication or “AND”-ing of maxterms give the Product of Sums.
1.3 Multiplexer
A multiplexer (MUX) is a device which passes one of several data inputs to one output.
Generally there are 2n data inputs and n control lines which determine which input is
steered to the output.
Hence, a MUX can take many data bits and put them, one at a time, on a single
output data line in a particular sequence. This is an example of transforming parallel
data to serial data.
By adding gate-level circuitry to MUX inputs, any arbitrary combinational function
can be realised with a 2:1 MUX. Also, any n variable combinational function can be
implemented with a 2n : 1 MUX, 2n−1 : 1 MUX and so on.
1.4 Decoder
Decoder (DEC) is basically, a combinational type logic circuit that converts the binary
code data at its input into an equivalent decimal code at its output. Generally there are
n inputs and 2n outputs. Depending on the input, the decoder activates only one of the
2
2n outputs.
Therefore, whichever output line is “HIGH” identifies the binary code present at the
input, in other words it “de-codes” the binary input and these types of binary decoders
are commonly used as Address Decoders in microprocessor memory applications.
1.5 Priority Encoder
An encoder is a combinational logic circuit that accepts an active level on one of its inputs
(inputs represents digits, such as decimal, octal and so on) and converts it to a coded
output. An encoder has 2n input lines, only one of which is activated at a given time and
produces an n-bit output code, depending on which input is activated.
However, if more than one input are active simultaneously, the output is unpredictable.
This ambiguity is resolved if priority is established so that only one input is encoded, no
matter how many inputs are active at a given point of time.
The priority encoder includes a priority function. The operation of the priority encoder
is such that if two or more inputs are active at the same time, the input having the highest
priority will take precedence.
1.6 Latches and Flip-Flops
Latches and flip-flops are the basic elements for storing information. One latch or flip-
flop can store one bit of information. The main difference between latches and flip-flops
is that for latches, their outputs are constantly affected by their inputs as long as the
enable signal is asserted. In other words, when they are enabled, their content changes
immediately when their inputs change. Flip-flops, on the other hand, have their content
change only either at the rising or falling edge of the enable signal. This enable signal
is usually the controlling clock signal. After the rising or falling edge of the clock, the
flip-flop content remains constant even if the input changes.
3
2 Tristate concept and Bus structure
2.1 Tristate logic
In digital logic, we have two states: HIGH and LOW. Let us consider the switch connected
between input (A) and output (Y) as shown below.
A
..
, _____
luput
___,7\
Switch
y
Output
Now let us switch it ON and apply 5V (HIGH) to the input. Since the switch is ON,
input goes to the output and we get 5V as output. Similarly, when we apply 0V (LOW)
as the input, we get 0V as output.
A y
•
Input Swit.ch Output
5V (RICH) 5V (HIGH)
OV (LOvV) OV (LOW)
However, when the switch in OFF, we cannot say that the output is at 0V (LOW).
This new state, when the input is not connected to the output, is called a High-Impedance
State (Z).
A
~,_ _ _ _ _ __,/ c>FF_~_ ____
Y
Input Switch Output
fiV (HIGH) High Impedance State
OV {LOW)
Thus, any logic device which has the provision to effectively remove its influence from
the circuit (usually through an ENABLE input) exhibits a tristate logic. For example,
let us take a NOT gate as shown. The gate works as usual when the EN input is HIGH,
but when EN is set to LOW, irrespective of the input, the output is at High-impedance
state.
F,N A y
1 fl 1
1 1 ()
0 X z
4
2.2 Understanding Bus
A group of signals or wires is called a Bus. The purpose of a bus structure together
with the tristate logic is to reduce the number of connections needed for transfer of data
between the components. A bus is usually represented as shown below.
Un - - - - - - - - -
D1 - - - - - - - - -
D, - - - - - - - - -
D, - - - - - - - - - l) 8/ ____
----7..,:.
U4 - - - - - - - - -
Us - - - - - - - - -
D" - - - - - - - - -
D1 - - - - - - - - -
A l(rou p of win% n,JR
Figure 2: Representation of a bus
When building a digital system, the number of interconnections between different

components becomes a significant problem. Let us take an example of a system of four
8-bit components A, B, C and D where data transfer between any two components is
permissible. A total of 12 “data highways” or bus as shown below are needed, each
containing 8 wires.
A D
8 8 8 8
B 8 C
Figure 3: Interconnection of 4 8-bit components
As more components are added to the system, the number of interconnections in-
creases and the design would become very complex. This interconnection problem can be
dramatically reduced by using tristate logic and a common bus structure.
Instead of having interconnections between each of the components separately, each
component can be connected to a common bus. Of course this can only work if each
device knows when to “speak” (give some data) and when to “listen” (take some data).
Otherwise the devices could try to access the common bus at the same time leading to
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garbage data (bus contention). Thus, each component needs to be designed with a tristate
logic, i.e., only when it is enabled, the component can give or take data and when it is
disabled it is at high impedance state (disconnected from the common bus).
The device that determines who will speak and who will listen is called the bus master.
Usually, the Control Unit of the processor does this job. Depending on our instruction,
the control unit will generate a control signal whereby only the required components are
enabled for data transfer.
For example, let us consider a data transfer from component C to A. The control unit
will first activate C and allow data from C to be outputted to the common bus. Now this
data is available at the inputs of all the components. But according to our instruction,
the control unit will activate only the component A and allow it to take the data from
the common bus.
A
LF: cm
Control
Unit
LP, - Lat.r,h P.n11hlfl
OE - Output Enable
C
cm
Figure 4: Data transfer using a bus structure
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3 Microprocessors
3.1 Basic Microprocessor
A microprocessor is a
• multipurpose − addition, subtraction, comparison, etc.,
• programmable − depending on user’s preference, it can be instructed to perform

given tasks,
• clock-driven − synchronous circuit,
• register-based − to store the data temporarily for processing
electronic device that reads binary instructions from a storage device called memory,
accepts data as input and processes data according to those instructions, and provides
results as output.
A typical microprocessor can be represented in block diagram as shown in figure below.
Arithmetic
Logic Unit Registers
(ALU)
Control Unit
Figure 5: Block diagram of a basic microprocessor
All the processing of a microprocessor can be boiled down to either arithmetic or

logical functions. These functions are performed by the ALU.
Any arithmetic or logical operation needs operands. The Registers are used primarily
to store, temporarily, the data required for the execution of various operations.
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The Control Unit provides the necessary timing and control signals to all the oper-
ations in the microprocessor. It basically tells when to do what.
3.2 Basic Microprocessor based System
A microprocessor on its own cannot perform its various tasks. It needs some device to
give it instructions (input), some device to show the results of the instructions (output)
and some device to store the instructions (memory).
So, any microprocessor based system can be represented in block diagram as shown
in figure below.
Microprocessor
Input / Output
Ari thm<'ltic'.
Logic Un it Registers
(ALU)
System Bus
-------------------I
Memory
Control Unit
ROM
'-----~
I I R/WM
Figure 6: Block diagram of a basic microprocessor based system with bus architecture
It includes three components: microprocessor, I/O device and memory (read/write

memory and read-only memory). These components are connected to each other via
System Bus.
3.3 Basic working of a microprocessor
The sequence of process a microprocessor does when it needs to perform a task can be
summarised as: fetch, decode and execute.
Let us assume some instructions for a task are stored in a memory. When we command
the microprocessor to perform the task, it “goes” to memory to get the first instruction
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(fetch), understands the instruction (decode) and then performs according to the instruc-
tion (execute).
This sequence of fetch, decode and execute is continued until the microprocessor is
instructed to stop or halt.
During the entire process, the microprocessor uses the system bus to fetch the in-
structions and data from the memory. It uses registers to store data temporarily and it
performs the computing function in the ALU.
3.4 Applications of Microprocessor and its versatility
Applications of microprocessor are discussed in the next section.
Versatility of microprocessor comes from its programmability feature. Microprocessors

are designed as stored -program computers. This means that by keeping the same hard-
ware, we can load or store different types of programs/softwares and thus use the same
microprocessor for numerous applications.
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3.5 Evolution of microprocessors
The evolution of microprocessor can be traced along three branches:
• General Purpose Processor Branch: These are typically used for making computers.
Applications include personal computers (PC), laptops, workstations, servers, etc.
• Microcontroller Branch: These are typically used for making embedded systems.
Applications include digital cameras, microwave ovens, washing machines, digital
oscilloscope, etc.
• Special Purpose Processor Branch: These are usually used for some specific purpose
like Digital Signal Processing, Communication, etc. Applications include Switches,
Routers, etc.
As the microprocessors were evolving, it moved from 4-bit to 8-bit and so on and the
current generation is 64-bit. Along with that, the processing power and features were also
increased.
ltenium
Pentium
-
-
80486
80386
-\
..-\~
~ <"
o> ---
~~
80286 ~~
u'
j.. v>
8088 ~
8086
8085
8008
1971 4004
Figure 7: Microprocessor evolution tree (Taken from NPTEL Lectures)
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(Credit - 4)
Unit Two: 8085 Architecture and

Pins & Signals

1
Interrupt Control Serial 1/ 0 Control
8085 Microprocessor Architecture

8-b it Internal Data Bus
AccurnulaLor Temp. Reg. lnsLrudion

(8) (8) Register MUX / D EM UX
(8) I
w (8) z (8)
Flag Reg. Temp. Reg. Temp. Reg.
Figure 1: 8085 Architecture
(8) B (8) C (8)

Register Register
.µ D (8) E (8)
'-'
<J.) Rcgi8Lcr RcgisLcr
oJ
Instruction
rJJ
H (8) L (8)
bO Register Register
2
Deco<ler
Ar ithmetic ~
Logic and
Unit Machine Stack Pointer (16)
(ALU) Cycling
Encoding Program Counter
(16)
(8) lncrementer / Decrementer
Address Latch (16)
Power Supply -c +5 V
GND
X1 ---------1CLK
Timing and Control Unit
X
2
---------1 GE! rntrr
SLaLus DMA Reset
CLK OUT l
READY
RD WR ALE So t I IO~M HlDA RESET OUT
HOLD RE SET IN A15 - As AD1 -=-A.Do
Address Bus Address/ Data Bus
The architecture of a microprocessor chip is a description of the physical layout of
the various elements that form it. Two common architecture model used in computer
organisation is von Neumann architecture and Harvard architecture.
The 8085 microprocessor uses the von Neumann architecture. The characteristics of
a von Neumann architecture are as follows:
• Both data and instructions are stored in R/W memory.
• The contents of memory (data and instructions) are accessed by location.
• Instructions are accessed and executed sequentially.
Since we are storing both data and program(instructions) in the memory, this architecture
is also called Stored-Program architecture.
The various units of the 8085 microprocessor are discussed next.
3
2 Registers
The data and instructions which are stored in memory are fetched to the microprocessor
and are stored temporarily in Registers for processing.
A register is nothing but a set of flip-flops. The number of flip-flops used depend on
the size of the data that the microprocessor needs to process.
Registers can be broadly classified into two categories, namely
• General Purpose − These registers have not been explicitly defined for any purpose
or to store any particular type of information.
• Special Purpose − These registers are used for some specific function.
2.1 General Purpose Registers
In 8085 microprocessor, we have six 8-bit general purpose registers identified as B, C, D,

E, H and L. They can be combined as register pairs−BC, DE and HL−to perform some
16-bit operations. The HL register pair also works as a memory pointer (M), i.e., the
16-bit data is the address of a particular memory location.
2.2 Accumulator
The accumulator is an 8-bit register that is used to store one of the operands needed to
perform arithmetic and logical operations. Also, the result of any operation is always
stored in the accumulator.
2.3 Flag Register
Flag register is a set of flip-flops which gives the status of the result in the accumula-
tor. After any arithmetic or logic operation, depending on the result, the flag register is
changed. The bit positions in the flag register are shown below:
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
Figure 2: Flag Register
4
The description and conditions of the flags are as follows:
S − Sign flag: After the execution of an arithmetic or logic operation, if bit D7 of the
accumulator (result) is 1, then the Sign flag is set (S=1).
Z − Zero flag: After the execution of an arithmetic or logic operation, if the result is
zero (Acc = 00H), then the Zero flag is set (Z=1).
AC − Auxiliary Carry flag: In an arithmetic operation, when a carry is generated
from lower nibble to upper nibble, i.e., carry from D3 bit to D4 bit, then the Auxiliary
Carry flag is set (AC=1). This flag is used only internally for BCD operations and is not
available for the programmer to change the sequence of a program with a jump operation.
P − Parity flag: After the execution of an arithmetic or logic operation, if the result has
an even number of 1s, then the Parity flag is set (P=1). For example, if the accumulator
(after certain operation) has the data byte 0000 0011, then the parity bit is set to 1.
CY − Carry flag: If an arithmetic operation results in a carry or borrow, then the
Carry bit is set (CY=1).
All the flags are independent of each other. So depending on the result of the accu-
mulator, some flags may be set(=1) and others may be reset(=0).
The flag register is also called Program Status Word (PSW).
2.4 Program Counter
It is a 16-bit register used to hold address of the memory location from which the next
instruction is to be fetched. So we can say that this register is used to sequence the
execution of the instructions.
2.5 Stack Pointer
It is a 16-bit register which points to a memory location where stack is implemented. The
beginning of the stack is defined by loading a 16-bit address in the stack pointer.
5
2.6 Incrementer/Decrementer - Address Latch
In the schematic, these are shown in one block, but actually they are two separate circuits.
The Incrementer/Decrementer block increments the program counter when instruc-

tions are executed, increments and decrements the stack pointer when needed, and sup-
ports 16-bit increment and decrement instructions. For example, once the first instruction
is fetched from a memory location, the program counter is incremented accordingly to
point to the memory location of the next instruction.
The Address Latch holds the 16-bit value that is written to the address bus. This
value is also the input to the 16-bit increment/decrement circuit.
2.7 Temporary Registers
It is an 8-bit register which is used to store one of the operand (other is stored in accu-
mulator) for any arithmetic or logic operation.
There are two more 8-bit temporary registers identified as W and Z. These registers
are used by microprocessor internally to hold any intermediate data, i.e., data which is
needed during the execution of an instruction.
The temporary registers are not accessible to the programmer.
2.8 MUX/DEMUX
MUX/DEMUX unit is used to select a register out of all the available registers. This
unit behaves as a MUX when data is going from the register to the internal data bus. It
behaves as a DEMUX when data is coming to a register from the internal data bus of the
microprocessor.
2.9 Register Select
The Register Select behaves as the select lines of MUX/DEMUX unit
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2.10 Address/Data Buffer and Address Buffer
The contents of the stack pointer and program counter are loaded into the address buffer
and address-data buffer. These buffers are then used to drive the external address bus
and address-data bus. Any exchange of data between memory or I/O devices is done
through these buffers.
2.11 Instruction Register
When an instruction (opcode) is fetched from the memory, it is loaded in the instruction
register for further processing.
2.12 Instruction Decoder and Machine Cycle Encoding
The instruction decoder decodes (understands) the instruction and establishes the se-
quence of events to follow, i.e., how many machine cycles are required to execute the
instruction.
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3 Arithmetic Logic Unit (ALU)
The Arithmetic Logic Unit performs the computing functions of the microprocessor. It
takes two 8-bit inputs (from accumulator and temporary register) and performs one of
the five basic operations: ADD, OR, XOR, AND and SHIFT-RIGHT.
If one of the operands (temporary register) is inverted, the ALU can perform SUB
(subtraction) and CMA (complement) operations. SHIFT-LEFT operation is performed
simply by adding the number to itself.
The detailed schematic of the 8085 ALU can be found at:

http://www.righto.com/2013/01/inside-alu-of-8085-microprocessor.html
4 Timing and Control Unit
This unit synchronizes all the microprocessor operations with the clock and generates the
control signal necessary for communication between the microprocessor and peripherals.
This unit is responsible for proper operation of the microprocessor. After an instruc-
tion is decoded, the timing and control unit will generate various signals based on the
instruction to make the microprocessor perform accordingly.
5 Other units
5.1 Interrupt Control
This unit is used to handle interrupt requests. It provides the mechanism for external
hardware to interrupt the microprocessor and also have the microprocessor acknowledge
the interrupts through various signals/pins.
5.2 Serial I/O Control
This unit is used to perform serial data communication. In serial transmission, data bits
are sent over a single line, one bit at a time.
8
6 8085 Microprocessor Pins and Signals
The 8085 is an 8-bit general-purpose microprocessor capable of addressing 64K of memory.

The device has 40 pins, requires a +5V single power supply and can operate with a 3-MHz
single-phase clock.
6.1 Pin Diagram
The 8085 microprocessor’s pinout is shown below.
X1 1 40 Vee
X2 2 39 HOLD
RESET OUT 3 38 HLDA
SOD 4 37 CLK (OUT)
SID 5 36 RESET IN
TRAP 6 35 READY
RST 7.5 7 34 IO / M
RST 6.5 8 33 S1
RST 5.5 9 32 RD
INTR 10 31 WR
8085 µP
INTA 11 30 ALE
ADo 12 29 So
AD1 13 28 A1s
AD2 14 27 A14
ADs 15 26 A1s
AD4 16 25 A12
ADs 17 24 A11
AD6 18 23 A10
AD1 19 22 Ag
Vss 20 21 A8
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6.2 Pin Configuration
The 8085 microprocessor signals can be classified into following groups as shown in the
figure below.
Power Supply and Clock Signals
+5 V GND
X1 X2 VCC VSS
1 2 40 20
SID A15
Serial I/O
Signals {------.i
SOD
5
4
28
b
21
Higher Order
Address Bus
TRAP 6 A8
RST 7.5
7
RST 6.5
8
RST 5.5
9
Externally INTR AD7
Initiated 10 19
Signals 8085 µP b
Multiplexed
b
b Address/Data Bus
12
READY AD0
35
RESET IN ALE
36 30
HOLD S0
39 29
S1
33 Control
INTA IO/M and
External Signal
Acknowledgment
{- HLDA
11
38
34
32
31
RD
WR
Status Signals
3 37
RESET OUT CLK (OUT)
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Address Bus
The 8085 has 16 signal lines (pins) that are used as the address bus; however these lines
are split into two segments: A15 − A8 and AD7 − AD0 . The eight signal lines, A15 − A8 ,
are unidirectional and used for the most significant bits, called the high-order address, of
a 16-bit address. The signal lines AD7 − AD0 are used for a dual purpose, as explained
in the next section.
Multiplexed Address/Data Bus
The signal lines AD7 − AD0 are bidirectional: they serve a dual purpose. They are used
as the low-order address bus as well as the data bus. In executing an instruction, during
the earlier part of the cycle, these lines are used as the low-order address bus. During
the later part of the cycle, these lines are used as the data bus. (This is also known as
multiplexing the bus.)
If we had 16 pins dedicated to address bus and 8 pins dedicated to data bus, then 24
pins are used only for addressing and data transfer. Since we do not require address and
data at the same time (i.e., first we need to know the address and then in that address we
perform the data transfer), we can share (multiplex) some of the pins for handling both
address and data, and use the remaining pins for other functions. Thus, by multiplexing
the address and data bus, we increase the functionality of the microprocessor and reduce
pin count, thereby reducing the size of the microprocessor.
Control and Status Signals
This group of signals includes two control signals (RD and WR), three status signals
(IO/M, S1 , S0 ) to identify the nature of the operation, and one special signal (ALE) to
indicate the beginning of the operation. These signals are as follows:
• ALE (output) — Address Latch Enable: This is a positive going pulse generated
every time the 8085 begins an operation (machine cycle); it indicates that the bits
on AD7 − AD0 are address bits. This signal is used primarily to latch the low-order
address from the multiplexed bus and generate a separate set of eight address lines,
A 7 − A0 .
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• RD (output) — Read: This is a Read control signal (active low). This signal
indicates that the data is to be read from the selected I/O or memory device, i.e.,
take the data from I/O or Memory and put it in the data bus.
• WR (output) — Write: This is a Write control signal (active low). This signal
indicates that the data from the data bus is to be written into a selected I/O or
memory device, i.e., give the data from µP to I/O or Memory.
• IO/M (output) — This is a status signal used to differentiate between I/O and
Memory operations. When it is high, it indicates I/O operation; when it is low,
it indicates a memory operation. This signal is combined with RD and WR to
generate I/O and memory control signals.
• S1 and S0 (output) — These status signals, similar to IO/M, can identify various
operations, but they are rarely used in small systems.
All the operations and their associated status signals are listed in the table below.
Status
Machine Cycle IO/M S1 S0 Control Signals
Opcode Fetch 0 1 1 RD = 0
Memory Read 0 1 0 RD = 0
Memory Write 0 0 1 WR = 0
I/O Read 1 1 0 RD = 0
I/O Write 1 0 1 WR = 0
Interrupt Acknowledge 1 1 1 INTA = 0
Halt Z 0 0
Hold Z X X RD, WR = Z and INTA = 1
Reset Z X X
Bus Idle 0 0 0 —
NOTE: Z = Tri-state (High Impedance), X = Unspecified (Don’t Care)
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Power Supply and Clock Signals
The power supply and frequency signals are as follow:
• VCC : +5 V power supply.
• VSS : Ground Reference.
• X1 , X2 (input): A crystal is connected a these two pins. The frequency is internally

divided by two; therefore to operate a system at 3 MHz, the crystal should have a
frequency of 6 MHz.
• CLK (OUT) (output) — Clock Output: This signal can be used as the system clock
for other devices.
Externally Initiated Signals, including Interrupts
The 8085 has five interrupt signals that can be used to interrupt a program execution.
The microprocessor acknowledges an interrupt request by the INTA signal.
• INTR (input) — Interrupt Request: This is used as a general purpose interrupt.
• INTA (output) — Interrupt Acknowledge: This is used to acknowledge an interrupt.
• RST 7.5, RST 6.5, RST 5.5 (inputs) — Restart Interrupts: These are vectored
interrupts that transfer the program control to specific memory locations. They
have higher priorities than the INTR interrupt. Among these the priority order is
7.5, 6.5, and 5.5.
• TRAP (input): This is a non-maskable interrupt and has the highest priority.
In addition to the interrupts, three pins — RESET IN, HOLD, and READY — accept
the externally initiated signals as inputs. To respond to the HOLD request, the 8085 has
one signal called HLDA. The functions of these signals are discussed below.
• RESET IN (input): When the signal on this pin goes low, the program counter is
set to zero, the buses are tri-stated, and the microprocessor is reset.
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• RESET OUT (output): This signal indicates that the microprocessor is being reset.
The signal can be used to reset other devices.
• HOLD (input): This signal indicates that a peripheral is requesting the use of the
address and data buses. When HOLD pin is activated by an external signal, the
microprocessor relinquishes control of buses and allow the external device to directly
use them. For example, the HOLD signal is used in Direct Memory Access (DMA)
data transfer.
• HLDA (output) — Hold Acknowledge: This signal acknowledges the HOLD request.
• READY (input): This signal is used to synchronize slower peripherals with the
microprocessor. When this pin is low, the microprocessor enters into a Wait State.
When the peripheral is ready to send or accept data, the READY pin gets high.
Serial I/O
The 8085 has two signals to implement serial transmission:
• SID (input) — Serial Input Data: This signal is used to input serial data.
• SOD (output) — Serial Output Data: This signal is used to output serial data
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6.3 Demultiplexing the bus AD7 – AD0
In order to save the pin count and increase the functionality of the microprocessor, we
went for multiplexed address and data bus. In 8085, the higher order address lines i.e.,
A15 − A8 are directly available, but the lower order address lines i.e., A7 − A0 are
multiplexed with the data lines i.e., D7 − D0 to get the multiplexed address/data bus
i.e., AD7 − AD0 . To properly identify a peripheral, we first need to know it’s address.
After that, data transfer can take place. In 8085, address is of 16 bits given by A15 − A0 .
Thus we need to demultiplex the AD7 − AD0 bus. This is done by using a latch and the
ALE signal as shown in the figure below.
A15 A15
Higher Order
Address Bus
A8 A8
ALE
Address Bus
G
AD7 (Enable) A7
Multiplexed Lower Order
Address/Data Bus Address Bus
8085 µP
AD0 A0
Octal Latch
74373
D7
Data Bus
D0
When ALE is high (during T1 ), the latch is enabled; this means that whatever data is
there in the multiplexed AD7 − AD0 bus gets latched and is treated as the lower order
address. When ALE is low (after T1 ), the latch is disabled; so whatever data is available
in the multiplexed bus is treated as data. As the latch is disabled after T1 , the lower
order address bus does not change its value.
For example, let’s say data CD is to be written in the memory address F003. The
higher order address bus, A15 − A8 will have the value F0. Now during T1 , ALE goes
high; latch is enabled. So the value 03 available in the multiplexed bus will be latched to
the output of 74373 IC and we get the lower order address, A7 − A0 as 03. After T1 ,
ALE goes low; latch is disabled. The value CD available in the multiplexed bus will be
treated as the data.
15
Previous Questions
2018
Addn. Endsem
1. What is the purpose of READY pin in 8085? [1]
2. Explain about program counter(PC), stack pointer(SP), and flag register in [1]
8085.
Endsem
1. What is the purpose of HOLD and READY pins in 8085? [1+1]
Midsem
1. Draw the architecture of 8085. [2]
2. What is the purpose of Program counter(PC). Draw a suitable circuit to gen- [1+2]
erate MEMR, M EM W , IOR and IOW signals in an 8085 microprocessor
system.
3. Write the 8-bit format of Flag register in 8085 microprocessor. [1]
2017
Endsem
1. Define tristate. Why are they essential in a bus oriented system? [1+1]
2. How is the lower address bus and data bus demultiplexed externally in an 8085 [2]
microprocessor system.
Midsem
1. What are tristate devices. Why are they essential in bus oriented system? [1]
2. Draw internal architecture diagram of 8085 microprocessor. [2]
3. Explain the role of program counter. [1]
4. What is the function of READY pin in an 8085 microprocessor? [1]
5. What are the different Control and Status signals available in 8085 micro- [2]
processor?
16
6. Draw a suitable circuit to generate MEMR signal out of IO/M and RD control [1]
signal for a 8085 microprocessor system.
2016
Endsem
1. What is the purpose of ALE pin in 8085? [1]
2. Explain about program counter(PC) and flag register of an 8085 micro- [3]
processor.
3. Draw a suitable circuit to generate MEMR and IOW signals out of IO/M, RD [2]
and WR control signals in an 8085 microprocessor system.
Midsem
1. What is the use of ALE pin in 8085 microprocessor. [1]
2. Draw the internal architecture of 8085 microprocessor. [2]
2015
Endsem
1. Write the 8-bit format of flag register in 8085 microprocessor. With suitable [1+2]
examples discuss how PF and ZF flags are set.
Midsem
1. Discuss about accumulator and program counter of 8085 microprocessor. [2]
2. After addition of two signed numbers in an 8085 system, the status of the flag [2]
register is 0 0 0 1 0 1 0 1. What information does it convey about the flags and
the sum?
3. What is the function of RESET IN and READY pins of 8085 microprocessor? [2]
2014
Endsem
1. What are the two 16-bit special purpose registers available in 8085 and specify [1]
the function of the registers.
17
2. Draw the internal architecture of 8085 microprocessor and explain about ac- [2]
cumulator and flag register.
Midsem
1. Explain the role of accumulator and program counter. [2]
2. After addition of two signed numbers in an 8085 system, the contents of flag [2]
register is 94H . What information does it convey about the data conditions of
the sum?
3. What is the function of S1 and S0 , RESET IN pins of 8085 microprocessor? [1+1]
4. What are tri-state logic devices? Why are they essential in a bus-oriented [2]
system?
2013
Endsem
1. Specify the content of Program counter presently, if the 8085 has just fetched [1]
a byte from a memory location F42CH .
2. After the addition of two signed numbers in an 8085 system, the status of the [2]
Flag register is 0 0 0 1 0 1 0 1. What information does it convey about the data
conditions of the sum?
3. What are tri-state devices? Why are they essential in a bus-oriented system? [2]
4. What are the control signals necessary in the memory-mapped I/O scheme? [1+1]
How are they generated from RD, WR and IO/M signal of 8085 micro-
processor?
Midsem
1. How is the Low-order address bus and data bus demultiplexed externally in [2]
an 8085 microprocessor system.
2. What is the function of READY and X1 , X2 pins in an 8085 microprocessor. [2]
3. Explain the role of flag register in 8085 microprocessor. [2]
4. What are tri-state logic devices? Why are they essential in a bus-oriented [2]
system?
18
(Credit - 4)
Unit Three: 8085 Instructions and

Timing Diagram

Instruction Size
1 Instruction
The 8085 microprocessor instruction set has 74 operation codes that result in 246 instruc-
tions. An instruction is a binary pattern designed inside a microprocessor to perform a
specific function.
Each instruction has two parts: first is the task to be performed, called the operation
code (opcode), and the second is the data to be operated on, called the operand.
The 8085 instructions can be classified based on three criteria:
1. Instruction size
2. Function
3. Addressing modes
2 Instruction Size
Instruction size refers to the number of bytes an instruction requires for its complete op-
eration. Based on instruction size, 8085 instruction set can be classified into the following
three groups:
• 1-byte instructions: An 1-byte instruction includes the opcode and the operand in
the same byte. For example– MOV C,A; ADD B. [Opcode and only registers]
• 2-byte instructions: In a 2-byte instruction, the first byte specifies the opera-
tion code and the second byte specifies the operand. For example– MVI A,32H;
ADI 54H. [Opcode and 8-bit data]
• 3-byte instructions: In a 3-byte instruction, the first specifies the opcode and the
following two bytes specify the operands. For example– LXI H,F150H; LDA 8000H.
[Opcode and 16-bit data]
2
Function
3 Function
The 8085 instruction set can be classified into the following five functional categories:
• Data Transfer: This group of instruction copies data from source location to desti-
nation location. The various types of data transfer that takes place are:
a) between registers – MOV D,B,
b) between memory location and register – LDA F200H,
c) specific data byte to a register or a memory location – MVI C,43H, and
d) between and I/O device and accumulator – IN 85H.
• Arithmetic: These instructions perform arithmetic operations such as:

a) addition – ADD B,
b) subtraction – SUB C,
c) increment – INR M, and
d) decrement – DCX H.
• Logical: These instructions perform various logical operations with the contents of
the accumulator such as:
a) AND, OR, XOR – ANA B, ORA M, XRI 43H,
b) Rotate – RLC, RAR,
c) Compare – CMP B, and
d) Complement – CMA.
• Branching: This group of instructions alters the sequence of program execution

either conditionally or unconditionally. Conditions here signify the state of flags.
JNZ F170H, CALL F070H.
• Machine Control: These instructions control machine functions such as stop, interrupt,
or do nothing. HLT, NOP
Note: In arithmetic and logical operations, one of the operands is always the accumulator.
The other operand can be a register, an 8-bit data, or a memory location. The increment
and decrement operations are a little bit different as they can be performed on any one
of the register or in memory location.
3
Addressing Modes
4 Addressing Modes
The various formats of specifying the operands in the instruction are called the Addressing
Modes. The term addressing mode signifies how the data to be operated upon by an
instruction is specified. Based on addressing modes, the 8085 instructions are classified
into the following five groups:
• Register Addressing Mode: In this mode, the data to be operated upon is in a

general purpose register. Eg. MOV A,B, ADD B.
• Direct Addressing Mode: In this mode, the data to be operated upon is given directly
by the address specified in the instruction. Eg. STA F500H, IN 85H.
• Register Indirect Addressing Mode: In this mode, the data to be operated upon is
given indirectly by the contents of a register pair. Eg. MOV M,A, LDAX B.
• Immediate Addressing Mode: In this mode, the data to be operated upon is given
in the instruction immediately. Eg. MVI A,32H, ADI 43H.
• Implicit Addressing Mode: In this mode, the data to be operated upon is already
known and need not be specified explicitly in the instruction. Eg. CMA, RLC.
4
Timing Diagram
5 Timing Diagram
Timing diagram is a graphical representation of various control signals generated during

execution of an instruction. In the timing diagram of an instruction, buses and various
control signals are shown which includes the following:
• Higher-order address bus: A15 −A8 ,
• Multiplexed data and lower-order address bus: AD7 −AD0 ,
• ALE,
• IO/M,
• RD, and WR.
5.1 Machine Cycle
Machine cycle is defined as the time required to complete one operation of accessing
memory, I/O, or acknowledging an external request. Depending on the operation, we
have the following machine cycles:
• Opcode Fetch M/C.
• Memory Read M/C and Memory Write M/C.
• I/O Read M/C and I/O Write M/C.
• Interrupt Acknowledge M/C.
• Halt M/C, Hold M/C and Reset M/C.
• Bus Idle M/C
5.2 T-state
T-state is defined as one subdivision of the operation performed in one clock period. Each
T-state is precisely equal to one clock period.
5
Timing Diagram
5.3 Instruction Cycle
Instruction cycle is defined as the time required to complete the total execution of an
instruction. It consists of the opcode fetch machine cycle and any other machine cycles if
required.
6
Opcode Fetch Machine Cycle
6 Opcode Fetch Machine Cycle
The first operation in any instruction is opcode fetch. The microprocessor needs to get
(fetch) the opcode from the memory; only after that the microprocessor can begin to
execute the instruction. So the first machine cycle of any instruction is Opcode Fetch
Machine Cycle.
The opcode fetch machine cycle is shown below
Opcode Fetch M/C
T1 T2 T3 T4
CLK
A15 –A8 Higher Order Memory Address Unspecified

I
I
I
I
I
.l,I _ _ _ _ _ _ _
AD7 –AD0 Lower Order
Opcode
Memory Address
I
I
I
I
ALE
IO/M, S1 , S0
IO/M = 0, S1 = 1, S0 = 1
RD cb
cb
WR
7
Opcode Fetch Machine Cycle
To perform opcode fetch, the microprocessor executes the following steps:

Step 1: T1 — The microprocessor places the 16-bit memory address from the Program
Counter (PC) on the address bus. The ALE signal goes high during T1 to indicate
that the multiplexed bus is now giving address; i.e.,
PCH → A15 − A8 ; PCL → AD7 − AD0 .
Since the opcode is to be fetched from memory IO/M = 0. The microprocessor
identifies that it is an opcode fetch machine cycle with the help of status signals;
S1 = 1, S0 = 1.
Step 2: T2 , T3 — During T2 and T3 , the RD signal goes low. Now the microprocessor can
take (read) the opcode from the memory location whose address was known dur-
ing T1 . After taking the opcode, the microprocessor places it in the Instruction
Register.
Step 3: T4 — The opcode placed in the IR is now decoded and the microprocessor
performs the instructions accordingly.
Note: After the T3 state, the contents of the bus A15 − A8 are unknown, and the data
bus AD7 − AD0 goes into high impedance.
For some instructions, the opcode fetch machine cycle takes more than 4 T-states. In
that case, the remaining T-states (T5 , T6 ) are used for internal microprocessor operations.
8
Memory Read Machine Cycle
7 Memory Read Machine Cycle
After performing the opcode fetch machine cycle, and depending on the instruction de-
coded the microprocessor may need to perform a memory read machine cycle. In this
machine cycle, data is transferred from the memory to the microprocessor.
The memory read machine cycle is shown below
Memory Read M/C
T1 T2 T3
CLK
A15 –A8 Higher Order Memory Address
AD7 –AD0 Lower Order

Data from Memory
Memory Address
ALE
IO/M, S1 , S0 T
IO/M I
= 0, S1 = 1, S0 = 0
RD cb bc
WR
9
Memory Read Machine Cycle
To perform memory read, the microprocessor executes the following steps:

Step 1: T1 — Depending on the instruction, the microprocessor places a 16-bit memory
address from either Program Counter (PC), Stack Pointer (SP), BC Register
pair, DE Register pair, HL Register pair or WZ Temporary register pair on the
address bus. The ALE signal goes high during T1 to indicate that the multiplexed
bus is now giving address; i.e.,
PCH PCL
SPH SPL
B C
A15 − A8 AD7 − AD0
D E
H L
W Z
Since data is to be read from memory IO/M = 0. The microprocessor identifies

that it is a read machine cycle with the help of status signals; S1 = 1, S0 = 0.
Step 2: T2 , T3 — During T2 and T3 , the RD signal goes low. Now the microprocessor
can take (read) the data from the IO device whose address was known during
T1 . After taking the data, the microprocessor places the data in any one of the
8-bit registers (except IR).
10
Memory Write Machine Cycle
8 Memory Write Machine Cycle
coded the microprocessor may need to perform a memory write machine cycle. In this
machine cycle, data is transferred from the microprocessor to the memory.
The memory write machine cycle is shown below
Memory Write M/C
T1 T2 T3
CLK
A15 –A8 Higher Order Memory Address
AD7 –AD0 Lower Order Data from µP

Memory Address
to Memory
ALE
IO/M, S1 , S0 T
IO/M I
= 0, S1 = 0, S0 = 1
RD
WR bc
bc
11
Memory Write Machine Cycle
To perform memory write, the microprocessor executes the following steps:

Step 1: T1 — The microprocessor places a 16-bit memory address from either Stack
Pointer (SP), BC Register pair, DE Register pair, HL Register pair or WZ
Temporary register pair on the address bus. The ALE signal goes high dur-
ing T1 to indicate that the multiplexed bus is now giving address; i.e.,
SPH SPL
B C
D A15 − A8 E AD7 − AD0
H L
W Z
Since data is to be written to memory IO/M = 0. The microprocessor identifies

that it is a write machine cycle with the help of status signals; S1 = 0, S0 = 1.
Step 2: T2 , T3 — During T2 and T3 , the WR signal goes low. Now the microprocessor can
give (write) the data to the memory location whose address was known during
T1 . So according to the instruction, data from any one of the 8-bit registers
(except W, Z and IR) is written to the memory.
12
IO Read Machine Cycle
9 IO Read Machine Cycle
coded the microprocessor may need to perform an IO read machine cycle. In this machine
cycle, data is transferred from the input device to the microprocessor.
The IO read machine cycle is shown below
IO Read M/C
T1 T2 T3
CLK
A15 –A8 8-bit Port Address
AD7 –AD0 8-bit Data from

Port Address Input Device to Acc.
ALE
IO/M, S1 , S0 T
IO/M I
= 1, S1 = 1, S0 = 0
RD bc bc
WR
13
IO Read Machine Cycle
To perform IO read, the microprocessor executes the following steps:

Step 1: T1 — The 8-bit IO port address is available in W register and the same 8-bit IO
port address is also available in the Z register, i.e., in IO read machine cycle, W
and Z will have identical 8-bit address of the input device from which data is to
be read. This port address will be placed on the address bus. The ALE signal
goes high during T1 to indicate that the multiplexed bus is now giving address;
i.e.,
W → A15 − A8 ; Z → AD7 − AD0 .
Since data is to be read from IO device IO/M = 1. The microprocessor identifies
that it is a read machine cycle with the help of status signals; S1 = 1, S0 = 0.
Step 2: T2 , T3 — During T2 and T3 , the RD signal goes low. Now the microprocessor
can take (read) the data from the IO device whose address was known during T1 .
After taking the data, the microprocessor places the data in the accumulator.
14
IO Write Machine Cycle
10 IO Write Machine Cycle
coded the microprocessor may need to perform an IO write machine cycle. In this machine
cycle, data is transferred from the microprocessor to the output device.
The IO write machine cycle is shown below
IO Write M/C
T1 T2 T3
CLK
A15 –A8 8-bit Port Address
AD7 –AD0 8-bit Data from Acc.

Port Address to Output Device
ALE
IO/M, S1 , S0 T
IO/M I
= 1, S1 = 0, S0 = 1
RD
WR bc
bc
15
IO Write Machine Cycle
To perform IO write, the microprocessor executes the following steps:

Step 1: T1 — The 8-bit IO port address is available in W register and the same 8-bit IO
port address is also available in the Z register, i.e., in IO write machine cycle, W
and Z will have identical 8-bit address of the output device to which data is to
be written. This port address will be placed on the address bus. The ALE signal
goes high during T1 to indicate that the multiplexed bus is now giving address;
i.e.,
W → A15 − A8 ; Z → AD7 − AD0 .
Since data is to be written to IO device IO/M = 1. The microprocessor identifies
that it is a write machine cycle with the help of status signals; S1 = 0, S0 = 1.
Step 2: T2 , T3 — During T2 and T3 , the WR signal goes low. Now the microprocessor
can give (write) the data to the IO device whose address was known during T1 .
So according to the instruction, data from the accumulator is written to the
output device.
16
Timing Diagram of IN instruction
11 Timing Diagram of IN instruction
The IN instruction timing diagram is shown using the following example.

F000: IN 85H
Assume data DAH is there in the input device.
The memory and I/O representation for this IN instruction is shown below.
1/ 0 Device
MEMORY
DB ,,,,,. ...
~
85 ......
µP
17
M1 : Opcode Fetch M/C M2 : Memory Read M/C M3 : IO Read M/C
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3
CLK
Higher Order Memory Address Higher Order Memory Address Higher Order Memory Address
8-bit address
A15 –A8 F0H Unspecified F0H of input device
I 85H
I
I
I
Lower Order Opcode I Lower Order Data from Memory Lower Order Data from Input Device to Acc.
J.I ______ _ 8-bit address 8-bit address
AD7 –AD0 00H DBH 01H of input device of input device
DAH
I 85H 85H
Memory Address I Memory Address Memory Address
18
I
I
I
ALE

IO/M, S1 , S0 T = 0, S = 1, S = 0 T = 1, S = 1, S = 0
IO/M = 0, S1 = 1, S0 = 1 IO/MI 1 0 IO/MI 1 0
RD
bc
bc
bc
bc
bc
bc
WR
Timing Diagram of OUT instruction
12 Timing Diagram of OUT instruction
The IN instruction timing diagram is shown using the following example.

F000: OUT 80H
Assume data ACH is there in the accumulator.
The memory and I/O representation for this OUT instruction is shown below.
1/ 0 Device
MEMORY
D3 ......
-.... _-_- - - - (FJ- - - - ..
80 . _____----------
- - - - - - - - - - !.-
- - -(R) - - - - .. ,
...
19
M1 : Opcode Fetch M/C M2 : Memory Read M/C M3 : IO Write M/C
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3
CLK
8-bit address
A15 –A8 F0H Unspecified F0H of output device
I 80H
I
I
I
Lower Order Opcode I Lower Order Data from Memory Lower Order Data from Acc. to Output Device
J.I ______ _ 8-bit address 8-bit address
AD7 –AD0 00H D3H 01H of output device of output device
ACH
I 80H 80H
Memory Address I Memory Address Memory Address
20
I
I
I
ALE

IO/M, S1 , S0 T = 0, S = 1, S = 0 T = 1, S = 0, S = 1
IO/M = 0, S1 = 1, S0 = 1 IO/MI 1 0 IO/MI 1 0
RD
bc
bc
bc
bc
WR
bc
bc
Timing Diagram of LDA instruction
13 Timing Diagram of LDA instruction
The LDA instructino timing diagram is shown using the following example.
F000: LDA F150H
Assume data 56H is there in memory location F150H .
The memory representation for this LDA instruction is shown below.
MEMORY
3A ~ --
50 -
'4 I""
F1 "'4,_
• µP
•
---- --
.... -- ~
56 J_,
-- -- --
, - - - -- (R) - - - -
21
M1 : Opcode Fetch M/C M2 : Memory Read M/C M3 : Memory Read M/C M4 : Memory Read M/C
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T1 T2 T3
CLK
Higher Order Memory Address Higher Order Memory Address Higher Order Memory Address Higher Order Memory Address
A15 –A8 F0H Unspecified F0H F0H F1H
I
' - - - - - - , - - - - - - , - - - - - - ' I .,__ _ _,
I
I
Lower Order Opcode I Lower Order Data from Memory Lower Order Data from Memory Lower Order Data from Memory
I Lower byte Higher byte Data at memory
AD7 –AD0 00H 3AH
l ______ _
01H of the address 02H of the address 50H address F150H
I 50H F1H 56H
Memory Address I Memory Address Memory Address Memory Address
I
22
I
I
ALE

IO/M, S1 , S0 T = 0, S = 1, S = 0 T = 0, S = 1, S = 0 T = 0, S = 1, S = 0
IO/M = 0, S1 = 1, S0 = 1 IO/MI 1 0 IO/MI 1 0 IO/MI 1 0
RD cb bc bc bc
bc bc bc bc
WR
Timing Diagram of STA instruction
14 Timing Diagram of STA instruction
The STA instructino timing diagram is shown using the following example.
F000: STA F650H
Assume data 78H is there in the accumulator.
The memory representation for this STA instruction is shown below.
MEMORY
F000H 32 ~ -------zFJ----,
F001H 50 ~ ----------------
r-
F002H F6 ~ ...
• µP
•
•
J-
23
M1 : Opcode Fetch M/C M2 : Memory Read M/C M3 : Memory Read M/C M4 : Memory Write M/C
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T1 T2 T3
CLK
Higher Order Memory Address Higher Order Memory Address Higher Order Memory Address Higher Order Memory Address
A15 –A8 F0H Unspecified F0H F0H F6H
' - - - - - - - , - - - - - - , - - - - - - ' II _ _ __,
I
I
Lower Order Opcode I Lower Order Data from Memory Lower Order Data from Memory Lower Order Data from µP
AD7 –AD0 lI ______ _ Lower byte Higher byte Data in Acc.
00H 32H 01H of the address 02H of the address 50H to memory address F650H
I 50H F6H 78H
Memory Address I Memory Address Memory Address Memory Address to Memory
I
24
I
I
ALE

IO/M, S1 , S0 T = 0, S = 1, S = 0 T = 0, S = 1, S = 0 T = 0, S = 0, S = 1
IO/M = 0, S1 = 1, S0 = 1 IO/MI 1 0 IO/MI 1 0 IO/MI 1 0
RD cb bc bc
bc bc bc
WR bc
bc
Previous Questions
2018
Addn. Endsem
1. Which of the following instructions will be used in I/O mapped IO scheme: [1]
STA 9000H , or OUT 20H
2. The content of the accumulator is 50H . What would be the content of accu- [1]
mulator and zero flag after the execution of CMP A instruction in 8085 micro-
processor?
3. If the time required to execute MOV B,C is 2µs, then find the time required to [1]
execute ADD M in the same microprocessor system
4. Identify the addressing modes and name the machine cycles used to fetch and [3]
execute each of the following instructions individually.
i. LDAX D ii. CMA iii. SHLD 2000H
5. Define a clock cycle and a machine cycle. Draw the timing diagram for fetching [1+3]
and executing the instruction STAX B and explain the various signals used in
the timing diagram. [Opcode for STAX B is 02H ]
6. Short notes: Difference between memory-mapped IO and IO-mapped IO. [2.5]
Endsem
1. List the machine cycles used to fetch and execute the instruction LXI H, [1]
5050H .
2. Explain the functioning of stack using PUSH and POP instructions. [3]
3. Identify the addressing modes and name the machine cycles used to fetch and [2]
execute each of the following instructions individually.
i. LHLD 2020H ii. MOV A,M
4. Draw the timing diagram for fetching and executing the instruction STA [3]
1947H . Explain the various signals used in the timing diagram. [Opcode
for STA is 32H ]
5. Differentiate between SUB and CMP instructions and JMP and CALL instructions [2]
of 8085.
6. Short notes: Rotate instructions of 8085 [2.5]
25
7. Short notes: Memory-mapped IO and IO-mapped IO [2.5]
Midsem
1. What would be the contents of accumulator after the execution of the following [0.5]
instructions: MVI A, 0FH and XRI 0FFH .
2. For accessing IO location 6100H in a memory mapped IO scheme which in- [0.5]
struction/s can be used
3. The contents of [SP], [[SP]] and [[SP]+1] are presently 209CH , CCH and 47H [1]
respectively. What would be the contents of [SP] and [DE] after the execution
of the instruction POP D?
4. If the time required to fetch and execute the instruction LDAX B is 3.5µs, then [1]
find the clock frequency.
5. With suitable instruction/s discuss how Z flag is set. [1]
6. Draw the timing diagram for INA machine cylce for fetching and executing the [3]
instruction RST 6 and explain the various signals used in the timing diagram.
[Opcode for RST 6 is F7H ]
7. What operations are performed on execution of the following instructions? [2]
Also identify the addressing modes for each of them.
i. DAA ii. CMP M
8. Name the machine cycles used to fetch and execute each of the instructions. [1]
i. LHLD 4BCDH ii. SUB M
9. Find the content of accumulator and flag register after the execution of MVI [1]
A, 77H and XRA A instructions.
10. Explain the addressing modes of 8085 with examples. [3]
11. Draw the timing diagram for fetching and executing the instruction INR M and [3]
explain the signals used in the timing diagram. [Opcode of INR M is 34H ]
2017
Endsem
1. If a crystal of 4MHz is connected across X1 and X2 pins of an 8085 micro- [1]
processor, what would be the time taken to execute the instruction CALL
5000H
26
2. What is the difference between INA and Opcode Fetch machine cycle? Draw [1+3]
the timing diagram for fetching and executing a one byte RST 5 opcode from
the external hardware and explain the various signals shown in the timing
diagram. [Opcode of RST 5 is EFH ]
3. Identify the addressing modes and name the machine cycles to fetch and exe- [3]
cute the following instructions.
i. SHLD 8085H ii. CMP M iii. ADI 80H
4. Short notes: Rotate instructions of 8085 [2.5]
Midsem
1. The contents of [SP], [[SP]] and [[SP]+1] are presently 3375H , 66H and 00H [1]
respectively. What would be the contents of [SP] and [BC] after the execution
of the instruction POP B?
2. Identify the machine cycles to fetch and execute the following instructions. [1]
i. LHLD 6000H ii. ADD M
3. If a crystal of 2MHz is connected across X1 and X2 pins of an 8085 micro- [1]
processor, what would be the time taken to execute the instruction STA
3050H ?
4. After the execution of the instructions MVI A, 0C8H and CPI 0C8H , what [1]
would be the status of accumulator and the zero flag?
5. What is the basic difference between IO-mapped and memory-mapped IO [2]
schemes?
6. Define a machine cycle and T-state. Draw the timing diagram for fetching and [1+3]
executing the instruction OUT 0FH and explain the various signals used in the
timing diagram. [Opcode for OUT is D3H ]
7. Explain what operations are performed on execution of the following instruc- [3]
tions? Also identify the addressing modes for each of them.
i. RLC ii. DAA iii. STAX D
27
(Credit - 4)
Unit Four: Software Development Tools

and Assemblers

Assembler Format
1 Assembler Format
A typical assembly language programming statement is divided into four parts called
fields: Label, Opcode, Operand, and Comment. These fields are separated by delimiters:
Colon‘:’, Space‘ ’, Semicolon‘;’, and Comma‘,’.
Colon is used after a label, space is used between an opcode and an operand, comma
is used between two operands and semicolon is used before the beginning of a comment.
There can be any number of spaces between the fields but they must be separated by
the specified delimiters, as shown.
Label : Opcode Operand ; Comment
START : LXI H, 0F000H ; Load HL pair with F000H
1.1 Label field
Labels are optional but they help in specifying jump locations easily. A label must always
start with an alphabetic character (A-Z) or special characters (‘?’, ‘@’) and can be of
maximum six characters long. A name used as a label can be defined only once in the
program. The label name must be terminated with a colon.
1.2 Opcode field
This is a mandatory field and contains the mnemonic operation code for the 8085 instruc-
tion to be performed.
1.3 Operand field
The operand field identifies the data to be operated on by the specified opcode. Some
instructions require no operands. Others require one or two operands. As a general rule,
when two operands are required (as in data transfer and arithmetic operations), the first
operand identifies the destination (or target) of the operation’s result, and the second
operand specifies the source data.
2
Assembler Format
1.4 Comment field
The comment field is optional and are generally included for proper documentation of the
program. The only coding requirement for this field is that it be preceded by a semicolon
Note: Specifying Hexadecimal Data
When specifying hexadecimal numbers in assembly language programming, if the number

starts with an alphabet (A-F), then it must be preceded by a 0. All hexadecimals numbers
must be followed by the letter H
Hexadecimal Number Proper Format
AB 0ABH
01 01H
5C 5CH
D4 0D4H
If hexadecimal numbers starting with alphabet are not preceded by a 0, then the
assembler will interpret it as a label.
3
Assembler Directives
2 Assembler Directives
The assembler directives are the instructions to the assembler concerning the program
being assembled. These instructions are related only to the assembler. They are not trans-
lated in to opcodes or assigned any memory locations. Some of the important assembler
directives are listed and described here.
2.1 ORG
The format of this directive is as shown.

<optional> : ORG expression ; <optional>
E.g., START : ORG 0F500H ; Start assembling from F500
The ORG directive tells the assembler that the next block of instructions should be
assembled starting from the location mentioned in the operand.
ORG 0F200H
MVI C,00H F200: 0E,00
LXI H,0F500H After Assembling F202: 21,00,F5
RST 1 F205: CF
END
2.2 END
The END directive identifies the end of the assembly and terminates each pass of the
assembler.

<optional> : END <optional> ; <optional>
E.g., FINISH : END ; End of assembly
Only one END statement may appear in a source program, and it must be the last
statement.
4
2.3 DB
The DB directive stores the specified 8-bit data in consecutive memory locations.

List of 8-bit value
<optional> : DB ; <optional>
separated by comma
E.g., DATA : DB 0FCH, 12H
The list can contain up to eight total items.
ORG 0F600H F600: 45
DB 45H, 65H, 0F2H, 0ABH F601: 65
DB 54H, 33H F602: F2

After Assembling
END F603: AB
F604: 54
F605: 33
2.4 DW
The DW directive stores the specified 16-bit data in consecutive memory locations, with
lower byte stored first and then the higher byte. The process is repeated for each item in
the list.

List of 16-bit value
<optional> : DW ; <optional>
separated by comma
E.g., ADDR : DW 0F500H, 1234H
The list can contain up to eight total items.
5
ORG 0F600H F600: 65
DW 4565H, 0F2ABH F601: 45
DW 5433H F602: AB
After Assembling
END F603: F2
F604: 33
F605: 54
2.5 DS
The DS directive can be used to define a block of storage or memory locations.


<optional> : DS expression ; <optional>
E.g., OUTBUF : DS 4 ; Reserve four memory locations
Unlike the DB and DW directives, DS assembles no data into the program. The
contents of the reserved storage are unpredictable when program execution is initiated.
2.6 EQU
The EQU directive assigns the value of ‘expression’ to the name specified in the label
field.
Label Opcode Operand ; Comment

name EQU expression ; <optional>
E.g., PORT1 EQU 01H ; Equate PORT1 with 01
The required name in the label field should not be terminated with a colon. Once a
name has been equated to some value using the EQU directive, the same name can not
be used again to equate it to some other value.
6
Sample Programs
3 Sample Programs
3.1 2’s complement of an 8-bit number
Addr. Opcode Label Mnemonics Comment
ORG 0F100H ; Starting address (origin) of the program

F100 3A 00 F2 LDA 0F200H ; Load accumulator with the value stored in
F200
F103 2F CMA ; Complement accumulator
F104 3C INR A ; Increment accumulator
F105 32 01 F2 STA 0F201H ; Store the result in F201
F108 CF RST 1 ; Reset
ORG 0F200H ; Starting address (origin) of data

F200 0F DB 0FH ; Define one 8-bit number
END
Data Result
F200H - 0FH F201H - F1H
7
Sample Programs
3.2 Addition of two 8-bit numbers, sum is 16-bit

F200 0E 00 MVI C,00H ; Initialize reg C which will represent carry
F202 21 00 F5 LXI H,0F500H ; Load HL with F500, i.e., the address
where data will be stored
F205 7E MOV A,M ; Move the first number from memory
pointed by HL to A
F206 23 INX H ; Increment HL pair to point to the memory
location of second number
F207 86 ADD M ; Add A with value in memory pointed by
HL and store in A
F208 D2 0C F2 JNC Ahead ; Jump if carry is not generated
F20B 0C INR C ; Increment C reg when carry is generated
F20C 32 02 F5 Ahead: STA 0F502H ; Store the value of A in F502
F20F 79 MOV A,C ; Move value of C to A
F210 32 03 F5 STA 0F503H ; Store value of A in F503

F500 F2 12 DB 0F2H, 12H ; Define two 8-bit numbers
END ; End of assembly
Data Result
F500H - F2H F502H - 04H
F501H - 12H F503H - 01H
8
Sample Programs
3.3 Square of a number using Lookup Table

F300 21 00 F6 LXI H,Square ; Load HL with the starting address of the
lookup table
F303 3A 00 F5 LDA 0F500H ; Load accumulator with the value stored in
F500, i.e., the number whose square is to
be calculated
F306 85 ADD L ; Add value of reg. L with A and store in A
F307 6F MOV L,A ; Update reg. L so that HL reg. pair points
to the correct location in the lookup table
F308 7E MOV A,M ; Move the value (square of the required
number) from the memory pointed by HL
reg. pair to accumulator
F309 32 01 F5 STA 0F501H ; Store contents of A in F501
F30C CF RST 1 ; Reset

F500 04 DB 04H ; Define an 8-bit number whose square is to
be calculated
ORG 0F600H ; Starting address of the lookup table

F600 00 01 04 Square: DB 00H,01H,04H ; Define the values of lookup table as
F603 09 16 25 DB 09H,16H,25H ; 0, 1, 4, 9, 16, . . . in ascending order
F606 36 49 64 DB 36H,49H,64H
F609 81 DB 81H
Data Result
F500H - 04H F501H - 16H
9
Sample Programs
3.4 Larger of two numbers

F400 21 00 F5 LXI H,0F500H ; Load HL with F500, i.e., the address
where data will be stored
F403 7E MOV A,M ; Move the first number from memory
pointed by HL to A
F404 23 INX H ; Increment HL reg. pair to point to the
memory location of second number
F405 BE CMP M ; Compare A with the value in memory
pointed by HL
F406 D2 0A F4 JNC Go ; Jump if carry is not generated, i.e., the
value in A is larger
F409 7E MOV A,M ; If carry is generated, then the second num-
ber is larger, move it to A
F40A 32 02 F5 Go: STA 0F502H ; Store the value of A (the larger number)
in F501
F40D CF RST 1 ; Reset

F500 98 97 DB 98H, 97H ; Define two 8-bit numbers
Data Result
F500H - 98H F502H - 98H
F501H - 97H
10
Sample Programs
3.5 Largest number in a series
ORG 0F500H ; Staring address (origin) of the program

F500 21 00 F1 LXI H,0F100H ; Load HL pair with F100, i.e., the starting
address where data will be stored
F503 4E MOV C,M ; Move the first value (count of number) to
C reg.
F504 23 INX H ; Increment HL reg. pair to point to next
memory location
F505 7E MOV A,M ; Move the first number to A
F506 0D DCR C ; Decrement C, i.e., count
F507 23 Loop: INX H ; Increment HL reg. pair to point to next
memory location
F508 BE CMP M ; Compare A with the value in memory
pointed by HL reg. pair
F509 D2 0D F5 JNC Ahead ; Jump if carry is not generated, i.e, the
value in A is larger
F50C 7E MOV A,M ; If carry is generated, then the second num-
ber is larger, move it to A
F50D 0D Ahead: DCR C ; Decrement C, i.e., count
F50E C2 07 F5 JNZ Loop ; Continue the loop if value of C is not zero
F511 32 10 F1 STA 0F110H ; Store the value (largest number) in F110

F100 05 11 32 DB 05H,11H,32H ; First byte is the count of numbers,
F103 53 24 45 DB 53H,24H,45H ; second byte onwards are the numbers
11
Sample Programs
Data Result
F100H - 05H (Count) F110H - 53H
F101H - 11H
F102H - 32H
F103H - 53H
F104H - 24H
F105H - 45H
N.B.: To find the smallest in a series of numbers, we can use JC in place of JNC
12
Sample Programs
3.6 Block transfer of Data

F600 21 20 F5 LXI H,0F520H ; Load HL pair with F520, address of source
of data
F603 11 20 F6 LXI D,0F620H ; Load DE pair with F620, address of des-
tination of data
F606 06 0A MVI B,0AH ; Load B with 0A, count of data
F608 7E Loop: MOV A,M ; Move the data from memory pointed by
HL reg. pair (source address) to A
F609 12 STAX D ; Store the value of A in the memory ad-
dress pointed by DE reg. pair (destination
address)
F60A 23 INX H ; Increment HL to point to next source ad-
dress
F60B 13 INX D ; Increment DE to point to next destination
address
F60C 05 DCR B ; Decrement B, i.e., count
F60D C2 08 F6 JNZ Loop ; Continue the loop if value of B is not zero
ORG 0F520H ; Starting address (origin) of source data

F520 01 02 03 DB 01H,02H,03H ; Define the source data
F523 04 05 06 DB 04H,05H,06H ;
F526 07 08 09 DB 07H,08H,09H ;
F529 0A DB 0AH ;
END ;
13
Sample Programs
Data Result
F520H - 01H F620H - 01H
F521H - 02H F621H - 02H
F522H - 03H F622H - 03H
F523H - 04H F623H - 04H
F524H - 05H F624H - 05H
F525H - 06H F625H - 06H
F526H - 07H F626H - 07H
F527H - 08H F627H - 08H
F528H - 09H F628H - 09H
F529H - 0AH F629H - 0AH
14
Sample Programs
3.7 Code conversion: Generation of Lookup Table and Interfacing
7-segment display
A 7-segment display consists of seven LEDs arranged in a rectangular fashion as shown.

The individual LEDs are labelled a through g representing each LED. An additional 8th
LED is sometimes used within the same package thus allowing the indication of a decimal
point labelled as dp or dot.
10 9 8 7 6
g b
f COM a
a
f b
e c
bc bc
d dot
d COM c
e dot
-
1 2 3 4 5
By forward biasing the appropriate pins of the LED segments in a particular order,
some segments (LEDs) will glow and others will remain dark thereby allowing the desired
pattern of the number to be generated on the display.
The common pin of the display is generally used to identify which type of 7-segment
display it is. As each LED has two connecting pins, “Anode” and “Cathode”, there are
therefore two types of LED 7-segment display called: Common Cathode (CC) and Com-
mon Anode (CA).
15
Sample Programs
1. Common Cathode: In the common cathode display, all the cathode connections
of the LED segments are joined together to logic 0 or Ground. The individual
segments are illuminated by application of a HIGH or logic 1 signal via a current
limiting resistor to forward bias the individual anode terminals (a-g).
g f e d c b a
So to display 0, terminals a through f will be connected to logic 1 and terminal g

will be grounded.
2. Common Anode: In the common anode display, all the anode connections of the
LED segments are joined together to logic 1 or VCC . The individual segments are
illuminated by application of a LOW or logic 0 signal via a current limiting resistor
to forward bias the individual cathode terminals (a-g).
VCC
g f e d c b a
So to display 0, terminals a through f will be grounded and terminal g will be

connected to VCC .
16
Sample Programs
By properly driving 0s and 1s to the terminals a through g, we can display the BCD digits
0 – 9 in the 7-segment display. The table below gives the hexadecimal encodings for both
CC and CA 7-segment display.
Connection of Data bus with 7-seg. display

Digit D7 D6 D5 D4 D3 D2 D1 D0 Code
– g f e d c b a
0 0 1 0 0 0 0 0 0 40H
1 0 1 1 1 1 0 0 1 79H
2 0 0 1 0 0 1 0 0 24H
3 0 0 1 1 0 0 0 0 30H
Common 4 0 0 0 1 1 0 0 1 19H
Anode 5 0 0 0 1 0 0 1 0 12H
6 0 0 0 0 0 0 1 0 02H
7 0 1 1 1 1 0 0 0 78H
8 0 1 1 1 1 1 1 1 7FH
9 0 1 1 0 1 1 1 1 6FH
0 0 0 1 1 1 1 1 1 3FH
1 0 0 0 0 0 1 1 0 06H
2 0 1 0 1 1 0 1 1 5BH
3 0 1 0 0 1 1 1 1 4FH
Common 4 0 1 1 0 0 1 1 0 66H
Cathode 5 0 1 1 0 1 1 0 1 6DH
6 0 1 1 1 1 1 0 1 7DH
7 0 0 0 0 0 1 1 1 07H
8 0 0 0 0 0 0 0 0 00H
9 0 0 0 1 0 0 0 0 10H
17
Sample Programs
3.7.1 Display ‘1’ in the 7-seg. display
CODE EQU 9000H ; Equate CODE with value 9000

PORT1 EQU 40H ; Equate code with value 40

F700 21 00 90 LXI H,CODE ; Load HL with the value of CODE (9000),
which is the starting address of the com-
mon anode lookup table
F703 3E 01 MVI A,01H ; Move the value to be displayed (1) to A
F705 85 ADD L ; Add value of A with L and store in A
F706 6F MOV L,A ; Update reg. L so that HL reg. pair points
to the correct location in the lookup table
F707 7E MOV A,M ; Move the value (code required to display
1) from memory pointed by HL to A
F708 D3 40 OUT PORT1 ; Output the value of A to PORT1, i.e., 7-
seg. display which is connected in PORT1
located in address 40
F70A CF RST 1 ; Reset
ORG 9000H ; Starting address of the lookup table

9000 40 79 24 DB 40H,79H,24H ; Define the values of lookup table
9003 30 19 12 DB 30H,19H,12H ; for common anode 7-seg. display
9006 02 78 7F DB 02H,78H,7FH ;
9009 6F DB 6FH ;
END ;
18
Sample Programs
3.8 Delay Subroutines
3.8.1 Using one register
MVI B,10H
Go: DCR B
JNZ Go
RET
Calculating the delay
Instruction No. of Machine Cycles No. of T-states How many times executed
2
MVI B,10H 4+3=7 1
(F R)
1
DCR B 4 16
(F)
3/2
JNZ Go 4+3+3=10 / 4+3=7 15 / 1
(F R R) / (F R)
3
RET 4+3+3=10 1
(F R R)
Total T-states = (7 × 1) + (4 × 16) + (10 × 15) + (7 × 1) + (10 × 1)
= 7 + 64 + 150 + 7 + 10
= 238
The crystal frequency fX is 6.25MHz, so 8085 internal frequency, f is 3.125MHz, therefore

each T-state is equal to 1/f = 320 ns. Hence the total delay of this subroutine is:
Delay, D = 238 × 320 ns
= 76160 ns
= 76.160 µs
= .07616 ms
19
Sample Programs
3.8.2 Using nested loop
MVI B,10H
Loop1: MVI C,78H
Loop: DCR C
JNZ Loop
DCR B
JNZ Loop1
RET
2
MVI B,10H 4+3=7 1
(F R)
2
MVI C,78H 4+3=7 16
(F R)
1
DCR C 4 120× 16
(F)
3/2
JNZ Loop 4+3+3=10 / 4+3=7 119× 16 / 1× 16
(F R R) / (F R)
1
DCR B 4 16
(F)
3/2
JNZ Loop1 4+3+3=10 / 4+3=7 15 / 1
(F R R) / (F R)
3
RET 4+3+3=10 1
(F R R)
Total T-states = (7 × 1) + (7 × 16) + (4 × (120 × 16)) + (10 × (119 × 6)) + (7 × (1 × 16))
+ (4 × 16) + (10 × 15) + (7 × 1) + (10 × 1)
= 7 + 112 + 7680 + 19040 + 112 + 64 + 150 + 7 + 10
= 27182
Delay, D = 27182 × 320 ns
= 8698240 ns
= 8698.24 µs
= 8.69824 ms
20
Sample Programs
3.8.3 Using register pair
LXI D, 0FFFFH
Loop: DCX D
MOV A,E
ORA D
JNZ Loop
RET
3
LXI D,0FFFFH 4+3+3=10 1
(F R R)
1
DCX D 6 65535
(S)
1
MOV A,E 4 65535
(F)
1
ORA D 4 65535
(F)
3/2
JNZ Loop 4+3+3=10 / 4+3=7 65534 / 1
(F R R) / (F R)
3
RET 4+3+3=10 1
(F R R)
Total T-states = (10 × 1) + (6 × 65535) + (4 × 65535) + (4 × 65535) + (10 × 65534)
+ (7 × 1) + (10 × 1)
= 65535(6 + 4 + 4 + 10) + 7 + 10
= 1572857
Delay, D = 1572857 × 320 ns
= 503314240 ns
= 503314.240 µs
= 503.314240 ms
21
Sample Programs
3.9 Generation of signals
3.9.1 Sawtooth
PORTA EQU 80H ; Equate PORTA with value 80

F900 3E 00 Start: MVI A,00H ; Move 0 to A
F902 D3 40 Loop: OUT PORTA ; Output the value of A to oscilloscope con-
nected to PORTA in address 80
F904 3C INR A ; Increment A
F905 C2 02 F9 JNZ Loop ; Continue the loop if value of A is zero
F908 C3 00 F9 JMP Start ; Jump to Start to begin the next cycle
3.9.2 Triangular
PORTA EQU 80H ; Equate PORTA with value 80

F910 2E 00 Start: MVI L,00H ; Move 0 to L
F912 7D Loop: MOV A,L ; Move value of L to A
F913 D3 80 OUT PORTA ; Output the value of A to PORTA
F915 2C INR L ; Increment L
F916 C2 12 F9 JNZ Loop ; Continue the loop if value of L is not zero
F919 2E FF MVI L,0FFH ; Move FF(255) to L
F91B 7D Loop1: MOV A,L ; Move value of L to A
F91C D3 80 OUT PORTA ; Output the value of A to PORTA
F91E 2D DCR L ; Decrement L
F91F C2 1B F9 JNZ Loop1 ; Continue the loop if value of L is not zero
F922 C3 10 F9 JMP Start ; Jump to Start to begin the next cycle
22
Software Development Tools
4 Software Development Tools
In addition to the operating system of a computer, various program are necessary to

develop assembly language programs. These programs include Editor, Assembler, Linker
(or Loader) and Debugger.
4.1 Editor
The Editor is a program that allows the user to write an assembly language program and
save it on the disk with a filename and the extension .ASM. This file is known as the
Source file.
The Editor program is not concerned with the format or syntax of the program. If an
assembly language program is to be written, then it must be ensured by the user that the
proper assembler format is maintained.
4.2 Assembler
The Assembler is a program that translates source code or mnemonics into the binary
code, called object code of the microprocessor and generates a file called the Object file
(.OBJ). In addition to translating mnemonics, the Assembler performs various functions,
such as error checking and memory allocations.
The assembler also generates a List file (.LST) that includes memory addresses, ma-
chine codes in Hex, labels and comments. This file is used primarily for documentation.
PCs are designed around Intel processors and the assemblers used inside PCs will be
able to translate mnemonics or instructions (opcodes) of Intel processors only. So, we
need an assembler which will run on PCs but will also be able to understand or translate
the mnemonics written for 8085. Such a program is called cross-assembler.
Assemblers are also classified as one-pass or multi-pass assemblers. A one-pass or
single-pass assembler scans the source program only once and creates the equivalent binary
object file. The assembler substitutes all the mnemonics with the corresponding opcode
and the labels with the appropriate memory address in the single pass.
In a two-pass assembler, first the starting memory location is determined from the
ORG statement. The assembler scans each instruction and records the location of each
23
Software Development Tools
instruction. It also generates a symbol table during this pass. The symbol table holds the
Hex value of any symbol or label used in the program. In the second pass, instructions are
again examined and mnemonics are replaced by their opcodes and labels are substituted
with their Hex values.
Source Program After Pass 1 After Pass 2
Symbol Table
PORT0 00H
PORT0 EQU 00H PORT1 01H Address Machine
PORT1 EQU 01H START 0F600H Hex Code Hex
ORG 0F600H
F600 DB 00
START: IN PORT0 Addr. Hex Label: Opcode Operand
F602 D3 01
OUT PORT1 F600 START: IN PORT0
F604 C3 00 F6
JMP START F602 OUT PORT1
END F604 JMP START
4.3 Linker
The Linker (or Loader) is a program that takes the Object file generated by the Assembler
program and generates a Hex file (.HEX). This file consists of only hexadecimal digits in
a specified format. Once the Hex file is generated it can be loaded (i.e., transferred from
PC) into the R/W memory of the microprocessor kit using a program called Download.
4.4 Debugger
The Debugger is a program that allows the user to test and debug the Object file. The
user can employ this program to perform the following functions:
• Make changes in the object code.
• Examine and modify the contents of memory.
• Set breakpoints, execute a segment of the program, and display register contents
after the execution.
• Trace the execution of the specified segment of the program, and display the register
and memory contents after the execution of each instruction.
• Disassemble a section of the program, i.e., convert the object code into the source
code or mnemonics.
24
(Credit - 4)
Unit Five: 8085 Interrupts

Classification of interrupts
1 Interrupts
Interrupt is a mechanism by which the microprocessor is made to transfer control from its
current program execution to another program. The interrupts are generated by a variety
of sources; either internal or external to the microprocessor. Depending on the type
of interrupt request generated, the microprocessor can ignore or respond immediately.
The interrupt mechanism allows communication with peripherals asynchronously and the
process is known as interrupt-driven data transfer.
The program or the routine that is executed upon interrupt is called interrupt service
routine (ISR). After execution of the ISR, the processor must return to the interrupted
program. The address of the memory where the ISR is located for a particular interrupt
signal is called interrupt vector address. The interrupt structure provides a mechanism of
enabling or disabling particular interrupts programmatically with the help of instructions.
This feature is called selective masking.
2 Classification of interrupts
The interrupt requests can be broadly classified in two categories: vectored or non-
vectored interrupts, and maskable or non-maskable interrupts. The interrupt requests
can also be classified as internal (software) or external (hardware) interrupts.
2.1 Vectored and Non-vectored interrupts
When an interrupt request is accepted by the microprocessor, if the program control

automatically transfers (vector) to a specific address without the need of an external
hardware, then the interrupt is called vectored interrupt. For vectored interrupts, the
necessary hardware is already implemented inside the microprocessor.
The non-vectored interrupts are those for which the vector address is not fixed and
has to be supplied by an external hardware circuit. The design of the external hardware
circuit is based on the opcode of the software interrupts of the microprocessor.
1
Interrupts in 8085
2.2 Maskable and Non-maskable interrupts
The interrupts which can be disabled or enabled programmatically with the help of in-
structions are maskable interrupts. If an interrupt is masked or disabled, then the micro-
processor will not respond to the interrupt, i.e., perform the ISR for that interrupt.
Non-maskable interrupts are those which cannot be disabled by the programmer. If
an interrupt occurs because of a non-maskable interrupt, then the microprocessor has to
be service it.
3 Interrupts in 8085
The 8085 microprocessor includes five hardware interrupts – INTR, RST5.5, RST6.5,
RST7.5, and TRAP.
Out of these, TRAP, RST7.5, RST6.5, and RST5.5 are vectored interrupts and their
corresponding vector address are as follows.
Interrupt Vector Address

TRAP 0024H
RST7.5 003CH
RST6.5 0034H
RST5.5 002CH
For INTR, the vector address will be decided by the external circuit designed to supply
the opcode corresponding to software interrupts. In 8085, there are 8 software interrupts
which are generated using RST n instruction. The opcode and vector address for the
software interrupts are shown below.
RST n Opcode Vector Address

RST 0 C7H 0000H
RST 1 CFH 0008H
RST 2 D7H 0010H
RST 3 DFH 0018H
RST 4 E7H 0020H
RST 5 EFH 0028H
RST 6 F7H 0030H
RST 7 FFH 0038H
2
External Hardware Circuit to supply RST n opcode for INTR interrupt
The interrupt TRAP has the highest priority, followed by RST7.5, RST6.5, RST5.5,
and INTR. It means if multiple interrupts occur, then microprocessor will service the
higher priority interrupt first and then the lower priority one.
Out of these, TRAP is non-maskable. The other interrupts are maskable, i.e., they
can be enabled or disabled using EI and DI instructions. To selectively mask interrupts
between RST7.5, RST6.5 and RST5.5, SIM instruction is used.
4 External Hardware Circuit to supply RST n opcode
for INTR interrupt
Let us assume that the opcode which needs to be supplied is DFH which corresponds to
RST 3 instruction.
+5V
Tri-state Buffer
1
b
DI7
1
b
DI6
b
0
DI5
b
1
b
DI4
b
DFH To Data Bus

1
b
DI3
b
1
b
DI2
b
1
b
DI1
b
1
DI0
b
bc
ENABLE
← INTA from microprocessor
3
SIM : Set Interrupt Mask
In response to the Interrupt Request (INTR), 8085 sends the INTA (Interrupt Ac-
knowledge) low signal. This is used to enable the buffer and the corresponding RST
instruction opcode (DF) is placed on the data bus. Once the microprocessor gets the
opcode, it decodes that the interrupt is due to RST 3 instruction and the program control
is transferred to the vector address (3 × 8 = 24D = 18H ) 0018H.
5 SIM : Set Interrupt Mask
SIM instruction is used to selectively disable the interrupts. For this, we need to know
the bit pattern of the SIM instruction which is as follows:
D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE X R7.5 MSE M7.5 M6.5 M5.5

I I I I I I I I I
For interrupt purpose, bit D7 (SOD) and bit D6 (SDE) are not used and are basically
in don’t care condition.
• To enable selective masking, first and foremost bit D3 , i.e., Mask Set Enable (MSE)
has to be 1.
• To mask RST 5.5, bit D0 , i.e., Mask RST5.5 (M5.5) should be 1; to enable RST 5.5,
bit D0 should be 0
• To mask RST 6.5, bit D1 , i.e., Mask RST6.5 (M6.5) should be 1; to enable RST 6.5,
bit D1 should be 0
• To mask RST 7.5, bit D2 , i.e., Mask RST7.5 (M7.5) should be 1 and bit D4 , i.e.,
Reset RST7.5 (R7.5) should be 1; to enable RST 7.5, bit D2 should be 0 and bit
D4 should be 0
4
Example 1
Write a set of instructions to satisfy the following requirements

• Mask RST 6.5 and enable RST 7.5 and RST 5.5 interrupt requests.
• Enable INTR interrupt request.
First, find the bit pattern according to the question.
SOD SID X R7.5 MSE M7.5 M6.5 M5.5
X X X 0 1 0 1 0
I I I I I I I I I
EI; Enable INTR interrupt request

MVI A,0AH; According to the question, bit pattern is 0A
SIM
Example 2

X X X 1 1 1 0 0
I I I I I I I I I

MVI A,1CH; According to the question, bit pattern is 1C
SIM
5
Example 3

X X X 0 1 0 0 1
I I I I I I I I I

MVI A,09H; According to the question, bit pattern is 09
SIM
Example 4

• Mask RST 5.5 and RST 6.5 and enable RST 7.5 interrupt requests.
X X X 0 1 0 1 1
I I I I I I I I I

MVI A,0BH; According to the question, bit pattern is 0B
SIM
6
RIM : Read Interrupt Mask
Example 5

• Mask RST 5.5 and RST 7.5 and enable RST 6.5 interrupt requests.
X X X 1 1 1 0 1
I I I I I I I I I

MVI A,1DH; According to the question, bit pattern is 1D
SIM
6 RIM : Read Interrupt Mask
RIM instruction is used to see the status of the interrupts. For this, we need to know the
bit pattern of the RIM instruction, which is as follows:
D7 D6 D5 D4 D3 D2 D1 D0
SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5
For interrupt process, bit D7 are not used and are basically in don’t care condition.
If RST 7.5 is pending, bit D6 will be 1
If interrupt flip-flop is set, i.e., interrupt process is enabled, bit D3 will be 1
If RST 7.5 is masked, bit D2 will be 1
7
RIM : Read Interrupt Mask
To do any checking, first select which one you want to check. Then put 1 in the
corresponding bit and put 0 in remaining bits.
Example 1
Write the instruction to check if RST 5.5 is pending or not.

To check RST 5.5 pending, we put 1 in bit D4 and the remaining bits are 0.
SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5
0 0 0 1 0 0 0 0
RIM; Read the status of Interrupts

ANI 10H; According to the question, check RST 5.5 pending
Example 2
Write the instruction to check if RST 7.5 is pending or not.

To check RST 7.5 pending, we put 1 in bit D6 and the remaining bits are 0.
SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5
0 1 0 0 0 0 0 0

ANI 40H; According to the question, check RST 7.5 pending
8
INA Machine Cycle
Example 3
Write the instruction to check if RST 6.5 is masked or not.

To check RST 6.5 masked, we put 1 in bit D1 and the remaining bits are 0.
SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5
0 0 0 0 0 0 1 0

ANI 02H; According to the question, check RST 6.5 masked
7 INA Machine Cycle
The timing diagram of RST n instruction is shown below. It consists of three machine
cycles.
The first machine cycle is Interrupt Acknowledge Machine Cycle (INA M/C) and not
the usual Opcode Fetch M/C. With this M/C, the microprocessor gets the opcode from the
external hardware circuit and understands the vector address for the INTR interrupt. In
this M/C, the opcode is given only when INTA is low. The RD will remain high. Since, in
this M/C opcode is fetched not from memory but from an external device (peripheral/IO)
the value of IO/M, S1 , S0 is 1, 1, 1 respectively. This M/C requires 6 T-states as because
return address has to be pushed to stack and as such Stack Pointer (16-bit) has to be
decremented.
The remaining two machine cycles are Memory Write M/Cs which are used to store
the return address in the stack.
9
Timing Diagram of RST instruction
M1 : Interrupt Acknowledge M/C M2 : Memory Write M/C M3 : Memory Write M/C
T1 T2 T3 T4 T5 T6 T1 T2 T3 T1 T2 T3
CLK
A15 –A8 PCH Unspecified (SP-1)H (SP-2)H
Lower Order Opcode Lower Order Data from µP Lower Order Data from µP
1
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PCL RST (SP-1)L (PC)H (SP-2)L (PC)L
-------i--
Memory Address Memory Address to Memory Memory Address to Memory
-----1----
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10
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-t-
IO/M = 1, S1 = 1, S0 = 1 IO/M = 0, S1 = 0, S0 = 1 IO/M = 0, S1 = 0, S0 = 1
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Unit Seven: Interfacing Chips

I. 8255 – Programmable Peripheral Interface

1 8255 Architecture and Pin Diagram
--c
Power Supplies
+5V
GND
Group
Group
A
Port
I/O
PA7 − PA0
A A
Control (8)
Bidirectional Data Bus Group I/O

A PC7 − PC4
Data Port C
D7 − D0 Bus Upper
Buffer 8-Bit (4) b
Internal
Data
Bus
Group
--
RD
WR
cb
bc
Read
B
Port C
Lower
(4) b
I/O
PC3 − PC0
A1 Write
Group
Control
A0 Logic b B
Control
Group
RESET B I/O
Port
PB7 − PB0
B
bc
(8)
CS t b
PA3 PA4
PA2 PA 5
P A1 PA6
PAo PA7
RD WR
cs RESET
GKD Do
Ai D1
Ao D2
PC7 D3
PCG D4
PC5 Do
PC4 D6
PCo D7
PC1 Vss
PC2 PB7
PC 0 PRr,
PBo PB 0
I'B 1 PB4
PD2 PB3
Figure 2: 8255 Pin Diagram
1
1.1 Need for IO ports
The 8255A has 24 I/O pins (out of total 40 pins) that can be grouped primarily in
two 8-bit parallel ports: A and B, with the remaining eight bits as port C. The eight bits
of port C can be used as individual bits or be grouped in two 4-bit ports: CUPPER (CU )
and CLOWER (CL ). The functions of these ports are defined by writing a control word in
the control register.
1.1 Need for IO ports
The I/O devices can not be directly interfaced with the microprocessors for reasons which
are described below:
• I/O devices are not usually equipped with tri-stated buffers, so direct interfacing
result in bus-contention.
• Device selection logic is usually not present in I/O device.
• In order to transfer data (asynchronous, interrupt-driven, etc), we need various

handshaking signals which are not provided by the I/O device.
• The rate at which data transfer between the µP and I/O device is not same.
The rough schematic of interfacing an I/O device is shown below
CS
Address Bus
µP I/O Port Data Bus I/O Device

Data Bus
Control Signals
2
2 Chip Select Logic and Port Address
In 8255, CS is used to select the chip, i.e., the decoded address is connected to this pin.
A0 and A1 are connected to µP address lines A0 and A1 , respectively and are used to
internally decode among Port A, Port B, Port C and Control Register as given below:
CS A1 A1 Selected Valid Operation
0 0 0 Port A Read and Write

0 0 1 Port B Read and Write
0 1 0 Port C Read and Write
0 1 1 Control Register Write
1 X X 8255 not selected –
As an example, the port addresses in the figure below are determined by the CS, A0 and A1
lines.
A7
bc
A6
bc
A5
bc bc
CS
bc
A4
A1 8255
bc
A3
A0
bc
A2
A1
A0
CS Hex Addr. Port

A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 = 80H A
0 1 = 81H B
1 0 = 82H C
1 1 = 83H Control Register
3
3 Control Word
I I D7 D6 D5
I I I I I I
D4 D3 D2 D1 D0
--
I Group B
\
Port C (Lower) : PC3 -PC0
1 = Input
0 = Output
Port B
1 = Input
0 = Output
Mode Selection
1 = Mode 1
0 = Mode 0
I Group A
\
Port C (Upper) : PC7 -PC4
1 = Input
0 = Output
Port A
1 = Input
0 = Output
Mode Selection
00 = Mode 0
01 = Mode 1
1X = Mode 2
1 = I/O Mode
0 = BSR Mode
Figure 3: 8255A Control Word Format
4
4 BSR Mode
The Bit Set/Reset Mode is concerned only with the eight bits of Port C, which can be set
or reset by writing an appropriate control word in the control register. The I/O operations
of Port A and Port B are not affected by a BSR control word.
Control Word
D7 D6 D5 D4 D3 D2 D1 D0
Bit Set/Reset
X X X - 1 = Set
I I 0 = Reset
DON’T
CARE
,
B2 B1 B0
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 0 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7
Bit Select
Bit Set Reset Flag
0 = Active
Figure 4: BSR Control Word Format
5
5 I/O Mode
There are three basic modes of operation that can be selected by the system hardware
(using appropriate control word):
• Mode 0 – Basic Input/Output
• Mode 1 – Strobed Input/Output
• Mode 2 – Bi-directional Bus
Each mode will be discussed in detail.
5.1 Mode 0: Simple Input or Output
This mode provides simple input and output operations for each of the three ports. No
“handshaking” is required, data is simply written to or read from a specified port. The
functional definitions are as follows:
1. Two 8-bit ports (A and B), and two 4-bit ports (CU and CL ).
2. Any port can be input or output.
3. Outputs are latched.
4. Inputs are not latched.
Note: 16 different Input/Output configurations are possible in this Mode.
5.2 Mode 1: Input or Output with Handshake
This mode provides a means for transferring I/O data to or from a specified port in
conjunction with strobes or “handshaking” signals. The features of this mode include the
following:
1. Two ports (A and B) function as 8-bit I/O ports. They can be configured either as
input or output ports.
2. Each port uses three lines from port C as handshake signals. The remaining two
lines can be used for simple I/O functions.
6
3. Input and output data are latched.
4. Interrupt logic is supported.
Note: Mode 1 can be used either in Asynchronous mode (using handshaking signals) or
in Interrupt-driven mode (using INTR signal).
In 8255, the specific lines from Port C used for handshake signals vary according to
the I/O function of a port.
5.2.1 Input
The associated control signals used for handshaking when ports A and B are configured
as input ports are shown below.
PA7 – PA0
Connected to I/O device

r----.,
I I STBA
IINTEA I PC4
. __ .
I I
IBFA
PC5
Connected to any one of the

INTRA interrupt pins of µP
PC3
(RST 7.5, RST 6.5, RST 5.5, INTR)
PB7 – PB0

r----,
I I
IINTEB I PC2 STBB
. __ .
I I
IBFB
PC1
bc INTRB Connected to any one of the

RD
PC0 interrupt pins of µP
(RST 7.5, RST 6.5, RST 5.5, INTR)
PC6,7 Simple I/O
Figure 5: 8255 Mode 1 Input Configuration
7
Let us first consider asynchronous data transfer and for the sake of brevity, we will
explain using Port A. First STBA goes “low”, signifying that data has been transfered from
the I/O device to 8255’s Port A. The 8255 in response to STBA will generate an IBFA
“high” signal to indicate that it has received the data. After this, µP will generate RD
signal to read the data from Port A. Once the read operation is completed, IBFA becomes
inactive (goes “low”) and the I/O device can start sending the next data by making STBA
“low”.
In Interrupt-driven data transfer, first STBA goes “low”, signifying that data has been
transfered from the I/O device to 8255’s Port A. The 8255 in response to STBA will gener-
ate an IBFA “high” signal to indicate that it has received the data. It will also generate an
INTRA “high” signal (assuming INTEA flip-flop is set). This INTRA signal will interrupt
the µP and as a consequence of this, the µP will jump to the corresponding Interrupt
Service Sub-routine (ISS) address. The INTRA signal becomes inactive (goes “low”) and
the µP performs a read operation to transfer the data from Port A to µP.
Timing Diagram
STB bc bc
bc
bc bc
bc
IBF
bc
bc
INTR
RD bc
bc
bc
Input from I/O Device

-----<_______,>--------------------------
Figure 6: Input Timing Diagram for both Asynchronous and Interrupt-driven
Data Transfer
8
Input Control Signals
The functions of the control signals can be summarized as follows:
• STB (Strobe Input): This signal (active low) is generated by an I/O device to
indicate that it has transmitted a byte of data.
• IBF (Input Buffer Full): This output signal is an acknowledgment by the 8255 to
indicate that the input latch has received the data byte. This is reset when the µP
reads the data.
• INTR (Interrupt Request): This is an output signal which is used to interrupt the
µP. This signal is generated if STB, IBF and INTE are all at logic 1. This is reset
by the falling edge of the RD signal.
• INTE (Interrupt Enable): This is an internal flip-flop used to enable or disable

the generation of INTR signal. This is set or reset using PC4 (for INTEA ) or
PC2 (for INTEB ) in BSR mode.
Control Word
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 1/0 1 1 X
I/O Mode Port B Input
Port A Mode 1 Port B Mode 1
Port A Input PC6 ,7

1 = Input
0 = Output
Figure 7: Mode 1 Input Control Word Format
9
5.2.2 Output
The associated control signals used for handshaking when ports A and B are configured
as output ports are shown below.
PA7 – PA0
OBFA
PC7
r---.,
I ACKA
IINTEA PC6
I _.
Connected to any one of the

INTRA interrupt pins of µP
PC3
(RST 7.5, RST 6.5, RST 5.5, INTR)
PB7 – PB0
bc
WR
OBFB
PC1
r---.,
I ACKB
IINTEB PC2
I _.
INTRB Connected to any one of the

PC0 interrupt pins of µP
(RST 7.5, RST 6.5, RST 5.5, INTR)
PC4,5 Simple I/O
Figure 8: 8255 Mode 1 Output Configuration
10
Let us first consider asynchronous data transfer and for the sake of brevity, we will
explain using Port B. First WR goes “low”, indicating that the µP has written some data
onto 8255’s Port B. In response to this, 8255 will make OBFB “low”, which will tell the
I/O device that new data is available. Once the I/O device has received the new data, it
will generate an ACKB “low” signal and make OBFB signal inactive (“high”) to indicate
that the output buffer is empty and that new data can be written by the µP.
In Interrupt-driven data transfer, an interrupt causes the µP to write data. Once data
has been written, the INTRB signal goes “low”. 8255 also makes OBFB signal “low”, which
will tell the I/O device that new data is available. Once the I/O device has received the
new data, it will generate an ACKB “low” signal and make OBFB signal inactive (“high”)
to indicate that the output buffer is empty. 8255 will now generate an INTRB “high”
signal (assuming INTEB flip-flop is set). This will interrupt the µP and as a consequence,
the µP will jump to the corresponding ISS address and perform the next write instruction.
Timing Diagram
bc
WR
bc
OBF bc bc
bc
bc
INTR
bc
bc bc
ACK
bc
Output
Figure 9: Output Timing Diagram for both Asynchronous and Interrupt-driven

Data Transfer
11
Output Control Signals
The functions of the control signals can be summarized as follows:
• OBF (Output Buffer Full): This is an output signal that goes low when the µP
writes data into the output latch of 8255. This signal indicates to an output pe-
ripheral that new data is ready to be read.
• ACK (Acknowledge): This is an input signal from an I/O device that goes low to
inform the 8255 that data from the port has been accepted.
• INTR (Interrupt Request): This is an output signal which is used to interrupt the
µP to request the next data. This signal is generated if OBF, ACK and INTE are
all at logic 1. This is reset by the falling edge of the WR signal.
• INTE (Interrupt Enable): This is an internal flip-flop used to enable or disable

the generation of INTR signal. This is set or reset using PC6 (for INTEA ) or
PC2 (for INTEB ) in BSR mode.
Control Word
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 1/0 1 0 X
I/O Mode Port B Output
Port A Mode 1 Port B Mode 1
Port A Output PC4 ,5

1 = Input
0 = Output
Figure 10: Mode 1 Output Control Word Format
12
5.3 Mode 2: Bidirectional Data Transfer
5.3 Mode 2: Bidirectional Data Transfer
This mode provides a means for communicating with a peripheral device on a single 8-bit
bus for both transmitting and receiving data. The features of this mode include:
1. Port A is used as the bidirectional port.
2. Port B can be configured either in Mode 0 or Mode 1.
3. Port A uses five lines from Port C (PC3 to PC7 ) as handshaking signals. These are
provided to maintain proper bus flow discipline. The remaining three lines (PC0 to
PC2 ) can be used for simple I/O functions or as handshake for Port B.
4. Both inputs and outputs are latched.
5. Interrupt logic is supported.
Control Word
D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X X 1/0 1/0 1/0
I/O Mode PC0−2

1 = Input
0 = Output
Port A Mode 2
Port B
1 = Input
0 = Output
Group B Mode
1 = Mode 1
0 = Mode 0
13
Summary
D7
0/1
BSR Mode I/O Mode
For Port C
No effect on I/O Mode

I
Mode 0
I
Mode 1
I
Mode 2
Simple I/O Handshake I/O Bidirectional data bus

for ports for ports A and/or B for port A
A, B, and C
Port B: either Mode 0 or 1
6 Port C bits 5 Port C bits

are used for are used for
handshake handshake for Port A
2 Port C bits 3 Port C bits
are used as are used as
Simple I/O Simple I/O or
handshake for Port B
Input Output Port B Port B

Port A
Mode 0 Mode 1
Port A PC3,4,5 PC3,6,7
PC3,4,5,6,7 PC0,1,2 PC0,1,2
Port B PC0,1,2 PC0,1,2
Handshake Simple I/O Handshake
Simple I/O PC6,7 PC4,5 for port A for port B
6 Examples
6.1 Write the instructions to incorporate the following settings in 8255 PPI.
• Port A as a bidirectional port.
• Port B as output port in Mode 0
• Rest pins of Port C as input ports.
Given that, address of the Control Register is D3H
Calculating the control word:
D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X X 0 0 1
I/O Mode PC0−2 Input
Port B output
Port A Mode 2
Group B Mode 0
MVI A, 0C1H ; Control Word, assume ‘0’ as don’t care

OUT 0D3H ; Control Word written to Control Register
; 8255 is now configured accordingly
15
• Port A as a bidirectional port.
• Port B as output port in Mode 1
Given that, address of the Control Register is F3H
Calculating the control word:
D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X X 1 0 X
I/O Mode Port B output
Port A Mode 2 Group B Mode 1
MVI A, 0C4H ; Control Word, assume ‘0’ as don’t care

OUT 0F3H ; Control Word written to Control Register
; 8255 is now configured accordingly
16
6.3 Write the instructions to set bits PC7 and PC3 and reset them after 10 ms. Assume
DELAY subroutine is available, Control Register address is 83H.
Calculating the control words to set and reset PC7 and PC3 respectively:
D7 D6 D5 D4 D3 D2 D1 D0
Control Word
BSR Mode Don’t Care Bit Select Set/Reset
Set bit PC7 0 X X X 1 1 1 1 0FH
Set bit PC3 0 X X X 0 1 1 1 07H
Reset bit PC7 0 X X X 1 1 1 0 0EH
Reset bit PC3 0 X X X 0 1 1 0 06H
MVI A, 0FH ; Load byte in accumulator to set PC 7

OUT 83H ; Set PC 7 = 1
MVI A, 07H ; Load byte in accumulator to set PC 3
OUT 83H ; Set PC 3 = 1
CALL DELAY ; This is a 10-ms delay
MVI A, 06H ; Load byte in accumulator to reset PC 3
OUT 83H ; Reset PC 3
MVI A, 0EH ; Load byte in accumulator to reset PC 7
OUT 83H ; Reset PC 7
17
• Port A as Input in Mode 1, interrupt-driven data transfer.
• Port B as Output in Mode 1, asynchronous data transfer.
Given that the address of the control register is FFH
For interrupt driven data transfer in Port A, INTEA has to be set. The corresponding bit
is PC4 .
Calculating the control word to initialize 8255:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 X 1 0 X
I/O Mode
Port A Mode 1 Port B Output
Port A Input Group B Mode 1
Calculating the control word to set INTEA :
D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 1 0 0 1
BSR Mode Selected bit is set
Bit PC4 selected
MVI A, B4H ; Control Word, assume ‘0’ as don’t care

OUT FFH ; CW written to CR, 8255 is initialized accordingly
MVI A, 09H ; BSR Control Word to set INTE A (PC 4 )
OUT FFH ; CW written to CR, INTE A is now set
; Initial configuration i.e.,
; (Port A as Mode 1 input , Port B as Mode 1 output)
; does not change.
Note: First initialize the ports accordingly, then use BSR mode to set or reset specific
bit.
18
(Credit - 4)

II. 8259 – Programmable Interrupt Controller

8259 Architecture and Pin Diagram
7 8259 Architecture and Pin Diagram
INTA INT
bc
Data
D7 – D0 Bus
Buffer Control Logic
RD IR0
Read/ IR1
b Interrupt
WR Write In-service IR2
Logic Register Priority Request IR3
A0 (ISR) Resolver Register IR4
(IRR) IR5
CS IR6
IR7
CAS 0
Cascade
CAS 1 Buffer/ Interrupt Mask Register
Comparator (IMR)
CAS 2
SP / EN
CS 1 28 VCC
WR 2 27 A0
RD 3 26 INTA
D7 4 25 IR7
D6 5 24 IR6
D5 6 23 IR5
D4 7 22 IR4
D3 8 21 IR3
D2 9 20 IR2
D1 10 19 IR1
8259
D0 11 18 IR0
CAS 0 12 17 INT
CAS 1 13 16 SP / EN
GND 14 15 CAS 2
Figure 12: 8259 Pin Diagram
1
8259 Architecture and Pin Diagram
7.1 Interrupt Request Register
The IRR stores the bits at which an interrupt is requested. It is used to store all the
interrupt levels which are requesting service.
7.2 In-Service Register
The ISR is used to store all the interrupt levels which are being serviced.
7.3 Interrupt Mask Register
The IMR stores the bits which mask the interrupt lines.
7.4 Priority Resolver
This logic block determines the priorities of the bits set in the IRR. It examines the IRR,
ISR, and IMR and determines whether INT should be sent to the microprocessor.
2
Sequence of Operation
8 Sequence of Operation
To implement interrupts, the Interrupt Enable flip-flop in the microprocessor should be

enabled by writing the EI instruction, and the 8259 should be initialized by writing control
words in the control register.
The 8259 requires two types of control words: Initialization Command Words (ICWs)
and Operational Command Words (OCWs). The ICWs are used to set up the proper
conditions and specify RST vector addresses. The OCWs are used to perform functions
such as masking interrupts, setting up status-read operations, etc.
After the 8259 is initialized, the following sequence of events occurs when one or more
interrupt request lines go high:
1. The IRR stores the requests.
2. The priority resolver checks three registers: the IRR for interrupt requests, the IMR
for masking bits, and the ISR for the interrupt request being served. It resolves the
priority and sets the INT high when appropriate.
3. The µP acknowledges the interrupt by sending INTA.
4. After the INTA is received, the appropriate priority bit in the ISR is set to indicate
which interrupt level is being served, and the corresponding bit in the IRR is reset
to indicate that the request is accepted. Then, 8259 will send the opcode for the
CALL instruction to µP
5. When the µP decodes the CALL instruction, it will send two more INTA signals.
6. When the 8259 receives the second INTA, it places the low-order byte of the CALL
address on the data bus. At the third INTA, it places the high-order byte on the
data bus.
7. During the third INTA pulse, the ISR bit is reset either automatically (AEOI) or
by a command (EOI).
8. The program sequence is transferred to the memory location specified by the CALL
instruction.
3
Command Words
9 Command Words
The 8259A accepts two types of command words generated by the µP:
1. Initialization Command Words (ICWs): Before normal operation can begin,

each 8259 in the system must be brought to a starting point – by a sequence of 2
to 4 ICWs.
2. Operation Command Words (OCWs): These are the command words which
command the 8259 to operate in various interrupt modes. These modes are:
(a) Fully nested mode
(b) Rotating priority mode
(c) Special mask mode
(d) Polled mode
9.1 Initialization Command Word
The 8259 can be initialized with four ICWs; the first two are essential, and the other two
are optional based on the modes being used.
ICW1
ICW1 starts the initialization sequence. It is interpreted with A0 = 0 and D4 = 1. It has

the following format:
A0 D4
□
0 D7 D6 D5 1 D3 D2 D1 D0
I I I I I I I I I
ICW4
I
1 = ICW4 needed
I I
0 = No ICW4 needed
Single/Multiple
1 = Single
0 = Cascaded
Call Address Interval

1 = Interval of 4
0 = Interval of 8
Triggering Mode
1 = Level Triggered Mode
0 = Edge Triggered Mode
Vector Address
A7 − A5 for interval of 4
A7 − A6 for interval of 8
4
Command Words
ICW2
The ICW2 specifies the high-order byte of the CALL instruction. It is interpreted with
A0 = 1. It has the following format:
A0
1 D7 D6 D5 D4 D3 D2 D1 D0
A15 −A8 of
Interrupt Vector Address
ICW3
This word is read only when there is more than one 8259 in the system and cascading is
used. In this case, one of the 8259 will be the master device and the others will be slave
device. The corresponding format of ICW3 for master and slave is shown below:
MASTER DEVICE SLAVE DEVICE
A0 A0 D7 D6 D5 D4 D3
□ I0 I0 I0
1 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 D2 D1 D0
1 = IR input has a slave

0 = IR input does not have IR0 0 0 0
a slave
IR1 0 0 1
IR2 0 1 0
IR3 0 1 1
IR4 1 0 0
IR5 1 0 1
IR6 1 1 0
IR7 1 1 1
Slave ID
ICW4
This specifies what type of µP is used, the type of End of Interrupts, etc.
5
Command Words
9.2 Operation Command Word
After the 8259 has been initialized using the ICWs, it can be made to operate in various
modes using the OCWs.
OCW1
OCW1 is used to set and clear the mask bits in the Interrupt Mask Register. By specifying
this command word, we can mask or enable any of the eight interrupts of the 8259. It
has the following format:
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0
Interrupt Mask
1 = Mask set
0 = Mask reset (Enable)
OCW2
OCW2 controls the Rotate and End of Interrupt modes and combinations of the two. It
also determines the interrupt level to be acted upon.
OCW3
OCW3 specifies some special commands like special mask mode, polling command and
read register command.
6
Priority Modes
10 Priority Modes
Many types of priority modes are available under software control in 8259, and they can
be changed dynamically during the program by writing appropriate OCWs. Commonly
used priority modes are discussed below:
10.1 Fully Nested Mode
This is a general purpose mode in which all Interrupt Requests (IRs) are arranged from
highest to lowest, with IR0 as the highest and IR7 as the lowest.
IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0

7 6 5 4 3 2 1 0
↑ ↑
Lowest Highest
10.2 Automatic Rotation Mode
In this mode, a device, after being serviced, receives the lowest priority. Assuming IR2
has the highest priority requiring service, then after it has been serviced, it will receive
the lowest priority, as shown below.

4 3 2 1 0 7 6 5
↑
Lowest
10.3 Specific Rotation Mode
This mode is similar to Automatic Rotation mode, except that the user can select any
IR for the lowest priority, thus fixing all other priorities. If IR4 is programmed as the
bottom priority device, then IR5 will have the highest priority.

2 1 0 7 6 5 4 3
↑ ↑
Highest Lowest
7
End of Interrupt (EOI)
11 End of Interrupt (EOI)
After the completion of an interrupt service, the corresponding ISR bit needs to be reset
to update the information in the ISR. This is called the End-of-Interrupt (EOI) command.
It can be issued in three formats:
11.1 Nonspecific EOI
When this command is sent to the 8259, it resets the highest priority ISR bit.
11.2 Specific EOI
This command specifies which ISR bit to reset.
11.3 Automatic EOI
In this mode, no command is necessary. During the third INTA, the ISR bit is reset.
Note: The major drawback with Automatic EOI is that the ISR does not have infor-
mation on which IR is being serviced. Thus, any IR can interrupt the service routine,
irrespective of its priority, if Interrupt Enable flip-flop is set.
8
Initialization Sequence
12 Initialization Sequence
ICW1
ICW2
NO (SNGL = 1)
YES (SNGL = 0)
ICW3
NO (IC4 = 0)
YES (IC4 = 1)
ICW4
READY TO ACCEPT
INTERRUPT REQUESTS
9
Examples
13 Examples
7.1 Find ICW1, ICW2 and call address of IR0 interrupt request for a single 8259 chip in
a 8085 system with the following parameters.
• Status of A7 A6 A5 = 1 0 1 and A15 –A8 = 50H .
• Call address interval of 4.
• Level triggered.
• ICW4 is not required.
ICW1 = BEH as calculated below.
A7 A6 A5 D4 LTIM ADI SNGL ICW4

1 0 1 1 1 1 1 0
ICW2 = A15 –A8 = 50H .
Call address for IR0 = 50A0H as calculated below.
A15 –A8 A7 A6 A5 A4 A3 A2 A1 A0 Address

50
I 1 I 0 I 1 I 0 I 0 I 0 I 0 I 0 I 50A0H
10
Examples
7.2 Find ICW1 and ICW2 for a single 8259 chip in a 8085 system with the following
parameters.
• Call address of IR3 interrupt request is 2038H .
• Interrupts are edge triggered.
• ICW4 is not required.
Given, call address of IR3 interrupt is 2038H , i.e.,
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0
Therefore, ICW2 = A15 –A8 = 20H .
Call address interval is 8. So A7 and A6 will come from the given call address, while
A5 –A0 are fixed. So we have
A7 A6 A5 A4 A3 A2 A1 A0 Interrupt
0 0 0 1 1 0 0 0 IR3
Therefore, ICW1 = 12H as calculated below.
A7 A6 A5 D4 LTIM ADI SNGL ICW4

0 0 0 1 0 0 1 0
11
Examples
7.3 How many 8259 ICs are required to have a total of 29 interrupts.
We know, for N 8259 ICs, the total number of interrupts is given by
T = 7N + 1
=⇒ 29 = 7N + 1
∴N =4
7.4 Find ICW3 for the 8259 ICs shown in the figure below.
IR0
IR1 8259
IR2
IR3
02
8259 IR4
8259
IR5
IR6 03
0 1 IR7 8259
04
The slaves are connected to IR1, IR4 and IR7 of the master 8259. So ICW3 are as follows.
Chip IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 ICW3
Master 1 0 0 1 0 0 1 0 92H
Chip D7 D6 D5 D4 D3 Slave ID ICW3

Slave 1 0 0 0 0 0 0 0 1 01H
Slave 2 0 0 0 0 0 1 0 0 04H
Slave 3 0 0 0 0 0 1 1 1 07H
12
(Credit - 4)

III. 8251 – Universal Synchronous Asynchronous
Receive Transmit (USART)

14 Signals
14.1 Control Signals
• CS − Chip Select: When this signal goes low, the 8251 is selected by the µP for
communication. This is usually connected to decoded address bus.
• C/D − Control/Data: When this signal is high, the control register or the status
register is addressed; when it is low, the data buffer is addressed. The control
register and status register are differentiated by WR and RD signals respectively.
• WR − Write: When this signal goes low, the µP writes either in the control
register or in the data buffer.
• RD − Read: When this signal goes low, the µP reads either from the status register
or from the data buffer.
CS C/D RD WR Function
0 1 1 0 µP writes instructions in the control register
0 1 0 1 µP reads status from the status register
0 0 1 0 µP outputs data to the Data Buffer
0 0 0 1 µP accepts data from the Data Buffer
1 X X X USART is not selected
Control Register
This 16-bit register for a control word consists of two independent bytes: the first byte
is called the Mode Word and the second byte is called the Command Word. This
register is accessed as an output port when the C/D pin is high. µP can only write to
this register.
Status Register
This input register checks the ready status of a peripheral. This register is addressed as
an input port when the CD pin is high. µP can only read from this register.
1
14.2 Receiver section signals
Data Buffer
This bidirectional register can be addressed as an input port and an output port when
the C/D pin is low.
14.2 Receiver section signals
The receiver section of 8251 consists of 2 input signals and 1 output signal. These are
described below.
• RX D − Receive Data: Bits are received serially on this line and converted into a
parallel byte in the receiver input register.
• RX C − Receiver Clock: This is a clock signal that controls the rate at which bits
are received by the USART. In the asynchronous mode, the clock can be set to 1,
16 or 64 times the baud.
• RX RDY − Receiver Ready: This is an output signal. It goes high when the
USART has a character in the buffer register and is ready to transfer it to the µP.
14.3 Transmitter section signals
The transmitter section of 8251 consists of 1 input signal and 3 output signals. These are
described below.
• TX D − Transmit Data: Serial bits are transmitted on this line.
• TX C − Transmitter Clock: This input signal controls the rate at which bits are
transmitted by the USART. It can be se to 1, 16 or 64 times the baud.
• TX RDY − Transmitter Ready: This is an output signal. When it is high, it

indicates that the buffer register is empty and the USART is ready to accept a byte.
• TX E − Transmitter Empty: This is an output signal. A high on his line indicates

that the output register is empty.
2
15 Control Word
Prior to starting data transmission or reception, the 8251 must be loaded with a set of
control words. The control words are divided into two formats: mode word and command
word.
15.1 Mode Word
The mode word defines the general characteristics of operation such as asynchronous or
synchronous mode of transmission, number of stop bits required, character length, parity,
etc. It has the following format:
D7 D6 D5 D4 D3 D2 D1 D0 ASYNC MODE SYNC MODE
Baud Rate Factor

01 = 1× 00 = Sync Mode
10 = 16× (Fixed)
11 = 64×
Character Length
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
Parity
X0 = No parity
01 = Odd parity
11 = Even Parity
D6
No. of Stop Bits
0= SYNDET is O/P
00 = Invalid 1= SYNDET is I/P
01 = 1 bit D7
10 = 1 21 bits 0= Double Sync Character
11 = 2 bits 1= Single Sync Character
3
15.2 Command Word
15.2 Command Word
The command word is used to control the actual operation of the 8251. It enables data
transmission and/or reception among various other functions. It has the following format:
I I I I I I I II I
D7 D6 D5 D4 D3 D2 D1 D0
Trasnmit Enable
- 1 = Enable
0 = Disable
Data Terminal Ready

-
“high” will force DTR
output to zero
Receive Enable
1 = Enable
0 = Disable
Send BREAK Character

- 1 = forces TX D “low”
0 = Normal Operation
Error Reset
1 = reset error flags
0 = Normal Operation
Request To- Send

- “high” will force RTS
output to zero
Internal Reset
- 1 = returns 8251 to
Mode Format
0 = normal operation
Enter Hunt Mode

1 = enable search for
- sync characters
X = Async Mode
4
15.2 Command Word
Questions related to framing of Control Words of 8255,
8259, and 8251
8255
Prob 1. Frame a control word for the following configuration of ports of 8255
• Port A as input port in mode 1.
• Port B as output port in mode 0.
• Port CL as input and rest pins of Port C as output.
Prob 2. Frame a control word for a 8255 PPI where Port A should be configured
as output port in mode 1, Port B as output port in Mode 1 and rest of
the pins of Port C as output port.
Prob 3. What should be the control word to set bit PC5 of 8255 in BSR mode?
Prob 4. Frame the control word to configure Port A of 8255 in the bidirectional
mode when port B is working as output port in mode 1.
Prob 5. What should be the control word to set bit PC7 of 8255 in BSR mode?
Prob 6. Frame a control word for the following configuration of ports of 8255.
• Port B as output port in mode 0.
• Port C lower as input port and Port C upper as output port
Prob 7. Frame a control word for a 8255 PPI where Port A should be configured
as output port in mode 1, Port B as input port in mode 1 and the rest
pins of Port C as input port.
Prob 8. What should be the control word to set bit PC6 of 8255 in BSR Mode?
5
15.2 Command Word
• Port B as input port in mode 0.
• Port CL as output and rest pins of Port C as input.
Prob 10. What should be the control word to reset bit PC4 of 8255 in BSR mode?
• Port A as output port in mode 1.
• Rest of the pins of Port C as input.
Prob 12. What should be the control word to set PC5 and reset PC6 of 8255 in BSR
mode?
Prob 13. Find the control word for the following configuration of ports of 8255 in
simple IO mode.
• Port A and Port CL as inputs.
• Port B and Port CU as outputs.
Prob 14. If the BSR mode control word in 8255 is 0DH, then specify which Port C
bit is set or reset.
Prob 15. Frame the control word to incorporate the following settings in 8255 PPI.
• Port A as bidirectional port.
• Rest of the pins of Port C as output ports.
8259
Prob 1. Determine OCW1 for a 8259 PIC to unmask only IR5 and mask the rest
of the interrupt inputs.
Prob 2. Frame the control words ICW1 and ICW2 for a single 8259 PIC such that
it meets the following specifications.
6
15.2 Command Word
• Interrupt vector address for IR0 to be placed at 2090H.
• Interrupts are to be edge-triggered.
Prob 3. Frame the ICW1 and ICW2 for a single 8259 chip in a 8085 system with
the following parameters.
• Call address for IR0 to be placed at 8000H.
• Level triggered.
Prob 4. Determine OCW1 for a 8259 to unmask only IR6 and IR7 and mask the
rest of the interrupts.
Prob 5. Frame the ICW1 and ICW2 for a single 8259 chip in a 8085 system with
the following specifications.
• Call address for IR3 to be placed at F008H.
• Edge triggered.
Prob 6. Frame the ICW1 and ICW2 for a single 8259 chip interfaced to a 8085
system with the following parameters.
• Call address for IR4 to be placed at F030H.
• Edge triggered.
Prob 7. Find ICW1 , ICW2 and call address of IR0 and IR1 interrupt requests for
a single 8259 chip in 8085 system with the following parameters.
• Value of A7 A6 A6 = 1 0 0, and A15 −A8 = 48H.
• Edge triggered.
7
15.2 Command Word
Prob 8. If an IO device has sent an interrupt request through IR2 line of 8259 PIC,
then find the interrupt vector address to which the program control will be
transferred to execute the interrupt service subroutine. Given that, 8259
PIC was initialized with ICW1 = 96H and ICW2 = 40H.
Prob 9. Frame the initialization control words of a single 8259 PIC interfaced to a
8085 system such that IR3 interrupt has a vector address of 807CH and is
edge triggered.
Prob 10. Determine OCW1 for a 8259 to unmask IR0 and mask the rest of the
interrupts.
8251
Prob 1. Frame the mode word of 8251 to transmit characters with the following
parameters
• Asynchronous mode with 9600 baud, when clock frequency at TxC is

153.6 kHz.
• Character length 7 bits and 1 stop bit.
• No parity check
Prob 2. Frame the mode word and command word of 8251 to transmit characters
with the te following specifications.
• Transmitter clock frequency is 9.6 kHz.
• Asynchronous mode with 9600 baud.
• Character length is 8 bits with 11⁄2 stop bits
• Odd parity
Prob 3. Frame the mode word and command word of 8251 to receive characters
with the following parameters.
8
15.2 Command Word
• Character length of 5 bits with even parity and 11⁄2 stop bits.
Prob 4. Frame the mode word of 8251 to receive characters with the following
specifications.
• Character length is 6 bits.
• Odd parity
• 1 stop bit.
Prob 5. Frame the mode word of 8251 to transmit characters with the following
parameters.
• Character length of 8 bits.
• Even parity and 2 stop bits.
9
(Credit - 4)
Unit Eight: 16-bit Processor (Intel 8086)

Introduction
1 Introduction
The Intel 8086 is a 16-bit microprocessor. The term 16-bit means that its arithmetic
logic unit, internal registers and most of its instructions are designed to work with 16-bit
binary words.
8086 has a 16-bit data bus which enables it to read or write data to a memory/port,
either 16 bits or 8 bits at a time. It has a 20-bit address bus which means it can address
up to 220 memory locations. If each of these memory locations (registers) are made up of
8 D-flip flops, then 8086 can address up to a maximum of 1MB of memory space.
An external clock generator chip is used to provide the required clock signal which
gets divided internally by 3. The standard internal clock frequency is 5MHz.
The 8086 is designed to operate in two modes, minimum and maximum. In the
minimum mode, the 8086 processor works in a single processor environment. The maximum
mode is designed to be used to work with the coprocessor 8087.
It can pre-fetch up to six instruction bytes from memory and queue them in order to
speed up instruction execution through pipelining.
It uses a 40-pin dual in line package and requires +5V power supply.
1
Architecture
2 Architecture
As shown in the block diagram, the 8086 CPU’s internal architecture is divided into two
independent functional parts, the bus interface unit or BIU, and the execution unit or
EU. The BIU handles all transfers of data and addresses on the buses to and from 8086,
while the EU decodes and executes the instructions fetched by BIU.
,--
1
I
BIU C-BUS
I
I
I
I
I
I
I 6
I
5
Instruction
4 Stream
B-BUS Byte
3
Queue
2
Extra Segment (ES) 1 I

I
Code Segment (CS) I
__ _J
1-
I
Stack Segment (SS) 1 I
I I
I I
Data Segment (DS) I I
I I
I I
Instruction Pointer (IP) I
I
I
I
I
I I
I
CONTROL I
I
I SYSTEM
I
1------ - - -
I
I
I
EU
I
I
I
I A-BUS
I
I
AH AL
ARITHMETIC LOGIC UNIT
BH BL
CH CL
DH DL
Stack Pointer (SP)
Base Pointer (BP)
Source Index (SI)

OPERANDS
Destination Index (DI)
FLAGS
2
Architecture
2.1 Bus Interface Unit
The BIU sends out addresses, fetches instructions from memory, reads data from ports
and memory, and writes data to ports and memory. In other words, the BIU performs all
bus related operations. It consists of the following.
1. Instruction Queue
2. Segment Registers
3. Instruction Pointer
2.1.1 Instruction Queue
While the EU is decoding or executing an instruction which does not require the use of the
buses, the BIU fetches up to six instruction bytes and stores these pre-fetched bytes in a
first-in-first-out register set called a queue. When the EU is ready for its next instruction,
it can now get the opcodes from the queue instead of waiting for another machine cycle.
This pre-fetch and queue scheme greatly speeds up processing.
Fetching the next instruction while the current instruction executes is called pipelining.
2.1.2 Segment Registers
The 8086 BIU sends out 20-bit addresses, so it can address any of the 220 bytes in memory.
However, at any given time the 8086 works with only four 64 KB segments within this
1MB range as shown in the illustrative example below.
The BIU has four 16-bit segment registers, named after the four memory segments—
code segment (CS) register, data segment (DS) register, stack segment (SS) register, and
extra segment (ES) register.
A segment register is used to hold the segment base, i.e., the upper 16 bits of the
starting address or base address for each of the segments. For example if the extra
segment starts from 70000H , then ES register will hold the value 7000H . Similarly, if the
stack segment starts from 548A0H , then SS register will hold the value 548AH .
Another point to be noted is that for example, if the CS register contains 348AH , it
is understood that the code segment starts from 348A0H and ends at (348A0+FFFF=)
3
Architecture
4489FH . Similarly, if DS register contains 2000H , it is understood that the data segment
starts from 20000H and ends at (20000+FFFF=) 2FFFFH .
PHYSICAL
ADDRESS MEMORY
FFFFFH
7FFFFH
T ------------
EXTRA
64 K
1 -------------
SEGMENT
Extra Segment Base

70000H ES = 7000H
6489FH
T ------------
STACK
64 K
1 -------------
SEGMENT
Stack Segment Base

548A0H SS = 5000H
4489FH
T ------------
CODE
64 K SEGMENT
348A0H
1 ------------- Code Segment Base
CS = 348AH
2FFFFH
T ------------
DATA
64 K
1 -------------
SEGMENT
Data Segment Base

20000H DS = 2000H
00000H
Note: The extra segment is used during string operations to store extra destination data.
4
Architecture
2.1.3 Instruction Pointer
The instruction pointer (IP) is a 16-bit register, analogous to the program counter (PC)
of 8085 µP, which holds the address or the offset from where (within the 64 KB code
segment) the next instruction (opcode) is to be fetched.
In 8086, all the opcodes are stored within the code segment. The CS register holds
the base address of this segment. The IP will contain the value which needs to be added
to the CS to get the location from where the next opcode is to be fetched.
An example is taken to illustrate the concept. If the CS register value (base) is 348AH ,
and the IP value (offset) is 4214H , then 8086 will fetch the next instruction from the mem-
ory location calculated as below.
CS I 3 4 8 A 0 ← Hardwired zero
IP + 4 2 1 4
PHYSICAL ADDRESS = I 3 8 A B 4
PHYSICAL
ADDRESS MEMORY
4489FH
CODE
SEGMENT
64 K
38AB4H OPCODE Next Instruction Location
IP = 4214H
Code Segment Base

348A0H CS = 348AH
The 20-bit physical address is often expressed as base:offset and the actual physical
or external address generated by BIU is calculated as shown above.
5
Architecture
2.2 Execution Unit
The execution unit tells the BIU where to fetch the instructions or data from, decodes
instructions, and executes instructions. It consists of the following.
1. Control System
2. Arithmetic Logic Unit
3. Flag Register
4. General Purpose Registers
5. Pointer and Index Registers
2.2.1 Control System
The control system of EU contains control circuitry which directs internal operations.
It also contains a decoder which translates the instructions fetched from memory into a
series of actions which the EU carries out.
2.2.2 Arithmetic Logic Unit
The 8086 EU has a 16-bit arithmetic logic unit which can add, subtract, AND, OR, XOR,
increment, decrement, complement, or shift binary numbers.
2.2.3 Flag Register
A 16-bit flag register in the EU contains nine active flags. Six of them are used to indicate
some condition produced by an instruction and are referred to as conditional flags, while
the remaining three flags are used to control certain operations of the processor and are
referred to as control flags.
8085 Compatible Flags
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1x1x1x1x1 OF DF IF TF SF
I IXI IXI IXI
ZF AF PF CF
: Undefined / Don’t Care
: Control Flags
: Conditional Flags
6
Architecture
The conditional flags are set or reset by the EU on the basis of the results of some arith-
metic or logic operation. The control flags are deliberately set or reset by the programmer
with specific instructions.
A. Conditional flags
1. Carry flag (CF): During 8-bit operation, carry flag is set if the sum is greater
than 8 bits. Likewise, during 16-bit operation, if the sum is greater than 16
bits, then carry flag will be set. Carry flag is also set if borrow is required to
perform subtraction.
2. Parity flag (PF): The 8086 parity flag will be set if the lower 8 bits of the
destination operand has an even number of 1’s.
3. Auxiliary flag (AF): If a carry is produced from lower to upper nibble, or a

borrow is required from upper to lower nibble, then this flag will be set. This
is not a general-purpose flag; it is used internally by the processor during DAA
and DAS instructions (BCD addition and subtraction).
4. Zero flag (ZF): This flag will be set if the result of an arithmetic or logic
operation is zero.
5. Sign flag (SF): If the most significant bit of a byte (i.e., D7 bit) or the most
significant bit of a word (i.e., D15 bit) is 1, then sign flag will be set. This flag is
used to indicate positive and negative numbers represented in 2’s complement
form during signed operations.
6. Overflow flag (OF): This flag will be set if overflow occurs, i.e., the result of a
signed operation is too large to fit in the number of bits available to represent
it.
B. Control flags
1. Trap flag (TF): It is used to set trace mode or single-stepping mode. Here the
microprocessor is interrupted after every instruction so that the program can
be debugged.
7
Architecture
2. Interrupt flag (IF): It is used to enable (unmask) or disable (mask) the INTR
interrupt of 8086.
3. Direction flag (DF): It is used with string instructions. If it is set, string bytes
are accessed from higher memory address to lower memory address. When it
is reset, the string bytes are accessed from lower memory address to higher
memory address.
2.2.4 General Purpose Registers
The general purpose registers are used primarily for holding operands for arithmetic and
logical operations.
In 8086, there are 4 16-bit registers, namely— AX, BX, CX, and DX. Each of these
can be used either as one 16-bit register or two 8-bit registers, with the least significant
l ower halves named as AL, BL, CL, and DL and the most significant higher halves named
as AH, BH, CH, and DH.
For the most part, the contents of the general registers can participate interchangeably
in the arithmetic and logical operations of the 8086. However, there are a few instructions
that dedicate certain general register to specific uses. They are as follows.
• AX : ACCUMULATOR — For MUL and DIV operations, it is required that one of

the operands be in the accumulator.
• BX : BASE Register — It is the only general-purpose register which is used for

indirect addressing.
• CX : COUNT Register — It is used to keep a count of the number of iterations in

a loop, number of bits to shift and rotate, or specify the number of characters in a
string.
• DX : DATA Register — It is used together with AX for 16-bit MUL and DIV opera-
tions. It is also used to hold the port address for IN and OUT instructions.
8
Architecture
2.2.5 Pointer and Index Registers
An instruction that accesses a location in memory could specify the address of that lo-
cation directly. This address takes up space in the instruction, thereby increasing the
size of the code. If addresses of frequently used locations were stored in special registers,
instructions that access these locations would no longer need to contain the address but
could instead specify the register that contained the address. Such registers are sometimes
called pointer or index registers.
The pointer and index registers of 8086 consist of the 16-bit registers SP, BP, SI, and
DI. The pointer registers are generally used as offset for stack segment, whereas the index
registers are generally used as offset for data segment.
• SP : Stack Pointer — It is used to hold the offset for the top-of-stack location within
the stack segment.
• BP : Base Pointer — It contains the offset of the base of a data area in the stack
segment.
• SI : Source Index — During string instructions, it contains the offset for the source
operand in the data segment.
• DI : Destination Index — During string instructions, it is used to hold the offset for
the destination operand in the extra segment
9
Pins and Signals
3 Pins and Signals
The 8086 is a 16-bit general-purpose microprocessor capable of addressing 1MB of mem-

ory. The device has 40 pins, requires a +5V power supply and can operate with a 5-10
MHz clock.
3.1 Pin Diagram
The 8086 is designed to operate in two modes — minimum and maximum. Its pinout is
shown below. Pins 24−31 function differently depending on the mode.
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16 /S3
AD12 4 37 A17 /S4
AD11 5 36 A18 /S5
AD10 6 35 A19 /S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD (RQ/GT0 )
AD5 11 µP 30 HLDA (RQ/GT1 )
AD4 12 29 WR (LOCK)
AD3 13 28 M/IO (S2 )
AD2 14 27 DT/R (S1 )
AD1 15 26 DEN (S0 )
AD0 16 25 ALE (QS0 )
NMI 17 24 INTA (QS1 )
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
10
Pins and Signals
3.2 Pin Description
The function of the various pins can be categorized in three groups — common to mini-
mum and maximum mode, only for minimum mode, and only for maximum mode.
3.2.1 Common for both Minimum and Maximum mode
The power supply and frequency signals are as follows.
• VCC (Pin 40): +5 V power supply.
• GND (Pin 1, 20): Ground Reference.
• CLK (Pin 19): It provides the basic timing to the processor for its operation. The
clock is usually provided through 8284 clock generator IC.
The externally initiated signals including interrupts are as follows.
• RESET (Pin 21): It is the system reset input signal. When the 8086 detects the
positive going edge of a pulse on this pin, it stops all activities until the signal goes
LOW. On reset, the 8086 initializes the registers as follows.
Register Content
CS FFFFH
DS 0000H
SS 0000H
ES 0000H
IP 0000H
Flag Register Cleared
Instruction Queue Empty
• NMI (Pin 17): The 8086 will automatically do a type 2 interrupt response when it
receives a low-to-high transition this pin. This interrupt cannot be disable by any
program instruction.
• INTR (Pin 18): This is the maskable interrupt pin of 8086. It is usually used in
conjunction with a Programmable Interrupt Controller (e.g., Intel 8259A) which in
turn is connected to devices that need interrupt services.
11
Pins and Signals
The bus related signals are as follows.
• AD15 −AD0 (Pin 39,2-16): These are time-multiplexed address and data bus. They
act as lower 16-bit address bus (A15 −A0 ) during the first part of the machine cycle
and as data bus (D15 −D0 ) during the later part.
• A19 −A16 /S6 −S3 (Pin 35-38): These are multiplexed address and status pins. Dur-
ing the first T-state, they work as address lines, and together with A15 −A0 , consti-
tute the 20-bit address bus (A19 −A0 ). During the later part of the machine cycle,
they function as status signals.
– S6 : This is used to signify the bus master. A LOW on this pin indicates that
8086 is handling the bus. When 8086 transfers the control of bus (HOLD), this
pin is driven to High Impedance (Z) state.
– S5 : This indicates the status of Interrupt flag (IF).
– S4 , S3 : These are used to identify which of the 8086 segment registers were used
to generate the physical address. These status lines can be used to expand the
memory up to 4 MB.
S4 S3 Segment Register
0 0 Extra segment (ES)
0 1 Stack segment (SS)
1 0 Code segment (CS) / None
1 1 Data segment (DS)
• BHE/S7 (Pin 34): This is used as Bus High Enable (active low) during the first
T-state of a machine cycle. Together with A0 pin, it is used to select memory banks.
During the later part of the cycle, it is used as a status signal, S7 which is kept for
future expansion.
BHE A0 Function
0 0 16-bit data transfer from even address (D15 − D0 )
0 1 8-bit data transfer from odd address (D15 − D8 )
1 0 8-bit data transfer from even address (D7 − D0 )
1 1 Not available.
12
Pins and Signals
The other common mode signal are as follows.
• RD (Pin 32): This is an output control signal which becomes active (LOW) when-
ever the microprocessor is performing a memory or an I/O read operation.
• READY (Pin 22): This is an input signal used to synchronize slow peripherals.
When it is HIGH, it indicates that the peripheral is ready for data transfer. When
it is LOW, the microprocessor will enter a wait state (wait an integral number of
T-states) till it becomes HIGH again to signal the next data transfer operation.
• TEST (Pin 23): This is an input signal and is used by the WAIT instruction.
This can be used to synchronize the operation of the 8086 to an event in external
hardware. Execution of a WAIT instruction causes the 8086 to check the logic level
at the TEST input.
If 0 is found, 8086 interprets it as NOP instruction and moves on to execute the
next instruction.
If 1 is found, the µP suspends operation and goes into the idle state. The 8086
no longer executes any instructions, instead it repeatedly checks the logic level of
the TEST input waiting for its transition back to logic 0. As TEST switches to 0,
execution resumes with the next instruction in the program.
• MN/MX (Pin 33): This is an input signal indicating the mode of operation of
8086. When it is HIGH, the µP operates in minimum mode. When it is LOW, the
µP is configured to work in maximum mode.
3.2.2 Minimum mode signals
In minimum mode, the 8086 is configured to support small, single processor systems using
a few devices that use the system bus. This mode is also referred to as an uniprocessor
system (single 8086). In this mode, the 8086 generates all bus control signals. The various
minimum mode signals are described below.
• HOLD, HLDA (Pin 31,30): These pins have the same purpose as the 8085
HOLD/HLDA pins and are used for DMA. A HIGH on the HOLD pin indicates that
13
Pins and Signals
another device (master) is requesting to take over the system bus. If the 8086 suc-
cessfully transfers the control of the bus, it will acknowledge the same by outputting
HIGH on HLDA pin.
• WR (Pin 29): The 8086 outputs LOW on this pin to indicate that the processor is
performing a write operation.
• M/IO (Pin 28): This is similar to 8085 IO/M signal. It is used to distinguish a
memory access (M/IO = HIGH) from an I/O access (M/IO = LOW).
• DT/R (Pin 27): This is a Data Transmit/Receive signal. It is an output signal

required in minimum systems that uses an 8286/8287 data bus transceiver. It is
used to control direction of data flow through the transceiver.
• DEN (Pin 26): This is the Data Enable (active low) signal. It is provided as an
output enable for the 8286/8287 in a minimum system which uses the transceiver.
• ALE (Pin 25): The Address Latch Enable is an output signal which is used to
demultiplex the AD15 −AD0 bus into A15 −A0 and D15 −D0 . It is similar to the 8085
ALE.
• INTA (Pin 24): The Interrupt Acknowledge signal is used by 8086 to indicate to the
external device that it has accepted its interrupt and is performing the corresponding
ISR.
3.2.3 Maximum mode signals
In maximum mode, the 8086 is configured to support multiprocessor systems. In this case,
the Intel 8288 bus controller is added to the 8086 to provide bus controls and compatibility
with the multibus architecture. Usually the 8086 maximum mode is used to work with
8087 co-processor.
• RQ/GT0,1 (Pin 31,30): These are Request/Grant pins and are used by other local
bus masters to force the processor to release the local bus at the end of the processor’s
current bus cycle. Each pin is directional, with RQ/GT0 having higher priority than
RQ/GT1 .
14
Pins and Signals
• LOCK (Pin 29): The 8086 outputs LOW on the LOCK pin to prevent other bus
masters from gaining control of the system bus. The LOCK signal is activated by
the LOCK prefix instruction and remains active until the completion of the next
instruction.
• S2 , S1 , S0 (Pin 28,27,26): These are status signals and are used by the 8288 bus
controller to generate bus timing and control signals required for a bus cycle. They
are decoded as follows.
S2 S1 S0 Function
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Code access
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Inactive
• QS0 , QS1 (Pin 25,24): These are Queue Status pins. These are provided so that
any external device can know (track) the status of 8086 internal instruction queue.
They are decoded as follows.
QS1 QS0 Function

No operation. During the last clock cycle, nothing was
0 0
taken from the queue.
First byte of opcode from queue. The byte taken from
0 1
the queue was the first byte of the instruction.
Queue Empty. The queue has been reinitialized as a
1 0 result of the execution of a transfer (JMP, CALL, etc)
instruction.
Subsequent byte from queue. The byte taken from the
1 1
queue was the next byte of the instruction.
15
Interrupts
4 Interrupts
An 8086 interrupt can come from any one of three sources. One source is an external signal
applied to the the nonmaskable interrupt (NMI) input pin or to the interrupt (INTR)
input pin. An interrupt caused by a signal applied to one of these inputs is referred to as
a hardware interrupt.
A second source of an interrupt is execution of the Interrupt instruction, INT n. This
is referred to as a software interrupt.
The third source of an interrupt is some error condition produced in the 8086 by the
execution of an instruction.
Interrupt Mechanism: If an interrupt has been requested, the 8086 responds to
the interrupt by stepping through the following series of major actions.
1. It completes the current instruction which is in progress.
2. It decrements the stack pointer by 2 and pushes the flag register on the stack
3. It disable the 8086 INTR interrupt input by clearing the interrupt flag (IF) in the
flag register.
4. It resets the trap flag (TF) in the flag register.
5. It decrements the stack pointer by 2 and pushes the current code segment (CS)
register contents on the stack.
6. It decrements the stack pointer again by 2 and pushes the current instruction pointer
(IP) contents on the stack.
7. It fetches the Interrupt-Service Routine (ISR) address from the Interrupt Vector
Table and jumps to that location.
MAIN LINE INTERRUPT

PROGRAM SERVICE
ROUTINE
PUSH FLAGS PUSH REGISTERS
CLEAR IF
CLEAR TF
PUSH CS
PUSH IP
FETCH ISR ADDRESS
POP IP
POP CS
POP FLAGS
POP REGISTERS
IRET
16
Interrupts
4.1 Interrupt Vector Table
Interrupt Pointer Table or Interrupt Vector Table stores the starting addresses of an
interrupt-service procedure. In an 8086 system, the first 1 KB of memory from 00000H
to 003FFH is set aside as IVT. Since 4 bytes are required to store CS and IP values for
each interrupt-service procedure, the table can hold the starting addresses for up to 256
interrupts procedures.
Each double-word interrupt vector is identified by a number from 0 to 255 which is
referred to as the type number of the interrupt.
The 256 interrupt vectors are arranged in the table in memory as shown below.
0003FF
CS
Type 255
User-Available
IP
003FC
·
· ::::::::: :::: :::
Available Interrupt
· (224)
00083
CS
Type 32
User-Available
IP
00080
0007F
CS
Type 31
Reserved
IP
0007C
·
· ::::::::: :::: :::
Reserved Interrupt
· (27)
00017
CS
Type 5
Reserved
IP
00014
00013
CS
Type 4
IP Overflow
00010
0000F
CS
Type 3
1-Byte INT Instruction
IP
0000C
0000B Dedicated Interrupt
CS
Type 2 (5)
Non-Maskable
IP
00008
00007
CS
Type 1
Single-Step
IP
00004
00003
CS
00002 Type 0
00001 Divide Error
IP
00000
17
Interrupts
4.2 Classification of Interrupts
8086 interrupts can be classified as follows.
A. Based on interrupt sources.
1. External Interrupts: 8086 has two hardware interrupt pins — NMI and INTR.
(a) NMI: Non-maskable interrupt (Type 2) is used to handle emergency situa-

tions such as power failure, memory error, etc.
(b) INTR: It is usually used in conjunction with a Programmable Interrupt

Controller (e.g., Intel 8259A) which in turn is connected to devices that
need interrupt services. The PIC provides the required type number (Type
0 – 255) for each of the interrupting devices.
2. Internal Interrupts: The source of these interrupts are internal to the 8086 µP.
(a) Error Interrupts: 8086 can be interrupted if some error is produced by the
execution of an instruction. These are divide-by-zero (Type 0) error and
overflow (Type 4) error.
(b) Software Interrupts: 8086 has an interrupt instruction, INT n (Type 0 – 255)
which generates an interrupt immediately upon completion of its execution.
Here, n refers to the type number. Since any type number may be specified,
software interrupts are used to test interrupt procedures. For example. INT
2 can be used to test NMI service subroutine, INT 50 can be used to test
if the interrupt service subroutine for Type 50 interrupt is working properly
or not.
B. Based on type number.
1. Dedicated interrupts (Type 0 – 4) : These 5 interrupts have specific purpose as

defined by Intel.
(a) Type 0 : Divide-by-zero error — The 8086 will automatically do a type 0

interrupt if the result of a DIV or an IDIV operation is too large to fit in the
destination register.
18
Interrupts
(b) Type 1 : Single-step — If the trap flag is set, then 8086 will automatically
perform a type 1 interrupt after each and every instruction. This helps in
debugging.
(c) Type 2 : Non-maskable — The 8086 will automatically do a type 2 interrupt

response when it receives a low-to-high transition on its NMI input pin. This
interrupt cannot be disable by any program instructions.
(d) Type 3 : 1-byte INT instruction / Breakpoint — The type 3 interrupt is

produced by the execution of the 1-byte INT instruction, INT 3. The main
use of this interrupt is to implement a breakpoint function in a system.
(e) Type 4 : Overflow error — If the overflow flag is set, then 8086 will perform
a type 4 interrupt after it executes the INTO instruction.
2. Reserved interrupts (Type 5 – 31) : These 27 interrupts are reserved by Intel for
future expansion and are used in more complex microprocessors.
3. User-available interrupts (Type 32 – 255) : These 224 interrupts are available to

user to be used to handle interrupts from external devices.
4.3 Interrupt Priority
The priorities of 8086 interrupts are arranged as follows.
Interrupt Priority
Internal Interrupts (Divide error, INT n, INTO) Highest
−−−−−−−→
NMI (Nonmaskable Interrupt)
Hardware Interrupt (INTR)
Single-step Lowest
19
(Credit - 4)
Unit Nine: 8051 Microcontroller

Introduction
1 Introduction
A microcontroller can be termed as a computer-on-chip in contrast to a microprocessor

which is only a processor-on-chip.
A microcontroller has a CPU (a microprocessor) in addition to a fixed amount of
RAM, ROM, I/O ports, interrupt logic, and timers all on a single chip. In other words,
all the components which make up a microprocessor-based system are embedded together
on one chip.
In 1981, Intel Corporation started the MCS-51 family of microcontrollers with the
introduction of 8051 microcontroller. It has the following features.
• 4KB of on-chip ROM.
• 256 bytes of on-chip RAM, where 128 bytes are user accessible RAM and the other
128 bytes are reserved for Special Function Registers (SFRs).
• 8-bit processor, meaning its ALU, most of the registers, and data bus is of 8 bits.
• 16-bit address bus capable of accessing 64 KB each of external RAM and ROM.
• Four 8-bit I/O ports.
• Five interrupts.
• Two 16-bit counter/timers.
• A serial interface.
• Oscillator and clock circuits operating with crystal frequency ranging from 12 to
40 MHZ giving an effective cycle rate of 1 to 3.33 MHz.
1
Architecture
2 Architecture
The basic internal block diagram of an 8051 microcontroller is shown below.
External Interrupts
r------, Internal
IOI
I
I
SFR I
I
IOI
I I Interrupts I 128 bytes I
I I I I
I 1•-------
Interrupt On-chip
I I I
I Control ROM I User-accessible I
I I I Timer 1
I I 128 bytes I Counter
L ______ J
I I Inputs
I I Timer 0
4KB I On-chip RAM I
,------,
I
I
I
I 8-bit
I
I
CPU
I
I
I
L_-J_-_-J_-_~
I I
I Oscillator I Bus Serial
I I 4 8-bit I/O Ports
I Circuit I Control Interface
I I
b b
TT P0 P2 P1
used to interface
64 KB external RAM and/or ROM
P3 TXD RXD
2
Pins and Signals
3 Pins and Signals
3.1 Pin Diagram
The 8051 microcontroller is packaged in a 40-pin DIP, requires a 5V power supply and
operates with 12-40 MHz crystal frequency. Its pinout is shown below.
P1.0 1 40 VCC
P1.1 2 39 P0.0 (AD0 )
P1.2 3 38 P0.1 (AD1 )
P1.3 4 37 P0.2 (AD2 )
P1.4 5 36 P0.3 (AD3 )
P1.5 6 35 P0.4 (AD4 )
P1.6 7 34 P0.5 (AD5 )
P1.7 8 33 P0.6 (AD6 )
RST 9 32 P0.7 (AD7 )
(RXD) P3.0 10 8051 31 EA/VPP
(TXD) P3.1 11 µC 30 ALE/PROG
(INT0) P3.2 12 29 PSEN
(INT1) P3.3 13 28 P2.0 (A15 )
(T0) P3.4 14 27 P2.1 (A14 )
(T1) P3.5 15 26 P2.2 (A13 )
(RD) P3.6 16 25 P2.3 (A12 )
(WR) P3.7 17 24 P2.4 (A11 )
XTAL2 18 23 P2.5 (A10 )
XTAL1 19 22 P2.6 (A9 )
GND 20 21 P2.7 (A8 )
3
Pins and Signals
3.2 Pin Description
The function of various pins are described below. It should be noted that, not all the
features of 8051 can be used at the same time.
Power supply and clock signals
• VCC (Pin 40): +5 V power supply.
• GND (Pin 20): Ground Reference.
• XTAL1, XTAL2 (Pin 18,19): The 8051 has an on-chip oscillator but requires an
external clock to run it. Most often a quartz crystal oscillator is connected to these
pins.
Ports 0,2 pins
When external memory is connected to the 8051 microcontroller, Port 0 acts as the mul-
tiplexed lower-order address and data bus, while Port 2 acts as the higher-order address
bus.
• AD7 −AD0 (Pin 32-39): During the first part of a machine cycle, these pins function
as the lower-order address bus (A7 −A0 ); and during the later part, these work as
the data bus (D7 −D0 ).
• A15 −A8 (Pin 21-28): These are the higher order address bus pins used in conjunc-
tion with demultiplexed A7 −A0 pins to get the 16-bit external memory address.
If external memory is not used, Port 0 pins must be connected to 10KΩ pull-up resistor
to function as simple I/O port. Port 2 does not need pull-up resistors and in the absence
of external memory, work as simple I/O port.
4
Pins and Signals
Port 3 pins
Besides working as simple I/O port, these pins also provide some additional functions
which are described below.
• RXD, TXD (Pin 10,11): These pins are used to receive and transmit data serially
with the help of on-chip UART controller.
• INT0, INT1 (Pin 12,13): These pins are used for external hardware interrupts.
• T0, T1 (Pin 14,15): When the timers in the microcontroller are configured as
counters, these pins are used to provide external clock pulses.
• RD, WR (Pin 16,17): These pins are used during data transfer (read or write)
operations from external memory.
Other pins
• Port 1 (Pin 1-8): These are the dedicated 8-bit port pins of 8051. They do not
serve any alternate function.
• RST (Pin 9): This is the reset pin. This is often referred to as a power-on-reset
and is implemented as shown below.
VCC
cb
C = 10µF
Reset
button bc
8051
µC
9 RST
R = 8.2kΩ
5
Pins and Signals
On reset, the values of 8051 registers are as follows. The ports are configured as
input ports and the register bank selected is RB0.
Register Reset value

Program Counter 0000H
Data Pointer 0000H
Accumulator 00H
Program Status Word 00H
Stack Pointer 07H
B-register 00H
Ports P0–P3 FFH
• EA/VPP (Pin 31): It stands for “external access". If this pin is low, then 8051
will access instructions (opcodes) from externally connected memory only. If this
pin is held high, 8051 executes programs from memory locations 0000H to 0FFFH of
internal ROM and from memory locations 1000H to FFFFH of external ROM/RAM.
• PSEN (Pin 29): This is an output pin and stands for “program store enable". This
pin is used when EA = 0 signifying that the instructions are stored in external
memory. It is connected to output enable pin of external ROM.
• ALE/PROG (Pin 30): When Port 0 is used in its alternate mode (as the mul-
tiplexed data bus and lower-order address bus), Address Latch Enable is used to
demultiplex them.
This pin is also used for programming input pulse for EPROM versions of 8051.
6
Memory Organisation
4 Memory Organisation
8051 implements a separate memory space for programs (code) and data. These code and
data memory is internal and limited; however both can be expanded to a maximum of
64KB.
The internal memory of 8051 consists of a 4KB on-chip ROM which is used as program
memory, and a 256 bytes on-chip RAM which is used as data memory. The on-chip RAM
contains a rich arrangement of general-purpose storage, bit-addressable storage, register
banks, and special function registers.
Both program and data memory can be expanded to a maximum of 64KB as shown
below.
FFFFH FFFFH
External RAM
External ROM
D
1000H FFH
EA = 0 SFR
128 bytes
□
0FFFH
Internal ROM 80H
D
EA = 1 7FH
Internal RAM
128 bytes
4KB 64KB 64KB
0000H i....______,J 00H 0000H
V,----_____JI IL-----~ I
PROGRAM MEMORY DATA MEMORY
4.1 Program Memory
If EA pin is connected to GND, it indicates that the program is stored in the externally
connected ROM. All the opcodes are fetched from the memory locations 0000H to FFFFH
of the external ROM.
If EA pin is connected to VCC , 8051 accesses instructions from the 4KB internal ROM
first; then, when it reaches the end of the on-chip ROM it switches to the external ROM
for the rest of the instructions. In other words, 8051 fetches opcodes starting from 0000H ,
then goes on to address 0FFFH (the last location of on-chip ROM); after that the opcodes
are fetched from the address 1000H to FFFFH of the external ROM.
Here, PSEN pin is connected to the OE (output enable) pin of the external ROM.
7
Memory Organisation
4.2 Data Memory
To access data from external 64KB RAM, specific instructions are used, the most common
being MOVX. Here RD and WR pins are connected to the OE (output enable) pin and WE
(write enable) pin of external RAM respectively.
The internal data memory organisation is as follows.
I. General purpose RAM: These are user-accessible general purpose storage area addressed
from 00 to 7FH . These 128 bytes are divided into three different groups as follows:
1. Working Registers: A total of 32 bytes from locations 00H to 1FH are set aside
for registers. These are organised as four banks of eight registers each. The four
register banks are numbered 0 to 3 and are made up of eight registers named R0
to R7. Each register can be addressed by name (when its bank is selected) or by
its RAM address. Register bank selection is done by programming the RS1 and
RS0 bits of Program Status Word.
RS1 RS0 Bank selected Address

0 0 RB0, default 00H –07H
0 1 RB1 08H –0FH
1 0 RB2 10H –17H
1 1 RB3 18H –1FH
2. Bit-Addressable Registers: A total of 16 byes from locations 20H to 2FH are set
aside for Bit-Addressable Registers, forming a total of 128 (16 locations, each of
8 bits) addressable bits. An addressable bit may be specified by its bit address
(00H − 7FH ) or 8 bits may form any byte address from 20H to 2FH . Depending
on the instructions, the microcontroller will address a bit or one of the working
registers.
3. General Purpose: A total of 80 bytes from locations 30H to 7FH are used for
general read and write storage, or what is normally called a scratch pad. As Stack
Pointer is of 8 bit, Stack is implemented using this general purpose area of internal
memory.
8
Memory Organisation
·
·
l
1F R7 I ----
Register
7F
·
·
·
· Bank 3
·
18 R0 ·
------- ·
17 R7 ·
·
· ·
· Register Scratch-Pad
· Bank 2 · Memory
·
10 R0 ·
-------
0F R7 2F 7F 78 ·
·
·
·
· Stack
· 2E 77 70 ·
·
·
·
· Register ·
· Bank 1 · ·
· ·
08 R0 ·
------- ·:: ::~ ·
07 R7 · ·
· ·
· ·
· · ·
T I____ _
Register
· Bank 0 21 0F 08 ·
·
·
·
·
00 R0 20 07 00 30
·
·
·
Working Registers Bit-Addressable Registers General Purpose
II. Special function Registers: Out of the 128 bytes reserved, 8051 uses only 21 special
function registers. These SFRs can be accessed by their names or by their addresses.
Some of the SFRs also support bit addressing. All these registers have specific pre-
defined functions. These registers are like the control words of various chips; and by
initializing them accordingly, 8051 can be operated in various modes. The list of 8051
SFRs is shown below.
Name Function Address

A* Accumulator E0H
B* Multiply and divide operation F0H
DPTR (DPH, DPL) Data pointer for external access 83H , 82H
IE* Interrupt enable control A8H
IP* Interrupt priority control B8H
P0–P3* I/O Ports 80H , 90H , A0H , B0H
PCON Power control 87H
PSW* Program status word D0H
SCON* Serial control 98H
SBUF Serial data buffer 99H
SP Stack pointer 81H
TMOD Timer/counter mode selection 89H
TCON* Timer/counter control 88H
TH0, TL0 Timer 0 data 8CH , 8AH
TH1, TL1 Timer 1 data 8DH , 8BH
*These SFRs support bit-addressing.
9
Memory Organisation
Data pointer
The data pointer (DPTR) is used to access external code or data memory. It is a 16-bit
register which holds the address of the externally connected memory from where data
is to be accessed. 8051 supports instruction where DPTR can be initialized either as a
16-bit register or as 2 8-bit registers—DPH and DPL.
Program Status Word
The 8-bit format of PSW register in 8051 microcontroller is shown below.
D7 D6 D5 D4 D3 D2 D1 D0
I CY I AC I F0 I RS1 I RS0 I OV I – I P I
Bit Symbol Bit Address Description

PSW.7 CY D7H Carry Flag
PSW.6 AC D6H Auxiliary carry Flag
PSW.5 F0 D5H General purpose, user defined flag
PSW.4 RS1 D4H Register bank select 1
PSW.3 RS0 D3H Register bank select 0
00 = Register bank 0, default
01 = Register bank 1
PSW.2 OV D2H Overflow flag
PSW.1 − − Reserved
PSW.0 P D0H Even Parity flag
10
Addressing Modes
5 Addressing Modes
Addressing modes are an integral part of each computer’s instruction set. They allow
specifying the source or destination data in different ways depending on the programming
situation. The various 8051 addressing modes are discussed below.
5.1 Register Addressing
Register addressing mode involves the use of registers to hold the data to be manipulated.
The 8051 programmer has access to 8 “working registers” numbered R0 through R7 for
each of the 4 register banks. Other registers used are A, B, and DPTR.
Examples include
ADD A, R7
MOV A, R3
INC DPTR
DIV AB
Note: Data transfer between Rn registers is not allowed, i.e., MOV R1, R2 is an invalid
instruction.
5.2 Direct Addressing
In direct addressing, the address of the operand is specified in the instruction. All 128
bytes of internal RAM (00H to 7FH ) as well as the SFRs (80H to FFH ) may be addressed
directly using the 1-byte address assigned to them. For SFRs, the address may be given
by its name also. For example, to transfer data from Port 0 to accumulator, we can either
use Port 0’s address (80H ) or its name (P0).
MOV A, 80h
MOV A, P0
Some more examples
MOV R0, 12h
MOV 8Ch, R7
MOV 01h, PSW
11
Addressing Modes
5.3 Indirect Addressing
The indirect addressing mode uses registers R0, R1, and DPTR to point to the actual
address from where data is to accessed. The mnemonic symbol used for indirect addressing
is the “at” sign (@). For example, if R0 = 32h, then whatever data is present in the
location 32h will be copied to the accumulator after the execution of MOV A,@R0. Other
examples include
MOV @R1, A
MOVX A, @DPTR
5.4 Immediate Addressing
When a source operand is a constant, then the constant can be incorporated into the
instruction as a byte of “immediate” data. In assembly language immediate operands are
preceded by the “number” sign (#). For example, to load accumulator with a count value
of 0Ah, we can use MOV A,#0Ah
All instructions using immediate addressing use an 8-bit data constant for the imme-
diate data. However, when initializing the data pointer, a 16-bit constant is required. For
example, MOV DPTR,#8000h.
5.5 Relative Addressing
Relative addressing is used only with certain 2-byte jump instructions. The first byte
specifies the opcode, and the second byte specifies the relative address or the offset. This
offset has to be added to the program counter to get the address from where the next
instruction is to be executed.
The offset is specified as an 8-bit signed number; hence the range for jumping is −128
to +127, i.e, both forward and backward jumps are possible.
For example, if the label THERE represents an instruction at location 8040H and the
instruction SJMP THERE is in memory location 8000H and 8001H , the assembler will
assign a relative offset of 3EH as byte 2 of the instruction (8002+3E = 8040H ).
12
Addressing Modes
5.6 Absolute and Long Addressing
Absolute addressing is used only with ACALL and AJMP instructions. These are 2-byte
branching instructions which allow branching within the current 2K page of code memory.
Out of the 16 bits of the destination address, only the lower 11 bits are specified within
the 2-byte instruction. The higher 5 bits (A15 − A11 ) are fixed by the current page used.
Long addressing is used only with LCALL and LJMP instructions. These are 3-byte
branching instructions where the 1st byte specifies the opcode, and the 2nd and 3rd bytes
specify the destination address.
Absolute addressing offers the advantage of short (2-byte) instruction, but has the
disadvantage of limiting the range for the destination. In long addressing, the full 64K
code space may be used, but the disadvantage is that the instruction are three bytes long.
5.7 Indexed Addressing
Indexed addressing uses a base register (either the program counter or the data pointer)
and an offset (the accumulator) in forming the effective address for a JMP or MOVC in-
struction. Examples are as follows.
MOVC A, @A+DPTR
MOVC A, @A+PC
JMP @A+DPTR
5.8 Bit Addressing
The 8051 supports bit addressing through 210 bit-addressable locations, of which 128
(16×8) are at addresses 20H to 2FH , and the rest are in the special function registers.
Using bit addressing, individual bits can be set, cleared, ANDed, ORed, etc., with a single
instruction.
The 128 general purpose bit-addressable locations (available in the memory space from
20H through 2FH ) are accessed using special single-bit instructions which support direct
addressing only. These 128 bits have addresses 00H to 7FH .
The remaining bit-addressable locations are in the special function registers. Out of
the 21 SFRs, 11 are bit-addressable. Some (6) of the bits of these 11 SFRs are left unused,
13
Addressing Modes
giving a total of 82 (11 × 8 − 6 = 82) bit-addressable locations. These bits have addresses
80H to F7H . They can be accessed by using single-bit instructions with either direct
addressing or dot notation.
Few examples are illustrated below.
SETB 67h
CLR 87h
CPL P0.3
CLR D7
CPL PSW.1
14
Interrupts
6 Interrupts
8051 microcontroller provides five interrupts. These are organised as follows.
1. External Interrupts: Two interrupts are set aside for external hardware interrupts.
Pin 12 (P3.2) and Pin 13 (P3.3) are the 8051’s external interrupts —INT0 and INT1
respectively. These external interrupts are also referred to as EX0 and EX1. These
interrupts can be programmed to be level- or edge-triggered. In level triggering,
if the pins are kept at low level for 4 machine cycles, microcontroller gets inter-
rupted. In edge-triggering, when a high-to-low edge transition occurs at the pins,
the corresponding flag (IE0 or IE1) is set and the microcontroller gets interrupted.
2. Internal Interrupts.
(a) Timer interrupts: Two interrupts are set aside for the timers: one for Timer 0
and one for Timer 1. Whenever the timer rolls over, the corresponding timer
flag (TF0 or TF1) is set, and the microcontroller gets interrupted.
(b) Serial interrupt: One interrupt is set aside for serial communication. When
microcontroller has received serial data or is ready to transmit serial data, the
corresponding flag (SI or TI) is set, and the microcontroller gets interrupted.
Only one interrupt is required to handle both transmit and receive operations.
All these interrupts can be enabled or disabled (masking) through proper instructions.
Also, these interrupts can be triggered through software by setting the appropriate flags.
Apart from these, 8051 also gets interrupted on reset (high on RST pin).
The vector address of the interrupt service routine for the interrupts are given below.
Interrupt Vector address

RESET 0000H
External interrupt 0 (INT0) 0003H
Timer 0 interrupt (TF0) 000BH
External interrupt 1 (INT1) 0013H
Timer 1 interrupt (TF1) 001BH
Serial COM interrupt (R1, T1) 0023H
15
Interrupts
6.1 Masking of interrupts
Upon reset, all interrupts are disabled (masked), meaning that none will be responded to
by the microcontroller if they are triggered. The interrupts must be enabled by software
in order for the microcontroller to respond to them. There is a special function register
called IE (interrupt enable) that is responsible for enabling (unmasking) and disabling
(masking) the interrupts.
The format of IE register and bit description is given below.
D7 D6 D5 D4 D3 D2 D1 D0
EA – ET2 ES ET1 EX1 ET0 EX0
Bit Description
Bit Symbol 1 = Enable
Address 0 = Masked/Disable
IE.7 EA AFH Global enable/disable
IE.6 − − Reserved
IE.5 ET2 AEH Enable Timer 2 overflow or capture interrupt (8052 only)
IE.4 ES BCH Enable serial port interrupt
IE.3 ET1 BBH Enable Timer 1 overflow interrupt
IE.2 EX1 BAH Enable External interrupt 1
IE.1 ET0 B9H Enable Timer 0 overflow interrupt
IE.0 EX0 B8H Enable External interrupt 0
6.2 Interrupt priority
In the event of two or more simultaneous interrupts or an interrupt occurring while another
one is being serviced, the schedule of interrupts is determined either by the fixed sequence
(i.e., polling) or by programming (i.e., using IP register).
The interrupt priority or the polling sequence in 8051 microcontroller is as follows.
Interrupts Priority
External Interrupt 0 (INT0) Highest
Timer Interrupt 0 (TF0) 


External Interrupt 1 (INT1) 
y
Timer Interrupt 1 (TF1)
Serial Communication (RI,TI) Lowest
16
Interrupts
Each interrupt source is individually programmed to one of two priority levels through
the bit-addressable special function register called Interrupt Priority (IP). Its format and
bit description is given below.
D7 D6 D5 D4 D3 D2 D1 D0
I – I – I PT2 I PS I PT1 PX1 PT0 PX0
Bit Description
Bit Symbol 1 = high priority,
Address 0 = low priority
IP.7 − − Reserved
IP.6 − − Reserved
IP.5 PT2 BDH Priority for Timer 2 interrupt (8052)
IP.4 PS BCH Priority for serial port interrupt
IP.3 PT1 BBH Priority for Timer 1 interrupt
IP.2 PX1 BAH Priority for External interrupt 1
IP.1 PT0 B9H Priority for Timer 0 interrupt
IP.0 PX0 B8H Priority for External interrupt 0
It should be noted that when two or more interrupts are set to high priority, they are
serviced according to the polling sequence.
17

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EC-3003 :: MICROPROCESSORS AND MICROCONTROLLERS

Unit One: Introduction

School of Electronics Engineering

1.1 Gate Types and Truth Tables

Logic Logic Truth Boolean

Buffer A-l>-Y ffffi Y=A

Figure 1: Basic Logic gates

1.5 Priority Encoder

1.6 Latches and Flip-Flops

2.1 Tristate logic

Figure 2: Representation of a bus

When building a digital system, the number of interconnections between different

Figure 3: Interconnection of 4 8-bit components

Figure 4: Data transfer using a bus structure

3.1 Basic Microprocessor

• multipurpose − addition, subtraction, comparison, etc.,

• programmable − depending on user’s preference, it can be instructed to perform

• clock-driven − synchronous circuit,

• register-based − to store the data temporarily for processing

Figure 5: Block diagram of a basic microprocessor

All the processing of a microprocessor can be boiled down to either arithmetic or

3.2 Basic Microprocessor based System

It includes three components: microprocessor, I/O device and memory (read/write

3.3 Basic working of a microprocessor

3.4 Applications of Microprocessor and its versatility

Applications of microprocessor are discussed in the next section.

Versatility of microprocessor comes from its programmability feature. Microprocessors

The evolution of microprocessor can be traced along three branches:

Unit Two: 8085 Architecture and

School of Electronics Engineering

8085 Microprocessor Architecture

AccurnulaLor Temp. Reg. lnsLrudion

(8) B (8) C (8)

• Both data and instructions are stored in R/W memory.

• The contents of memory (data and instructions) are accessed by location.

• Instructions are accessed and executed sequentially.

The various units of the 8085 microprocessor are discussed next.

2.1 General Purpose Registers

In 8085 microprocessor, we have six 8-bit general purpose registers identified as B, C, D,

2.3 Flag Register

Figure 2: Flag Register

2.4 Program Counter

2.5 Stack Pointer

The Incrementer/Decrementer block increments the program counter when instruc-

2.7 Temporary Registers

The temporary registers are not accessible to the programmer.

2.9 Register Select

The Register Select behaves as the select lines of MUX/DEMUX unit

2.11 Instruction Register

2.12 Instruction Decoder and Machine Cycle Encoding

The detailed schematic of the 8085 ALU can be found at:

4 Timing and Control Unit

5.1 Interrupt Control

5.2 Serial I/O Control

The 8085 is an 8-bit general-purpose microprocessor capable of addressing 64K of memory.

6.1 Pin Diagram

The 8085 microprocessor’s pinout is shown below.

Power Supply and Clock Signals

RESET OUT CLK (OUT)

Multiplexed Address/Data Bus

Control and Status Signals

Machine Cycle IO/M S1 S0 Control Signals

Interrupt Acknowledge 1 1 1 INTA = 0