FAST LOCKING DIGITAL PHASE LOCKED LOOP DESIGN

DISSERTATION

Submitted in partial fulfillment of the requirements of the

MS Microelectronics Degree programme

By

Bharat B Roonwal
2008HB99501

Under the supervision of

Mr. Shivaraj G Dharne, Engineering Manager,

Intel Technology India Pvt. Ltd.

Dissertation work carried out at

Professional Development Centre, Bangalore

BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE

Pilani (Rajasthan) INDIA
 January, 2011
MEL PDC ZG629T DISSERTATION

FAST LOCKING DIGITAL PHASE LOCKED LOOP DESIGN

DISSERTATION

Submitted in partial fulfillment of the requirements of the

MS Microelectronics Degree programme

By

Bharat B Roonwal
2008HB99501

Under the supervision of

Mr. Shivaraj G Dharne, Engineering Manager,

Intel Technology India Pvt. Ltd.

Dissertation work carried out at

Professional Development Centre, Bangalore

BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE

Pilani (Rajasthan) INDIA
Project Guide BITS Co-ordinator

Mr. Shivaraj G Dharne Prof.D.V.Pooraniah

Engineering Manager,

Intel India
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BHARAT ROONWAL
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BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE

Pilani (Rajasthan) INDIA

CERTIFICATE

This is to certify that the Dissertation entitled “FAST LOCKING DIGITAL

PHASE LOCKED LOOP DESIGN” submitted by Mr. BHARAT ROONWAL,
ID.No. 2008HB99501 in partial fulfillment of the requirements of MEL PDC
ZG629T Dissertation embodies the work done by him under my supervision.

Signature of the Supervisor

Place: Bangalore Name: Shivaraj G Dharne

Date: 07.01.2011 Designation: Engineering Manager

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TABLE OF CONTENT

ACKNOWLEDGMENTS......................................................................................................... 7
ABSTRACT..........................................................................................................................9
CHAPTER 1 :INTRODUCTION.................................................................................................10
1.1 Problem Definition .....................................................................................................10
1.2 Significance of PLL.....................................................................................................10
1.3 Phase Locked Loop Fundamentals.............................................................................11
1.3.1 Loop Filter.............................................................................................................12
1.3.2 Frequency Synthesizer.........................................................................................12
1.4 Applications of PLL ................................................................................................... 13
1.5 Classification of PLLs .................................................................................................14
1.6 Goal ...........................................................................................................................14
1.7 Thesis Organization....................................................................................................15
CHAPTER 2 :A BRIEF REVIEW OF PREVIOUS WORK...............................................................16
1.8 Background................................................................................................................. 16
1.9 Phase Detector ........................................................................................................... 18
1.10 Voltage-Controlled Oscillator.....................................................................................19
1.11 Loop Filter ................................................................................................................19
1.12 Configuration of PLL Application ...............................................................................22
1.13 Analog , Digital, and Hybrid PLL’S.............................................................................23
1.14 Popular PLL Integrated Circuits (IC’s)........................................................................24
CHAPTER 3 :PROPOSED APPROACH AND IMPLEMENTATION................................25
1.15 Architecture of proposed PLL....................................................................................25
1.16 Phase Frequency Detector........................................................................................25
1.16.1 Conventional Phase Detector.............................................................................26
1.16.2 Phase Detector Incorporated in Proposed PLL....................................................28
1.16.3 Simulation Output and Results of Incorporated Phase Frequency Detector........30
1.17 Charge Pump and Loop Filter....................................................................................32
1.17.1 Conventional Charge Pump ..............................................................................34
1.17.2 Charge pump incorporated in the proposed PLL.................................................36
1.18 Loop Filter Design..................................................................................................... 39
1.18.1 Linear model of PLL............................................................................................39
1.19 Voltage Controlled Oscillator (VCO)..........................................................................41
1.19.1 The most important specifications of the VCO....................................................42
1.19.2 Ring oscillator architecture.................................................................................42
1.19.3 High speed ring oscillator with dual delay paths................................................46
1.20 Frequency Divider....................................................................................................48
1.20.1 Digital dividers....................................................................................................49
CHAPTER 4 : SIMULATION RESULTS......................................................................................53
CHAPTER 5 :CONCLUSION AND FUTURE SCOPE....................................................................56
REFERENCES.................................................................................................................... 58
GLOSSARY OF TERMS USED.............................................................................................60
................................................................................................................................... 61
...............................................................................................61
CHECKLIST....................................................................................................................... 61
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LIST OF FIGURES

Figure 1-1: Basic pll block diagram.......................................................................................11

Figure 1-2 Basic frequency Synthesizer................................................................................13
Figure 2-3 Conventional PLL Block Diagram.........................................................................17
Figure 2-4: Phase detector characteristic.............................................................................18
Figure 2-5 : linear model of the phase locked loop...............................................................21
Figure 2-6:Figure (a) Passive filter (b) Active Filter............................................................22
Figure 2-7: Ranges of the dynamic limit of a PLL..................................................................22
Figure 2-8:Synthesizer PLL...................................................................................................23
Figure 3-9: Block diagram of the proposed PLL....................................................................25
Figure 3-10 :Conventional phase detector using NAND gates..............................................27
Figure 3-11: Phase detector using TSPC type D flip flop.......................................................28
Figure 3-12:Phase Frequency Detector.................................................................................29
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Figure 3-13 : when Vref is leading Fout................................................................................31

Figure 3-14: when Vref is lagging Fout.................................................................................31
Figure 3-15:when Vref is exactly in phase with Fout............................................................32
Figure 3-16: when Vref is exactly in phase with Fout...........................................................34
Figure 3-17:Conventional Charge pump...............................................................................34
Figure 3-18:Proposed charge pump circuit...........................................................................36
Figure 3-19: Bias generator used in the charge pump..........................................................37
Figure 3-20:The output of control voltage when up signal got activated..............................38
Figure 3-21:The output of control voltage when dn signal got activated..............................39
Figure 3-22: Linear model of PLL..........................................................................................39
Figure 3-23: Loop filter of PLL...............................................................................................40
Figure 3-24:Basic structure of the ring oscillator..................................................................43
Figure 3-25: problem of insufficient gain..............................................................................43
Figure 3-26: delay stage cell schematic in VCO....................................................................44
Figure 3-27: Load used in proposed ring oscillator showing inductive impedance...............45
Figure 3-28 : simulation results of three types of VCO’s.......................................................46
Figure 3-29:ring oscillator structure with dual delay paths...................................................47
Figure 3-30: output waveforms of the VCO for different control voltage and linearity range.
.............................................................................................................................................48
Figure 3-31: output waveforms of the VCO for different control voltage..............................49
Figure 3-32: Divide by 2 frequency divider output...............................................................50
Figure 3-33: D Flip flop.........................................................................................................50
Figure 3-34: Proposed 6 bit frequency divider......................................................................52
Figure 3-35:Output waveforms of the frequency divider......................................................53
Figure 4-36: Full loop simulation of the PLL..........................................................................54

ACKNOWLEDGMENTS

Apart from the efforts of me, the success of this project depends largely on the encouragement
and guidelines of many others. I take this opportunity to express my gratitude to the people who
have been instrumental in the successful completion of this project.

I would like to gratefully and sincerely thanks Prof. Pooraniah for his guidance, understanding,
patience, and most importantly, for his friendly behaviour during my studies at BITs PDC. I feel
motivated and encouraged every time I attend his classes. He encouraged me to not only grow as
a professionally but also as an instructor and an independent thinker. I would like to thank again
Prof. Pooraniah for giving me opportunity to act as a Class Co-ordinator, which helped me in
improving my leadership and mangement skills. I like to thank for everything you’ve done for
me. Same time I thanks all the faculties who taught me during my MS course at BITs PDC.

Throughout the course of implementing this work, I had the opportunity to interact with the best
of minds in the field of analog circuit design. Foremost, I would like to express my deepest
gratitude to my thesis advisor, Mr. Shivaraj G Dharne, for his vision, motivation and guidance.
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The guidance and support received from all my friends Pranjal, Chaitanya, Pavan, Rajkiran,
Akhilesh Pathak, Hari K, Nagendra , I am grateful for their constant support and help.

I am deeply indebted to my parents, Gopal K Roonwal and Sheela Roonwal, for teaching me
the value in accumulating the wealth of knowledge, and to my Brothers& Sister, for their constant
encouragement.

BHARAT B ROONWAL

MS (BITs PDC)
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BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

SECOND SEMESTER 2010-2011

MEL PDC ZG629T DISSERTATION

Dissertation Title: Fast Locking Digital Phase Locked Loop

Name of Supervisor: Mr. Shivaraj G Dharne
Name of Student: Bharat B Roonwal
ID No. of Student: 2008HB99501

ABSTRACT

In this thesis, we present the design of Fast Locking Digital Phase Locked Loop (DPLL), which
has low-power consumption and fast locking considerations. The previously proposed circuits for
various units of PLL are modified for better performance and characteristics. Here we first
systematically analyzed the working of basic PLL and its inner blocks from aspects of theoretical
analysis and circuit operation. Based on the circuit architecture, both classifications and
comparisons are made. Then we propose a high speed phase frequency detector. The proposed
phase frequency detector is simple in its structure and has no glitch output as well as better phase
characteristics. The speed of the proposed phase frequency detector is up to 16 GHz. Charge
pump current is aimed at 150 μA and the output-frequency range of the oscillator is from 2 GHz
to 7 GHz for 100mv to 500mv control voltage range. The simulated PLL will use 100 MHz
reference frequency. The lock time of proposed PLL is less than 50ns and average power
consumption is 7mw.

Key Words: Phase locked loop, CMOS process, PDF, Charge pump,loop filter, process
technology, VCO ,Frequency divider etc.
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CHAPTER 1 : INTRODUCTION

1.1 Problem Definition

For many years; generally until the 60’s, early radios did not have automatic frequency
synchronization or Automatic Fine Tune (AFC). Without AFC consumers radios had a frequency
stability of 0.1% . With that era’s high gain amplifiers(G=250),the control circuit would yields a
frequency stability of about 0.0004% .In color television the color subcarrier at 3.158 Mhz
required precise phase control to maintain color picture stability in NTSC format[1] .

Similarly in today’s fast growing fields like radio, telecommunication and computers where we
need to recovers signals from noisy communication channel ,recovers the carrier from satellite
transmission signals[2], performs frequency and phase modulation and demodulation and
synthesize exact frequencies for receiver tuning .There are many other fields where frequency
and phase synchronization and frequency synthesis is required .

So we need a control system or electronic circuit which can automatically synchronizing the
signals in phase and frequency and also generate various frequencies signals .One of the
electronic circuit which can be used for above application is PLL.

1.2 Significance of PLL

The number of telecommunications innovations grew rapidly during the last half of the 20th
century [1]. Currently, there is widespread and growing use of cellular phones, cordless phones,
digital satellite systems, and personal mobile radio networks.

Over the past decade, there has been a tremendous growth in the popularity of wireless
networking technologies [2]. Schools and universities are providing wireless access to students
and faculty members. Malls are providing customers with wireless connectivity to allow them to
search products, virtually navigate shops, and interact with services. Tourist sites are providing
wireless devices to aid tourists in navigating, exploring and learning about attractions. Moreover,
the emergence of new computing paradigms such as pervasiveness, ubiquity, and mobility has
necessitated the rapid deployment of wireless networks as an infrastructure underneath such
technologies.

One of the technologies that can lay the foundation for the next generation ,fourth generation
(4G), of mobile broadband networks is popularly known as “WiMAX.” WiMAX, Worldwide
Interoperability for Microwave Access, is designed to deliver wireless broadband bitrates, with
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Quality of Service (QoS) guarantees for different traffic classes, robust security, and mobility. A
significant part in WiMax system is the phase-locked loop.

Phase Locked Loop has become one of the most versatile building blocks in electronics [5]. They
are at the heart of circuits and systems ranging from clock recovery blocks in data
communications to the local oscillators that power the ubiquitous cellular phones. The property of
making its output frequency an exact multiple of the reference frequency makes the Phase
Locked Loop (PLL) the circuit of choice for frequency synthesizers. PLL is also used for aligning
various clocks in synchronous systems and for a myriad of applications ranging from tracking
satellite Doppler shift to sensing minute reactance changes in industrial proximity sensors.

1.3 Phase Locked Loop Fundamentals

A Phase Locked Loop or a PLL is a feedback control circuit. As the name suggests, the phase
locked loop operates by trying to lock to the phase of a very accurate input signal through the use
of its negative feedback path. A basic form of a PLL consists of three fundamental functional
blocks namely [3]

• A Phase Detector (PD)

• A Loop Filter (LF)
• A voltage controlled oscillator (VCO)

with the circuit configuration shown in Figure 1.1

Figure 1-1: Basic pll block diagram

The phase detector compares the phase of the output signal to the phase of the reference signal. If
there is a phase difference between the two signals, it generates an output voltage, which is
proportional to the phase error of the two signals. This output voltage passes through the loop
filter and then as an input to the voltage controlled oscillator (VCO) controls the output
frequency. Due to this self correcting technique, the output signal will be in phase with the
reference signal. When both signals are synchronized the PLL is said to be in lock condition. The
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phase error between the two signals is zero or almost zero at this. As long as the initial difference
between the input signal and the VCO is not too big, the PLL eventually locks onto the input
signal. This period of frequency acquisition, is referred as pull-in time, this can be very long or
very short, depending on the bandwidth of the PLL. The bandwidth of a PLL depends on the
characteristics of the phase detector (PD), voltage controlled oscillator and on the loop filter[3].

1.3.1 Loop Filter

The filtering operation of the error voltage (coming out from the Phase Detector) is performed by
the loop filter. The output of PD consists of a dc component superimposed with an ac component.
The ac part is undesired as an input to the VCO, hence a low pass filter is used to filter out the ac
component. Loop filter is one of the most important functional blocks in determining the
performance of the loop. A loop filter introduces poles to the PLL transfer function, which in turn
is a parameter in determining the bandwidth of the PLL. Since higher order loop filters offer
better noise cancelation, a loop filter of order 2 or more are used in most of the critical application
PLL circuits.

1.3.2 Frequency Synthesizer

One of the most common uses of a PLL is in Frequency synthesizers of Wireless systems[2]. A
frequency synthesizer generates a range of output frequencies from a single stable reference
frequency of a crystal oscillator [9]. Many applications in communication require a range of
frequencies or a multiplication of a periodic signal. For example, in most of the FM radios, a
phase-locked loop frequency synthesizer technique is used to generate 101 different frequencies.
Also most of the wireless transceiver designs employ a frequency synthesizer to generate highly
accurate frequencies, varying in precise steps, such as from 600 MHz to 800 MHz in steps of 200
KHz. Frequency Synthesizers are also widely used in signal generators and in instrumentation
systems, such as spectrum analyzers and modulation analyzers. Besides a PLL, it also includes a
very stable crystal oscillator with a divide by N-programmable divider in the feedback loop. The
programmable divider divides the output of the VCO by N and locks to the reference frequency
generated by a crystal oscillator.
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Figure 1-2 Basic frequency Synthesizer

The output frequency of VCO is a function of the control voltage generated by the PD. The
Output of the phase comparator, which is proportional to the phase difference between the signals
applied at its two inputs, control the frequency of the VCO. So the phase comparator input from
the VCO through the programmable divider remains in phase with the reference input of crystal
oscillator. The VCO frequency is thus maintained. This relation can be expressed as

fr =f0/N (1.1)

This implies that the output frequency is equal to

f0=Nfr (1.2)

Using this technique one can produce a number of frequencies separated by and a multiple of N.
For example if the input frequency is 24KHz and the N is selected to be 32 ( a single integer )
then the output frequency will be 0.768 MHz In the same way, if N is a range of numbers, the
output frequencies will be in the proportional range. This basic technique can be used to develop
a frequency synthesizer from a single reference frequency. This is the most basic form of a
frequency synthesizer using phase locked loop technique.

1.4 Applications of PLL

Phase-locked loops are widely used for synchronization purposes; in space communications for
coherent demodulation and threshold extension, bit synchronization, and symbol synchronization.
Phase-locked loops can also be used to demodulate frequency-modulated signals. In radio
transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference
frequency, with the same stability as the reference frequency[2].

Other applications include:

• Demodulation of both FM and AM signals

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• Recovery of small signals that otherwise would be lost in noise (lock-in amplifier)
• Recovery of clock timing information from a data stream such as from a disk drive
• Clock multipliers in microprocessors that allow internal processor elements to run faster
than external connections, while maintaining precise timing relationships
• DTMF decoders, modems, and other tone decoders, for remote control and
telecommunications.
1.5 Classification of PLLs

1.5.1 Linear PLL: The first PLL ICs appeared around 1965 and were also purely
analog devices. An analog multiplier was used as the phase detector, the loop
filter was built from a passive or active RC filter, and the well-known voltage-
controlled oscillator (VCO) was used to generate the output signal of the PLL.
This type of PLL is known as the linear PLL (LPLL) today.

1.5.2 Digital PLL: In the years that followed, the PLL drifted slowly but steadily
into digital territory. The very first digital PLL(DPLL), which appeared around
1970, was in effect a hybrid device: only the phase detector was built from a
digital circuit(for instance, from an EXOR gate or a JK flip-flop), but the
remaining blocks were still analog. That is why it is a semi analog circuit.

1.5.3 All digital PLL: A few years later, the ―all digital PLL (ADPLL) was
invented. The ADPLL is exclusively built from digital function blocks; hence it
doesn‘t contain any passive components like resistors and capacitors.

1.5.4 Software PLL: PLLs can also be implemented ―by software. In this case;
the function of the PLL is no longer performed by a piece of hardware, rather by
a computer program. This type of PLL is referred to as SPLL.

1.6 Goal
My goal is to design PLL circuit which can be used for frequency synchronization and frequency
synthesis with fast locking, less power consumption and with below specification .

 Reference frequency is 100MHz

 Charge pump current is 150µA
 Loop filter is of second order
 VCO gain is 18GHz/v
 Linearity range of VCO is 400mV(100mV-500mV)
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 Frequency divider is 6 bit

 Lock time of PLL is less than 50ns

 Power consumption of PLL in locked state is 7mW

 PLL output is 2 to 7 Ghz GHz .Error is 10MHz (0.15%)

1.7 Thesis Organization

The thesis is organized as follows. Chapter 2 cover the literature survey of Phase Locked Loops,
In this chapter we present basic fundamental of PLL.In Chapter 3 the proposed arechitecture and
various units of PLL are compare, the proposed one in the circuit with the conventional ones.
Chapter 4 includes the simulation results for all the units of PLL and top level PLL .Chapter 5
talks about the conclusion of the thesis and scope of future work in this area.
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CHAPTER 2 : A BRIEF REVIEW OF PREVIOUS WORK

The purpose of this chapter is to present a systematic survey of the theoretical/experimental work
accomplished in the area of digital phase locked loop (DPLL’s) during the period of 1960 to
2010.The DPLL represent the heart of the blocks required in the implementation of coherent (all
digital) communications and tracking receivers[6].

This survey is particularly motivated by the fact that microprocessor technology is advancing
rapidly to the extent that sophisticated and flexible signal processing algorithms for
communications and control can be realized in the digital domain. In fact, it is anticipated that the
use of this signal processing technology will continue to expand rapidly in the development of
advanced communications tracking receives, e.g, aIl digital modems. Consequently, one major
purpose of this chapter is to provide the reader with a survey and an overview of the theoretical
and experimental work accomplished to date, thereby offering speedy access to the techniques
and hardware developments which have been presented in a scattered literature[3]. In addition,
the I feel that a tutorial article revealing the various theories, their relationship to one another,
their shortcomings, their advantages and the assumptions on which each is based, would be of
tremendous value to the engineer trying to decide what particular analysis procedure is applicable
to his peculiar problem.

1.8 Background
Continued progress in increasing performance, speed, reliability, and the simultaneous reduction
in size and cost of integrated circuits (LSI and VLSI) has resulted in strong interest in the
implementation of the phase locked loop (PLL) in the digital domain. A survey on analog
PLL’s in 1975[4] included over 40 publications in this direction. Aside from the obvious
advantages associated with digital systems, a digital version of the PLL (DPLL) alleviates some
of the problems associated with its analog counterpart; namely, sensitivity to dc drifts and
component saturations, difficulties encountered in building higher order loops, and the need for
initial calibration and periodic adjustments. In addition, with the ability to perform elaborate real-
time processing on the signal samples, the DPLL‘s can be made more flexible and versatile.

In contrast to the matured status of the study of the analog PLL (APLL) the development of the
all DPLL has just started to take shape over the last ten years. Like most aspects.
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Figure 2-3 Conventional PLL Block Diagram

of engineering, the work on DPLL’s is motivated by the steady availability of components that
offer advantages over the conventional ones. The classical APLL consists of three major
functional units: 1) a phase detector (PD), 2) a loop filter and 3) a voltage-controlled oscillator
(VCO)[1]. A block diagram of the APLL is shown in Fig. 2-1 .The incoming signal whose phase
is to be tracked is mixed with a locally generated sine wave to produce a voltage proportional to
their instantaneous phase difference. This error voltage is filtered and used to control the
instantaneous frequency of the VCO. All three components are realized with analog circuitry,
e.g., the PD is a balanced mixer, the loop filter is a simple RC low-pass circuit, and the VCO is
tuned by adjusting the bias voltage on a varicap in the tuned circuit controlling the resonant
frequency of the VCO. The earliest efforts on DPLL’s concentrated on partially replacing the
APLL components with digital ones. Apparently, Westlake was the fit to document the work in
this direction in 1960. He introduced a sample and hold circuit at the output of the loop filter in
order to take advantage of the improvements offered by a digital VCO. In 1962, Byrne analyzed
the performance of a PLL when the phase detector was implemented with a flipflop and hence
exhibited a sawtooth PD characteristic. As another example along the same line in 1968 analyzed
the effect of replacing the loop fiiter with a digital one. Towards the end of the 1963, researchers
in the field turned their attention to the implementation and design of digital PLL‘s. Perhaps the
first “all digital loop” was reported by Drogin [3] in 1967. The second-order loop built and tested
was used as a VHF omnidirectional range fiider. It was designed to track a relatively slow 30-Hz
sine wave. All digital components were clocked synchronously by a common 1.097 MHz
reference. Since then, the DPLL field has been somewhat active; the most noticeable years being
1968- 1972. Different authors explored various avenues and aspects of implementing the DPLL
concept. We have found it convenient to categorize the different implementations into four
classes based on the mechanization of the phase detector.

They are: 1) Flip-Flop IFF) -DPLL in which the phase error is derived from the duration between
the set and reset time of a flip-flop triggered by positive zero crossings of the input signal and the
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local clock; 2) Nyquist Rate (NR)-DPLL in which the input signal is sampled at the Nyquist rate;
3) Zero Crossing (2C)-DPLL in which the loop tries to sample at the zero crossings of the
incoming signal; and 4) LeadlLag (LL)- DPLL in which the PD determines at each cycle whether
the input leads or lags the locally generated clock. Notice that in I), 3), and 4) the phase of the
incoming signal is measured against the reconstructed signal. However, in the case of 2),

the phase of the signal is measured against a reference. For this reason, 2) is often referred to as a
uniform sampling scheme whereas l), 3) and 4) are nonuniform sampling schemes.

1.9 Phase Detector

There are two types of PD’s, namely, the sinusoidal PD’s and the square signal PD’s. A
sinusoidal PD inherently has phase detection interval (-pai/2, +pai/2). It operates as a multiplier,
which is a zero memory device[7]. The square signal PD’s, also called sequential PD’s, are
implemented by sequential logic circuits. Sequential PD’s contain memory of past events, which
can generate PD characteristics that are difficult or impossible to obtain with multiplier circuits.
They are usually built up from digital circuits and operate with binary rectangular input
waveforms. Accordingly, they are often called digital phase detectors. The characteristics of the
square signal PD’s are of the linear type over the phase detection interval (-pai/2, +pai/2) for
triangular PD, (-pai,+n) for sawtooth PD, and (-2pai,+2pai) for sequential phase/frequency
detector (PFD) [6] .The different PD’s all have the same factor K d . Increasing PD phase
detection interval provides a larger tracking range, larger lock limit, than those obtainable from a
sinusoidal PD.

Figure 2-4: Phase detector characteristic

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1.10 Voltage-Controlled Oscillator

The voltage-controlled oscillators (VCO’s) used in the PLL basically are not different from those
employed for other applications, such as modulation and automatic frequency control. The main
requirements for the VCO are 1) phase stability, 2) large frequency deviation, 3) high modulation
sensitivity K, 4) linearity of frequency versus control voltage, and 5) capability for accepting
wide-band modulation[17]. The phase stability requirement is in direct opposition to all other
four requirements. Four types of VCO commonly used are given in the order of decreasing
stability, namely, voltage controlled crystal oscillators (VCXO’s), resonator oscillators, RC
multivibrators, and YIG-tuned oscillators. The phase stability can be enhanced by a number of
ways: 1) using high Q crystal and circuit, 2) maintaining low noise in the amplifier portion, 3)
stabilizing temperature, and 4) keeping mechanical stability. Most of the phase jitter of an
oscillator arises from noise in the associated amplifier. If a wider frequency range is required, an
LC oscillator must be used. In this application, the standard Hartley, Colpitts, and Clapp circuits
make their appearance. The tuning is accomplished by means of a varactor, junction capacitance
of a diode. At microwave frequencies, YIG-tuned Gunn oscillators have become popular. Tuning
of the YIG-tuned oscillator is accomplished by altering a magnetic field.

1.11 Loop Filter

The LF in PLL is a low-pass filter. It is used to suppress the noise and high-frequency signal
components from the I’D and provide a dc-controlled signal for the VCO. We assume that the
loop is in lock, that the PD is linear, and the ILF output voltage is proportional to phase error. The
phase error voltage we is filtered by the loop filter. The servo scheme of the PLL in linear locking
state is shown in Fig. 3, where F( s) is the loop transfer function. According to servo terminology,
the type of the loop is determined by the number of perfect integrators within the loop. Any PLL
is at least a type-one loop because of the perfect integrator inherent in the VCO. If the loop filter
contains one perfect integrator, then the loop is type two. A second-order PLL with a high-gain
active filter can be approximated as a type-two loop, whereas a PLL with a passive filter is type
one. The widely used passive and active filters for the PLL are discuss. The closed-loop transfer
function of the PLL for the passive filter is given by

For the active filter

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For convenience in description, both above can be rewritten into the forms

in which w, is the natural frequency of the loop and eta is the damping ratio. The relevant
parameters for passive filter are
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Figure 2-5 : linear model of the phase locked loop

And

The two transfer functions are nearly the same if 1/K,Kd << PLL has the form

A large value of KO is usually required for achieving a good performance of the loop . Define the
hold-in range of a loop as AWH = KO. If the input frequency is sufficiently close to the VCO
frequency, a PLL locks up with just a phase transient; there is no cycle slipping prior to lock. The
frequency range over which the loop acquires phase to lock without slips is called the lock-in
range of the PLL. In a first-order loop, the lock-in range is equal to the hold-in range, but for the
secondor higher order loops, the lock-in range is always less than the hold-in range. Besides,
there is a frequency interval, smaller than the hold-in interval and larger than the lock-in interval,
over which the loop will acquire lock after slipping cycles for a while. This interval is called the
pull-in range. Their relations are indicated in Fig. 2-3. To ensure stable tracking, it is common
practice to build loop filters with equal numbers of poles and zeros. At high frequencies the loop
is indistinguishable from a first-order loop with gain K = KdK,F(oo). As a fair approximation, we
can say that the higher order loop has the same lock-in range as the equivalent-gain first-order
loop. The lock-in limit of a first-order loop is equal to the loop gain. We argue here that a higher
order loop has nearly the same lock limit. The lock-in range AWL can be approximately
estimated as
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Acquisition of frequency in PLL is more difficult and slower, and requires more design attention
than phase acquisition. The self-acquisition of frequency is known as frequency pull-in, or simply
pull-in, and the self-acquisition of phase is known as phase lock-in, or lock-in.

Figure 2-6:Figure (a) Passive filter (b) Active Filter

Figure 2-7: Ranges of the dynamic limit of a PLL

1.12 Configuration of PLL Application

Integrated phase-locked loops developed since the 1970's are versatile systems, which are suitable
for use in a variety of frequency-selective demodulation, signal conditioning, or frequency-
synthesis applications. PLL techniques in communication are well developed and widely used for
FM, AM, video, signal processing, telecommunication systems, etc. PLL's are widely applied in
versatile systems as reference signal sources or oscillators. Besides, PLL is frequently realized as
a signal modulator or synthesizer due to its inherent configuration. Fig. 6 is a phase modulator
formed by the phase-locked loop. The modulating signal m(t) combining with the phase error
from the PD modulates the PLL to achieve a phase modulation and indirect frequency
modulation. A typical phase-locked indirect synthesizer is shown in Fig 2-4 and 2-5, in which N
is the division factor. The output frequency is synthesized by N.fref .
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The use of PLL with analog PLL IC (NE565 developed by Signe tics) for a synchronous motor
and for a dc motor began in the 1970's[2] . A PLS system is a frequency feedback control
configuration that continuously maintains the motor speed or the motor position by tracking the
phase and frequency of the incoming reference signal that corresponds to the input command,
such as speed or position.

Figure 2-8:Synthesizer PLL

1.13 Analog , Digital, and Hybrid PLL’S

Due to rapid progress in analog and digital IC’s in the 1970’s, the integrated PLL has been
developed for filtering, frequency synthesis, motor-speed control, frequency modulation,
demodulation, signal detection, and a variety of other applications. The configuration of PLL’s
can be either analog or digital, but most of them are hybrids composed of both analog and digital
components. The first analog PLL IC’s, NE565 and CD4046, were developed by Signetics and
RCA in the 1970’s. They are integrated on a chip including a sinusoidal PD, an LF, and a VCO.
The phase detector is a multiplier, whose phase-lock range is from - pai/2to +pai/2. In order to
extend-the lock-in range of PLL, the Motorola digital PFD MC4044 capable of phase-detection
range from -2pai to + 2pai was proposed in 1972 . A hybrid PLL realized by combining discrete
analog and digital components was then achieved. Hereafter, the versatile PLL’s components for
improving the locking performance are developed in succession. Nowadays, it is a future-
exploited trend to integrate the PD, prescaler, programmable counter, and VCO on a chip IC to
form a PLL module device. The difficulty for realizing chip PLL is how to constitute a high-
frequency VCO on a single chip IC, which operates at a frequency above 2.5 GHz [20]. The type
of PLL used in the realization system is determined according to the application.
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1.14 Popular PLL Integrated Circuits (IC’s)

A wide variety of IC’s for PLL are available from semiconductor manufacturers. The techniques
widely used to implement the PLL are transistor-transistor logic (TTL), complementary metal-
oxide-semiconductor (CMOS), and emitter coupled logic (ECL). Nowadays, fully integrated PLL
on a single chip can operate at frequencies up to 35 MHz, such as Exar XR-215 PLL. Other
higher frequency PLL’s are easily achieved by combining sub-PLL IC’s (including only PD,
prescaler, and programmable counter) and discrete higher frequency VCO’s. It is an important
trend to realize fully integrated higher frequency PLL formed by constituting a high-frequency
VCO into a modulus device in the near future. Nowadays, Motorola and Plessey are developing
versatile PLL IC’s operating at frequencies above 2.5 GHz. The Motorola MC 12210 is a 2.5-
GHz bipolar monolithic series-input phase locked loop synthesizer with phase-swallow function.
It is designed for the high-frequency local oscillator of an RF transceiver in handheld
communication applications. This PLL IC can operate at a minimum supply voltage of 2.7 V for
input frequencies up to 2.5 GHz with a typical current drain of 9.5 mA. A dual modulus prescaler
is integrated to provide either a 32/33 or 64/65 divide ratio [21]. Besides, new Motorola
VCO’s MC12147 and MC12149 with operating frequency up to 1.1 GHz were introduced in
1995 [23]. The GEC Plessey SP5070 and SP5655 are, respectively, 2.4-GHz and a 2.7- GHz
single modulus frequency synthesizers for use in satellite TV receivers, high IF cable tuning
systems, and C-band with frequency doubling mixer. Both two PLL synthesizers operate at a low
power consumption (5 V and 30 mA). The SP5655 capable of standard 12C BUS[2] control
format contains two addressable current-limited outputs and four addressable bidirectional open
collector ports, one of which is a three bit ADC. The information on these ports can be read via
the 12C BUS. The device has one fixed 12C BUS address and three programmable addresses,
programmed by applying a specific input voltage to one of the current-limited outputs. This
enables two or more synthesizers to be used in a system.
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CHAPTER 3 : PROPOSED APPROACH AND

IMPLEMENTATION
1.15 Architecture of proposed PLL

The basic building blocks of the proposed PLL are phase frequency detector, charge pump, loop
filter, voltage controlled oscillator and frequency divider[8] as shown in fig 3-1.

Figure 3-9: Block diagram of the proposed PLL

1.16 Phase Frequency Detector

The phase detector is the foremost unit of a phase locked loop. Its purpose is to detect phase
difference between the two signals applied at the input. A tri-state phase detector, mentioned in
chapter 2, has an advantage of better linearity range from -2 to +2 and is the most widely
used phase detector in phase locked loop. Due to this we incorporate a tri-state phase detector in
our phase locked loop. The most important design considerations for a tri-state phase detector are:

• Dead Zone
• Power Consumption
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• Maximum frequency of operation

Dead zone, resulting in undetectable phase difference between the inputs, can be minimized by
designing the circuit such that, there exists a finite reset pulse width, when the two input signals
are exactly in phase. The reset pulse width should be wide enough to just turn on the charge
pump. Also, it should not be too wide, as in that case it would limit the maximum frequency of
operation and cause more ripples on the control voltage line (due to inherent current mismatch).
The power consumption can be kept minimum by using minimum number of transistors and
using lower supply voltage.

1.16.1 Conventional Phase Detector

Figure 3.2 shows one of the conventional phase detectors, which is implemented using static
CMOS technology. As seen, this PD consists of D type flip flop made up of NAND gates [10].
This PD has severe limitations. It consists of large number of NAND gates, which corresponds to
an excessively large number of transistors and thereby requiring a large chip area. Also, large
number of transistors results in large power consumption.
In order to overcome its limitation a pre-charge type (PT) phase detector was proposed by
Kondoh et al [5]. It worked on dynamic CMOS technology, utilizing the voltage generated at
various nodes. However, the error detecting range of this phase detector was limited to - to + .
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Figure 3-10 :Conventional phase detector using NAND gates

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Figure 3-11: Phase detector using TSPC type D flip flop

This limitation is removed by phase detector proposed by Lee et al [11]. It again works on
dynamic CMOS technology and uses a TSPC-type D flip flop structure. It has good performance
characteristic in terms of dead zone and provides a linearity range of -2 to +2 , but requires an
additional reset circuitry consisting of a pseudo-NMOS NOR gate. The pseudo-NMOS NOR gate
makes the operation fast, but consumes static power when the NOR gate output is low and also
the logic becomes ratioed.

1.16.2 Phase Detector Incorporated in Proposed PLL

The phase detector incorporated in the proposed PLL is shown in figure 3-4. It works on dynamic
CMOS technology and is similar to the previously mentioned PD. It removes the reset circuitry
which was required by the PD of figure 3-3, without sacrificing on its performance.
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Working:
Initially both Fref and Fout are low therefore the transistors m1 and m7 are on (P-MOS). Due to
this node A and node B gets charged to Vdd and hence switching off transistors m4 and m10.
This also results in switching on of N-MOS transistors m6 and m12.

Figure 3-12:Phase Frequency Detector

Consider the case when Fref lead Fout in phase. When rising edge of Fref (leading in phase)
arrives, it causes N-MOS transistor m5 to turn on and hence creating a low resistance path from
node C to ground (m6 already on). Thus, node C discharges to ground potential and thereby
causing UP to go high instantaneously. This high UP signal switches on m3 and m8. The circuit
will remain in this state, even if Fref goes low. This is because node C is prevented from being
pulled up as m4 is off (due to charges at node A).
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Now, when rising edge Fout (lagging in phase) arrives DN signal goes high by similar
mechanism as explained before. When this DN signal becomes sufficiently high, transistors m2
and m9 are turned on causing a low resistance path for node A and node B. Therefore, node A
and node B discharges to ground potential, which results in P-MOS transistors m4 and m10
turning on. Due to this node C and node D are pulled up and causing UP and DN signal to go
low. Exactly the reverse happens when Fout leads Fref. When both Fref and Fout are in phase,
reset pulses are obtained at UP and DN signals.

Thus, the above PD circuit utilizes the UP and DN signal directly for the reset operation, and
hence eliminating the need for extra reset circuitry. The reset pulse generated is of sufficient
width such that dead zone is almost completely eliminated.
The PD consists of minimum number (16) of transistors. Proper relative sizing of various
transistors is required in order have rail to rail swings. The combined strength of m2, m3 (m8,
m9) should be more than m1 (m7). This is because, there exists a contention if Fout arrives when
Fref is already low (in case of Fref leading Fout). Node A (B) must have a stronger pull down
path than pull up, in order to get discharged. Similarly strengths of m4 and m10 should be weak
in order to prevent UP and DN signal to go low until node A and node B are completely
discharged to ground potential. The strengths of m5 (m11) and m6 (m12) should be high in order
to generate instant response from the rising edge of Fref (Fout).

1.16.3 Simulation Output and Results of Incorporated Phase Frequency Detector

Figure 3.5 shows the simulation output for the case when Fref is leading Fout. The rising edge of
Fref sets the UP signal, this UP signal is then reset by the rising edge of Fout. A short duration
reset pulse is seen on DN signal when the reset operation takes place.
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Figure 3-13 : when Vref is leading Fout

2. Figure 3-6 shows the simulation output for the case when Fout is leading Fref. The rising edge
of Fout sets the DN signal, this DN signal is then reset by the rising edge of Fref. A short duration
reset pulse is seen on UP signal when the reset operation takes place.

Figure 3-14: when Vref is lagging Fout

3. Fig. (3.7) shows the simulation output for the case when Fref and Fout is exactly in phase. As
seen, only short duration reset pulse are obtained at UP and DN signal. These pulses are essential
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in order to eliminate dead zone. Also, the reset pulses are shown on a magnified scale.

Figure 3-15:when Vref is exactly in phase with Fout

1.17 Charge Pump and Loop Filter

The charge pump is the second unit of PLL. It is responsible for generating necessary control
voltage to the VCO unit. It utilizes the UP and DN signal provided by the phase detector, in order
to pump in or pump out the charge from the loop filter capacitor[13]. When PLL is in locked
state, the control voltage is constant with some inherent ripples.
The important design considerations for an effective charge pump circuit are
• There should be minimum peak current mismatch
• The charge sharing phenomenon should be avoided
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• The effect caused by channel charge injection and clock feed through should be minimized
• Output voltage range provided should be large

Minimum peak current mismatch ensures minimum static phase error between the two input
signals (Fref and Fout) in locked state. The reason for this is as follows. In locked state the phase
detector generates equal UP & DN pulses and the control voltage (Vctrl) is supposed to be
constant. This means that quantity of charge Qcharge and the one of discharge Qdischarge must
be equal and given by eqn.(3.1)
Qcharge=IUP* TUP = Qdischarge = IDN * TDN
(3.1)
where TUP and TDN are duration of UP and DN pulses in locked state, or charging and
discharging time in one cycle. If IUP and IDN are different, then there has to be some difference
between the duration of UP and DN pulse in order to satisfy eqn. (3.1) . The PLL, thus creates a
static phase difference between its inputs in order to maintain the difference between the duration
of UP and DN pulse in accordance with eqn. (3.1).
The charge sharing, charge injection and clock feed through phenomenon results in periodic
ripples and sudden jumps on the control voltage line. This results in generation of spurious tones
and jitters at the output. This becomes critical when PLL is used as a frequency multiplier in a
local oscillator of a transceiver [14]. These non ideal effects can be reduced by suitable circuit
level manipulations. The output voltage range provided by charge pump should be as large as
possible. This helps to keep the VCO gain to a lower value (for a given operating frequency
range), which further helps to decrease the sensitivity of VCO to sudden variations on control
voltage line.
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1.17.1 Conventional Charge Pump

Figure 3-16: when Vref is exactly in phase with Fout

Figure 3-8 shows the conceptual circuit of the charge pump. It consists of two switched current
sources. The current sources are switched by UP/DN pulses from the phase detector. When there
is an UP pulse the charge pump pumps in charge to the loop filter capacitor[15]. Similarly, when
there is a DN pulse the charge pump pumps out the charge from the loop filter capacitor. This
results in a staircase waveform during the transient period. When the PLL is locked, the output
voltage remains constant.

Figure 3-17:Conventional Charge pump

The conventional charge pump is based on the conceptual circuit of figure 3-1 and is shown in
figure 3-9. The transistors m6 and m7 acts as switch and transistors m4 and m5 act as a constant
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current source. The desired value of current is mirrored from Iref via current mirror configuration
formed by m1, m2, m5 and m3, m4.
However, the circuit of figure 3-2 shows many non ideal effects like charge sharing, clock feed
through and channel charge injection. These phenomenons tend to produce ripples on control
voltage line, which is transformed in phase noise and spurious tones in VCO output. The charge
sharing is due to balancing of charge between node X, node Y and output voltage Vctrl, when the
equal duration UP/DN pulse arrives (during locked state of PLL). Channel charge injection
occurs due to flow of part of the channel charge from the channel to the output load capacitor
(loop filter capacitor), at the drain terminal. This happens when the MOS switch, in on condition
operating in triode region, is suddenly turned off. The magnitude of voltage error is given by
∆V= =
(3.2)
Where k is the fraction of channel charge moving to drain, Qch is the channel charge, Cox is the
oxide capacitance, Vgs is the gate to source voltage, Vt is the threshold voltage and C is the
output capacitance (loop filter capacitance)
Clock feed through results due to non ideal behavior of MOS switches, which presents a parasitic
gate to drain capacitance. These errors cause sudden jumps on the control voltage line. The
magnitude of the error caused by clock feed through is given by

∆V= (3.3)

Where Vdd and Vss are the high and low values of UP/DN signal, Cpar is the parasitic gate to
drain capacitance. In order to minimize the error due to clock feed through, the circuit should be
designed carefully enough such that the parasitic capacitance Cpar is made to be a small fraction
of the loop filter capacitance C.
There are some circuit level techniques to suppress the effects due to above mentioned non-
idealities. For example in order to suppress the effects due to charge sharing an OP AMP is
connected in unity gain configuration and to suppress the effect due to channel charge injection
and clock feed through ‘dummy switches’ are connected, which creates opposite effect to the one
created by UP/DN signal, hence minimize sudden jumps. Chang and Kuo’s model provides one
of the best solutions for charge pump design. The circuit eliminates all the non ideal effects
completely by isolating the output node from the switching transistors and thus making the output
is free from sudden jumps. As the technology node decreases this circuit shows significant
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mismatch in pump up and pumps down currents. This is due to Channel Length Modulation
(CLM) effects which becomes prominent at short channel lengths. The current mismatch further
results in static phase error between the inputs when PLL is in locked state.

1.17.2 Charge pump incorporated in the proposed PLL

In order to remove the channel length modulation effects, we have to use the bias generator to
generate the bias voltages and then these bias voltages are used to produce the constant current
sources. The circuit is as follows.

Figure 3-18:Proposed charge pump circuit

Here m1, m2 constitutes the current source and m5, m6 also constitutes the other current source.
The bias voltages for these constant current sources come from the bias generator shown in the
figure 3-10.
The internal circuit of the bias generator is shown in figure 3-11 and the working and design is
also explained. At first for the drain of transistor m9 we have to give minimum voltage and
calculate the width and length of the transistor for getting required current 150 µA. Similarly do
the same procedure for m14 also.
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Figure 3-19: Bias generator used in the charge pump

when the simulation is started the m9 and m14 will produce 150 µA current and the gate voltage
of m14 is given to m5, m6 and m10. Gate voltage of m9 is given to m3, m4 and m13. The widths
of the transistors m5, m6, m7, m8, m10 and m11 should be 6 times that of the transistor m14. The
width of the transistors m1, m2, m3, m4, m12 and m13 should be 6 times of the width of the
transistor m9. The resistor value should be selected in such a way that the output current must be
150µA when simulated.
Bias voltages biasp and biaspc will come from the gate voltage of m12 and m13 respectively.
And the bias voltages biasn and biasnc will come from the gate voltages of m7 and m14
respectively. By using these bias voltages we can make constant current sources.
The simulated output of the pump in current with respect to the output voltage is shown. From
this plot we can observe that current is not varying with the output voltage that means the channel
length modulation effect is neglected[15].
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The working of the charge pump circuit is explained with the help of the figure 3.3. Transistors
m1 and m2 with bias voltages biasp and biaspc will constitute a current source so when the up
signal goes high then the transistor m3 will get switched on so the charge will be pumped through
m3 into the loop filter capacitor.

Figure 3-20:The output of control voltage when up signal got activated.

Similarly m5 and m6 with bias voltages biasn and biasnc will constitute a current source so when
dn signal goes high then transistor m4 will get switched on then the charge will be pump out of
the capacitor.
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Figure 3-21:The output of control voltage when dn signal got activated.

1.18 Loop Filter Design

1.18.1 Linear model of PLL

Figure 3-22: Linear model of PLL

The linear mathematical model of a PLL is shown in figure 3-14. Even though PLL is a highly
non linear system, it can be approximated to a linear system using continuous time
approximation, wherein the sampling nature of the PFD is ignored .
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In the figure 3-14 KPD is the gain of PFD+CP combination. F(s) is the transfer function of the
loop filter. KVCO/s is the transfer function of VCO.
When PLL is in locked state, the phase transfer function is given by:

H(s) = = (3.3)

If a single capacitor (C) is used as a loop filter (like PLL) the transfer function becomes.

H(s) = = (3.4)

As seen from eqn. 3-15 the transfer function of the closed loop system has two poles on
imaginary axis and hence unstable. It would result in un-damped oscillations at the output and the
output will never settle.
A zero added to the above system ( by adding a resistor (R1) in series to loop filter capacitor
(C1)) makes the system stable, but cause sudden jumps on the voltage control line, which can
further result in potential overload of VCO.
Therefore, to avoid it (sudden jumps), another capacitor (C2) is added in parallel to the series
combination of resistor and loop filter capacitor, as shown in figure 3.10.

Figure 3-23: Loop filter of PLL

Thus, a PLL requires a minimum of second order loop filter to ensure its stability.
The loop filter is important to the performance of the PLL because
1) Removes high frequency noise of the detector
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2) Influences the capture and tracking ranges

3) Influences the switching speed of the loop in lock.
4) Easy way to change the dynamics of the PLL
We will consider the filters that give us more flexibility in controlling the characteristics of the
PLL. Filters are of two types: passive filters and active filters.
The advantages of the passive filters are they are linear, relatively low noise and unlimited
frequency range. We have some disadvantages also in using the passive filters. If the filter
components are larger in value(c>200pF and R>100kohm) then they are hard to integrate.
Another disadvantage is it is difficult to get a pole at the origin (increase the order of the type of
PLL). In order to remove the drawbacks of passive filters we will go for the active filters. Active
filters can reduce the sizes of the passive elements but the disadvantages are they will produce
more noise, consume more power and it has some frequency limitations.
The loop filter component values are R1 is 500 ohms, capacitor c1 is 100pF and c2 is 10pF.
Generally the ratio of c1/c2 should be 10.

1.19 Voltage Controlled Oscillator (VCO)

Voltage controlled oscillators are one of the important blocks of data communication systems and
have wide applications, from data modulating in transmitters to demodulation and clock recovery
in receivers[18]. A CMOS VCO can be built using ring structures, relaxation circuits, or an LC
resonant circuit. Ring inverter based oscillators have some advantages among the other oscillators
that have made them a good choice for designers.

Compared to other alternatives, especially the LC resonator-based oscillators, the ring oscillator
are having the following advantages.
• The ring oscillator is compact, as it doesn’t need on chip inductors [19]
• Its tuning range can span orders of magnitude as the ring oscillator is tuned by
voltage.
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Meanwhile, it is desirable to scale down the current consumption of the VCO proportional to
frequency variations which can be reached using ring oscillators. However, ring oscillators suffer
from low Q factor and consequently larger phase noise. Ring oscillators with differential delay
stages exhibit greater immunity to supply disturbance and substrate induced noise than single
delay stage ones.

1.19.1 The most important specifications of the VCO

Electrical tuning range: The tunable frequency range of the VCO must be able to cover the
entire required frequency range of the interested application.

Tuning linearity: An ideal VCO has a constant VCO gain, Kvco at the entire frequency range.
A constant VCO gain can simplifies the design procedure of a PLL.
Supply voltage sensitivity: Since there are many digital circuits in a modern transceiver
circuit, the switching activities of the digital circuits will influence the supply voltage, Vdd, of the
whole system [20]. Besides, the switching noise will also couple to Vdd of the VCO and
influence its output waveform. Therefore the dependency of the VCO oscillation frequency on
the supply voltage must be as low as possible.
Power consumption: The VCO at high frequency has large dynamic power consumption and at
low frequency, has large short-circuit power consumption. The main power consumption of the
PLL comes from the VCO, so reducing the power of the VCO is very important.
According to above analyses, when we design the circuit of the VCO, we should pay attention to
the main problems of the tuning range, noise, power consumption and linearity.

1.19.2 Ring oscillator architecture

The ring oscillators consist of delay cells connected in cascade as shown in figure 3-16. These are
connected in a closed loop for providing enough gain and phase shift to satisfy the Bark hausen´s
oscillation criteria [21].
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Figure 3-24:Basic structure of the ring oscillator

In these topologies the oscillation frequency is given as

Where N is the number of delay cells in the ring and is the delay time in the cell. shows that the
increase of the oscillators speed can be realized by two ways: through the reduction of the delay
time in the cell or by decreasing the number of cells in the ring.

Figure 3-25: problem of insufficient gain

The reduction of the number of cells is very attractive not only for the operation speed increment
but for the power consumption reduction and the saving in area for its implementation. However,
as N diminishes it is more difficult to satisfy the Barkhausen´s oscillation criteria: the steady
oscillation in a ring oscillator requires a total phase shift of 360º around the loop at a frequency
where the small signal gain is above 0 dB.

In N cells ring oscillator, each cell contributes with a frequency dependent phase shift of 180°/N
and the dc phase shift provides the 180° remaining. For small N the problem of insufficient gain
(or insufficient phase shift) arises. Insufficient gain means that at the frequency where the
frequency-dependent absolute phase shift reaches 180º, the loop gain is less than 0 dB, in other
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words, the crossover points of the phase (-180º) and the unity loop gain are different and the
oscillation criteria cannot be met simultaneously, as is shown in figure 3-18.

In this project, a new differential ring oscillator with new composite load is proposed, resulting in
relatively higher frequencies and wider tuning ranges. Figure 3-18 shows the schematic of delay
stage.

Figure 3-26: delay stage cell schematic in VCO

In this delay stage, the nmos transistors m1 and m2 create the input pair for primary loop, while
the pmos transistors m7 and m8 form the input pair for secondary loop. The proposed differential
ring oscillator uses composite load (m8 & m9- m7 & m10) and feed-forward technique to reduce
the delay of each cell. The transistors m3 and m4 are utilized to control the frequency of
operation by varying their gate voltage. Applying control voltage to pmos transistors helps
avoiding tail current control mode and increasing output voltage swing and reducing 1/f noise.
Furthermore, single control voltage relaxes the implementation of charge pumps and loop filters
in the PLLs. The size of m3 and m4 determines the tuning range. The single control voltage also
eases the implementation of the charge pump and loop filter within the PLL.
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The nmos transistors m9 and m10 are used as a load besides m8 and m7 to create a composite
load, showing inductive impedance at the drain of m7 and m8. This new load helps the cell to
oscillate at higher frequency and reaches wider tuning ranges. As shown in Figure 3-19,
considering the gate source capacitance of m8 we have:

Figure 3-27: Load used in proposed ring oscillator showing inductive impedance

Therefore, the impedance at the drain of M3 is always inductive. Its magnitude can be changed
by varying the widths of M7 and M8.

Therefore, the impedance at the drain of m8 is always inductive. Its magnitude can be changed by
varying the widths of m9 and m10. Considering that the nmos switches faster than the pmos, a
cross coupled nmos pair m5 and m6, is introduced at between the outputs to provide the essential
self-balancing of the delay cell to prevent the differential ouputs from settling to the same
voltage. In addition to that, the cross-coupled nmos pair can also help to improve the phase noise
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performance of the oscillator by a significant amount since the positive feedback within the delay
cell provided by this nmos pair helps to reduce the transition time of the output nodes.

1.19.3 High speed ring oscillator with dual delay paths

In a conventional ring oscillator, the oscillation frequency is determined , where N is the number
of stages and t is the unit delay time of a delay cell. Hence the frequency of the oscillator is
decided by the delay time of one delay element. The delay time cannot be smaller than that of a
single inverter; therefore, the maximum frequency of the VCO is limited by the delay time of the
basic inverter delay cell.

To solve this frequency-limitation problem, a single-ended ring oscillator with a negative skewed
delay scheme has been used [20]. If the delay cell is single ended, and the oscillator is sensitive to
the power-supply noise and not controllable. In this work, by using a dual-delay scheme to
implement the VCO, higher operation frequency and wider tuning range are achieved
simultaneously. The dual-delay scheme means that both the negative skewed delay paths and the
normal delay paths exist in the same ring oscillator. The negative skewed delay paths decrease
the unit delay time of the ring oscillator below the single inverter delay time. As a result, higher
operation frequency can be obtained. Since the normal delay paths also exist, the frequency range
of the VCO can be wider than that of an oscillator with only skewed delay paths.

Figure 3-28 : simulation results of three types of VCO’s

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Figure 3-20 shows the simulation results of the three types of VCO, with dual-delay path, only
normal delay path, and only negative skewed delay path. The same types of delay cells are used
to implement the VCO’s. The figure shows that the dual delay scheme achieves both a high
oscillation frequency and a wide tuning range.

To utilize both the negative skewed and the normal delay paths, a pair of PMOS transistors, are
added to the PMOS loads of the delay cell and are used to take the negative skewed signals, as
shown in figure 3-21.

Figure 3-29:ring oscillator structure with dual delay paths

The negative skewed signal is connected to the PMOS input of the delay cell, and the normal
signal is connected to the NMOS input of the delay cell. The negative skewed signal is taken
from the two stages before the current delay stage. The signal prematurely turns on the PMOS
during the output transition and compensates for the performance of the PMOS, which is usually
slower than that of the NMOS. This operation enhances the rise time of the output and contributes
to reducing the phase noise of the overall VCO. In figure 4.6, the negative skewed delay paths are
the paths which are coming from the outputs to the inputs of in2+ and in2-, and the normal delay
paths are the paths which are coming from outputs of previous stage to the inputs in1+ and in1-.
Figure 3-21 illustrates the tuning characteristics of proposed VCO. Changing the control voltage
between 100mV-500mV, the frequency varies between 7GHz - 2 GHz in differential voltage
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controlled ring oscillator. It shows linear characteristics and wide tuning range of oscillator. The
VCO gain is 18GHz/v.
Figure 3-22 is the plot of output waveforms of the VCO for different control voltages. From this
we can understand that as the control voltage is increasing the VCO is taking more time to change

Figure 3-30: output waveforms of the VCO for different control voltage and linearity
range.

1.20 Frequency Divider

The frequency divider is an important building block in today’s RFIC and microwave circuits
because it is an integral part of the phase-locked loop (PLL) circuit. In a typical PLL loop, the
output of the voltage-controlled oscillator (VCO) is divided down by the frequency divider to a
stable reference frequency signal produced by the crystal oscillator[21]. The divided signal and
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reference frequency signal are fed into the phase detector for comparison. The output phase
difference is used to adjust the VCO output frequency.

1.20.1 Digital dividers

To divide a digital signal by an integer multiple a Johnson counter is used. This is a type of shift
register network that is clocked by the input signal. The last register’s complemented output is
fed back to the first register’s input. The output signal is derived from the combination of the
register outputs. For example, a divide-by-3 divider can be constructed with a 3-register Johnson
counter. The three valid values for each register are 000, 100, 110, 111, 011, and 001. This
pattern repeats each time the network is clocked by the input signal. The values 000 and 111
occur with three clock pulses apart and control the state change of the output signal. Additional
registers can be added to provide additional integer divisors.

For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal.
The least-significant output bit alternates at the same rate as the input, the next bit is the 1/2 the
rate, the third bit is 1/4 the rate, etc. An arrangement of flip-flops is a classic method for integer-n
division. Such division is frequency and phase coherent to the source over environmental
variations including temperature. The easiest configuration is a series where each flip-flop is a
divide-by-2. For a series of three of these, such system would be a divide-by-8. By adding
additional logic gates to the chain of flip flops, other division ratios can be obtained.

Figure 3-31: output waveforms of the VCO for different control voltage

In the figure 4.1 we give a frequency divider which divides the frequency by two. It is
implemented using only one D flip-flop.
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It is essentially an edge triggered master/slave D flip-flop (DFF). The inverted output is fed back
to the input port D. As shown in Figure 4.2, each positive input clock cycle is loaded into the
DFF. On the next cycle, inverted output again is fed back to the input, which causes the output to
toggle. It is why toggle DFF is a more descriptive name for this circuit. The same event repeats
for every two input clock cycle. Thus, output frequency is half of the input frequency.

Figure 3-32: Divide by 2 frequency divider output

Now we will see the implementation of the D flip flop. The proposed DFF uses two sets of
clocks. The clocks applied on transmission gates M1 and M3 are denoted clk and clkbar, and the
clocks applied on gates M2 and M4 are denoted clk_d and clkbar_d clocks are generated by
delaying clocks clk and clkbar, respectively, with two stages of inverters [22].

Figure 3-33: D Flip flop

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Now we will see the implementation of the D flip flop. The proposed DFF uses two sets of
clocks. The clocks applied on transmission gates M1 and M3 are denoted clk and clkbar, and the
clocks applied on gates M2 and M4 are denoted clk_d and clkbar_d clocks are generated by
delaying clocks clk and clkbar, respectively, with two stages of inverters.

The proposed static DFF has a reduced setup time compared to that of a conventional static DFF.
In the conventional static DFF we will not have two clocks, but in our proposed D flip flop we
have two clocks. Let us see what happens if we use same clock that is instead of clk_d we use clk
signal only.

When the clock clk is high, the data D is loaded to node A and stored in the first memory unit
composed of inverters inv and inv2. When the clock clk goes low, the data stored in the first
memory unit is propagated to the output terminal. In order for the DFF to function correctly, a
sufficiently large setup time is required to allow the new data to be propagated to node B, through
the path of node A, inv1, and inv2.

If the clock is too fast, the DFF will not have sufficient setup time and the following scenario
might cause the DFF to not function correctly. Assume that the clock is high and the input data
changes from low to high, then the signal at node A will change from low to high. At this
moment, due to the delay of inverters inv1, and inv2, node B is still in the previous state. If the
clock goes high before node B changes to the present state, the transmission gate M2 will be
closed, causing the data previously stored at node B to be propagated to node A. If the previous
data is different from the new data, they will ‘fight’ with each other. Since the transmission gate
M1 is now open, the final state of node A is uncertain and the DFF may function incorrectly[22].

The proposed design uses two sets of clocks on gates M1 and M2.When clock clk, is high, the
new data is propagated to node A through M1. Then, as soon as the new data is propagated to the
output of INV1, the clock can go low and the new data can be propagated to the output of the
DFF. Since clock clk_d is the delayed version of clock clk, when clock clk goes high, clock clk_d
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is still low. Thus gate M2 is still open and the previous data stored at node B cannot be
propagated to node A through M2. The ‘fighting’ condition between the new data and the
previous data is then avoided. As a result, the setup time of the proposed DFF is reduced.
Simulation results of the proposed D flip flop:
Setup time of the flip flop = 50 ps
Hold time of the flip flop = 22 ps

In the proposed PLL we have used 6 bit frequency divider. Let us suppose the frequency of the
clock given to the first D flip flop is “ f ” then the output of that flip flop is coming out to be the
half of the frequency of the input clock i.e. f/2. This output is given to the next flip flop as clock
then the frequency of output of the second flip flop will the half of the input clock i.e. f/4. This
output is given to third flip flop then the frequency of the output of that flip flop will be f/8. Like
this the output of the forth flip flop is f/16, output of fifth flip flop is f/32 and the output of the
sixth flip flop is f/64. In this way our frequency divider will produce the output frequency which
1/64th of the input frequency.

Figure 3-34: Proposed 6 bit frequency divider

The output waveforms of the frequency divider are shown below.

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Figure 3-35:Output waveforms of the frequency divider

CHAPTER 4 : SIMULATION RESULTS

Full loop simulation of the proposed PLL is shown in the following figure 4.1. Initial control
voltage given at the starting of the simulation is Vdd. So as the reference frequency is 100MHz
and the frequency divider is 6 bit, the output frequency of the VCO should be 7GHz. So the
control voltage should get settled to a specified value such that the output frequency of VCO is
7GHz.
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Figure 4-36: Full loop simulation of the PLL

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When the PLL is in locked state the control voltage should be stabilized to a constant value which
is clearly shown in the figure 4-1. The control voltage got stabilized to 50mV after time of 50ns.
The time taken by the PLL to get lock to a new specified frequency is called lock time. So the
lock time of the PLL is 50 ns.

When the PLL is in locked state the reference frequency and the feedback signal i.e. the output
frequency of the frequency divider should be in phase. This is clearly shown in the figure 4-1.

Summary of overall PLL:

 Reference frequency is 100MHz
 Charge pump current is 150µA
 Loop filter is of second order
 VCO gain is 18GHz/v
 Linearity range of VCO is 400mV(100mV-500mV)

 Frequency divider is 6 bit

 Lock time of PLL is less than 50ns

 Power consumption of PLL in locked state is 7mW

 PLL output is 4-7Ghz GHz

 Error is 10MHz (0.15%)

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CHAPTER 5 : CONCLUSION AND FUTURE SCOPE

In this thesis we presented the design of CMOS based Fast Locking DPLL for generating high
frequency clocks. In the proposed digital PLL, the previously proposed circuits for various units
of DPLL were modified for better performance.
It incorporates a high performance phase frequency detector that requires minimum number of
transistors and consumes as low as 0.4 µW of power. It provides a linearity range of -2π to +2 π
and eliminates dead zone almost completely.
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The charge pump unit incorporated in the proposed PLL gave satisfactory simulation results.
Various non idealities (channel charge injection, clock feed through and charge sharing) that were
present in conventional charge pump were eliminated. Therefore no sudden jump phenomenon
was observed in output during pump up or pump down operation. The problem of current
mismatch that was present before (due to channel length modulation (CLM) effect) was
suppressed by using stable bias voltages which are generated by the bias generator. The charge
pump is designed to produce an output current of 150µA. The average power consumption is
0.625 µW.
The VCO unit incorporated will have dual delay paths in order to reduce delay of the single
delay stage so that the frequency of operation will get maximized. The transfer characteristic of
VCO was satisfactory in the operating range provided by charge pump (100mV- 500 mV). The
average power consumption of the VCO circuit is 0.5 µW at 5GHz frequency and the frequency
divider used is 6 bit.
The proposed PLL obtained by integrating all the units gave good simulation results. The lock
time of PLL is less than 0.45µs and the average power consumption in locked state is 7 mw. The
static phase error of proposed PLL is as low as 57 ps. The proposed circuit (DPLL) is suitable for
various applications in high speed systems due to advantages of low power, fast locking and low
static phase error.

Future scope includes making this PLL programmable PLL in which CP,PFD and VCO
are control through programmable unit which allow very fast locking . To validate the
performance of this PLL Layout drawing, extraction and post layout simulation are
important So this may be part of future work.
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REFERENCES

TEXT BOOKs:
1 John L. stensby, Phase locked loop - theory and application. CRC Press, Bocca Raton,
1997.
2 Donald R Stephens, Phase locked loop for wireless communication for Digital, Analog
and optical communication. Kluwer Academic Publishers, 1998.
3 Roland Best, Phase locked Loop Design, Simulation and Analysis. CRC Press LLC, 1997.
4 Philip & Holberg, CMOS Analog Circuit Design Second Editio. Oxford Uni Press, 2002.
5 Behzad Razavi, Design of Analog CMOS ICs. TATA MCGRAW HILL Edition, 2001.
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IEEE PAPERs

6 Behzad Razavi, “The Role of PLLs in Future Wireline Transmitters”, IEEE TRAN ON
Circuits and Systems, VOL. 56, NO. 8, AUGUST 2009.
7 Jinbao Lan, Yuxin Wang, Lintao Liu, Ruzhang Li, “A Nonlinear Phase Frequency
Detector with Zero Blind Zone for Fast-Locking Phase-Locked Loops”, IEEE Conf. pp.
41–44, July 2010.
8 Jinbao Lan, Fengchang Lai, Zhiqiang Gao, Hua Ma and Jianwei Zhang, “A nonlinear
phase frequency detector for fast-lock phase-locked loops”, in IEEE 8th International
Conf. on ASIC (ASICON 2009), pp. 1117-1120, Oct. 2009.
9 W. Hu, L. Chunglen and X. Wang, “Fast frequency acquisition phase frequency detector
with zero blind zone in PLL,” Electronics Letters, vol. 43, pp. 1018-1020, Sept. 2007.
10 Jun Pan and Tsutomu Yoshihara, “A fast lock phase-locked loop using a continuous-

time phase frequency detector,” in IEEE Electron Devices and Solid-State Circuits
Conf., pp.393–396, Dec. 2007.
11 Mozhgan Mansuri, Dean Liu, and Chih-Kong Ken Yang, “Fast frequency acquisition

phase-frequency detectors for GSamples/s phaselocked loops”, IEEE J. Solid-State

Circuits, vol. 37, pp.1331–1334, Oct. 2002.
12 Ali, M., Elsemary, H, Shawkey, H, Zekry, “A Fast Locking Digital Phase-Locked Loop

using Programmable Charge Pump”, IEEE Conf. vol. 32, Page(s): 135 – 138, 2010.
13 Chen, P.-I., Mak ,Y. Zhou, “Self-tracking charge pump for fast-locking PLL”,IEEE

Electronics Letters, Vol 46,Page 755, June 2010.

14 Lee, J.S., Keel, M.S., Lim, S.I., and Kim, “Charge pump with perfect current matching

characteristics in phase-locked loops”, Electron. Lett., 35, (23), pp. 1907–1908, 2004.
15 Lin, T.H., Ti, C.L., and Liu, Y.H. “Dynamic current-matching charge pump and gated-

offset linearization technique for delta-sigma fractional-N PLLs”, IEEE Trans. Circuits
Syst. I, Reg. Papers, 2009, 56, (5), pp. 877–885.
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16 Kuo-Hsing Cheng ,Ch'ing- Wen Lai and Yu-Lung Lo, “A CMOS VCO for lV, lGHz

PLL Applications”, IEEE Conf. Vol27 , page 150-155 Aug,2004.

17 J.G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased

techniques,” IEEE J. Solid-Srare Circuits, vol.31 no.11, pp. 1723-1732 Nov. 1996.
18 Huiting Chen, Geiger, “Transfer characterization of CMOS ring voltage controlled

oscillators”, IEEE Proc. Vol 1, pp 66-70 , August 2002.

19 Wei-Hsuan Tu, Jyh-Yih Yeh, Hung-Chieh and Tsai Chorng-Kuang Wang, “A 1.8V

2.5-5.2 GHz CMOS Dual-input Two-stage Ring VCO”, IEEE Asia-Pacific Conference
on Advanced System Integrated Circuits, pp. 134-137 Aug. ,2004.
20 Yan, W.S.T., Luong, H.C., “A 900 MHz CMOS Low Phase noise voltage controlled ring

oscillator,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal
Processing, vol. 48, pp.216 – 221, Aug 2001.
21 Changhua Cao; Yanping Ding; O, K.K. “A 50-GHz Phase-Locked Loop in 130-nm

CMOS”, IEEE CICC , Vol26 pp 21-24 ,Feb 2007 .

22 Wagdy, M.F.; Vaishnava, S., “A FAST-Locking Digital Phase Locked Loop”, IEEE

Conf., pages(s) 742-746 , 2006.

GLOSSARY OF TERMS USED

CMOS - Complimentary Metal Oxide Semiconductor

UDSM - Ultra Deep Sub Micron
PFD - Phase Frequency Detector
IC - Integrated Circuit
DSP - Digital Signal Processing
CP - Charge Pump
VCO - Voltage Control Oscillator
PLL - Phase Lock Loop
PSRR - Power Supply Rejection Ratio
CMRR - Common Mode Rejection Ratio
CMR - Common Mode Range
MOSFET - Metal Oxide Semiconductor Field Effect Transistor
WiMAX, - Worldwide Interoperability for Microwave Access,
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CHECKLIST

a) Is the Cover page in proper format? Y

b) Is the Title page in proper format? Y
c) Is the Certificate from the Supervisor in proper format? Has it been signed? Y
d) Is Abstract included in the Report? Is it properly written? Y
e) Does the Table of Contents page include chapter page numbers? Y
f) Does the Report contain a summary of the literature survey? Y
i. Are the Pages numbered properly? Y
ii. Are the Figures numbered properly? Y
iii. Are the Captions for the Figures and Tables proper? Y
iv. Are the Appendices numbered? Y
Does the Report have Conclusion / Recommendations of the work? Y
Are References/Bibliography given in the Report? Y
Have the References been cited in the Report? Y
Is the citation of References / Bibliography in proper format? Y