09.24.

98 Mitsubishi M32Rx/D: EDN's 25th

Annual Microprocessor/Microcontroller
Director
EDN Staff - September 24, 1998
September 24, 1998
EDN's 25th Annual Microprocessor/Microcontroller Directory
Mitsubishi M32Rx/D
View block diagram

The Mitsubishi M32Rx/D contains a 32-bit RISC CPU; as much as 4 Mbytes of on-chip DRAM,
which Mitsubishi calls "eRAM"; a 32X16-bit multiply-accumulate (MAC) unit; and a bus-
interface unit (BIU). A 128-bit, 66-MHz internal bus connects the CPU, DRAM, cache, and
BIU. The M32Rx/D's circuitry automatically refreshes the internal DRAM.

The M32Rx/D family comprises the M32R/D and the new superscalar M32Rx/D architectures.
Both architectures are instruction-set-compatible and comprise a combination of 16- and 32-
bit-wide instruction formats with six addressing modes. The devices include 16 32-bit,
general-purpose registers and two 56-bit accumulators.

The M32R/D CPU executes most instructions in one clock cycle, using an instruction-fetch,
decode, execute, memory-access, and write-back pipeline. The decode stage dispatches
instructions in order, and the remaining stages execute them out of order to hide memory-
access latency. The MAC unit contains a single-cycle, 32X16-bit multiplier and a 56-bit adder.

The M32Rx/D contains a dual-issue, six-stage pipeline and performs out-of-order execution; it
can execute two 16-bit instructions in parallel. The pipelines are asymmetrical, and
instructions have to align properly to keep the pipes full. For example, both pipelines can
execute arithmetic and logical operations, but only Pipeline 1 can execute load/store and
jump/branch instructions. Additionally, only Pipeline 2 can execute MAC instructions.

Both CPUs have an instruction queue of two 128-bit entries. The cache maps directly to the
address space and has caching modes for internal instruction and data, for internal and
external instructions, and for cache off. If a cache miss occurs, the CPU fetches one 128-bit
data line in five cycles. The BIU has 128-bit data buffers and supports burst transfers on 128-
bit boundary data.

A 16.67-MHz bus clock and four digital PLLs generate the internal 66-MHz clock. The PLL
contains a digital frequency multiplier. Four cascaded, 64-tap inverter chains generate four
timing edges in one-half of a clock cycle. A phase detector and an up/down counter adjust the
pulse width to one-fourth of the one-half clock cycle to keep the duty cycle of the four-times
clock at 50%. The generated clock then feeds into a digital phase shifter to reduce the phase
difference between the external and internal clocks to 400 psec.

Power management: The M32Rx/D supports sleep and standby modes, during which the
average power consumption is 170 and 2 mW for the two modes, respectively, for the 2-Mbyte
version. In the sleep mode, the CPU and caches stop; in standby mode, only the DRAM is
clocked.

Special instructions: The M32Rx/D supports MACs of 32X16 and 16X16 bits. It also
performs data rounding in the accumulator and block moves. The M32R/D and M32Rx/D
support 83 and 95 instructions, respectively. The M32Rx/D's additional instructions include
five DSP-function instructions for MAC and rounding operations.

Special off-chip peripherals: Mitsubishi's M65439FP peripheral-function "super-I/O" chip

performs such functions as M32000D bus control, DRAM control supporting two banks and
page-mode burst transfers, and chip-select control for as many as five 64-kbyte to 4-Mbyte
blocks with one to eight wait states. The peripheral I/O ASIC also contains a two-channel DMA
controller that can transfer as much as 2 Mbytes using cycle-steal, single-transfer,
continuous-burst-transfer mode or cycle-steal, continuous-transfer mode. An interrupt
controller handles 20 sources with priority resolution for as many as seven levels. Other
functions of the M65439FP include timers, a two-channel UART, and a two-slot IC-card
controller. The device sells for $8 (10,000).

Development tools: Cygnus (www.cygnus.com) supplies C and C++ compilers and

debuggers for the M32Rx/D. Mitsubishi also supplies a C compiler and debugger, an
evaluation board, and an in-circuit emulator. Wind River (www.windriver.com) supplies the
Tornado development environment, which includes the VxWorks RTOS. Integrated Systems
(www.isi.com) supplies the Prism+ development environment, which includes the pSOS
RTOS, Diab Data's (www.diabdata.com) C compiler and Light Source debugger.

Second sources: There are no second sources for the M32R/D or M32Rx/D.
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