Vidyalankar

S.E. Sem. III [CMPN]

Computer Organization & Architecture
Time : 3 Hrs.] Prelim Question Paper [Marks : 100

N.B. : (1) Question no. 1 is compulsory.

(2) Answer any four out of remaining six questions.
(3) Figures to the right indicate full marks.

1. (a) Explain structure of computer defined by Sir Von Neumann. [5]

(b) Explain in brief the IEEE 754 format  for floating point number representation. Hence, [6]
convert the number as directed.
(i) 15.4 to IEEE 754 format. (ii) (BFC00000)16 to floating point real number.
(c) Give the micro operation required to implement the following instructions [4]
(i) ADD A, B (ii) SUB A, B
where, A and B are two registers. The microoperation should take into account all the
stages of instruction execution cycle.
(d) The access time of a cache memory is 100 ns and that of main memory is 1000 ns. It is [5]
estimated that 75% of memory requests all for read and remaining for write. The bit ratio
for read access only is 0.9 and for write is 0.8. A write through procedure is used.
1) What is the average access time of the system considering only memory read cycle?
2) What is the average access time of one system for both read and write requests?
Given :
Tall (ns) Read bit Write bit
Cache 100 90% 80%
Main memory 1000 10% 20%
75% of memory requests are for read.
25% of memory requests are for write.

2. (a) Explain various addressing modes. [10]

(b) Differentiate between : (any two) [5]
(i) RISC and CISC computer. (ii) Hardwired control and Microprogrammed control unit
(iii) SRAM and DRAM. (iv) Synchronous and Asynchronous bus
(c) Design and implement a 4bit ALU, which will have the following functions : [5]
(i) Subtraction (ii) And (iii) OR

3. Write notes on: [20]

(a) SPARC Architecture (b) USB
(c) Systolic architecture (d) SCSI

7 2
4. (a) In a two level virtual memory, t A1  10 S, t A2  10 S, what, must be the hit ratio H be in [5]
order for the access efficiency to be atleast 90% of its maximum possible value.
Given : t A1  107 s, t A2  102 s,   90% Required : Hit ratio = H = ?
(b) Explain in brief "Virtual memory concept and its address translation procedure". [5]
(c) Explain Booth's algorithm. Also write Booth's algorithm for 2's complement multiplication [10]
using flow chart.

5. (a) Write short notes on (any two) : [6]

(i) Nano programming (ii) Fault tolerant computing
(iii) Dataflow computing
(2) Vidyalankar : S.E.  COA

(b) State and explain types of memories according to their usage. [4]
(c) What is meant by Synchronous Bus. What are its basic operations ? [10]

6. (a) Explain in detail the various properties to be considered when evaluating any memory [10]
technology.
(b) Design a 16K byte RAM using 256  4 bit RAM ICs. [10]

7. (a) Explain the implementation of : (i) Paged memory system [10]

(ii) Demand paged memory system.
(b) Explain the following : [10]
(i) Memory mapped I/O
(ii) I/O mapped I/O

