Flip-Flops Part1

1. D Latch
Figure 1 illustrates the internal and block diagram of a D latch
D Q
D Q
En En
Q’ Q’

(a) (b)

Figure 1 (a) Internal configuration of a D latch with active high Enable

(b) Block diagram of a D latch with active high Enable

• We demonstrated that the D latch is transparent when En signal is asserted (= 1). In

this case the output (Q) is a COPY of the input (D).
• When En is not asserted, the D latch is OPAQUE (locked) and remains the state it
was left the last time En was asserted.

2. Flip Flops
2.1 Overview
• Latches are known as level-sensitive devices. Their outputs follow their inputs as
long as they are enabled.
• Their state can therefore change during the entire time when the En signal is
asserted.
• There are situations where it is more convenient and useful to have the output
changes only at the rising or falling edges of the enable signal.
• This signal is the synchronizing clock signal
• Flip Flops (FFs) are such devices. They are edge-triggered devices.
2.2 General Representation of a FF
Figure 2 below illustrates a general representation of a FF.
Asynchronous
Input
PR
Synchronous
Input(s) Q
FF Outputs

Q’
Clock
CLR
Asynchronous
Input
Figure 2 Block diagram of a generic flip flop

1
In general, a FF has
• A clock input signal (Clk)
• One or two synchronous control inputs (depending on the FF’s type)
- D
for D-FF
- T
for T-FF
- J,K
for JK-FF
• Two asynchronous inputs Preset (PR) and Clear (CLR)
• Usually 2 outputs (Q and Q’)
(Q’ stands for Q bar)

A FF has2 stable states (reason why FFs are also called Bistables): state-0 and state-1.
• When Q = 1, Q’ = 0; the FF is in the SET state or state 1.
• When Q = 0, Q’ = 1; the FF is in the RESET (Clear) state or state 0.

Normally, a FF can remain in either state for an infinite period of time until it is triggered
into the alternate state by an input(s) signal(s) either synchronously (via synchronous
control inputs and the clock) or asynchronously via (PR and CLR).

2.3 Design of Edge-Triggered FF.

There are 2 techniques to construct edge-triggered FFs
• Master-Slave
• Fast edge-triggered

2.3.1 Master/Slave D-FF

This D-FF type uses 2 D latches connected in series, Figure 3. The clock (Clk) signal is
connected to the Enable input of the latches; one directly, and one through an inverter.
MASTER SLAVE
Qm Qs

Q’s

(b)
(a)

Figure 3 (a) internal configuration of Master/Slave D-FF

(b) Block diagram of a positive edge-triggered MS D-FF

• The 1st latch is the MASTER, the 2nd, the SLAVE.

• The CLK enables either the MASTER or the SLAVE but not both at the same time

• The master stage is active during ½ of the clock cycle, the slave during the 2nd half.
o When Clk = 0, the MASTER is enabled:
• Qm follows D i.e., Qm = D
• Qs remains unchanged (frozen)

2
 o When Clk = 1, the MASTER latch is disabled, while the SLAVE is enabled.
• Qm is transferred to the output Q of the FF
• The slave is enabled all the time Clk = 1, but its content
changes only when the Clk signal changes from 0 to 1 that is,
at the positive edge of the Clk.

The circuit of Figure 3 is referred to as a Positive edge-triggered master/slave D-FF or

(MS D-FF).
The FF output Q changes ONLY after the positive edge of the Clk

If the slave D-latch is enabled when the Clk is LOW, then it is referred to as a negative
edge-triggered MS D-FF.

Figure 4 illustrates the logic symbols of D-latches and D-FFs.

- (a) Active HIGH enable D-latch
- (b) Active LOW enable D-latch
- (c) Positive edge-triggered master/slave D-FF
- (d) Negative edge-triggered master/slave D-FF

You have certainly remarked the difference between a D-LATCH and a D-FF resides in
the synchronizing input signal.
FF’s synchronizing signals are provided with arrows to represent edges
Absence of arrows on latches means these devices are level sensitive.

D Q D Q D Q D Q
D-Latch D-Latch D-FF D-FF

En Q’ En Q’ Clk Q’ Clk Q’

(a) (b) (c) (d)

Figure 4 (a-b) D-latches; (c-d) D-FFs logic symbols

2.3.2 Timing Behavior of a Positive edge-triggered MS D-FF

Clk

x x
D x x x

Qm

Figure 5 Timing diagram of a positive edge-triggered D-FF

3
Figure 5 shows a sample trace for the positive edge-triggered D flip-flop.
When Clk = 0, Qm follows D, and the output of the slave latch, Q, remains constant.
On the other hand, when Clk = 1, Q follows Qm, and the output of the master latch, Qm,
remains constant.

NB: If we consider Clk, D, and Q, we notice that the output Q changes only at the positive
edges of the Clk signal. The output Q takes the value of D at the occurrence of the positive
edge. The output Q remains frozen (unchanged) between 2 successive positive edges

2.3.3 Fast Edge-Triggered D-FF

An alternative to the master-slave edge-triggered D-FF is the so called a fast edge-
triggered D-FF.
The fast edge-triggered D-FF uses 3 interconnected SR latches as shown in Figure 6.
The 3 SR latches are:
- a Set latch (gates 1 and 2)
- a Reset Latch (gates 3 and 4)
- an Output Latch (gates 5 and 6)

D Q
D-FF

Clock Q’

Figure 6 Internal circuit of the fast edge-triggered d-FF

This configuration requires 6 NAND gates compared to the MS D-FF which uses 11
NAND gates.

The operation of the circuit is as follows:

1. When Clock = 0, then P1 = P2 = 1 which maintains the output latch (Q and Q ) in
its present state. At the same time, the signal P4 is equal to D , and P3 is equal to D.
2. When Clock changes to 1, the following changes take place.
The values of P3 and P4 are transmitted through gates 2 and 3 to cause P1 = D’ and
P2 = D, which sets Q = D and Q’ = D’.
For proper operation, we should show that when the Clock changes from 0 to 1 any
further changes in D will not affect the output latch as long as Clock = 1.

We have to consider 2 cases:

4
 1. Suppose D = 0 at the rising edge of the Clock, then P2 = 0, which keeps P4 = 1
regardless of the value of the D input.
2. If D = 1 at the rising edge of the Clock, then P1 = 0 which forces P3 = P2 = 1
regardless of the value of input D.
Therefore, the D-FF ignores changes in the D input while clock = 1.

The input data to a D flip-flop is transferred to the output and held there on a 0 to1
transition of the Cock pulse. In other words, the D flip-flop is triggered on the positive
edge of the Clock.

2.4. Description of a FF
There are 5 ways to describe the functionality of a FF. they are
1. Logic symbol
2. State (characteristic) table
3. State (characteristic) equation
4. Excitation table
5. State diagram.

Description of the D-FF

2.4.1 Logic symbol

D Q D Q
D-FF D-FF

Clk Q’ Clk Q’

(a) (b)

Figure 7 D-FF logic symbols : (a) positive edge-triggered

(b) negative edge-triggered

2.4.2 State table

D(t) Q(t) Q(t+1) D Q Q+

0 0 0 0 0 0
0 1 0 0 1 0
1 0 1 1 0 1
1 1 1 1 1 1

Where Q(t) (or Q) is the present state, and Q(t+1) (or Q+)the next state.

2.4.3 State equation

Q(t+1) = D(t) or Q+ = D

2.4.4 Excitation table

The excitation table is the image (mirror) of the state table

5
Q Q+ D The state table tells what the FF’s inputs should be in order to change
0 0 0 from FF’s present state (Q) to the next state (Q+).
0 1 1 This table is usually used in the synthesis of sequential circuits such as
1 0 0 counters, registers, FSM etc.
1 1 1 For example, line 2 (Q= 0; Q+ = 1; D =1), we read this line as follows:
If PS is 0 and we want the NS to be 1, how should we excite the FF?
By making D =1. (Given that D = Q+)

2.4.5 State diagram

• It is a graphical representation of the FF’s behavior
• It consists of nodes (circles) and arcs connecting nodes
• The nodes are labelled with states of the FF and the arcs are labeled with input
signals that cause the transition to go from one state to another
• It is a graphical representation of the excitation table.
The state diagram of the D-FF

D=1

D=0 D=1

D=0
We read the diagram as follows:
• If PS is 0 (Q =0) and D =1, then the NS will be Q=1
• If PS is 0 and D=0, then NS will be Q=0
• If PS is 1 and D=1 then NS will be Q=1
• If PS is 1 and D = 0 then NS will be Q = 0.

6
2.5 Flip Flop Variants

• There are basically 3 main types of flip-flops: D, T, and JK.

• The major differences in these flip-flop types are in the number of inputs they have
and how they change states.
• Any desired FF type can be built using any of the other FF types available. In other
words, given a FF type, we can transform it in any other FF type.

2.5.1 The JK flip-flop (JK-FF)

The JK FF was named after Jack Kilby. A Ti engineer who invented the IC in 1958

The JK-FF has two inputs that act like the S and R but the combination J = k =1 toggles the
FF.

2.5.1.1 The state table of the JK-FF

J K Q+ Q+’ Mode
0 0 Q Q’ Memory or hold Q’ stands for Q bar
0 1 0 1 Reset (Complement of Q)
1 0 1 0 Set
1 1 Q’ Q Toggle

2.5.1.2 The state equation

Q J K Q+
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
Q+ = K’Q + JQ’
1 1 1 0

7
2.5.2 The T-FF (Toggle)

The T-FF has one input T (stands for toggle), in addition to the clock signal.
The T-FF operates as follows:
• When T = 1, the T-FF state toggles (changes state) at each active edge of the clock.
• When T = 0, the T-FF keeps its current state
2.5.2.1 The State table

Q T Q+ Mode
0 0 0 Hold
0 1 1 Toggle
1 0 1 Hold
1 1 0 toggle

2.5.2.2 The State equation

The state equation is easily derived from the above state table as:

Q+ = Q O
+ T
Summary
The state equations of the three FFs are
D-FF QD+ = D or QD(t+1) = D(t)
T-FF QT+ +T
=QO

JK-FF Q +JK = KQ + J Q

2.6 Construction of a JK-FF using a D-FF

Equating the two state equations,
QD(t+1) = QJK(t+1)
yields
D(t) = KQ( t ) + JQ( t )

Clk

2.7. Construction of a T-FF using a D-FF

Similarly, equating the two state equations,
QD(t+1) = QT(t+1)
Yields
D(t) = Q(t) O+T
Clk

8
2.8 Asynchronous inputs

• The J, K; D; and T are called synchronous inputs

• They affect the corresponding FF only when the device is clocked (they are clock
dependent)
• Sometimes, it is convenient to be able to alter the state of the FF without waiting
for the arrival of the active edge of the clock pulse
• In addition to synchronous inputs most FFs have one or two asynchronous inputs
• The two asynchronous inputs (independent of the clock) are usually called
PRESET (PR) or SET and CLEAR (CLR) or RESET.
• PR sets the FF to state 1; CLR resets the FF to state 0.
• The primary use of these inputs is to set the FF to a known state
• Asynchronous inputs OVERRIDE synchronous inputs i.e., if both synchronous and
asynchronous inputs are activated at the same time, the FF responds to the
asynchronous inputs.

2.8.1 Representation of asynchronous inputs

Figure 8 illustrates the logic symbols of a negative edge-triggered D-FF with (a) active
LOW asynchronous inputs and (b) active HIGH asynchronous inputs
PR PR

D Q D Q
D-FF D-FF

Clk Q’ Clk Q’

CLR CLR
(a) (b)
Figure 8 (a) active LOW asynchronous inputs;
(b) active HIGH asynchronous inputs

Because asynchronous inputs override the synchronous ones, therefore, to operate the FF
in the synchronous mode, PR and CLR must be disabled
• Active LOW asynchronous inputs are disabled by making them equal to 1.
• Active HIGH asynchronous inputs are disabled by making them equal to 0.
Asynchronous inputs should never be active at the same time. (There is no practical
application that requires the FF to be SET and RESET at the same time).
Therefore, ONLY one input can be active at one time or both disabled.

2.8.1 Internal Circuit with Asynchronous inputs

The circuit of Figure 9 illustrates the internal circuit of a positive edge-triggered D-FF
with active LOW asynchronous inputs SET and RESET.

9
 1

2 5

3 6

Figure 9 A positive edge-triggered D-FF with active LOW

asynchronous SET and RESET

The circuit operates as follows:

1. Asynchronous RESET
RESET = 0 => G2 = G4 = G6 = 1  Q = 1
With SET = 1, then G5 =0  Q = 0

2. Asynchronous SET
SET = 0  G1 = G5 =1  Q =1
With RESET = 1 then
i- if Clock = 1  G2 = 0  G3 = 1  Q = 0

ii- if Clock = 0  G3 = 1  Q = 0

2.9 Functional table of a JK-FF with asynchronous inputs

The logic symbol of Figure 10 represents a negative edge-triggered JK-FF provided with
active LOW asynchronous inputs PR and CLR.

PR

J Q
JK-FF
Clk
Q’
K

CLR
Figure 10 Logic symbol of JK-FF with asynchronous inputs

10
The functionality of the logic symbol of Figure 10 can be described by
1. A functional table

CLR PR Clk J K Q(t+1) Q’(t+1) mode

0 1 x x x 0 1 Asynchronous RESET
1 0 x x x 1 0 Asynchronous SET
1 1 0 0 Q(t) Q’(t) Memory or Hold
1 1 0 1 0 1 Synchronous RESET
1 1 1 0 1 0 Synchronous SET
1 1 1 1 Q’(t) Q(t) Toggle

2. A timing diagram

Clk

CLR

PR

Q’

Toggle mode
Asy Clr

Asy Set

Asy mode Sync mode

Next section: VHDL description of Latches and FFs

11