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JEDEC TO-220AB JEDEC TO-263AB
SOURCE
DRAIN
GATE DRAIN
(FLANGE)
DRAIN (FLANGE) GATE
SOURCE
4-33 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
IRF9640, RF1S9640SM
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC
Thermal Resistance Junction to Ambient RθJA Typical Socket Mount - - 62.5 oC/W
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IRF9640, RF1S9640SM
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = -11A, VGS = 0V (Figure 13) - - -1.5 V
Reverse Recovery Time trr TJ = 150oC, ISD = -11A, dISD/dt = 100A/µs - 300 - ns
Reverse Recovery Charge QRR TJ = 150oC, ISD = -11A, dISD/dt = 100A/µs - 1.9 - µC
NOTES:
2. Pulse Test: Pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, starting TJ = 25oC, L = 9.8mH, RG = 25Ω, peak IAS = 11A. See Figures 15, 16.
1.2 -15
POWER DISSIPATION MULTIPLIER
1.0
ID, DRAIN CURRENT (A)
0.8 -10
0.6
0.4 -5
0.2
0 0
0 50 100 150 0 50 100 150
TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE
TRANSIENT THERMAL IMPEDANCE
0.5
ZθJC, NORMALIZED
0.2
0.1
0.1 PDM
0.05
0.02 t1
0.01 t2
NOTES:
SINGLE PULSE DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 1 10
t 1, RECTANGULAR PULSE DURATION (s)
4-35
IRF9640, RF1S9640SM
-100 -50
VGS = -11V VGS = -10V
100µs
-10 VGS = -9V
1ms -30
VGS = -8V
10ms
OPERATION IN THIS -20
AREA MAY BE 100ms VGS = -7V
-1
LIMITED BY rDS(ON)
DC VGS = -6V
TC = 25oC -10
TJ = MAX RATED VGS = -5V VGS = -4V
SINGLE PULSE
-0.1 0
-1 -10 -100 -1000 0 -10 -20 -30 -40 -50
VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)
-20 100
PULSE DURATION = 80µs VGS = -10V VDS ≥ I D(ON) x rDS(ON)
DUTY CYCLE = 0.5% MAX VGS = -8V
PULSE DURATION = 80µs
VGS = -9V VGS = -7V DUTY CYCLE = 0.5% MAX
-16
ID, DRAIN CURRENT (A)
-10
-12
VGS = -4V
0 -0.1
0 -2 -4 -6 -8 -10 0 -2 -4 -6 -8 -10
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)
2.0
0.6
ON RESISTANCE
0.5 1.5
0.4
1.0
0.3
VGS = - 20V
0.2 0.5
0 0.0
0 -15 -30 -45 -60 -75 -40 0 40 80 120 160
ID, DRAIN CURRENT (A) TJ , JUNCTION TEMPERATURE (oC)
NOTE: Heating effect of 5µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE
4-36
IRF9640, RF1S9640SM
1.15 2000
ID = 250µA VGS = 0V, f = 1MHz
NORMALIZED DRAIN TO SOURCE
C, CAPACITANCE (pF)
1.05
1200 CISS
1.00
800
0.95
400 COSS
0.90
CRSS
0.85 0
-80 -40 0 40 80 120 160 0 10 20 30 40 50
TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE
10 -100
PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX TJ = -55oC DUTY CYCLE = 0.5% MAX
gfs, TRANSCONDUCTANCE (S)
8
ISD, DRAIN CURRENT (A)
TJ = 25oC
TJ = 150oC
TJ = 125oC -10
6
TJ = 25oC
4
-1.0
-0.1
0 -10 -20 -30 -40 -50 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8
I D , DRAIN CURRENT (A) VSD, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
0
ID = -11A
VGS, GATE TO SOURCE (V)
-5
VDS = -40V
0 20 40 60 80
Qg(TOT), Total GATE CHARGE (nC)
4-37
IRF9640, RF1S9640SM
VDS
tAV
L 0
VARY tP TO OBTAIN
REQUIRED PEAK IAS RG
-
VDD
+
0V DUT VDD
tP IAS
VGS
VDS
IAS tP
0.01Ω
BVDSS
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON tOFF
td(ON) td(OFF)
tr tf
0
RL 10% 10%
DUT - VDS
VDD 90% 90%
RG
VGS + VGS
0
10%
50% 50%
PULSE WIDTH
90%
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
-VDS
CURRENT (ISOLATED
REGULATOR SUPPLY)
0
VDS
DUT
12V
0.2µF 50kΩ
BATTERY
0.3µF
Qgs VGS
D Qgd
Qg(TOT)
G DUT
VDD
0
Ig(REF) S 0
+VDS
IG CURRENT ID CURRENT
SAMPLING SAMPLING
RESISTOR RESISTOR Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
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IRF9640, RF1S9640SM
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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4-39