Introduction to Computer Organization

KR Chowdhary
Professor & Head
Email: kr.chowdhary@acm.org

Department of Computer Science and Engineering

MBM Engineering College, Jodhpur

January 13, 2011

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The course

Introduction: Overview of basic digital building blocks; truth

tables; basic structure of a digital computer.
Number representation: Integer - unsigned, signed (sign
magnitude, 1’s complement, 2’s complement, r’s
complement); Characters - ASCII coding, other coding
schemes; Real numbers - fixed and floating point, IEEE754
representation.
Assembly language programming for some processor.
Basic building blocks for the ALU: Adder, Subtractor, Shifter,
Multiplication and division circuits.
CPU Subblock: Datapath - ALU, Registers, CPU buses;
Control path - microprogramming (only the idea), hardwired
logic; External interface.

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Memory Subblock: Memory organization; Technology - ROM,
RAM, EPROM, Flash, etc. Cache; Cache coherence protocol
for uniprocessor (simple).
I/O Subblock: I/O techniques - interrupts, polling, DMA;
Synchronous vs. Asynchronous I/O; Controllers.
Peripherals: Disk drives; Printers - impact, dot matrix, ink jet,
laser; Plotters; Keyboards; Monitors.
Advanced Concepts: Pipelining; Introduction to Advanced
Processors.

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Books and References:

Computer Architecture and Organization: J.P. Hayes,

McGrawHill
Computer Architecture and organization: William Stallings
Computer Architecture: H. Patterson, Elsevier
Net, Wikipedia, OCW MIT

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Class test, attendance, Midsem, endsem evaluation:

20% Quizes, Assignments, attendance (attendance 5%)

20% first midsem, 20% II midsem,
40% endsem
Evaluation method for final grades: Clustering of scores. e.g.
descending scores are 69, 68, 67, 67, 66 62, 61, 60, 60, 55,
54, 33, 52, 48, 47, 46, 45, 44, 38, 36 then
A = {69, 68, 67, 67, 66}, B = {62, 61, 60, 60}, C =
{55, 54, 53, 52}, D = {48, 47, 46, 45, 44}, F = {38, 36}

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Computer Functional Diagram

Figure: Functional block diagram of computer

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Computer Functional Diagram2

Blocks:

Figure: Functional block diagram of computer with IO

connections are busses, size of busses: 8, 16, 32, 64. (older

systems: 8, 12, 24, 40, etc.)
Von Neumann Model (Arithmetic and Boolean logic, memory
-R/W, Execution Control-branches and Jumps.

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Instructions and data

Instructions and data are in binary (1, 0) format

Binary levels in logics: TTL (0-0.8) = logic 0, (2.0-5.0v)=
logic 1(true), ECL, DTL, RTL, etc.
how the CPU identifies a binary string as data or instructions?
What is minimum ckt to store bit (0, 1)?

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Single memory cell

Flip-flop as single memory cell.

Figure: Single cell to store 1 or 0

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Logic Gates

basic gates and universal gates

Truth table AND GATE
Z

X Y Z Z=X
----------------
==
0 0 0
0 1 0
1 0 0
X Y
1 1 1 X
------------------
Z
TT not gate ==
truth Table OR GATE
X Z
X Y Z -------
------------- 0 1
X Y 0 0 0 1 0
0 1 1 ---------
1 0 1
1 1 1
-------------

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Simple Boolean logic circuits
Building circuits from basic gates
X Y

X Y

Z
Y W
X Exclusive
== OR gate

XY’ X’Y
Z.W XY’+X’Y
X.Y

XY’+X’Y More complex

X.Y+Z.W
expressions?
Expressions: Half adder ckt
S=X’Y+XY’ ?
C=XY?
These circuits’ output is directly dependent on I/P?

These are called combinational circuits (they have no

memory element)
Sequential circuits: O/P is function of current I/P and
previous I/P.
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Combinational circuits
Adders, subtractors, multipliers, dividers, multiplexers,
demultiplexers (O/P depends on current input)
A B
truth table

A B Sum= A’B+AB’ = A XOR B Carry=AB

0 0 0 0
0 1 1 0
1 0 1 0
A XOR B AB 1 1 0 1
-----------------------------------------------------------
Full Adder (FA) TT:
A B Ci S CO
A s=A XOR B
HA 0 0 0 0 0
B C =AB 0 0 1 1 0 S=A XOR B XOR Ci
0 1 0 1 0 Co=AB OR ACi OR BCi
A S=? 0 1 1 0 1
B FA 1 0 0 1 0
Co=?
Ci 1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

A full adder adds two bits and carry of previous addition. How
many FAs are required to add two 4-bit binary nos.? Why FA
is FA?
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A TTL NAND gate

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Design Levels

Design level Components IC type unit of Info

Processor CPU, IOPs, LSI, VLSI Blocks of
memories, IO devices words
Register Register, combinational, MSI Words
ckts simple sequential ckst
Gate logic gates, SSI Bits
flip-flops
Computer centre manager’s view: Processor level; Assembly
language programmer’s view: Register level, gate level: classical
switching theory

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hierarchical Design

Low or high levels. Should we proceed L to H or reverse?

One component at level Li is equal to a network of
components at level Li −1
Specify the processor level components, then register level
components, then gate level
components at each level should be as independent as
possible, standard interfaces.

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Gate Level Design

Switching theory deals with binary variables {xi } ∈ {0, 1}

A combinational switching function:
z = B k → B, B ∈ {0, 1}, B k is 2n binary tuples
combinational circuit can be designed by truth tables, I/P =
(x1 , . . . , xn ), O/P z(x1 , . . . , xn )

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boolean Algebra

f (x1 , . . . , xn ) = ∑i x˙i 1 . . . x˙in , where xij = xij |xij (SOP)

f (x1 , . . . , xn ) = ∏i (x˙i 1 + · · · + x˙in ). (POS)
The above is called Quinne-McClusky Method.
S = ĀB̄Ci + ĀB C̄i + AB̄ C̄i + ABCi , from truth table
Co = ĀBCi + AB̄Ci + AB C̄i + ABCi , from truth table
(Or, function Co (A, B, Ci ) = (m3 , m5 , m6 , m7 ). The minterm
mi assumes a value 1 for unique value of variables. Maxterm
defines the 0s in the truth table).
Alternatively, sum S is: (A ⊕ B) ⊕ Ci
= (ĀB + AB̄) ⊕ Ci
= ABCi + ĀB̄Ci + ĀB C̄i + AB̄ C̄i
Co , the carry out of full adder, is AB + ACi + BCi

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Karaugh Map or K-map for minimization of gate circuits
After Maurice Kaurnaugh (Bell Labs, 1950)

The function Co(A, B, Ci ) Can be implemented by three AND

gates plus one OR gate. Alternatively by: four gates each having
fan-in 2.
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K-map for minimization using maxterms

Co (A, b, Ci ) = (A + B)(A + Ci )(B + Ci )

= (A + ACi + AB + BCi )(B + Ci )
= ...
= AB + BCi + ACi
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Sequential circuits

z(t + ∆) = y (t) = x1 (t).x¯2 . y is internal state variable.

SR = 00 ⇒ y1 = y¯2 = 0, or y1 = y¯2 = 0
SR = 10 ⇒ y1 = y¯2 = 1, SR = 01 ⇒ y1 = y¯2 = 0
Race Condition? (if SR =11) Let SR =11, ∴, y1 = y2 = 0 after ∆
time.
Now let SR=00, y1 = y2 = 0 ⇒ y1 = y2 = 1 ⇒ . . . (Oscillates
between 0 and 1). this happens if ∆1 = ∆2 . Solution: SR = 11 is
kept forbidden state.
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Sequential circuits-2

Race conditions are eliminated by timing signals (clock)

Sequential circuits + clock = Synchronous circuits
circuits not timed by clock are asynchronous circuits (prone
too race conditions)
Triggering takes place on rising or trailing edge of clock pulse.
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