CAS (tCL) Timing: CAS stands for Column Address Strobe or Column Address Select.

It controls the amount of time in cycles between sending a reading command and
the time to act on it. From the beginning of the CAS to the end of the CAS is th
e latency. The lower the time of these in cycles, the higher the memory performa
nce.
e.g.: 2.5-3-3-8 The bold 2.5 is the CAS timing.

tRCD Timing: RAS to CAS Delay (Row Address Strobe/Select to Column Address Strob
e/Select). Is the amount of time in cycles for issuing an active command and the
read/write commands.
e.g.: 2.5-3-3-8 The bold 3 is the tRCD timing.

tRP Timing: Row Precharge Time. This is the minimum time between active commands
and the read/writes of the next bank on the memory module.
e.g.: 2.5-3-3-8 The bold 3 is the tRP timing.

tRAS Timing: Min RAS Active Time. The amount of time between a row being activat
ed by precharge and deactivated. A row cannot be deactivated until tRAS has comp
leted. The lower this is, the faster the performance, but if it is set too low,
it can cause data corruption by deactivating the row too soon.
tRAS = tCL + tRCD + tRP (+/- 1) so that it gives everything enought time before
closing the bank.
e.g.: 2.5-3-3-8 The bold 8 is the tRAS timing.
(The 2.5-3-3-8 figure is just an example for memory timings.)
These are the four timings that you would see when memory is being rated. It is
in the order of CAS-tRCD-tRP-tRAS. The lower these timings, the higher the perfo
rmance of the memory. Some motherboard manufactors (DFI for example) list the ti
mings in their bios CAS-tRCD-tRAS-tRP.
Certain memories can take tighter (lower) timings at higher speeds. These are th
e more expensive memory modules out of the bunch. There are also other timings t
o consider in your BIOS. Not all boards will have options like these.
[page=Other Timings & Conclusion]
Other Timings.
Command Rate: Also called CPC (Command Per Clock). The amount of time in cycles
when the chip select is executed and the commands can be issued. The lower (1T)
the faster the performance, but 2T is used to maintain system stability. On Inte
l based machines, 1T is always used where the number of banks per channel are li
mited to 4.

tRC Timing: Row Cycle Time. The minimum time in cycles it takes a row to complet
e a full cycle. This can be determined by; tRC = tRAS + tRP. If this is set too
short it can cause corruption of data and if it is to high, it will cause a loss
in performance, but increase stability.

tRRD Timing: Row to Row Delay or RAS to RAS Delay. The amount of cycles that it
takes to activate the next bank of memory. It is the opposite of tRAS. The lower
the timing, the better the performance, but it can cause instability.

tRFC Timing: Row Refresh Cycle Timing. This determines the amount of cycles to r
efresh a row on a memory bank. If this is set too short it can cause corruption
of data and if it is too high, it will cause a loss in performance, but increase
d stability.

tRW Timing: Write Recovery Time. The amount of cycles that are required after a
valid write operation and precharge. This is to insure that data is written prop
erly.

tRTW/tRWT Timing: Read to Write Delay. When a write command is received, this is
the amount of cycles for the command to be executed.

tWTR Timing: Write to Read Delay. The amount of cycles required between a valid
write command and the next read command. Lower is better performance, but can ca
use instability.

tREF Timing: The amount of time it takes before a charge is refreshed so it does
not lose its charge and corrupt. Measured in micro-seconds (µsec).

tWCL Timing: Write CAS number. Write to whatever bank is open to be written too.
Operates at a rate of 1T, but can be set to others. It does not seem to work wi
th other settings than 1T on DDR. DDR2 is different though.