LAB MANUAL

DIGITAL SYSTEM DESIGN

COMSATS INSTITUTE OF INFORMTION TECHNOLOGY

Department of Electrical Engineering (Wah campus)

DIGITAL SYSTEM DESIGN

NAME________________

REG# ________________

Instructor: Engineer Saba Iqbal.

 Experiment 1
Introduction to Verilog HDL and Xilinx ISE, implementation of 4x1
multiplexer using gate level, data flow and behavioral modeling

Verilog
• Describes complex designs (millions of gates)

• Input to synthesis tools (synthesizable subset)

Verilog Software language to Design Hardware

• Verilog is an implementation language.

• Verilog is a type of software used to describe hardware; it is an HDL, or Hardware description

Language, NOT a software programming language.

Simulation and Synthesis

• Simulation is used to verify the functionality of the circuit. Simulation tools check the logical
functionality of circuit via test benches that stimulate the design, and check for expected results.

• Synthesis is implementation of design into actual hardware. Synthesis is one of the foremost in
back end steps where by synthesizing is nothing but converting VHDL or VERILOG description
to a set of components(as in FPGA'S)to fit into the target technology. Basically the synthesis
tools convert the design description into equations or components.

• Synthesis tools take the Verilog as input and attempt to create the circuit described by the
Verilog.

Modules
The Module Concept:

• The module is the basic building block in Verilog.

• The Modules are: Declared and Instantiated.

Modeling Structure: Ports

Modules Ports

• Similar to pins on chips

• Provide a way to communicate with outside world

• Pots can be input, output or inout.

Modeling Structure: Instances
Modeling Instances

• Verilog models consist of a hierarchy of module instances.

Data Types

Nets
• Nets are physical connections between devices.

• Nets always reflect the logic value of the driving device.

Registers
• Register type is denoted by reg

• Implicit storage-unless variable of this type is modified it retains previously assigned value.

Variable Declarations

Hardware description
• reg a;

• reg [7:0] sum;

• reg variable is assigned a value by behavioral code.

• wire b;

• wire [3:0] c;

• wire variable is assigned a value in a continuous assignment.

Ports and Data Types

Abstraction Levels in Verilog

• There are four level of abstractions

1. Gate level or structural modeling

2. Data flow level

3. Behavioral or algorithmic level

Gate –Level Modeling

• Specifies primitive gates and wires i.e. structure of a logical net list.

• Easiest to model and code and most difficult to design for complex circuits.

• Verilog has built in gate level primitives NAND. NOR, AND, OR, XOR, NOT and some others.

module andoperation(out,in1,in2);

output out;

input in1,in2;

and andoperation (out,in1,in2);

endmodule
Data Flow Modeling in Verilog
Introduction
Dataflow modeling provides a powerful way to implement a design. Verilog allows a design processes
data rather than instantiation of individual gates. Dataflow modeling has become a popular design
approach as logic synthesis tools have become sophisticated.

Operands in Verilog
Operators in Verilog

Continuous Assignment
• Use keyword “assign”.

• Left hand side of assignment is wire.

• Right hand side of assignment is net or reg.

• Used to model combinational logic or make connections between wires.

module and(out,in1,in2);

output out;

input in1,in2;

assign out=in1&in2;

end module

Behavioral Modeling in Verilog

• Behavioral Models: Higher level of modeling where behavior of logic is modeled.
• RTL Models : Logic is modeled at register level
 • Structural Models: Logic is modeled at both register level and gate level.

Procedural Blocks
Verilog behavioral code is inside procedure blocks, but there is an exception: some behavioral code also
exist outside procedure blocks.
There are two types of procedural blocks in Verilog:
• initial: initial blocks execute only once at time zero (start execution at time zero).
• always: always blocks loop to execute over and over again; in other words, as the name suggests,
it executes always.

Initial Block
• All statements inside an initial statement constitute and initial block.

• An initial block starts at time 0, executes exactly once during a simulation, and then does not
execute again.

• If there are multiple blocks, each block starts to execute concurrently at time 0.

• Each block finishes execution independently of other blocks.

• Multiple behavioral statements must be grouped; typically using the keywords begin and end.
module initial_example();
reg clk,reset,enable,data;
initial begin
clk = 0;
reset = 0;
enable = 0;
data = 0;
Always Block end
• All behavioral statementsendmodule
inside an always statement constitute an always block.

• The always statements starts at time 0 and executes the statements in the always block
continuously in a looping fashion.

• This statement is used to model a block of activity that is repeated continuously in a digital
circuit.
module always_example();
reg clk,reset,enable,q_in,data;

always @ (posedge clk)

if (reset) begin
data <= 0;
end else if (enable) begin
data <= q_in;
end
endmodule
Procedural Statements
Blocking statements
Blocking assignments are executed in the order they are coded, hence they are sequential.
Since they block the execution of next statment, till the current statement is executed, they
are called blocking assignments. Assignment are made with "=" symbol. Example a = b;

Non-Blocking statements
Non-blocking assignments are executed in parallel. Since the execution of next statement
is not blocked due to execution of current statement, they are called nonblocking
statement. Assignments are made with "<=" symbol. Example a <= b;

Creation of Project

open Xilinx ISE go to File →New Project

Write the project name, directory and HDL and click next

Select the categories according to figure and click next then click on Finish
Creating Source file: right click on Project name __>select new source file

Select ‘Verilog module’ and give file name and click next new window will open just click next
and then finish
Now project and source file is created and it is ready to write Verilog code.

How to simulate your code in ISim simulator:

Right click on project name add new source file for test bench, select test fixture and name test file
 Test file will be automatically create just give values of input ,

Select test bench file and double click on “simulate behavioral Model”

Lab task: Implementation of 4x1 multiplexer using Gate Level, Data

Flow and Behavioral Modeling

Select inputs Output

s1 S0 Y

0 0 A

0 1 B

1 0 C

1 1 D
 Inputs 4 X1
Output
MUX

Select

Equation
y=As1s2+Bs1s2+Cs1s2+Ds1s2
a) Gate Level Modeling
Verilog code
module gatelevel_mux_4x1(y,a,b,c,d,s1,s2);
input a,b,c,d,s1,s2;
output y;
wire x2,x1,w1,w2,w3,w4,w5;
not n1(x2,s1);
not n2(x1,s2);
and a1(w1,a,x1,x2);
and a2(w2,b,s1,x1);
and a3(w3,c,s2,x2);
and a4(w4,d,s2,s1);
or o1(w5,w1,w2,w3);
or o2(y,w5,w4);
endmodule

Test bench
module gatelevel_mux_4x1_TB;

// Inputs
reg a;
reg b;
reg c;
reg d;
reg s1;
reg s2;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

gatelevel_mux_4x1 uut (
.y(y),
.a(a),
.b(b),
.c(c),
.d(d),
.s1(s1),
.s2(s2)
);

initial begin
// Initialize Inputs
a = 1;
b = 1;
c = 1;
d = 1;
s1 = 0;
s2 = 0;

// Wait 100 ns for global reset to finish

#100;
a = 1;
b = 1;
 c = 1;
d = 1;
s1 = 0;
s2 = 1;
#100;
a = 1;
b = 1;
c = 1;
d = 1;
s1 = 1;
s2 = 0;
#100;
a = 1;
b = 1;
c = 1;
d = 1;
s1 = 1;
s2 = 1;

// Add stimulus here

end

endmodule
Simulation

b) Data flow Modeling

Verilog code
module dataflow_mux_4x1(y,a,b,c,d,s1,s2);
input a,b,c,d,s1,s2;
output y;
assign y=a & ~s1 & ~s2 | b & ~s1 & s2 | c & s1 & ~s2 | d & s1 & s2;
endmodule

Test bench
module dataflow_mux_4x1_TB;

// Inputs
reg a;
reg b;
reg c;
reg d;
reg s1;
reg s2;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

dataflow_mux_4x1 uut (
.y(y),
.a(a),
.b(b),
.c(c),
.d(d),
.s1(s1),
.s2(s2)
);

initial begin
// Initialize Inputs
a = 1;
b = 1;
c = 1;
d = 1;
s1 = 0;
s2 = 0;

// Wait 100 ns for global reset to finish

#100;
a = 1;
b = 1;
c = 1;
 d = 1;
s1 = 0;
s2 = 1;
#100;
a = 1;
b = 1;
c = 1;
d = 1;
s1 = 1;
s2 = 0;
#100;
a = 1;
b = 1;
c = 1;
d = 1;
s1 = 1;
s2 = 1;

// Add stimulus here

End

endmodule
Simulation

c) Behavioral Modeling
Verilog code
module bahavioural_mux_4x1(y,a,b,c,d,s1,s2);
input a,b,c,d,s1,s2;
output reg y;
always @ (a,b,c,d,s1,s2);
case({s1,s2})
2'b00 : y=a;
2'b01 : y=b;
2'b10 : y=c;
2'b11 : y=d;
default : y=z;
endcase
end
endmodule
Test bench
module dataflow_mux_4x1_TB;

// Inputs
reg a;
reg b;
reg c;
reg d;
reg s1;
reg s2;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

dataflow_mux_4x1 uut (
.y(y),
.a(a),
.b(b),
.c(c),
.d(d),
.s1(s1),
.s2(s2)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
 #100;
a = 0;
b = 1;
// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 0;

// Wait 100 ns for global reset to finish

#100;
a = 1;
b = 1;

// Add stimulus here

end
endmodule

Simulation