A Fractional-N PLL Frequency Synthesizer Design
Seoncheol Kim and Youngsik Kim
Dept. of Information and Technology Eng., Handong Global University
young@handong.edu
Abstract
This paper proposes a fractional-N phase-locked loop
(PLL) frequency synthesizer using 3rd order ǻȈ modulator
for 915MHz medium speed FSK wireless link. The voltage-
controlled oscillator (VCO), pre-scaler of divide-by-8,
phase frequency detector (PFD), and charge pump (CP)
have been developed with 0.25-µm CMOS process. A 3rd
order external loop filter has been optimized to reduce the
lock-in time. The fractional-N divider and 3rd order ǻȈ
modulator have been designed with the VHDL codes, and
implemented through the FPGA board of the Xilinx
Spartan2E. The VCO has been designed to span from
900MHz to 950MHz band using LC resonator, and a
fractional-N divider uses a 36/37 modulus and 3rd order
ǻȈ modulator to reduce the fractional spur. The measured
result shows that the RF output power of the frequency
synthesizer is -10dBm, the phase noise is -78dBc/Hz at
100KHz offset frequency, the minimum frequency step is
10kHz, and the maximum lock-in time is around 800ms
with 10MHz step change.
1. Introduction
Recently, the wireless communications is widening in
life continuously. Most people have a cellular phone, PDA,
or notebook that uses wireless communications. The
wireless communication system consists of many
components such as low-noise amplifier (LNA), mixer,
filter, power amplifier, frequency synthesizer, and base-
band modem. Among them, the frequency synthesizer is
one of the key components for high quality communication.
It generates the local oscillator (LO) signal for mixer, and
also for the carrier recovery in wireless receiver.
There are several different types of frequency
synthesizers: the direct digital synthesizer, the direct analog
synthesizer, and the phase-locked or indirect synthesizer
[1]. In the direct digital synthesizer and direct analog
synthesizer, their power consumption is very much because
their structure is complex and their size is big. The power
consumption of the phase-locked loop is relatively small
because its simple structure and small size. Thus, the phase-
locked loop (PLL) type of frequency synthesizer is most
suitable for the system on a chip (SOC) in wireless
communication systems. The phase-locked loop (PLL)
frequency synthesizer consists of a voltage controlled
oscillator (VCO), pre-scaler, divider, phase frequency
detector (PFD), charge pump, and loop filter. The key
parameters in the PLL frequency synthesizer are the phase
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noise and lock-in time. In general, it is obvious to reduce
the phase noise of VCO itself for better phase noise. In
addition, the phase noise will be improved by reducing the
loop bandwidth, but the reduced loop bandwidth will
increase the lock-in time. Therefore, the reference
frequency and loop bandwidth should be carefully
designed.
In section 2, the structure and design procedure of the
fractional-N PLL frequency synthesizer are explained, and
the measurement result are describes in section 3.
2. Fractional-N PLL Frequency Synthesizer
The block diagram of the Fractional-N PLL frequency
synthesizer is shown in Figure 1. In the fractional-N divider,
a 36/37 dual modulus divider has been used, and 3rd order
delta-sigma modulator is added to remove the fractional
spurs, which come out inevitably. The fractional N divider
enables the minimum frequency step could be controlled
regardless of reference frequency not like the integer-N
divider [2].
Figure 1. Block diagram of the fractional-N PLL
frequency synthesizer
Figure 2 shows the schematic of the LC VCO. To reduce
the phase noise in LC VCO, it is required to maximize the
LC resonator Q-factor, and the low 1/f noise elements
should be used. The VCO is designed with PMOS
transistor except the output buffer because it is known as
good noise performance better than NMOS transistor. The
output buffer is designed as inverter structure. The M1
transistor decides the tail current level of the VCO core. To
reduce the power consumption of the VCO, it needs to
minimize the current level oscillating the VCO core. The
M2 and M3 are connected by cross-coupled to have
negative resistance. PMOS transistors are used as the
variable capacitors, which determine the tuning range of the
VCO. To increase the Q-factor in resonator, the external
inductors have been used. The M4~M7 build the output
84
 buffers. The VB2 and VB3 are biased the half value of the
VDD.

(a)

Figure 2. LC VCO

The maximum operating frequency of the Xilinx

Spartan2e board is less than 200MHz, so that it is required
to lower the VCO frequency down to the frequency
acceptable in the FPGA board. A divide-by-8 pre-scaler is
designed to down the VCO frequency. Figure 3 shows the
block diagram of the pre-scaler. The D flip-flop is designed
with source-coupled logic structure to reduce the switching (b)
noise in high frequency. The Vbias is grounded to increase
the maximum input frequency by operating M1 and M2 in Figure 3. (a) Block diagram of the pre-scaler (b) D
the linear region, which lowers the RC time constants flip-flop using source-coupled logic (SCL)
associated with the output nodes. The bias-dependent structure.
channel resistance of M1 and M2 also helps to increase
maximum speed at low power consumption. The bias § M −K K ·
current is adjusted by changing the sizes of M1, M2. To f vco = ¨ 36 ⋅ + 37 ⋅ ¸ ⋅ f ref
ensure the maximum operating frequency, the maximum © M M ¹
(1)
operation frequency in the pre-scaler should be much K·
§
higher than the maximum VCO frequency [3]. = ¨ 36 + ¸ ⋅ f ref
A fractional-N divider is used to increase the reference © M¹
frequency of the phase frequency detector (PFD) and to
reduce the minimum frequency step simultaneously. The The PFD is very simple structure and consists of two
fractional-N divider consists of a 36/37 dual modulus clearable D flip-flops, a AND gate and delay cell [1].
divider and a 3rd order ǻȈ modulator. The 3rd order ǻȈ Figure 4 shows the block diagram of the PFD.
modulator is used to reduce the fractional spur [2]. The
fractional-N divider has been designed with the VHDL
code. The output frequency of the VCO is determined by
the following equation.

Figure 4. Block diagram of the PFD

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 The schematic of the charge pump is shown in Figure 5.
A general charge pump has the up and down signals. On
the other hand, the proposed charge pump has three inputs
of up, down, and Vcp. M4 ~ M6 consist the bias circuit to
provide the up and down current. The pumping current
level could be controlled through the gate voltage of M5.
The tuning range of the VCO is measured of 900 MHz ~
950 MHz with the input control voltage of 0.5V ~ 2.5V.
The output power of the VCO is -10 dBm. Figure 6 shows
the spectral characteristics of the PLL. The measured phase
noise is -78dBc/Hz at 100 KHz offset frequency.

Figure 6. Output Spectrum

The lock-in time of the PLL is measured indirectly by

probing the VCO control voltage with periodic change of
the output frequency. Figure 7 shows the control voltage
pattern with 10MHz frequency change.

Figure 5. Charge Pump Circuit

The loop filter is designed with 3rd order RC filter using

two resistors and three capacitors [1].

3. Measured Results

The VCO, divide-by-8 prescaler, PFD, charge pump
have been fabricated through Hynix 0.25um CMOS
process, and the fractional-N divider is implemented with a
Xilinx Spartan2E FPGA board. The 3rd order passive loop
filter is designed with the external components to optimize
the lock-in time and phase noise characteristics.
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Figure 7. Lock-in time of the PLL ( measured with
10MHz step change )
4. Conclusion
A fractional-N PLL frequency synthesizer has been
developed. The VCO, divider, PFD, and charge pump are
fabricated by 0.25µm CMOS process. The fractional-N

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 divider is implemented in the FPGA board. The output
power of the frequency synthesizer is -10dBm, the phase
noise is -78dBc/Hz at the 100KHz offset frequency, the
minimum frequency step is 10KHz, and the lock-in time is
800 us with the 10MHz frequency change.

5. Acknowledgement
This research supported by the Program of the Training
of Graduate Students in Regional Innovation which was
conducted by the Ministry of Commerce, Industry and
Energy of the Korean Government.

6. References

[1] William F. Egan, Frequency Synthesis by Phase Lock, Wiley

Inter-science, 1999.

[2] Tom A. D. Riley, Miles A. Copeland, Tad A. Kwasniewski,

"Delta-Sigma Modulation in Fractional-N Frequency Synthesis,"
IEEE J. Solid-State Circuits, vol. 304, no. 5, 1993, pp.553-559.

[3] Chih-Ming Hung and Kenneth K. O, "A Fully Integrated 1.5-V

5.5-GHz CMOS Phase-Locked Loop," IEEE J. Solid-State
Circuits, vol. 37, no. 4, 2002, pp.521-525.

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