P6.

1 SEQUENTIAL BLOCKS
(continuation)

Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain
 2 REGISTER BANK P6 .1

Functional specification
loop
case program(number) is Sequential circuit:
when (ASSIGN_VALUE, k, A) => X0, ··· , X15 are internally stored.
X(k) := reg_in; left_out := don't care; right_out := don't care;
when (DATA_INPUT, k, j) =>
X(k) := reg_in; left_out := don't care; right_out := don't care;
when (DATA_OUTPUT, i, j) => instruction write_reg
left_out := don't care; right_out := X(j);
ASSIGN_VALUE 1
when (OUTPUT_VALUE, i, A) =>
left_out := don't care; right_out := don't care; DATA_INPUT 1
when (OPERATION, i, j, k, f) => OPERATION 1
X(k) := reg_in; left_out := X(i); right_out := X(j); others 0
when (JUMP, N) =>
left_out := don't care; right_out := don't care; control signals
when (JUMP_POS, i, N) =>
left_out := X(i); right_out := don't care;
when (JUMP_NEG, i, N) =>
left_out := X(i); right_out := don't care;
end case; 2
end loop;
 (register bank) P6 .1
instruction write_reg
ASSIGN_VALUE 1
DATA_INPUT 1
Functional specification OPERATION 1
loop others 0
case program(number) is
when (ASSIGN_VALUE, k, A) =>
X(k) := reg_in; left_out := don't care; right_out := don't care;
when (DATA_INPUT, k, j) =>
X(k) := reg_in; left_out := don't care; right_out := don't care;
when (DATA_OUTPUT, i, j) =>
left_out := don't care; right_out := X(j); loop
when (OUTPUT_VALUE, i, A) =>
left_out := don't care; right_out := don't care;
if write_reg = 1 then X(k) := reg_in; end if;
when (OPERATION, i, j, k, f) => left_out := X(i);
X(k) := reg_in; left_out := X(i); right_out := X(j); right_out := X(j);
when (JUMP, N) =>
left_out := don't care; right_out := don't care;
end loop;
when (JUMP_POS, i, N) =>
left_out := X(i); right_out := don't care;
when (JUMP_NEG, i, N) =>
left_out := X(i); right_out := don't care;
end case; 3
end loop;
 (register bank) P6 .1
straightforward implementation:

reg_in

write_reg ···
EN0
0 EN0 CEN EN1 CEN EN15 CEN
EN1
1
k ··· ···
···

15 EN15
···

0 1
···
15 0 1
···
15
loop
i j
if write_reg = 1 then X(k) := reg_in; end if;
left_out right_out
left_out := X(i);
right_out := X(j);
end loop;

4
 (register bank: VHDL model) P6 .1

reg_in
library ieee; use ieee.std_logic_1164.all;
write_reg ··· use ieee.std_logic_arith.all;
0
EN0

EN1
EN0 CEN EN1 CEN EN15 CEN use ieee.std_logic_unsigned.all;
1
k ··· ···
··· use work.main_parameters.all;
15 EN15
··· entity register_bank is
··· ··· port (
i
0 1 15
j
0 1 15 reg_in: in std_logic_vector(m-1 downto 0);
clk, write_reg: in std_logic;
left_out right_out i, j, k: in std_logic_vector(3 downto 0);
left_out, right_out:
out std_logic_vector(m-1 downto 0)
);
end register_bank;

5
 (register bank: VHDL model) P6 .1

reg_in architecture structure of register_bank is

write_reg ··· type memory is array (0 to 15) of
0
EN0
EN0 CEN EN1 CEN EN15 CEN
std_logic_vector(m-1 downto 0);
k
1
EN1

···
signal X: memory;
··· ···

15 EN15
··· signal EN: std_logic_vector(0 to 15);
begin
··· ···
0 1 15 0 1 15 decoder: process(k, write_reg)
i j
begin
left_out right_out
for i in 0 to 15 loop
if i < conv_integer(k) then EN(i) <= '0';
elsif i = conv_integer(k) then EN(i) <= write_reg;
else EN(i) <= '0'; end if;
end loop;
end process;

6
 (register bank: VHDL model) P6 .1

reg_in
bank_registers: process(clk)
write_reg ··· begin
0
EN0

EN1
EN0 CEN EN1 CEN EN15 CEN if clk'event and clk = '1' then
1
k ··· ···
··· for i in 0 to 15 loop
15 EN15
··· if EN(i) = '1' then X(i) <= reg_in;
··· ··· end if;
0 1 15 0 1 15
i j end loop;
end if;
left_out right_out end process;

7
 (register bank: VHDL model) P6 .1
first_multiplexer: process(i, X)
begin
reg_in case i is
when "0000" => left_out <= X(0);
write_reg ···
EN0
······
0
1
EN1
EN0 CEN EN1 CEN EN15 CEN
when "1110" => left_out <= X(14);
k ··· ···
···
when others => left_out <= X(15);
EN15
···
15
end case;
··· ··· end process;
0 1 15 0 1 15
i j second_multiplexer: process(j, X)
begin
left_out right_out case j is
when "0000" => right_out <= X(0);
············
when "1110" => right_out <= X(14);
when others => right_out <= X(15);
end case;
end process;
8
end structure;
SUMMARY P6 .1

 VHDL models of sequential blocks:

 register bank.